Age | Commit message (Expand) | Author |
---|---|---|
2022-05-11 | riscv: add memory-type errata for T-Head | Heiko Stuebner |
2022-05-11 | riscv: integrate alternatives better into the main architecture | Heiko Stuebner |
2021-04-26 | riscv: sifive: Add SiFive alternative ports | Vincent Chen |
2021-04-26 | riscv: Introduce alternative mechanism to apply errata solution | Vincent Chen |