diff options
Diffstat (limited to 'drivers/gpu/drm/i915')
311 files changed, 11043 insertions, 8433 deletions
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 3dda9f0eda82..ed05b131ed3a 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -231,6 +231,7 @@ i915-y += \ display/intel_bo.o \ display/intel_bw.o \ display/intel_cdclk.o \ + display/intel_cmtg.o \ display/intel_color.o \ display/intel_combo_phy.o \ display/intel_connector.o \ @@ -346,6 +347,7 @@ i915-y += \ display/intel_pps.o \ display/intel_qp_tables.o \ display/intel_sdvo.o \ + display/intel_snps_hdmi_pll.o \ display/intel_snps_phy.o \ display/intel_tv.o \ display/intel_vdsc.o \ diff --git a/drivers/gpu/drm/i915/display/dvo_ch7017.c b/drivers/gpu/drm/i915/display/dvo_ch7017.c index 493e730c685b..206818f9ad49 100644 --- a/drivers/gpu/drm/i915/display/dvo_ch7017.c +++ b/drivers/gpu/drm/i915/display/dvo_ch7017.c @@ -247,7 +247,7 @@ static enum drm_connector_status ch7017_detect(struct intel_dvo_device *dvo) } static enum drm_mode_status ch7017_mode_valid(struct intel_dvo_device *dvo, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { if (mode->clock > 160000) return MODE_CLOCK_HIGH; diff --git a/drivers/gpu/drm/i915/display/dvo_ch7xxx.c b/drivers/gpu/drm/i915/display/dvo_ch7xxx.c index 534b8544e0a4..10ab3cc73e58 100644 --- a/drivers/gpu/drm/i915/display/dvo_ch7xxx.c +++ b/drivers/gpu/drm/i915/display/dvo_ch7xxx.c @@ -276,7 +276,7 @@ static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo) } static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { if (mode->clock > 165000) return MODE_CLOCK_HIGH; diff --git a/drivers/gpu/drm/i915/display/dvo_ivch.c b/drivers/gpu/drm/i915/display/dvo_ivch.c index 0d5cce6051b1..d9c3152d4338 100644 --- a/drivers/gpu/drm/i915/display/dvo_ivch.c +++ b/drivers/gpu/drm/i915/display/dvo_ivch.c @@ -314,7 +314,7 @@ static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo) } static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { if (mode->clock > 112000) return MODE_CLOCK_HIGH; diff --git a/drivers/gpu/drm/i915/display/dvo_ns2501.c b/drivers/gpu/drm/i915/display/dvo_ns2501.c index 686393dfbbf5..92d32d6b5bce 100644 --- a/drivers/gpu/drm/i915/display/dvo_ns2501.c +++ b/drivers/gpu/drm/i915/display/dvo_ns2501.c @@ -517,13 +517,13 @@ static enum drm_connector_status ns2501_detect(struct intel_dvo_device *dvo) * Even if not, the detection bit of the 2501 is unreliable as * it only works for some display types. * It is even more unreliable as the PLL must be active for - * allowing reading from the chiop. + * allowing reading from the chip. */ return connector_status_connected; } static enum drm_mode_status ns2501_mode_valid(struct intel_dvo_device *dvo, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { DRM_DEBUG_KMS ("is mode valid (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d)\n", diff --git a/drivers/gpu/drm/i915/display/dvo_sil164.c b/drivers/gpu/drm/i915/display/dvo_sil164.c index a8dd40c00997..b42c717085f3 100644 --- a/drivers/gpu/drm/i915/display/dvo_sil164.c +++ b/drivers/gpu/drm/i915/display/dvo_sil164.c @@ -189,7 +189,7 @@ static enum drm_connector_status sil164_detect(struct intel_dvo_device *dvo) } static enum drm_mode_status sil164_mode_valid(struct intel_dvo_device *dvo, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { return MODE_OK; } diff --git a/drivers/gpu/drm/i915/display/dvo_tfp410.c b/drivers/gpu/drm/i915/display/dvo_tfp410.c index d9a0cd753a87..280699438526 100644 --- a/drivers/gpu/drm/i915/display/dvo_tfp410.c +++ b/drivers/gpu/drm/i915/display/dvo_tfp410.c @@ -217,7 +217,7 @@ static enum drm_connector_status tfp410_detect(struct intel_dvo_device *dvo) } static enum drm_mode_status tfp410_mode_valid(struct intel_dvo_device *dvo, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { return MODE_OK; } diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 56353377466c..55b9e9bfcc4d 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -51,28 +51,29 @@ static const struct dpll chv_dpll[] = { { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ }, }; -const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) +const struct dpll *vlv_get_dpll(struct intel_display *display) { - return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0]; + return display->platform.cherryview ? &chv_dpll[0] : &vlv_dpll[0]; } static void g4x_dp_set_clock(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); const struct dpll *divisor = NULL; int i, count = 0; - if (IS_G4X(dev_priv)) { + if (display->platform.g4x) { divisor = g4x_dpll; count = ARRAY_SIZE(g4x_dpll); } else if (HAS_PCH_SPLIT(dev_priv)) { divisor = pch_dpll; count = ARRAY_SIZE(pch_dpll); - } else if (IS_CHERRYVIEW(dev_priv)) { + } else if (display->platform.cherryview) { divisor = chv_dpll; count = ARRAY_SIZE(chv_dpll); - } else if (IS_VALLEYVIEW(dev_priv)) { + } else if (display->platform.valleyview) { divisor = vlv_dpll; count = ARRAY_SIZE(vlv_dpll); } @@ -129,7 +130,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, /* Split out the IBX/CPU vs CPT settings */ - if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { + if (display->platform.ivybridge && port == PORT_A) { if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) intel_dp->DP |= DP_SYNC_HS_HIGH; if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) @@ -148,7 +149,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, pipe_config->enhanced_framing ? TRANS_DP_ENH_FRAMING : 0); } else { - if (IS_G4X(dev_priv) && pipe_config->limited_color_range) + if (display->platform.g4x && pipe_config->limited_color_range) intel_dp->DP |= DP_COLOR_RANGE_16_235; if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) @@ -160,7 +161,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, if (pipe_config->enhanced_framing) intel_dp->DP |= DP_ENHANCED_FRAMING; - if (IS_CHERRYVIEW(dev_priv)) + if (display->platform.cherryview) intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe); else intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); @@ -180,9 +181,8 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state) } #define assert_dp_port_disabled(d) assert_dp_port((d), false) -static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) +static void assert_edp_pll(struct intel_display *display, bool state) { - struct intel_display *display = &dev_priv->display; bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE; INTEL_DISPLAY_STATE_WARN(display, cur_state != state, @@ -197,11 +197,10 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, { struct intel_display *display = to_intel_display(intel_dp); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder); + assert_transcoder_disabled(display, pipe_config->cpu_transcoder); assert_dp_port_disabled(intel_dp); - assert_edp_pll_disabled(dev_priv); + assert_edp_pll_disabled(display); drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n", pipe_config->port_clock); @@ -223,8 +222,8 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, * 1. Wait for the start of vertical blank on the enabled pipe going to FDI * 2. Program DP PLL enable */ - if (IS_IRONLAKE(dev_priv)) - intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); + if (display->platform.ironlake) + intel_wait_for_vblank_if_active(display, !crtc->pipe); intel_dp->DP |= DP_PLL_ENABLE; @@ -237,12 +236,10 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp, const struct intel_crtc_state *old_crtc_state) { struct intel_display *display = to_intel_display(intel_dp); - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); + assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder); assert_dp_port_disabled(intel_dp); - assert_edp_pll_enabled(dev_priv); + assert_edp_pll_enabled(display); drm_dbg_kms(display->drm, "disabling eDP PLL\n"); @@ -253,10 +250,9 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp, udelay(200); } -static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, +static bool cpt_dp_port_selected(struct intel_display *display, enum port port, enum pipe *pipe) { - struct intel_display *display = &dev_priv->display; enum pipe p; for_each_pipe(display, p) { @@ -277,11 +273,11 @@ static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, return false; } -bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, +bool g4x_dp_port_enabled(struct intel_display *display, i915_reg_t dp_reg, enum port port, enum pipe *pipe) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); bool ret; u32 val; @@ -290,11 +286,11 @@ bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, ret = val & DP_PORT_EN; /* asserts want to know the pipe even if the port is disabled */ - if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) + if (display->platform.ivybridge && port == PORT_A) *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB; else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) - ret &= cpt_dp_port_selected(dev_priv, port, pipe); - else if (IS_CHERRYVIEW(dev_priv)) + ret &= cpt_dp_port_selected(display, port, pipe); + else if (display->platform.cherryview) *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV; else *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT; @@ -305,20 +301,20 @@ bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, static bool intel_dp_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); intel_wakeref_t wakeref; bool ret; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; - ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg, + ret = g4x_dp_port_enabled(display, intel_dp->output_reg, encoder->port, pipe); - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } @@ -390,7 +386,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder, pipe_config->hw.adjusted_mode.flags |= flags; - if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) + if (display->platform.g4x && tmp & DP_COLOR_RANGE_16_235) pipe_config->limited_color_range = true; pipe_config->lane_count = @@ -432,7 +428,7 @@ intel_dp_link_down(struct intel_encoder *encoder, drm_dbg_kms(display->drm, "\n"); - if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || + if ((display->platform.ivybridge && port == PORT_A) || (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT; intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; @@ -457,8 +453,8 @@ intel_dp_link_down(struct intel_encoder *encoder, * We get CPU/PCH FIFO underruns on the other pipe when * doing the workaround. Sweep them under the rug. */ - intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); + intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); + intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); /* always enable with pattern 1 (as per spec) */ intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK); @@ -471,14 +467,14 @@ intel_dp_link_down(struct intel_encoder *encoder, intel_de_write(display, intel_dp->output_reg, intel_dp->DP); intel_de_posting_read(display, intel_dp->output_reg); - intel_wait_for_vblank_if_active(dev_priv, PIPE_A); - intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); + intel_wait_for_vblank_if_active(display, PIPE_A); + intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); + intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); } msleep(intel_dp->pps.panel_power_down_delay); - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + if (display->platform.valleyview || display->platform.cherryview) vlv_pps_port_disable(encoder, old_crtc_state); } @@ -681,7 +677,6 @@ static void intel_enable_dp(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); u32 dp_reg = intel_de_read(display, intel_dp->output_reg); intel_wakeref_t wakeref; @@ -690,7 +685,7 @@ static void intel_enable_dp(struct intel_atomic_state *state, return; with_intel_pps_lock(intel_dp, wakeref) { - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + if (display->platform.valleyview || display->platform.cherryview) vlv_pps_port_enable_unlocked(encoder, pipe_config); intel_dp_enable_port(intel_dp, pipe_config); @@ -700,13 +695,13 @@ static void intel_enable_dp(struct intel_atomic_state *state, intel_pps_vdd_off_unlocked(intel_dp, true); } - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + if (display->platform.valleyview || display->platform.cherryview) { unsigned int lane_mask = 0x0; - if (IS_CHERRYVIEW(dev_priv)) + if (display->platform.cherryview) lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); - vlv_wait_port_ready(display, dp_to_dig_port(intel_dp), lane_mask); + vlv_wait_port_ready(encoder, lane_mask); } intel_dp_set_power(intel_dp, DP_SET_POWER_D0); @@ -1263,7 +1258,6 @@ static void intel_dp_encoder_destroy(struct drm_encoder *encoder) static void intel_dp_encoder_reset(struct drm_encoder *encoder) { struct intel_display *display = to_intel_display(encoder->dev); - struct drm_i915_private *dev_priv = to_i915(encoder->dev); struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)); intel_dp->DP = intel_de_read(display, intel_dp->output_reg); @@ -1271,7 +1265,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder) intel_dp->reset_link_params = true; intel_dp_invalidate_source_oui(intel_dp); - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + if (display->platform.valleyview || display->platform.cherryview) vlv_pps_pipe_reset(intel_dp); intel_pps_encoder_reset(intel_dp); @@ -1282,17 +1276,17 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = { .destroy = intel_dp_encoder_destroy, }; -bool g4x_dp_init(struct drm_i915_private *dev_priv, +bool g4x_dp_init(struct intel_display *display, i915_reg_t output_reg, enum port port) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); const struct intel_bios_encoder_data *devdata; struct intel_digital_port *dig_port; struct intel_encoder *intel_encoder; struct drm_encoder *encoder; struct intel_connector *intel_connector; - if (!assert_port_valid(dev_priv, port)) + if (!assert_port_valid(display, port)) return false; devdata = intel_bios_encoder_data_lookup(display, port); @@ -1317,7 +1311,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, intel_encoder->devdata = devdata; - mutex_init(&dig_port->hdcp_mutex); + mutex_init(&dig_port->hdcp.mutex); if (drm_encoder_init(display->drm, &intel_encoder->base, &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, @@ -1336,14 +1330,14 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, intel_encoder->suspend = intel_dp_encoder_suspend; intel_encoder->suspend_complete = g4x_dp_suspend_complete; intel_encoder->shutdown = intel_dp_encoder_shutdown; - if (IS_CHERRYVIEW(dev_priv)) { + if (display->platform.cherryview) { intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; intel_encoder->pre_enable = chv_pre_enable_dp; intel_encoder->enable = vlv_enable_dp; intel_encoder->disable = vlv_disable_dp; intel_encoder->post_disable = chv_post_disable_dp; intel_encoder->post_pll_disable = chv_dp_post_pll_disable; - } else if (IS_VALLEYVIEW(dev_priv)) { + } else if (display->platform.valleyview) { intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; intel_encoder->pre_enable = vlv_pre_enable_dp; intel_encoder->enable = vlv_enable_dp; @@ -1358,24 +1352,24 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, intel_encoder->audio_enable = g4x_dp_audio_enable; intel_encoder->audio_disable = g4x_dp_audio_disable; - if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || + if ((display->platform.ivybridge && port == PORT_A) || (HAS_PCH_CPT(dev_priv) && port != PORT_A)) dig_port->dp.set_link_train = cpt_set_link_train; else dig_port->dp.set_link_train = g4x_set_link_train; - if (IS_CHERRYVIEW(dev_priv)) + if (display->platform.cherryview) intel_encoder->set_signal_levels = chv_set_signal_levels; - else if (IS_VALLEYVIEW(dev_priv)) + else if (display->platform.valleyview) intel_encoder->set_signal_levels = vlv_set_signal_levels; - else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) + else if (display->platform.ivybridge && port == PORT_A) intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels; - else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A) + else if (display->platform.sandybridge && port == PORT_A) intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels; else intel_encoder->set_signal_levels = g4x_set_signal_levels; - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || + if (display->platform.valleyview || display->platform.cherryview || (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) { dig_port->dp.preemph_max = intel_dp_preemph_max_3; dig_port->dp.voltage_max = intel_dp_voltage_max_3; @@ -1388,8 +1382,8 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, dig_port->max_lanes = 4; intel_encoder->type = INTEL_OUTPUT_DP; - intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); - if (IS_CHERRYVIEW(dev_priv)) { + intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); + if (display->platform.cherryview) { if (port == PORT_D) intel_encoder->pipe_mask = BIT(PIPE_C); else @@ -1399,7 +1393,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, } intel_encoder->cloneable = 0; intel_encoder->port = port; - intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); + intel_encoder->hpd_pin = intel_hpd_pin_default(port); dig_port->hpd_pulse = intel_dp_hpd_pulse; diff --git a/drivers/gpu/drm/i915/display/g4x_dp.h b/drivers/gpu/drm/i915/display/g4x_dp.h index 839a251dc069..0b28951b8365 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.h +++ b/drivers/gpu/drm/i915/display/g4x_dp.h @@ -12,30 +12,30 @@ enum pipe; enum port; -struct drm_i915_private; struct intel_crtc_state; +struct intel_display; struct intel_dp; struct intel_encoder; #ifdef I915 -const struct dpll *vlv_get_dpll(struct drm_i915_private *i915); -bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, +const struct dpll *vlv_get_dpll(struct intel_display *display); +bool g4x_dp_port_enabled(struct intel_display *display, i915_reg_t dp_reg, enum port port, enum pipe *pipe); -bool g4x_dp_init(struct drm_i915_private *dev_priv, +bool g4x_dp_init(struct intel_display *display, i915_reg_t output_reg, enum port port); #else -static inline const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) +static inline const struct dpll *vlv_get_dpll(struct intel_display *display) { return NULL; } -static inline bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, +static inline bool g4x_dp_port_enabled(struct intel_display *display, i915_reg_t dp_reg, int port, enum pipe *pipe) { return false; } -static inline bool g4x_dp_init(struct drm_i915_private *dev_priv, +static inline bool g4x_dp_init(struct intel_display *display, i915_reg_t output_reg, int port) { return false; diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c index 98e6a931042f..3dc2c59a3df0 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c @@ -27,8 +27,8 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(encoder); + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; @@ -54,31 +54,31 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder, if (HAS_PCH_CPT(dev_priv)) hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); - else if (IS_CHERRYVIEW(dev_priv)) + else if (display->platform.cherryview) hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); else hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); + intel_de_write(display, intel_hdmi->hdmi_reg, hdmi_val); + intel_de_posting_read(display, intel_hdmi->hdmi_reg); } static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); intel_wakeref_t wakeref; bool ret; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; - ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); + ret = intel_sdvo_port_enabled(display, intel_hdmi->hdmi_reg, pipe); - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } @@ -131,6 +131,7 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -141,7 +142,7 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder, return -EINVAL; } - if (IS_G4X(i915)) + if (display->platform.g4x) crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc); else crtc_state->has_hdmi_sink = @@ -153,15 +154,15 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder, static void intel_hdmi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { + struct intel_display *display = to_intel_display(encoder); + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); u32 tmp, flags = 0; int dotclock; pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); - tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); + tmp = intel_de_read(display, intel_hdmi->hdmi_reg); if (tmp & SDVO_HSYNC_ACTIVE_HIGH) flags |= DRM_MODE_FLAG_PHSYNC; @@ -221,33 +222,32 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, static void g4x_hdmi_enable_port(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(encoder); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); u32 temp; - temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); + temp = intel_de_read(display, intel_hdmi->hdmi_reg); temp |= SDVO_ENABLE; - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); + intel_de_write(display, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(display, intel_hdmi->hdmi_reg); } static void g4x_hdmi_audio_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); if (!crtc_state->has_audio) return; - drm_WARN_ON(&i915->drm, !crtc_state->has_hdmi_sink); + drm_WARN_ON(display->drm, !crtc_state->has_hdmi_sink); /* Enable audio presence detect */ - intel_de_rmw(i915, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE); + intel_de_rmw(display, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE); intel_audio_codec_enable(encoder, crtc_state, conn_state); } @@ -256,7 +256,7 @@ static void g4x_hdmi_audio_disable(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); if (!old_crtc_state->has_audio) @@ -265,7 +265,7 @@ static void g4x_hdmi_audio_disable(struct intel_encoder *encoder, intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); /* Disable audio presence detect */ - intel_de_rmw(i915, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0); + intel_de_rmw(display, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0); } static void g4x_enable_hdmi(struct intel_atomic_state *state, @@ -281,12 +281,11 @@ static void ibx_enable_hdmi(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(encoder); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); u32 temp; - temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); + temp = intel_de_read(display, intel_hdmi->hdmi_reg); temp |= SDVO_ENABLE; @@ -294,10 +293,10 @@ static void ibx_enable_hdmi(struct intel_atomic_state *state, * HW workaround, need to write this twice for issue * that may result in first write getting masked. */ - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); + intel_de_write(display, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(display, intel_hdmi->hdmi_reg); + intel_de_write(display, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(display, intel_hdmi->hdmi_reg); /* * HW workaround, need to toggle enable bit off and on @@ -308,18 +307,18 @@ static void ibx_enable_hdmi(struct intel_atomic_state *state, */ if (pipe_config->pipe_bpp > 24 && pipe_config->pixel_multiplier > 1) { - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, + intel_de_write(display, intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); + intel_de_posting_read(display, intel_hdmi->hdmi_reg); /* * HW workaround, need to write this twice for issue * that may result in first write getting masked. */ - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); + intel_de_write(display, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(display, intel_hdmi->hdmi_reg); + intel_de_write(display, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(display, intel_hdmi->hdmi_reg); } } @@ -328,14 +327,13 @@ static void cpt_enable_hdmi(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); enum pipe pipe = crtc->pipe; u32 temp; - temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); + temp = intel_de_read(display, intel_hdmi->hdmi_reg); temp |= SDVO_ENABLE; @@ -350,24 +348,24 @@ static void cpt_enable_hdmi(struct intel_atomic_state *state, */ if (pipe_config->pipe_bpp > 24) { - intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe), + intel_de_rmw(display, TRANS_CHICKEN1(pipe), 0, TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); temp &= ~SDVO_COLOR_FORMAT_MASK; temp |= SDVO_COLOR_FORMAT_8bpc; } - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); + intel_de_write(display, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(display, intel_hdmi->hdmi_reg); if (pipe_config->pipe_bpp > 24) { temp &= ~SDVO_COLOR_FORMAT_MASK; temp |= HDMI_COLOR_FORMAT_12bpc; - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); + intel_de_write(display, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(display, intel_hdmi->hdmi_reg); - intel_de_rmw(dev_priv, TRANS_CHICKEN1(pipe), + intel_de_rmw(display, TRANS_CHICKEN1(pipe), TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE, 0); } } @@ -384,19 +382,19 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(encoder); + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); struct intel_digital_port *dig_port = hdmi_to_dig_port(intel_hdmi); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); u32 temp; - temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); + temp = intel_de_read(display, intel_hdmi->hdmi_reg); temp &= ~SDVO_ENABLE; - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); + intel_de_write(display, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(display, intel_hdmi->hdmi_reg); /* * HW workaround for IBX, we need to move the port @@ -408,8 +406,8 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, * We get CPU/PCH FIFO underruns on the other pipe when * doing the workaround. Sweep them under the rug. */ - intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); + intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); + intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); temp &= ~SDVO_PIPE_SEL_MASK; temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); @@ -417,18 +415,18 @@ static void intel_disable_hdmi(struct intel_atomic_state *state, * HW workaround, need to write this twice for issue * that may result in first write getting masked. */ - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); + intel_de_write(display, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(display, intel_hdmi->hdmi_reg); + intel_de_write(display, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(display, intel_hdmi->hdmi_reg); temp &= ~SDVO_ENABLE; - intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); - intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); + intel_de_write(display, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(display, intel_hdmi->hdmi_reg); - intel_wait_for_vblank_if_active(dev_priv, PIPE_A); - intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); + intel_wait_for_vblank_if_active(display, PIPE_A); + intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); + intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); } dig_port->set_infoframes(encoder, @@ -481,7 +479,6 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { - struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); vlv_phy_pre_encoder_enable(encoder, pipe_config); @@ -497,7 +494,7 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, g4x_hdmi_enable_port(encoder, pipe_config); - vlv_wait_port_ready(display, dig_port, 0x0); + vlv_wait_port_ready(encoder, 0x0); } static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state, @@ -542,8 +539,8 @@ static void chv_hdmi_post_disable(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(encoder); + struct drm_i915_private *dev_priv = to_i915(display->drm); vlv_dpio_get(dev_priv); @@ -558,7 +555,6 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { - struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); chv_phy_pre_encoder_enable(encoder, pipe_config); @@ -573,7 +569,7 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state, g4x_hdmi_enable_port(encoder, pipe_config); - vlv_wait_port_ready(display, dig_port, 0x0); + vlv_wait_port_ready(encoder, 0x0); /* Second common lane will stay alive on its own now */ chv_phy_release_cl2_override(encoder); @@ -612,7 +608,7 @@ intel_hdmi_hotplug(struct intel_encoder *encoder, int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state) { - struct drm_i915_private *i915 = to_i915(state->dev); + struct intel_display *display = to_intel_display(connector->dev); struct drm_connector_list_iter conn_iter; struct drm_connector *conn; int ret; @@ -621,7 +617,7 @@ int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, if (ret) return ret; - if (!IS_G4X(i915)) + if (!display->platform.g4x) return 0; if (!intel_connector_needs_modeset(to_intel_atomic_state(state), connector)) @@ -635,7 +631,7 @@ int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, * * See also g4x_compute_has_hdmi_sink(). */ - drm_connector_list_iter_begin(&i915->drm, &conn_iter); + drm_connector_list_iter_begin(display->drm, &conn_iter); drm_for_each_connector_iter(conn, &conn_iter) { struct drm_connector_state *conn_state; struct drm_crtc_state *crtc_state; @@ -644,7 +640,7 @@ int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, if (!connector_is_hdmi(conn)) continue; - drm_dbg_kms(&i915->drm, "Adding [CONNECTOR:%d:%s]\n", + drm_dbg_kms(display->drm, "Adding [CONNECTOR:%d:%s]\n", conn->base.id, conn->name); conn_state = drm_atomic_get_connector_state(state, conn); @@ -669,40 +665,40 @@ int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, return ret; } -static bool is_hdmi_port_valid(struct drm_i915_private *i915, enum port port) +static bool is_hdmi_port_valid(struct intel_display *display, enum port port) { - if (IS_G4X(i915) || IS_VALLEYVIEW(i915)) + if (display->platform.g4x || display->platform.valleyview) return port == PORT_B || port == PORT_C; else return port == PORT_B || port == PORT_C || port == PORT_D; } -static bool assert_hdmi_port_valid(struct drm_i915_private *i915, enum port port) +static bool assert_hdmi_port_valid(struct intel_display *display, enum port port) { - return !drm_WARN(&i915->drm, !is_hdmi_port_valid(i915, port), + return !drm_WARN(display->drm, !is_hdmi_port_valid(display, port), "Platform does not support HDMI %c\n", port_name(port)); } -bool g4x_hdmi_init(struct drm_i915_private *dev_priv, +bool g4x_hdmi_init(struct intel_display *display, i915_reg_t hdmi_reg, enum port port) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); const struct intel_bios_encoder_data *devdata; struct intel_digital_port *dig_port; struct intel_encoder *intel_encoder; struct intel_connector *intel_connector; - if (!assert_port_valid(dev_priv, port)) + if (!assert_port_valid(display, port)) return false; - if (!assert_hdmi_port_valid(dev_priv, port)) + if (!assert_hdmi_port_valid(display, port)) return false; devdata = intel_bios_encoder_data_lookup(display, port); /* FIXME bail? */ if (!devdata) - drm_dbg_kms(&dev_priv->drm, "No VBT child device for HDMI-%c\n", + drm_dbg_kms(display->drm, "No VBT child device for HDMI-%c\n", port_name(port)); dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL); @@ -719,9 +715,9 @@ bool g4x_hdmi_init(struct drm_i915_private *dev_priv, intel_encoder->devdata = devdata; - mutex_init(&dig_port->hdcp_mutex); + mutex_init(&dig_port->hdcp.mutex); - if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, + if (drm_encoder_init(display->drm, &intel_encoder->base, &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port))) goto err_encoder_init; @@ -736,13 +732,13 @@ bool g4x_hdmi_init(struct drm_i915_private *dev_priv, } intel_encoder->get_hw_state = intel_hdmi_get_hw_state; intel_encoder->get_config = intel_hdmi_get_config; - if (IS_CHERRYVIEW(dev_priv)) { + if (display->platform.cherryview) { intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; intel_encoder->pre_enable = chv_hdmi_pre_enable; intel_encoder->enable = vlv_enable_hdmi; intel_encoder->post_disable = chv_hdmi_post_disable; intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; - } else if (IS_VALLEYVIEW(dev_priv)) { + } else if (display->platform.valleyview) { intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; intel_encoder->pre_enable = vlv_hdmi_pre_enable; intel_encoder->enable = vlv_enable_hdmi; @@ -761,9 +757,9 @@ bool g4x_hdmi_init(struct drm_i915_private *dev_priv, intel_encoder->shutdown = intel_hdmi_encoder_shutdown; intel_encoder->type = INTEL_OUTPUT_HDMI; - intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); + intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); intel_encoder->port = port; - if (IS_CHERRYVIEW(dev_priv)) { + if (display->platform.cherryview) { if (port == PORT_D) intel_encoder->pipe_mask = BIT(PIPE_C); else @@ -772,13 +768,13 @@ bool g4x_hdmi_init(struct drm_i915_private *dev_priv, intel_encoder->pipe_mask = ~0; } intel_encoder->cloneable = BIT(INTEL_OUTPUT_ANALOG); - intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); + intel_encoder->hpd_pin = intel_hpd_pin_default(port); /* * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems * to work on real hardware. And since g4x can send infoframes to * only one port anyway, nothing is lost by allowing it. */ - if (IS_G4X(dev_priv)) + if (display->platform.g4x) intel_encoder->cloneable |= BIT(INTEL_OUTPUT_HDMI); dig_port->hdmi.hdmi_reg = hdmi_reg; diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.h b/drivers/gpu/drm/i915/display/g4x_hdmi.h index a52e8986ec7a..039d2bdba06c 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.h +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.h @@ -13,15 +13,15 @@ enum port; struct drm_atomic_state; struct drm_connector; -struct drm_i915_private; +struct intel_display; #ifdef I915 -bool g4x_hdmi_init(struct drm_i915_private *dev_priv, +bool g4x_hdmi_init(struct intel_display *display, i915_reg_t hdmi_reg, enum port port); int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state); #else -static inline bool g4x_hdmi_init(struct drm_i915_private *dev_priv, +static inline bool g4x_hdmi_init(struct intel_display *display, i915_reg_t hdmi_reg, int port) { return false; diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c index d02c328bf902..674a0e5f0858 100644 --- a/drivers/gpu/drm/i915/display/hsw_ips.c +++ b/drivers/gpu/drm/i915/display/hsw_ips.c @@ -36,7 +36,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state) if (display->ips.false_color) val |= IPS_FALSE_COLOR; - if (IS_BROADWELL(i915)) { + if (display->platform.broadwell) { drm_WARN_ON(display->drm, snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, val | IPS_PCODE_CONTROL)); @@ -71,7 +71,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state) if (!crtc_state->ips_enabled) return need_vblank_wait; - if (IS_BROADWELL(i915)) { + if (display->platform.broadwell) { drm_WARN_ON(display->drm, snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0)); /* @@ -96,7 +96,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state) static bool hsw_ips_need_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); const struct intel_crtc_state *new_crtc_state = @@ -114,7 +114,7 @@ static bool hsw_ips_need_disable(struct intel_atomic_state *state, * * Disable IPS before we program the LUT. */ - if (IS_HASWELL(i915) && + if (display->platform.haswell && intel_crtc_needs_color_update(new_crtc_state) && new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) return true; @@ -137,7 +137,7 @@ bool hsw_ips_pre_update(struct intel_atomic_state *state, static bool hsw_ips_need_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); const struct intel_crtc_state *new_crtc_state = @@ -155,7 +155,7 @@ static bool hsw_ips_need_enable(struct intel_atomic_state *state, * * Re-enable IPS after the LUT has been programmed. */ - if (IS_HASWELL(i915) && + if (display->platform.haswell && intel_crtc_needs_color_update(new_crtc_state) && new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) return true; @@ -194,7 +194,6 @@ static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); /* IPS only exists on ULT machines and is tied to pipe A. */ if (!hsw_crtc_supports_ips(crtc)) @@ -213,7 +212,7 @@ static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state * * Should measure whether using a lower cdclk w/o IPS */ - if (IS_BROADWELL(i915) && + if (display->platform.broadwell && crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100) return false; @@ -222,9 +221,9 @@ static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); - if (!IS_BROADWELL(i915)) + if (!display->platform.broadwell) return 0; if (!hsw_crtc_state_ips_capable(crtc_state)) @@ -237,7 +236,7 @@ int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state) int hsw_ips_compute_config(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); @@ -259,7 +258,7 @@ int hsw_ips_compute_config(struct intel_atomic_state *state, if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))) return 0; - if (IS_BROADWELL(i915)) { + if (display->platform.broadwell) { const struct intel_cdclk_state *cdclk_state; cdclk_state = intel_atomic_get_cdclk_state(state); @@ -280,12 +279,11 @@ void hsw_ips_get_config(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); if (!hsw_crtc_supports_ips(crtc)) return; - if (IS_HASWELL(i915)) { + if (display->platform.haswell) { crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE; } else { /* diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 48e657a80a16..013295f66d56 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -109,42 +109,42 @@ static bool i965_plane_format_mod_supported(struct drm_plane *_plane, } } -static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, +static bool i9xx_plane_has_fbc(struct intel_display *display, enum i9xx_plane_id i9xx_plane) { - if (!HAS_FBC(dev_priv)) + if (!HAS_FBC(display)) return false; - if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + if (display->platform.broadwell || display->platform.haswell) return i9xx_plane == PLANE_A; /* tied to pipe A */ - else if (IS_IVYBRIDGE(dev_priv)) + else if (display->platform.ivybridge) return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || i9xx_plane == PLANE_C; - else if (DISPLAY_VER(dev_priv) >= 4) + else if (DISPLAY_VER(display) >= 4) return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; else return i9xx_plane == PLANE_A; } -static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv, +static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display, enum i9xx_plane_id i9xx_plane) { - if (i9xx_plane_has_fbc(dev_priv, i9xx_plane)) - return dev_priv->display.fbc[INTEL_FBC_A]; + if (i9xx_plane_has_fbc(display, i9xx_plane)) + return display->fbc[INTEL_FBC_A]; else return NULL; } static bool i9xx_plane_has_windowing(struct intel_plane *plane) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - if (IS_CHERRYVIEW(dev_priv)) + if (display->platform.cherryview) return i9xx_plane == PLANE_B; - else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) + else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) return false; - else if (DISPLAY_VER(dev_priv) == 4) + else if (DISPLAY_VER(display) == 4) return i9xx_plane == PLANE_C; else return i9xx_plane == PLANE_B || @@ -154,16 +154,15 @@ static bool i9xx_plane_has_windowing(struct intel_plane *plane) static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; u32 dspcntr; dspcntr = DISP_ENABLE; - if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) || - IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) + if (display->platform.g4x || display->platform.ironlake || + display->platform.sandybridge || display->platform.ivybridge) dspcntr |= DISP_TRICKLE_FEED_DISABLE; switch (fb->format->format) { @@ -211,7 +210,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, return 0; } - if (DISPLAY_VER(dev_priv) >= 4 && + if (DISPLAY_VER(display) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) dspcntr |= DISP_TILED; @@ -226,8 +225,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, int i9xx_check_plane_surface(struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; int src_x, src_y, src_w; u32 offset; @@ -245,12 +244,16 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) src_y = plane_state->uapi.src.y1 >> 16; /* Undocumented hardware limit on i965/g4x/vlv/chv */ - if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048) + if (HAS_GMCH(display) && fb->format->cpp[0] == 8 && src_w > 2048) { + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] plane too wide (%d) for 64bpp\n", + plane->base.base.id, plane->base.name, src_w); return -EINVAL; + } intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) offset = intel_plane_compute_aligned_offset(&src_x, &src_y, plane_state, 0); else @@ -267,14 +270,15 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) * Linear surfaces seem to work just fine, even on hsw/bdw * despite them not using the linear offset anymore. */ - if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { + if (DISPLAY_VER(display) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { unsigned int alignment = plane->min_alignment(plane, fb, 0); int cpp = fb->format->cpp[0]; while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) { if (offset == 0) { - drm_dbg_kms(&dev_priv->drm, - "Unable to find suitable display surface offset due to X-tiling\n"); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] unable to find suitable display surface offset due to X-tiling\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -291,7 +295,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) src_x << 16, src_y << 16); /* HSW/BDW do this automagically in hardware */ - if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { + if (!display->platform.haswell && !display->platform.broadwell) { unsigned int rotation = plane_state->hw.rotation; int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; @@ -304,11 +308,11 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) } } - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - drm_WARN_ON(&dev_priv->drm, src_x > 8191 || src_y > 4095); - } else if (DISPLAY_VER(dev_priv) >= 4 && + if (display->platform.haswell || display->platform.broadwell) { + drm_WARN_ON(display->drm, src_x > 8191 || src_y > 4095); + } else if (DISPLAY_VER(display) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { - drm_WARN_ON(&dev_priv->drm, src_x > 4095 || src_y > 4095); + drm_WARN_ON(display->drm, src_x > 4095 || src_y > 4095); } plane_state->view.color_plane[0].offset = offset; @@ -354,8 +358,8 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state, static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dspcntr = 0; if (crtc_state->gamma_enable) @@ -364,7 +368,7 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) if (crtc_state->csc_enable) dspcntr |= DISP_PIPE_CSC_ENABLE; - if (DISPLAY_VER(dev_priv) < 5) + if (DISPLAY_VER(display) < 5) dspcntr |= DISP_PIPE_SEL(crtc->pipe); return dspcntr; @@ -422,13 +426,13 @@ static void i9xx_plane_update_noarm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - intel_de_write_fw(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPSTRIDE(display, i9xx_plane), plane_state->view.color_plane[0].mapping_stride); - if (DISPLAY_VER(dev_priv) < 4) { + if (DISPLAY_VER(display) < 4) { int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; int crtc_w = drm_rect_width(&plane_state->uapi.dst); @@ -439,9 +443,9 @@ static void i9xx_plane_update_noarm(struct intel_dsb *dsb, * generator but let's assume we still need to * program whatever is there. */ - intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPPOS(display, i9xx_plane), DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); - intel_de_write_fw(dev_priv, DSPSIZE(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPSIZE(display, i9xx_plane), DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); } } @@ -451,7 +455,7 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; int x = plane_state->view.color_plane[0].x; int y = plane_state->view.color_plane[0].y; @@ -466,32 +470,32 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) dspaddr_offset = plane_state->view.color_plane[0].offset; else dspaddr_offset = linear_offset; - if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { + if (display->platform.cherryview && i9xx_plane == PLANE_B) { int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; int crtc_w = drm_rect_width(&plane_state->uapi.dst); int crtc_h = drm_rect_height(&plane_state->uapi.dst); - intel_de_write_fw(dev_priv, PRIMPOS(dev_priv, i9xx_plane), + intel_de_write_fw(display, PRIMPOS(display, i9xx_plane), PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); - intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane), + intel_de_write_fw(display, PRIMSIZE(display, i9xx_plane), PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); - intel_de_write_fw(dev_priv, - PRIMCNSTALPHA(dev_priv, i9xx_plane), 0); + intel_de_write_fw(display, + PRIMCNSTALPHA(display, i9xx_plane), 0); } - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - intel_de_write_fw(dev_priv, DSPOFFSET(dev_priv, i9xx_plane), + if (display->platform.haswell || display->platform.broadwell) { + intel_de_write_fw(display, DSPOFFSET(display, i9xx_plane), DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); - } else if (DISPLAY_VER(dev_priv) >= 4) { - intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane), + } else if (DISPLAY_VER(display) >= 4) { + intel_de_write_fw(display, DSPLINOFF(display, i9xx_plane), linear_offset); - intel_de_write_fw(dev_priv, DSPTILEOFF(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPTILEOFF(display, i9xx_plane), DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); } @@ -500,13 +504,13 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); + intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); - if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), + if (DISPLAY_VER(display) >= 4) + intel_de_write_fw(display, DSPSURF(display, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); else - intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPADDR(display, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } @@ -529,7 +533,7 @@ static void i9xx_plane_disable_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; u32 dspcntr; @@ -545,12 +549,46 @@ static void i9xx_plane_disable_arm(struct intel_dsb *dsb, */ dspcntr = i9xx_plane_ctl_crtc(crtc_state); - intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); + intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); - if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), 0); + if (DISPLAY_VER(display) >= 4) + intel_de_write_fw(display, DSPSURF(display, i9xx_plane), 0); else - intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0); + intel_de_write_fw(display, DSPADDR(display, i9xx_plane), 0); +} + +static void g4x_primary_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; + + error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); + error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane)); + error->surflive = intel_de_read(display, DSPSURFLIVE(display, i9xx_plane)); +} + +static void i965_plane_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; + + error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); + error->surf = intel_de_read(display, DSPSURF(display, i9xx_plane)); +} + +static void i8xx_plane_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; + + error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); + error->surf = intel_de_read(display, DSPADDR(display, i9xx_plane)); } static void @@ -560,7 +598,7 @@ g4x_primary_async_flip(struct intel_dsb *dsb, const struct intel_plane_state *plane_state, bool async_flip) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); u32 dspaddr_offset = plane_state->view.color_plane[0].offset; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; @@ -568,9 +606,9 @@ g4x_primary_async_flip(struct intel_dsb *dsb, if (async_flip) dspcntr |= DISP_ASYNC_FLIP; - intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); + intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); - intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPSURF(display, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } @@ -581,11 +619,11 @@ vlv_primary_async_flip(struct intel_dsb *dsb, const struct intel_plane_state *plane_state, bool async_flip) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); u32 dspaddr_offset = plane_state->view.color_plane[0].offset; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - intel_de_write_fw(dev_priv, DSPADDR_VLV(dev_priv, i9xx_plane), + intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } @@ -673,10 +711,15 @@ vlv_primary_disable_flip_done(struct intel_plane *plane) spin_unlock_irq(&i915->irq_lock); } +static bool i9xx_plane_can_async_flip(u64 modifier) +{ + return modifier == I915_FORMAT_MOD_X_TILED; +} + static bool i9xx_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; intel_wakeref_t wakeref; @@ -689,20 +732,20 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, * display power wells. */ power_domain = POWER_DOMAIN_PIPE(plane->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; - val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); + val = intel_de_read(display, DSPCNTR(display, i9xx_plane)); ret = val & DISP_ENABLE; - if (DISPLAY_VER(dev_priv) >= 5) + if (DISPLAY_VER(display) >= 5) *pipe = plane->pipe; else *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val); - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } @@ -771,16 +814,21 @@ i8xx_plane_max_stride(struct intel_plane *plane, return 8 * 1024; } -static unsigned int vlv_primary_min_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane) +unsigned int vlv_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int color_plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); + + if (intel_plane_can_async_flip(plane, fb->modifier)) + return 256 * 1024; + + /* FIXME undocumented so not sure what's actually needed */ + if (intel_scanout_needs_vtd_wa(display)) + return 256 * 1024; switch (fb->modifier) { case I915_FORMAT_MOD_X_TILED: - if (HAS_ASYNC_FLIPS(i915)) - return 256 * 1024; return 4 * 1024; case DRM_FORMAT_MOD_LINEAR: return 128 * 1024; @@ -794,13 +842,16 @@ static unsigned int g4x_primary_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); + + if (intel_plane_can_async_flip(plane, fb->modifier)) + return 256 * 1024; + + if (intel_scanout_needs_vtd_wa(display)) + return 256 * 1024; switch (fb->modifier) { case I915_FORMAT_MOD_X_TILED: - if (HAS_ASYNC_FLIPS(i915)) - return 256 * 1024; - return 4 * 1024; case DRM_FORMAT_MOD_LINEAR: return 4 * 1024; default: @@ -850,7 +901,7 @@ static const struct drm_plane_funcs i8xx_plane_funcs = { }; struct intel_plane * -intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) +intel_primary_plane_create(struct intel_display *display, enum pipe pipe) { struct intel_plane *plane; const struct drm_plane_funcs *plane_funcs; @@ -869,20 +920,20 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS * port is hooked to pipe B. Hence we want plane A feeding pipe B. */ - if (HAS_FBC(dev_priv) && DISPLAY_VER(dev_priv) < 4 && - INTEL_NUM_PIPES(dev_priv) == 2) + if (HAS_FBC(display) && DISPLAY_VER(display) < 4 && + INTEL_NUM_PIPES(display) == 2) plane->i9xx_plane = (enum i9xx_plane_id) !pipe; else plane->i9xx_plane = (enum i9xx_plane_id) pipe; plane->id = PLANE_PRIMARY; plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); - intel_fbc_add_plane(i9xx_plane_fbc(dev_priv, plane->i9xx_plane), plane); + intel_fbc_add_plane(i9xx_plane_fbc(display, plane->i9xx_plane), plane); - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + if (display->platform.valleyview || display->platform.cherryview) { formats = vlv_primary_formats; num_formats = ARRAY_SIZE(vlv_primary_formats); - } else if (DISPLAY_VER(dev_priv) >= 4) { + } else if (DISPLAY_VER(display) >= 4) { /* * WaFP16GammaEnabling:ivb * "Workaround : When using the 64-bit format, the plane @@ -896,7 +947,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) * planes, so we choose not to expose fp16 on IVB primary * planes. HSW primary planes no longer have this problem. */ - if (IS_IVYBRIDGE(dev_priv)) { + if (display->platform.ivybridge) { formats = ivb_primary_formats; num_formats = ARRAY_SIZE(ivb_primary_formats); } else { @@ -908,44 +959,48 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) num_formats = ARRAY_SIZE(i8xx_primary_formats); } - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) plane_funcs = &i965_plane_funcs; else plane_funcs = &i8xx_plane_funcs; - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + if (display->platform.valleyview || display->platform.cherryview) plane->min_cdclk = vlv_plane_min_cdclk; - else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + else if (display->platform.broadwell || display->platform.haswell) plane->min_cdclk = hsw_plane_min_cdclk; - else if (IS_IVYBRIDGE(dev_priv)) + else if (display->platform.ivybridge) plane->min_cdclk = ivb_plane_min_cdclk; else plane->min_cdclk = i9xx_plane_min_cdclk; - if (HAS_GMCH(dev_priv)) { - if (DISPLAY_VER(dev_priv) >= 4) + if (HAS_GMCH(display)) { + if (DISPLAY_VER(display) >= 4) plane->max_stride = i965_plane_max_stride; - else if (DISPLAY_VER(dev_priv) == 3) + else if (DISPLAY_VER(display) == 3) plane->max_stride = i915_plane_max_stride; else plane->max_stride = i8xx_plane_max_stride; } else { - if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + if (display->platform.broadwell || display->platform.haswell) plane->max_stride = hsw_primary_max_stride; else plane->max_stride = ilk_primary_max_stride; } - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - plane->min_alignment = vlv_primary_min_alignment; - else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) + if (display->platform.valleyview || display->platform.cherryview) + plane->min_alignment = vlv_plane_min_alignment; + else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) plane->min_alignment = g4x_primary_min_alignment; - else if (DISPLAY_VER(dev_priv) == 4) + else if (DISPLAY_VER(display) == 4) plane->min_alignment = i965_plane_min_alignment; else plane->min_alignment = i9xx_plane_min_alignment; - if (IS_I830(dev_priv) || IS_I845G(dev_priv)) { + /* FIXME undocumented for VLV/CHV so not sure what's actually needed */ + if (intel_scanout_needs_vtd_wa(display)) + plane->vtd_guard = 128; + + if (display->platform.i830 || display->platform.i845g) { plane->update_arm = i830_plane_update_arm; } else { plane->update_noarm = i9xx_plane_update_noarm; @@ -955,36 +1010,49 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->get_hw_state = i9xx_plane_get_hw_state; plane->check_plane = i9xx_plane_check; - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - plane->async_flip = vlv_primary_async_flip; - plane->enable_flip_done = vlv_primary_enable_flip_done; - plane->disable_flip_done = vlv_primary_disable_flip_done; - } else if (IS_BROADWELL(dev_priv)) { - plane->need_async_flip_toggle_wa = true; - plane->async_flip = g4x_primary_async_flip; - plane->enable_flip_done = bdw_primary_enable_flip_done; - plane->disable_flip_done = bdw_primary_disable_flip_done; - } else if (DISPLAY_VER(dev_priv) >= 7) { - plane->async_flip = g4x_primary_async_flip; - plane->enable_flip_done = ivb_primary_enable_flip_done; - plane->disable_flip_done = ivb_primary_disable_flip_done; - } else if (DISPLAY_VER(dev_priv) >= 5) { - plane->async_flip = g4x_primary_async_flip; - plane->enable_flip_done = ilk_primary_enable_flip_done; - plane->disable_flip_done = ilk_primary_disable_flip_done; + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) + plane->capture_error = g4x_primary_capture_error; + else if (DISPLAY_VER(display) >= 4) + plane->capture_error = i965_plane_capture_error; + else + plane->capture_error = i8xx_plane_capture_error; + + if (HAS_ASYNC_FLIPS(display)) { + if (display->platform.valleyview || display->platform.cherryview) { + plane->async_flip = vlv_primary_async_flip; + plane->enable_flip_done = vlv_primary_enable_flip_done; + plane->disable_flip_done = vlv_primary_disable_flip_done; + plane->can_async_flip = i9xx_plane_can_async_flip; + } else if (display->platform.broadwell) { + plane->need_async_flip_toggle_wa = true; + plane->async_flip = g4x_primary_async_flip; + plane->enable_flip_done = bdw_primary_enable_flip_done; + plane->disable_flip_done = bdw_primary_disable_flip_done; + plane->can_async_flip = i9xx_plane_can_async_flip; + } else if (DISPLAY_VER(display) >= 7) { + plane->async_flip = g4x_primary_async_flip; + plane->enable_flip_done = ivb_primary_enable_flip_done; + plane->disable_flip_done = ivb_primary_disable_flip_done; + plane->can_async_flip = i9xx_plane_can_async_flip; + } else if (DISPLAY_VER(display) >= 5) { + plane->async_flip = g4x_primary_async_flip; + plane->enable_flip_done = ilk_primary_enable_flip_done; + plane->disable_flip_done = ilk_primary_disable_flip_done; + plane->can_async_flip = i9xx_plane_can_async_flip; + } } - modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); + modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X); - if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) - ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) + ret = drm_universal_plane_init(display->drm, &plane->base, 0, plane_funcs, formats, num_formats, modifiers, DRM_PLANE_TYPE_PRIMARY, "primary %c", pipe_name(pipe)); else - ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, + ret = drm_universal_plane_init(display->drm, &plane->base, 0, plane_funcs, formats, num_formats, modifiers, @@ -997,18 +1065,18 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) if (ret) goto fail; - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { + if (display->platform.cherryview && pipe == PIPE_B) { supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X; - } else if (DISPLAY_VER(dev_priv) >= 4) { + } else if (DISPLAY_VER(display) >= 4) { supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; } else { supported_rotations = DRM_MODE_ROTATE_0; } - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, supported_rotations); @@ -1063,8 +1131,7 @@ void i9xx_get_initial_plane_config(struct intel_crtc *crtc, struct intel_initial_plane_config *plane_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(crtc); struct intel_plane *plane = to_intel_plane(crtc->base.primary); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; enum pipe pipe; @@ -1077,21 +1144,21 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, if (!plane->get_hw_state(plane, &pipe)) return; - drm_WARN_ON(dev, pipe != crtc->pipe); + drm_WARN_ON(display->drm, pipe != crtc->pipe); intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); if (!intel_fb) { - drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); + drm_dbg_kms(display->drm, "failed to alloc fb\n"); return; } fb = &intel_fb->base; - fb->dev = dev; + fb->dev = display->drm; - val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); + val = intel_de_read(display, DSPCNTR(display, i9xx_plane)); - if (DISPLAY_VER(dev_priv) >= 4) { + if (DISPLAY_VER(display) >= 4) { if (val & DISP_TILED) { plane_config->tiling = I915_TILING_X; fb->modifier = I915_FORMAT_MOD_X_TILED; @@ -1101,50 +1168,51 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, plane_config->rotation = DRM_MODE_ROTATE_180; } - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && - val & DISP_MIRROR) + if (display->platform.cherryview && + pipe == PIPE_B && val & DISP_MIRROR) plane_config->rotation |= DRM_MODE_REFLECT_X; pixel_format = val & DISP_FORMAT_MASK; fourcc = i9xx_format_to_fourcc(pixel_format); fb->format = drm_format_info(fourcc); - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - offset = intel_de_read(dev_priv, - DSPOFFSET(dev_priv, i9xx_plane)); - base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK; - } else if (DISPLAY_VER(dev_priv) >= 4) { + if (display->platform.haswell || display->platform.broadwell) { + offset = intel_de_read(display, + DSPOFFSET(display, i9xx_plane)); + base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK; + } else if (DISPLAY_VER(display) >= 4) { if (plane_config->tiling) - offset = intel_de_read(dev_priv, - DSPTILEOFF(dev_priv, i9xx_plane)); + offset = intel_de_read(display, + DSPTILEOFF(display, i9xx_plane)); else - offset = intel_de_read(dev_priv, - DSPLINOFF(dev_priv, i9xx_plane)); - base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK; + offset = intel_de_read(display, + DSPLINOFF(display, i9xx_plane)); + base = intel_de_read(display, DSPSURF(display, i9xx_plane)) & DISP_ADDR_MASK; } else { offset = 0; - base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane)); + base = intel_de_read(display, DSPADDR(display, i9xx_plane)); } plane_config->base = base; - drm_WARN_ON(&dev_priv->drm, offset != 0); + drm_WARN_ON(display->drm, offset != 0); - val = intel_de_read(dev_priv, PIPESRC(dev_priv, pipe)); + val = intel_de_read(display, PIPESRC(display, pipe)); fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1; fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1; - val = intel_de_read(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane)); + val = intel_de_read(display, DSPSTRIDE(display, i9xx_plane)); fb->pitches[0] = val & 0xffffffc0; aligned_height = intel_fb_align_height(fb, 0, fb->height); plane_config->size = fb->pitches[0] * aligned_height; - drm_dbg_kms(&dev_priv->drm, - "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", - crtc->base.name, plane->base.name, fb->width, fb->height, - fb->format->cpp[0] * 8, base, fb->pitches[0], - plane_config->size); + drm_dbg_kms(display->drm, + "[CRTC:%d:%s][PLANE:%d:%s] with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", + crtc->base.base.id, crtc->base.name, + plane->base.base.id, plane->base.name, + fb->width, fb->height, fb->format->cpp[0] * 8, + base, fb->pitches[0], plane_config->size); plane_config->fb = intel_fb; } @@ -1152,7 +1220,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, const struct intel_initial_plane_config *plane_config) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_plane *plane = to_intel_plane(crtc->base.primary); const struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); @@ -1171,10 +1239,10 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, if (plane_config->base == base) return false; - if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write(dev_priv, DSPSURF(dev_priv, i9xx_plane), base); + if (DISPLAY_VER(display) >= 4) + intel_de_write(display, DSPSURF(display, i9xx_plane), base); else - intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base); + intel_de_write(display, DSPADDR(display, i9xx_plane), base); return true; } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.h b/drivers/gpu/drm/i915/display/i9xx_plane.h index 0ca12d1e6839..d90546d60855 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane.h @@ -9,8 +9,9 @@ #include <linux/types.h> enum pipe; -struct drm_i915_private; +struct drm_framebuffer; struct intel_crtc; +struct intel_display; struct intel_initial_plane_config; struct intel_plane; struct intel_plane_state; @@ -19,10 +20,13 @@ struct intel_plane_state; unsigned int i965_plane_max_stride(struct intel_plane *plane, u32 pixel_format, u64 modifier, unsigned int rotation); +unsigned int vlv_plane_min_alignment(struct intel_plane *plane, + const struct drm_framebuffer *fb, + int colot_plane); int i9xx_check_plane_surface(struct intel_plane_state *plane_state); struct intel_plane * -intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe); +intel_primary_plane_create(struct intel_display *display, enum pipe pipe); void i9xx_get_initial_plane_config(struct intel_crtc *crtc, struct intel_initial_plane_config *plane_config); @@ -40,7 +44,7 @@ static inline int i9xx_check_plane_surface(struct intel_plane_state *plane_state return 0; } static inline struct intel_plane * -intel_primary_plane_create(struct drm_i915_private *dev_priv, int pipe) +intel_primary_plane_create(struct intel_display *display, int pipe) { return NULL; } diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index db78c1e6b0a3..7c80e37c1c5f 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -446,7 +446,7 @@ static const struct intel_watermark_params i845_wm_info = { * @latency: Memory wakeup latency in 0.1us units * * Compute the watermark using the method 1 or "small buffer" - * formula. The caller may additonally add extra cachelines + * formula. The caller may additionally add extra cachelines * to account for TLB misses and clock crossings. * * This method is concerned with the short term drain rate @@ -493,7 +493,7 @@ static unsigned int intel_wm_method1(unsigned int pixel_rate, * @latency: Memory wakeup latency in 0.1us units * * Compute the watermark using the method 2 or "large buffer" - * formula. The caller may additonally add extra cachelines + * formula. The caller may additionally add extra cachelines * to account for TLB misses and clock crossings. * * This method is concerned with the long term drain rate @@ -1562,7 +1562,7 @@ static int vlv_compute_fifo(struct intel_crtc_state *crtc_state) /* * When enabling sprite0 after sprite1 has already been enabled * we tend to get an underrun unless sprite0 already has some - * FIFO space allcoated. Hence we always allocate at least one + * FIFO space allocated. Hence we always allocate at least one * cacheline for sprite0 whenever sprite1 is enabled. * * All other plane enable sequences appear immune to this problem. @@ -3902,12 +3902,6 @@ static void g4x_wm_sanitize(struct drm_i915_private *dev_priv) mutex_unlock(&dev_priv->display.wm.wm_mutex); } -static void g4x_wm_get_hw_state_and_sanitize(struct drm_i915_private *i915) -{ - g4x_wm_get_hw_state(i915); - g4x_wm_sanitize(i915); -} - static void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv) { struct vlv_wm_values *wm = &dev_priv->display.wm.vlv; @@ -4055,12 +4049,6 @@ static void vlv_wm_sanitize(struct drm_i915_private *dev_priv) mutex_unlock(&dev_priv->display.wm.wm_mutex); } -static void vlv_wm_get_hw_state_and_sanitize(struct drm_i915_private *i915) -{ - vlv_wm_get_hw_state(i915); - vlv_wm_sanitize(i915); -} - /* * FIXME should probably kill this and improve * the real watermark readout/sanitation instead @@ -4122,14 +4110,16 @@ static const struct intel_wm_funcs vlv_wm_funcs = { .initial_watermarks = vlv_initial_watermarks, .optimize_watermarks = vlv_optimize_watermarks, .atomic_update_watermarks = vlv_atomic_update_fifo, - .get_hw_state = vlv_wm_get_hw_state_and_sanitize, + .get_hw_state = vlv_wm_get_hw_state, + .sanitize = vlv_wm_sanitize, }; static const struct intel_wm_funcs g4x_wm_funcs = { .compute_watermarks = g4x_compute_watermarks, .initial_watermarks = g4x_initial_watermarks, .optimize_watermarks = g4x_optimize_watermarks, - .get_hw_state = g4x_wm_get_hw_state_and_sanitize, + .get_hw_state = g4x_wm_get_hw_state, + .sanitize = g4x_wm_sanitize, }; static const struct intel_wm_funcs pnv_wm_funcs = { diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index c977b74f82f0..402b7b2e1829 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -31,8 +31,8 @@ #include <drm/drm_mipi_dsi.h> #include <drm/drm_probe_helper.h> -#include "i915_drv.h" #include "i915_reg.h" +#include "i915_utils.h" #include "icl_dsi.h" #include "icl_dsi_regs.h" #include "intel_atomic.h" @@ -243,7 +243,7 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) for_each_dsi_phy(phy, intel_dsi->phys) { /* * Program voltage swing and pre-emphasis level values as per - * table in BSPEC under DDI buffer programing + * table in BSPEC under DDI buffer programming. */ mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK; val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE | @@ -345,7 +345,6 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; int afe_clk_khz; @@ -354,7 +353,7 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, afe_clk_khz = afe_clk(encoder, crtc_state); - if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { + if (display->platform.alderlake_s || display->platform.alderlake_p) { theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK); act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2); esc_clk_div_m = act_word_clk * 8; @@ -375,7 +374,7 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port)); } - if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) { + if (display->platform.alderlake_s || display->platform.alderlake_p) { for_each_dsi_port(port, intel_dsi->ports) { intel_de_write(display, ADL_MIPIO_DW(port, 8), esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY); @@ -387,13 +386,12 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi) { struct intel_display *display = to_intel_display(&intel_dsi->base); - struct drm_i915_private *dev_priv = to_i915(display->drm); enum port port; for_each_dsi_port(port, intel_dsi->ports) { drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]); intel_dsi->io_wakeref[port] = - intel_display_power_get(dev_priv, + intel_display_power_get(display, port == PORT_A ? POWER_DOMAIN_PORT_DDI_IO_A : POWER_DOMAIN_PORT_DDI_IO_B); @@ -415,19 +413,18 @@ static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum phy phy; for_each_dsi_phy(phy, intel_dsi->phys) - intel_combo_phy_power_up_lanes(dev_priv, phy, true, + intel_combo_phy_power_up_lanes(display, phy, true, intel_dsi->lane_count, false); } static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum phy phy; u32 tmp; @@ -452,7 +449,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp); /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ - if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) || + if (display->platform.jasperlake || display->platform.elkhartlake || (DISPLAY_VER(display) >= 12)) { intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0)); @@ -534,7 +531,6 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; enum phy phy; @@ -564,7 +560,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, } } - if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { + if (display->platform.jasperlake || display->platform.elkhartlake) { for_each_dsi_phy(phy, intel_dsi->phys) intel_de_rmw(display, ICL_DPHY_CHKN(phy), 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP); @@ -809,8 +805,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, /* select data lane width */ tmp = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, dsi_trans)); - tmp &= ~DDI_PORT_WIDTH_MASK; - tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); + tmp &= ~TRANS_DDI_PORT_WIDTH_MASK; + tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count); /* select input pipe */ tmp &= ~TRANS_DDI_EDP_INPUT_MASK; @@ -961,7 +957,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); /* - * FIXME: Programing this by assuming progressive mode, since + * FIXME: Programming this by assuming progressive mode, since * non-interlaced info from VBT is not saved inside * struct drm_display_mode. * For interlace mode: program required pixel minus 2 @@ -1385,7 +1381,6 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder) static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; @@ -1393,7 +1388,7 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) intel_wakeref_t wakeref; wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); - intel_display_power_put(dev_priv, + intel_display_power_put(display, port == PORT_A ? POWER_DOMAIN_PORT_DDI_IO_A : POWER_DOMAIN_PORT_DDI_IO_B, @@ -1460,12 +1455,12 @@ static void gen11_dsi_post_disable(struct intel_atomic_state *state, } static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { - struct drm_i915_private *i915 = to_i915(connector->dev); + struct intel_display *display = to_intel_display(connector->dev); enum drm_mode_status status; - status = intel_cpu_transcoder_mode_valid(i915, mode); + status = intel_cpu_transcoder_mode_valid(display, mode); if (status != MODE_OK) return status; @@ -1652,7 +1647,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder, if (ret) return ret; - ret = intel_panel_fitting(pipe_config, conn_state); + ret = intel_pfit_compute_config(pipe_config, conn_state); if (ret) return ret; @@ -1697,7 +1692,6 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum transcoder dsi_trans; intel_wakeref_t wakeref; @@ -1705,7 +1699,7 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, bool ret = false; u32 tmp; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; @@ -1736,7 +1730,7 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, ret = tmp & TRANSCONF_ENABLE; } out: - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c b/drivers/gpu/drm/i915/display/intel_acpi.c index bbf8c5a8fdbd..1addd6288241 100644 --- a/drivers/gpu/drm/i915/display/intel_acpi.c +++ b/drivers/gpu/drm/i915/display/intel_acpi.c @@ -9,6 +9,8 @@ #include <linux/acpi.h> #include <acpi/video.h> +#include <drm/drm_print.h> + #include "i915_utils.h" #include "intel_acpi.h" #include "intel_display_core.h" diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h index e506f6a87344..a5a7e2906ba8 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.h +++ b/drivers/gpu/drm/i915/display/intel_atomic.h @@ -14,7 +14,6 @@ struct drm_connector_state; struct drm_crtc; struct drm_crtc_state; struct drm_device; -struct drm_i915_private; struct drm_property; struct intel_atomic_state; struct intel_connector; diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 612e9b0ec14a..7276179df878 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -36,12 +36,15 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_blend.h> +#include <drm/drm_damage_helper.h> #include <drm/drm_fourcc.h> #include <drm/drm_gem.h> #include <drm/drm_gem_atomic_helper.h> -#include "i915_drv.h" +#include "gem/i915_gem_object.h" #include "i915_config.h" +#include "i915_scheduler_types.h" +#include "i915_vma.h" #include "i9xx_plane_regs.h" #include "intel_atomic_plane.h" #include "intel_cdclk.h" @@ -52,6 +55,7 @@ #include "intel_fb.h" #include "intel_fb_pin.h" #include "skl_scaler.h" +#include "skl_universal_plane.h" #include "skl_watermark.h" static void intel_plane_state_reset(struct intel_plane_state *plane_state, @@ -93,6 +97,19 @@ void intel_plane_free(struct intel_plane *plane) } /** + * intel_plane_destroy - destroy a plane + * @plane: plane to destroy + * + * Common destruction function for all types of planes (primary, cursor, + * sprite). + */ +void intel_plane_destroy(struct drm_plane *plane) +{ + drm_plane_cleanup(plane); + kfree(to_intel_plane(plane)); +} + +/** * intel_plane_duplicate_state - duplicate plane state * @plane: drm plane * @@ -117,6 +134,7 @@ intel_plane_duplicate_state(struct drm_plane *plane) intel_state->ggtt_vma = NULL; intel_state->dpt_vma = NULL; intel_state->flags = 0; + intel_state->damage = DRM_RECT_INIT(0, 0, 0, 0); /* add reference to fb */ if (intel_state->hw.fb) @@ -150,10 +168,15 @@ intel_plane_destroy_state(struct drm_plane *plane, bool intel_plane_needs_physical(struct intel_plane *plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); return plane->id == PLANE_CURSOR && - DISPLAY_INFO(i915)->cursor_needs_physical; + DISPLAY_INFO(display)->cursor_needs_physical; +} + +bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier) +{ + return plane->can_async_flip && plane->can_async_flip(modifier); } unsigned int intel_adjusted_rate(const struct drm_rect *src, @@ -253,7 +276,7 @@ int intel_plane_calc_min_cdclk(struct intel_atomic_state *state, struct intel_plane *plane, bool *need_cdclk_calc) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); const struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); @@ -298,7 +321,7 @@ int intel_plane_calc_min_cdclk(struct intel_atomic_state *state, cdclk_state->min_cdclk[crtc->pipe]) return 0; - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n", plane->base.base.id, plane->base.name, new_crtc_state->min_cdclk[plane->id], @@ -317,6 +340,25 @@ static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state) memset(&plane_state->hw, 0, sizeof(plane_state->hw)); } +static void +intel_plane_copy_uapi_plane_damage(struct intel_plane_state *new_plane_state, + const struct intel_plane_state *old_uapi_plane_state, + const struct intel_plane_state *new_uapi_plane_state) +{ + struct intel_display *display = to_intel_display(new_plane_state); + struct drm_rect *damage = &new_plane_state->damage; + + /* damage property tracking enabled from display version 12 onwards */ + if (DISPLAY_VER(display) < 12) + return; + + if (!drm_atomic_helper_damage_merged(&old_uapi_plane_state->uapi, + &new_uapi_plane_state->uapi, + damage)) + /* Incase helper fails, mark whole plane region as damage */ + *damage = drm_plane_state_src(&new_uapi_plane_state->uapi); +} + void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state, const struct intel_plane_state *from_plane_state, struct intel_crtc *crtc) @@ -392,7 +434,7 @@ static bool intel_plane_do_async_flip(struct intel_plane *plane, const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); if (!plane->async_flip) return false; @@ -413,7 +455,7 @@ static bool intel_plane_do_async_flip(struct intel_plane *plane, * extend this so other scanout parameters (stride/etc) could * be changed as well... */ - return DISPLAY_VER(i915) < 9 || old_crtc_state->uapi.async_flip; + return DISPLAY_VER(display) < 9 || old_crtc_state->uapi.async_flip; } static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state, @@ -517,16 +559,16 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr const struct intel_plane_state *old_plane_state, struct intel_plane_state *new_plane_state) { + struct intel_display *display = to_intel_display(new_crtc_state); struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); bool mode_changed = intel_crtc_needs_modeset(new_crtc_state); bool was_crtc_enabled = old_crtc_state->hw.active; bool is_crtc_enabled = new_crtc_state->hw.active; bool turn_off, turn_on, visible, was_visible; int ret; - if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { + if (DISPLAY_VER(display) >= 9 && plane->id != PLANE_CURSOR) { ret = skl_update_scaler_plane(new_crtc_state, new_plane_state); if (ret) return ret; @@ -535,7 +577,7 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr was_visible = old_plane_state->uapi.visible; visible = new_plane_state->uapi.visible; - if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible)) + if (!was_crtc_enabled && drm_WARN_ON(display->drm, was_visible)) was_visible = false; /* @@ -559,7 +601,7 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr turn_off = was_visible && (!visible || mode_changed); turn_on = visible && (!was_visible || mode_changed); - drm_dbg_atomic(&dev_priv->drm, + drm_dbg_atomic(display->drm, "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", crtc->base.base.id, crtc->base.name, plane->base.base.id, plane->base.name, @@ -569,11 +611,11 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr if (visible || was_visible) new_crtc_state->fb_bits |= plane->frontbuffer_bit; - if (HAS_GMCH(dev_priv) && + if (HAS_GMCH(display) && i9xx_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state)) new_crtc_state->disable_cxsr = true; - if ((IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) && + if ((display->platform.ironlake || display->platform.sandybridge || display->platform.ivybridge) && ilk_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state)) new_crtc_state->disable_cxsr = true; @@ -663,13 +705,13 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ old_plane_state, new_plane_state); } -static struct intel_plane * +struct intel_plane * intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_plane *plane; - for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { + for_each_intel_plane_on_crtc(display->drm, crtc, plane) { if (plane->id == plane_id) return plane; } @@ -686,6 +728,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state, const struct intel_plane_state *old_plane_state = intel_atomic_get_old_plane_state(state, plane); const struct intel_plane_state *new_primary_crtc_plane_state; + const struct intel_plane_state *old_primary_crtc_plane_state; struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); @@ -700,10 +743,17 @@ int intel_plane_atomic_check(struct intel_atomic_state *state, new_primary_crtc_plane_state = intel_atomic_get_new_plane_state(state, primary_crtc_plane); + old_primary_crtc_plane_state = + intel_atomic_get_old_plane_state(state, primary_crtc_plane); } else { new_primary_crtc_plane_state = new_plane_state; + old_primary_crtc_plane_state = old_plane_state; } + intel_plane_copy_uapi_plane_damage(new_plane_state, + old_primary_crtc_plane_state, + new_primary_crtc_plane_state); + intel_plane_copy_uapi_to_hw_state(new_plane_state, new_primary_crtc_plane_state, crtc); @@ -767,7 +817,10 @@ void intel_plane_update_noarm(struct intel_dsb *dsb, { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - trace_intel_plane_update_noarm(plane, crtc); + trace_intel_plane_update_noarm(plane_state, crtc); + + if (plane->fbc) + intel_fbc_dirty_rect_update_noarm(dsb, plane); if (plane->update_noarm) plane->update_noarm(dsb, plane, crtc_state, plane_state); @@ -797,7 +850,7 @@ void intel_plane_update_arm(struct intel_dsb *dsb, return; } - trace_intel_plane_update_arm(plane, crtc); + trace_intel_plane_update_arm(plane_state, crtc); plane->update_arm(dsb, plane, crtc_state, plane_state); } @@ -836,7 +889,7 @@ void intel_crtc_planes_update_noarm(struct intel_dsb *dsb, /* TODO: for mailbox updates this should be skipped */ if (new_plane_state->uapi.visible || - new_plane_state->planar_slave) + new_plane_state->is_y_plane) intel_plane_update_noarm(dsb, plane, new_crtc_state, new_plane_state); } @@ -869,7 +922,7 @@ static void skl_crtc_planes_update_arm(struct intel_dsb *dsb, * would have to be called here as well. */ if (new_plane_state->uapi.visible || - new_plane_state->planar_slave) + new_plane_state->is_y_plane) intel_plane_update_arm(dsb, plane, new_crtc_state, new_plane_state); else intel_plane_disable_arm(dsb, plane, new_crtc_state); @@ -907,9 +960,9 @@ void intel_crtc_planes_update_arm(struct intel_dsb *dsb, struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); - if (DISPLAY_VER(i915) >= 9) + if (DISPLAY_VER(display) >= 9) skl_crtc_planes_update_arm(dsb, state, crtc); else i9xx_crtc_planes_update_arm(dsb, state, crtc); @@ -920,7 +973,8 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, int min_scale, int max_scale, bool can_position) { - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); struct drm_framebuffer *fb = plane_state->hw.fb; struct drm_rect *src = &plane_state->uapi.src; struct drm_rect *dst = &plane_state->uapi.dst; @@ -939,9 +993,10 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); if (hscale < 0 || vscale < 0) { - drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n"); - drm_rect_debug_print("src: ", src, true); - drm_rect_debug_print("dst: ", dst, false); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] invalid scaling "DRM_RECT_FP_FMT " -> " DRM_RECT_FMT "\n", + plane->base.base.id, plane->base.name, + DRM_RECT_FP_ARG(src), DRM_RECT_ARG(dst)); return -ERANGE; } @@ -955,9 +1010,10 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, if (!can_position && plane_state->uapi.visible && !drm_rect_equals(dst, clip)) { - drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n"); - drm_rect_debug_print("dst: ", dst, false); - drm_rect_debug_print("clip: ", clip, false); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] plane (" DRM_RECT_FMT ") must cover entire CRTC (" DRM_RECT_FMT ")\n", + plane->base.base.id, plane->base.name, + DRM_RECT_ARG(dst), DRM_RECT_ARG(clip)); return -EINVAL; } @@ -969,7 +1025,8 @@ int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state, int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) { - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct drm_framebuffer *fb = plane_state->hw.fb; struct drm_rect *src = &plane_state->uapi.src; u32 src_x, src_y, src_w, src_h, hsub, vsub; @@ -1002,18 +1059,18 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) if (fb->format->format == DRM_FORMAT_RGB565 && rotated) { hsub = 2; vsub = 2; - } else if (DISPLAY_VER(i915) >= 20 && + } else if (DISPLAY_VER(display) >= 20 && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { /* * This allows NV12 and P0xx formats to have odd size and/or odd - * source coordinates on DISPLAY_VER(i915) >= 20 + * source coordinates on DISPLAY_VER(display) >= 20 */ hsub = 1; vsub = 1; /* Wa_16023981245 */ - if ((DISPLAY_VERx100(i915) == 2000 || - DISPLAY_VERx100(i915) == 3000) && + if ((DISPLAY_VERx100(display) == 2000 || + DISPLAY_VERx100(display) == 3000) && src_x % 2 != 0) hsub = 2; } else { @@ -1025,13 +1082,17 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) hsub = vsub = max(hsub, vsub); if (src_x % hsub || src_w % hsub) { - drm_dbg_kms(&i915->drm, "src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n", + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n", + plane->base.base.id, plane->base.name, src_x, src_w, hsub, str_yes_no(rotated)); return -EINVAL; } if (src_y % vsub || src_h % vsub) { - drm_dbg_kms(&i915->drm, "src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n", + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n", + plane->base.base.id, plane->base.name, src_y, src_h, vsub, str_yes_no(rotated)); return -EINVAL; } @@ -1092,11 +1153,11 @@ intel_prepare_plane_fb(struct drm_plane *_plane, { struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY }; struct intel_plane *plane = to_intel_plane(_plane); + struct intel_display *display = to_intel_display(plane); struct intel_plane_state *new_plane_state = to_intel_plane_state(_new_plane_state); struct intel_atomic_state *state = to_intel_atomic_state(new_plane_state->uapi.state); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); struct intel_plane_state *old_plane_state = intel_atomic_get_old_plane_state(state, plane); struct drm_gem_object *obj = intel_fb_bo(new_plane_state->hw.fb); @@ -1119,7 +1180,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane, * This should only fail upon a hung GPU, in which case we * can safely continue. */ - if (new_crtc_state && intel_crtc_needs_modeset(new_crtc_state)) { + if (intel_crtc_needs_modeset(new_crtc_state)) { ret = add_dma_resv_fences(old_obj->resv, &new_plane_state->uapi); if (ret < 0) @@ -1130,7 +1191,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane, if (!obj) return 0; - ret = intel_plane_pin_fb(new_plane_state); + ret = intel_plane_pin_fb(new_plane_state, old_plane_state); if (ret) return ret; @@ -1154,7 +1215,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane, * that are not quite steady state without resorting to forcing * maximum clocks following a vblank miss (see do_rps_boost()). */ - intel_display_rps_mark_interactive(dev_priv, state, true); + intel_display_rps_mark_interactive(display, state, true); return 0; @@ -1175,17 +1236,17 @@ static void intel_cleanup_plane_fb(struct drm_plane *plane, struct drm_plane_state *_old_plane_state) { + struct intel_display *display = to_intel_display(plane->dev); struct intel_plane_state *old_plane_state = to_intel_plane_state(_old_plane_state); struct intel_atomic_state *state = to_intel_atomic_state(old_plane_state->uapi.state); - struct drm_i915_private *dev_priv = to_i915(plane->dev); struct drm_gem_object *obj = intel_fb_bo(old_plane_state->hw.fb); if (!obj) return; - intel_display_rps_mark_interactive(dev_priv, state, false); + intel_display_rps_mark_interactive(display, state, false); intel_plane_unpin_fb(old_plane_state); } @@ -1210,3 +1271,302 @@ void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_sta drm_vblank_work_init(&old_plane_state->unpin_work, old_plane_state->uapi.crtc, intel_cursor_unpin_work); } + +static void link_nv12_planes(struct intel_crtc_state *crtc_state, + struct intel_plane_state *uv_plane_state, + struct intel_plane_state *y_plane_state) +{ + struct intel_display *display = to_intel_display(uv_plane_state); + struct intel_plane *uv_plane = to_intel_plane(uv_plane_state->uapi.plane); + struct intel_plane *y_plane = to_intel_plane(y_plane_state->uapi.plane); + + drm_dbg_kms(display->drm, "UV plane [PLANE:%d:%s] using Y plane [PLANE:%d:%s]\n", + uv_plane->base.base.id, uv_plane->base.name, + y_plane->base.base.id, y_plane->base.name); + + uv_plane_state->planar_linked_plane = y_plane; + + y_plane_state->is_y_plane = true; + y_plane_state->planar_linked_plane = uv_plane; + + crtc_state->enabled_planes |= BIT(y_plane->id); + crtc_state->active_planes |= BIT(y_plane->id); + crtc_state->update_planes |= BIT(y_plane->id); + + crtc_state->data_rate[y_plane->id] = crtc_state->data_rate_y[uv_plane->id]; + crtc_state->rel_data_rate[y_plane->id] = crtc_state->rel_data_rate_y[uv_plane->id]; + + /* Copy parameters to Y plane */ + intel_plane_copy_hw_state(y_plane_state, uv_plane_state); + y_plane_state->uapi.src = uv_plane_state->uapi.src; + y_plane_state->uapi.dst = uv_plane_state->uapi.dst; + + y_plane_state->ctl = uv_plane_state->ctl; + y_plane_state->color_ctl = uv_plane_state->color_ctl; + y_plane_state->view = uv_plane_state->view; + y_plane_state->decrypt = uv_plane_state->decrypt; + + icl_link_nv12_planes(uv_plane_state, y_plane_state); +} + +static void unlink_nv12_plane(struct intel_crtc_state *crtc_state, + struct intel_plane_state *plane_state) +{ + struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + + plane_state->planar_linked_plane = NULL; + + if (!plane_state->is_y_plane) + return; + + drm_WARN_ON(display->drm, plane_state->uapi.visible); + + plane_state->is_y_plane = false; + + crtc_state->enabled_planes &= ~BIT(plane->id); + crtc_state->active_planes &= ~BIT(plane->id); + crtc_state->update_planes |= BIT(plane->id); + crtc_state->data_rate[plane->id] = 0; + crtc_state->rel_data_rate[plane->id] = 0; +} + +static int icl_check_nv12_planes(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(state); + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + struct intel_plane_state *plane_state; + struct intel_plane *plane; + int i; + + if (DISPLAY_VER(display) < 11) + return 0; + + /* + * Destroy all old plane links and make the Y plane invisible + * in the crtc_state->active_planes mask. + */ + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + if (plane->pipe != crtc->pipe) + continue; + + if (plane_state->planar_linked_plane) + unlink_nv12_plane(crtc_state, plane_state); + } + + if (!crtc_state->nv12_planes) + return 0; + + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + struct intel_plane_state *y_plane_state = NULL; + struct intel_plane *y_plane; + + if (plane->pipe != crtc->pipe) + continue; + + if ((crtc_state->nv12_planes & BIT(plane->id)) == 0) + continue; + + for_each_intel_plane_on_crtc(display->drm, crtc, y_plane) { + if (!icl_is_nv12_y_plane(display, y_plane->id)) + continue; + + if (crtc_state->active_planes & BIT(y_plane->id)) + continue; + + y_plane_state = intel_atomic_get_plane_state(state, y_plane); + if (IS_ERR(y_plane_state)) + return PTR_ERR(y_plane_state); + + break; + } + + if (!y_plane_state) { + drm_dbg_kms(display->drm, + "[CRTC:%d:%s] need %d free Y planes for planar YUV\n", + crtc->base.base.id, crtc->base.name, + hweight8(crtc_state->nv12_planes)); + return -EINVAL; + } + + link_nv12_planes(crtc_state, plane_state, y_plane_state); + } + + return 0; +} + +static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, + struct intel_crtc *crtc, + u8 plane_ids_mask) +{ + struct intel_display *display = to_intel_display(state); + struct intel_plane *plane; + + for_each_intel_plane_on_crtc(display->drm, crtc, plane) { + struct intel_plane_state *plane_state; + + if ((plane_ids_mask & BIT(plane->id)) == 0) + continue; + + plane_state = intel_atomic_get_plane_state(state, plane); + if (IS_ERR(plane_state)) + return PTR_ERR(plane_state); + } + + return 0; +} + +int intel_atomic_add_affected_planes(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + + return intel_crtc_add_planes_to_state(state, crtc, + old_crtc_state->enabled_planes | + new_crtc_state->enabled_planes); +} + +static bool active_planes_affects_min_cdclk(struct intel_display *display) +{ + /* See {hsw,vlv,ivb}_plane_ratio() */ + return display->platform.broadwell || display->platform.haswell || + display->platform.cherryview || display->platform.valleyview || + display->platform.ivybridge; +} + +static u8 intel_joiner_affected_planes(struct intel_atomic_state *state, + u8 joined_pipes) +{ + const struct intel_plane_state *plane_state; + struct intel_plane *plane; + u8 affected_planes = 0; + int i; + + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + struct intel_plane *linked = plane_state->planar_linked_plane; + + if ((joined_pipes & BIT(plane->pipe)) == 0) + continue; + + affected_planes |= BIT(plane->id); + if (linked) + affected_planes |= BIT(linked->id); + } + + return affected_planes; +} + +static int intel_joiner_add_affected_planes(struct intel_atomic_state *state, + u8 joined_pipes) +{ + u8 prev_affected_planes, affected_planes = 0; + + /* + * We want all the joined pipes to have the same + * set of planes in the atomic state, to make sure + * state copying always works correctly, and the + * UV<->Y plane linkage is always up to date. + * Keep pulling planes in until we've determined + * the full set of affected planes. A bit complicated + * on account of each pipe being capable of selecting + * their own Y planes independently of the other pipes, + * and the selection being done from the set of + * inactive planes. + */ + do { + struct intel_crtc *crtc; + + for_each_intel_crtc_in_pipe_mask(state->base.dev, crtc, joined_pipes) { + int ret; + + ret = intel_crtc_add_planes_to_state(state, crtc, affected_planes); + if (ret) + return ret; + } + + prev_affected_planes = affected_planes; + affected_planes = intel_joiner_affected_planes(state, joined_pipes); + } while (affected_planes != prev_affected_planes); + + return 0; +} + +static int intel_add_affected_planes(struct intel_atomic_state *state) +{ + const struct intel_crtc_state *crtc_state; + struct intel_crtc *crtc; + int i; + + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { + int ret; + + ret = intel_joiner_add_affected_planes(state, intel_crtc_joined_pipe_mask(crtc_state)); + if (ret) + return ret; + } + + return 0; +} + +int intel_atomic_check_planes(struct intel_atomic_state *state) +{ + struct intel_display *display = to_intel_display(state); + struct intel_crtc_state *old_crtc_state, *new_crtc_state; + struct intel_plane_state __maybe_unused *plane_state; + struct intel_plane *plane; + struct intel_crtc *crtc; + int i, ret; + + ret = intel_add_affected_planes(state); + if (ret) + return ret; + + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + ret = intel_plane_atomic_check(state, plane); + if (ret) { + drm_dbg_atomic(display->drm, + "[PLANE:%d:%s] atomic driver check failed\n", + plane->base.base.id, plane->base.name); + return ret; + } + } + + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + u8 old_active_planes, new_active_planes; + + ret = icl_check_nv12_planes(state, crtc); + if (ret) + return ret; + + /* + * On some platforms the number of active planes affects + * the planes' minimum cdclk calculation. Add such planes + * to the state before we compute the minimum cdclk. + */ + if (!active_planes_affects_min_cdclk(display)) + continue; + + old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); + new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); + + if (hweight8(old_active_planes) == hweight8(new_active_planes)) + continue; + + ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); + if (ret) + return ret; + } + + return 0; +} + +u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state) +{ + return i915_ggtt_offset(plane_state->ggtt_vma); +} diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index 0f982f452ff3..6efac923dcbc 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -19,6 +19,9 @@ struct intel_plane; struct intel_plane_state; enum plane_id; +struct intel_plane * +intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id); +bool intel_plane_can_async_flip(struct intel_plane *plane, u64 modifier); unsigned int intel_adjusted_rate(const struct drm_rect *src, const struct drm_rect *dst, unsigned int rate); @@ -51,6 +54,7 @@ void intel_plane_disable_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state); struct intel_plane *intel_plane_alloc(void); void intel_plane_free(struct intel_plane *plane); +void intel_plane_destroy(struct drm_plane *plane); struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); void intel_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state); @@ -80,5 +84,10 @@ void intel_plane_helper_add(struct intel_plane *plane); bool intel_plane_needs_physical(struct intel_plane *plane); void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_state, struct intel_plane_state *new_plane_state); +int intel_atomic_add_affected_planes(struct intel_atomic_state *state, + struct intel_crtc *crtc); +int intel_atomic_check_planes(struct intel_atomic_state *state); + +u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state); #endif /* __INTEL_ATOMIC_PLANE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index ce8a4319a63c..ea935a5d94c8 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -188,15 +188,17 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { * WA_14020863754: Implement Audio Workaround * Corner case with Min Hblank Fix can cause audio hang */ -static bool needs_wa_14020863754(struct drm_i915_private *i915) +static bool needs_wa_14020863754(struct intel_display *display) { - return (DISPLAY_VER(i915) == 20 || IS_BATTLEMAGE(i915)); + return DISPLAY_VERx100(display) == 3000 || + DISPLAY_VERx100(display) == 2000 || + DISPLAY_VERx100(display) == 1401; } /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; int i; @@ -206,17 +208,17 @@ static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_sta break; } - if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500) + if (DISPLAY_VER(display) < 12 && adjusted_mode->crtc_clock > 148500) i = ARRAY_SIZE(hdmi_audio_clock); if (i == ARRAY_SIZE(hdmi_audio_clock)) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "HDMI audio pixel clock setting for %d not found, falling back to defaults\n", adjusted_mode->crtc_clock); i = 1; } - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "Configuring HDMI audio for pixel clock %d (0x%08x)\n", hdmi_audio_clock[i].clock, hdmi_audio_clock[i].config); @@ -251,11 +253,11 @@ static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, } /* ELD buffer size in dwords */ -static int g4x_eld_buffer_size(struct drm_i915_private *i915) +static int g4x_eld_buffer_size(struct intel_display *display) { u32 tmp; - tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); + tmp = intel_de_read(display, G4X_AUD_CNTL_ST); return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp); } @@ -263,33 +265,33 @@ static int g4x_eld_buffer_size(struct drm_i915_private *i915) static void g4x_audio_codec_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); u32 *eld = (u32 *)crtc_state->eld; int eld_buffer_size, len, i; u32 tmp; - tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); + tmp = intel_de_read(display, G4X_AUD_CNTL_ST); if ((tmp & G4X_ELD_VALID) == 0) return; - intel_de_rmw(i915, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0); + intel_de_rmw(display, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0); - eld_buffer_size = g4x_eld_buffer_size(i915); + eld_buffer_size = g4x_eld_buffer_size(display); len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size); for (i = 0; i < len; i++) - eld[i] = intel_de_read(i915, G4X_HDMIW_HDMIEDID); + eld[i] = intel_de_read(display, G4X_HDMIW_HDMIEDID); } static void g4x_audio_codec_disable(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); /* Invalidate ELD */ - intel_de_rmw(i915, G4X_AUD_CNTL_ST, + intel_de_rmw(display, G4X_AUD_CNTL_ST, G4X_ELD_VALID, 0); intel_crtc_wait_for_next_vblank(crtc); @@ -300,28 +302,28 @@ static void g4x_audio_codec_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const u32 *eld = (const u32 *)crtc_state->eld; int eld_buffer_size, len, i; intel_crtc_wait_for_next_vblank(crtc); - intel_de_rmw(i915, G4X_AUD_CNTL_ST, + intel_de_rmw(display, G4X_AUD_CNTL_ST, G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0); - eld_buffer_size = g4x_eld_buffer_size(i915); + eld_buffer_size = g4x_eld_buffer_size(display); len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size); for (i = 0; i < len; i++) - intel_de_write(i915, G4X_HDMIW_HDMIEDID, eld[i]); + intel_de_write(display, G4X_HDMIW_HDMIEDID, eld[i]); for (; i < eld_buffer_size; i++) - intel_de_write(i915, G4X_HDMIW_HDMIEDID, 0); + intel_de_write(display, G4X_HDMIW_HDMIEDID, 0); - drm_WARN_ON(&i915->drm, - (intel_de_read(i915, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0); + drm_WARN_ON(display->drm, + (intel_de_read(display, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0); - intel_de_rmw(i915, G4X_AUD_CNTL_ST, + intel_de_rmw(display, G4X_AUD_CNTL_ST, 0, G4X_ELD_VALID); } @@ -329,11 +331,11 @@ static void hsw_dp_audio_config_update(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; /* Enable time stamps. Let HW calculate Maud/Naud values */ - intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), + intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder), AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK | AUD_CONFIG_UPPER_N_MASK | @@ -347,8 +349,8 @@ static void hsw_hdmi_audio_config_update(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); - struct i915_audio_component *acomp = i915->display.audio.component; + struct intel_display *display = to_intel_display(encoder); + struct i915_audio_component *acomp = display->audio.component; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum port port = encoder->port; int n, rate; @@ -356,7 +358,7 @@ hsw_hdmi_audio_config_update(struct intel_encoder *encoder, rate = acomp ? acomp->aud_sample_rate[port] : 0; - tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder)); + tmp = intel_de_read(display, HSW_AUD_CFG(cpu_transcoder)); tmp &= ~AUD_CONFIG_N_VALUE_INDEX; tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; tmp &= ~AUD_CONFIG_N_PROG_ENABLE; @@ -364,25 +366,25 @@ hsw_hdmi_audio_config_update(struct intel_encoder *encoder, n = audio_config_hdmi_get_n(crtc_state, rate); if (n != 0) { - drm_dbg_kms(&i915->drm, "using N %d\n", n); + drm_dbg_kms(display->drm, "using N %d\n", n); tmp &= ~AUD_CONFIG_N_MASK; tmp |= AUD_CONFIG_N(n); tmp |= AUD_CONFIG_N_PROG_ENABLE; } else { - drm_dbg_kms(&i915->drm, "using automatic N\n"); + drm_dbg_kms(display->drm, "using automatic N\n"); } - intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp); + intel_de_write(display, HSW_AUD_CFG(cpu_transcoder), tmp); /* * Let's disable "Enable CTS or M Prog bit" * and let HW calculate the value */ - tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); + tmp = intel_de_read(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); tmp &= ~AUD_M_CTS_M_PROG_ENABLE; tmp &= ~AUD_M_CTS_M_VALUE_INDEX; - intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); + intel_de_write(display, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); } static void @@ -399,14 +401,14 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; - mutex_lock(&i915->display.audio.mutex); + mutex_lock(&display->audio.mutex); /* Disable timestamps */ - intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), + intel_de_rmw(display, HSW_AUD_CFG(cpu_transcoder), AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK, @@ -415,26 +417,26 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder, AUD_CONFIG_N_VALUE_INDEX : 0)); /* Invalidate ELD */ - intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, + intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, AUDIO_ELD_VALID(cpu_transcoder), 0); intel_crtc_wait_for_next_vblank(crtc); intel_crtc_wait_for_next_vblank(crtc); /* Disable audio presence detect */ - intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, + intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0); - if (needs_wa_14020863754(i915)) - intel_de_rmw(i915, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0); + if (needs_wa_14020863754(display)) + intel_de_rmw(display, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0); - mutex_unlock(&i915->display.audio.mutex); + mutex_unlock(&display->audio.mutex); } static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); unsigned int link_clks_available, link_clks_required; unsigned int tu_data, tu_line, link_clks_active; unsigned int h_active, h_total, hblank_delta, pixel_clk; @@ -446,13 +448,13 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder, h_total = crtc_state->hw.adjusted_mode.crtc_htotal; pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock; vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16; - cdclk = i915->display.cdclk.hw.cdclk; + cdclk = display->cdclk.hw.cdclk; /* fec= 0.972261, using rounding multiplier of 1000000 */ fec_coeff = 972261; link_clk = crtc_state->port_clock; lanes = crtc_state->lane_count; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n", h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk); @@ -497,19 +499,19 @@ static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state) static void enable_audio_dsc_wa(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; unsigned int hblank_early_prog, samples_room; unsigned int val; - if (DISPLAY_VER(i915) < 11) + if (DISPLAY_VER(display) < 11) return; - val = intel_de_read(i915, AUD_CONFIG_BE); + val = intel_de_read(display, AUD_CONFIG_BE); - if (DISPLAY_VER(i915) == 11) + if (DISPLAY_VER(display) == 11) val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder); - else if (DISPLAY_VER(i915) >= 12) + else if (DISPLAY_VER(display) >= 12) val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder); if (crtc_state->dsc.compression_enable && @@ -536,56 +538,58 @@ static void enable_audio_dsc_wa(struct intel_encoder *encoder, val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0); } - intel_de_write(i915, AUD_CONFIG_BE, val); + intel_de_write(display, AUD_CONFIG_BE, val); } static void hsw_audio_codec_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - mutex_lock(&i915->display.audio.mutex); + mutex_lock(&display->audio.mutex); /* Enable Audio WA for 4k DSC usecases */ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) enable_audio_dsc_wa(encoder, crtc_state); - if (needs_wa_14020863754(i915)) - intel_de_rmw(i915, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX); + if (needs_wa_14020863754(display)) + intel_de_rmw(display, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX); /* Enable audio presence detect */ - intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, + intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder)); intel_crtc_wait_for_next_vblank(crtc); /* Invalidate ELD */ - intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, + intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, AUDIO_ELD_VALID(cpu_transcoder), 0); /* - * The audio componenent is used to convey the ELD + * The audio component is used to convey the ELD * instead using of the hardware ELD buffer. */ /* Enable timestamps */ hsw_audio_config_update(encoder, crtc_state); - mutex_unlock(&i915->display.audio.mutex); + mutex_unlock(&display->audio.mutex); } struct ibx_audio_regs { i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; }; -static void ibx_audio_regs_init(struct drm_i915_private *i915, +static void ibx_audio_regs_init(struct intel_display *display, enum pipe pipe, struct ibx_audio_regs *regs) { - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { + struct drm_i915_private *i915 = to_i915(display->drm); + + if (display->platform.valleyview || display->platform.cherryview) { regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); regs->aud_config = VLV_AUD_CFG(pipe); regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe); @@ -607,21 +611,21 @@ static void ibx_audio_codec_disable(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); enum port port = encoder->port; enum pipe pipe = crtc->pipe; struct ibx_audio_regs regs; - if (drm_WARN_ON(&i915->drm, port == PORT_A)) + if (drm_WARN_ON(display->drm, port == PORT_A)) return; - ibx_audio_regs_init(i915, pipe, ®s); + ibx_audio_regs_init(display, pipe, ®s); - mutex_lock(&i915->display.audio.mutex); + mutex_lock(&display->audio.mutex); /* Disable timestamps */ - intel_de_rmw(i915, regs.aud_config, + intel_de_rmw(display, regs.aud_config, AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK, @@ -630,10 +634,10 @@ static void ibx_audio_codec_disable(struct intel_encoder *encoder, AUD_CONFIG_N_VALUE_INDEX : 0)); /* Invalidate ELD */ - intel_de_rmw(i915, regs.aud_cntrl_st2, + intel_de_rmw(display, regs.aud_cntrl_st2, IBX_ELD_VALID(port), 0); - mutex_unlock(&i915->display.audio.mutex); + mutex_unlock(&display->audio.mutex); intel_crtc_wait_for_next_vblank(crtc); intel_crtc_wait_for_next_vblank(crtc); @@ -643,32 +647,32 @@ static void ibx_audio_codec_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum port port = encoder->port; enum pipe pipe = crtc->pipe; struct ibx_audio_regs regs; - if (drm_WARN_ON(&i915->drm, port == PORT_A)) + if (drm_WARN_ON(display->drm, port == PORT_A)) return; intel_crtc_wait_for_next_vblank(crtc); - ibx_audio_regs_init(i915, pipe, ®s); + ibx_audio_regs_init(display, pipe, ®s); - mutex_lock(&i915->display.audio.mutex); + mutex_lock(&display->audio.mutex); /* Invalidate ELD */ - intel_de_rmw(i915, regs.aud_cntrl_st2, + intel_de_rmw(display, regs.aud_cntrl_st2, IBX_ELD_VALID(port), 0); /* - * The audio componenent is used to convey the ELD + * The audio component is used to convey the ELD * instead using of the hardware ELD buffer. */ /* Enable timestamps */ - intel_de_rmw(i915, regs.aud_config, + intel_de_rmw(display, regs.aud_config, AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE | AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, @@ -676,7 +680,7 @@ static void ibx_audio_codec_enable(struct intel_encoder *encoder, AUD_CONFIG_N_VALUE_INDEX : audio_config_hdmi_pixel_clock(crtc_state))); - mutex_unlock(&i915->display.audio.mutex); + mutex_unlock(&display->audio.mutex); } void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state) @@ -693,14 +697,14 @@ bool intel_audio_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct drm_connector *connector = conn_state->connector; const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; mutex_lock(&connector->eld_mutex); if (!connector->eld[0]) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "Bogus ELD on [CONNECTOR:%d:%s]\n", connector->base.id, connector->name); mutex_unlock(&connector->eld_mutex); @@ -729,8 +733,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); - struct i915_audio_component *acomp = i915->display.audio.component; + struct intel_display *display = to_intel_display(encoder); + struct i915_audio_component *acomp = display->audio.component; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_connector *connector = to_intel_connector(conn_state->connector); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; @@ -740,26 +744,27 @@ void intel_audio_codec_enable(struct intel_encoder *encoder, if (!crtc_state->has_audio) return; - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n", + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n", connector->base.base.id, connector->base.name, encoder->base.base.id, encoder->base.name, crtc->base.base.id, crtc->base.name, drm_eld_size(crtc_state->eld)); - if (i915->display.funcs.audio) - i915->display.funcs.audio->audio_codec_enable(encoder, + if (display->funcs.audio) + display->funcs.audio->audio_codec_enable(encoder, crtc_state, conn_state); - mutex_lock(&i915->display.audio.mutex); + mutex_lock(&display->audio.mutex); - audio_state = &i915->display.audio.state[cpu_transcoder]; + audio_state = &display->audio.state[cpu_transcoder]; audio_state->encoder = encoder; BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld)); memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld)); - mutex_unlock(&i915->display.audio.mutex); + mutex_unlock(&display->audio.mutex); if (acomp && acomp->base.audio_ops && acomp->base.audio_ops->pin_eld_notify) { @@ -770,7 +775,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder, (int)port, (int)cpu_transcoder); } - intel_lpe_audio_notify(i915, cpu_transcoder, port, crtc_state->eld, + intel_lpe_audio_notify(display, cpu_transcoder, port, crtc_state->eld, crtc_state->port_clock, intel_crtc_has_dp_encoder(crtc_state)); } @@ -788,8 +793,8 @@ void intel_audio_codec_disable(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); - struct i915_audio_component *acomp = i915->display.audio.component; + struct intel_display *display = to_intel_display(encoder); + struct i915_audio_component *acomp = display->audio.component; struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); struct intel_connector *connector = to_intel_connector(old_conn_state->connector); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; @@ -799,24 +804,25 @@ void intel_audio_codec_disable(struct intel_encoder *encoder, if (!old_crtc_state->has_audio) return; - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n", + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n", connector->base.base.id, connector->base.name, encoder->base.base.id, encoder->base.name, crtc->base.base.id, crtc->base.name); - if (i915->display.funcs.audio) - i915->display.funcs.audio->audio_codec_disable(encoder, + if (display->funcs.audio) + display->funcs.audio->audio_codec_disable(encoder, old_crtc_state, old_conn_state); - mutex_lock(&i915->display.audio.mutex); + mutex_lock(&display->audio.mutex); - audio_state = &i915->display.audio.state[cpu_transcoder]; + audio_state = &display->audio.state[cpu_transcoder]; audio_state->encoder = NULL; memset(audio_state->eld, 0, sizeof(audio_state->eld)); - mutex_unlock(&i915->display.audio.mutex); + mutex_unlock(&display->audio.mutex); if (acomp && acomp->base.audio_ops && acomp->base.audio_ops->pin_eld_notify) { @@ -827,36 +833,36 @@ void intel_audio_codec_disable(struct intel_encoder *encoder, (int)port, (int)cpu_transcoder); } - intel_lpe_audio_notify(i915, cpu_transcoder, port, NULL, 0, false); + intel_lpe_audio_notify(display, cpu_transcoder, port, NULL, 0, false); } static void intel_acomp_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; struct intel_audio_state *audio_state; - mutex_lock(&i915->display.audio.mutex); + mutex_lock(&display->audio.mutex); - audio_state = &i915->display.audio.state[cpu_transcoder]; + audio_state = &display->audio.state[cpu_transcoder]; if (audio_state->encoder) memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld)); - mutex_unlock(&i915->display.audio.mutex); + mutex_unlock(&display->audio.mutex); } void intel_audio_codec_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); if (!crtc_state->has_audio) return; - if (i915->display.funcs.audio) - i915->display.funcs.audio->audio_codec_get_config(encoder, crtc_state); + if (display->funcs.audio) + display->funcs.audio->audio_codec_get_config(encoder, crtc_state); } static const struct intel_audio_funcs g4x_audio_funcs = { @@ -879,17 +885,19 @@ static const struct intel_audio_funcs hsw_audio_funcs = { /** * intel_audio_hooks_init - Set up chip specific audio hooks - * @i915: device private + * @display: display device */ -void intel_audio_hooks_init(struct drm_i915_private *i915) +void intel_audio_hooks_init(struct intel_display *display) { - if (IS_G4X(i915)) - i915->display.funcs.audio = &g4x_audio_funcs; - else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915) || + struct drm_i915_private *i915 = to_i915(display->drm); + + if (display->platform.g4x) + display->funcs.audio = &g4x_audio_funcs; + else if (display->platform.valleyview || display->platform.cherryview || HAS_PCH_CPT(i915) || HAS_PCH_IBX(i915)) - i915->display.funcs.audio = &ibx_audio_funcs; - else if (IS_HASWELL(i915) || DISPLAY_VER(i915) >= 8) - i915->display.funcs.audio = &hsw_audio_funcs; + display->funcs.audio = &ibx_audio_funcs; + else if (display->platform.haswell || DISPLAY_VER(display) >= 8) + display->funcs.audio = &hsw_audio_funcs; } struct aud_ts_cdclk_m_n { @@ -897,10 +905,10 @@ struct aud_ts_cdclk_m_n { u16 n; }; -void intel_audio_cdclk_change_pre(struct drm_i915_private *i915) +void intel_audio_cdclk_change_pre(struct intel_display *display) { - if (DISPLAY_VER(i915) >= 13) - intel_de_rmw(i915, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); + if (DISPLAY_VER(display) >= 13) + intel_de_rmw(display, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0); } static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts) @@ -909,16 +917,18 @@ static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n aud_ts->n = cdclk * aud_ts->m / 24000; } -void intel_audio_cdclk_change_post(struct drm_i915_private *i915) +void intel_audio_cdclk_change_post(struct intel_display *display) { struct aud_ts_cdclk_m_n aud_ts; - if (DISPLAY_VER(i915) >= 13) { - get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts); + if (DISPLAY_VER(display) >= 13) { + get_aud_ts_cdclk_m_n(display->cdclk.hw.ref, + display->cdclk.hw.cdclk, &aud_ts); - intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n); - intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); - drm_dbg_kms(&i915->drm, "aud_ts_cdclk set to M=%u, N=%u\n", aud_ts.m, aud_ts.n); + intel_de_write(display, AUD_TS_CDCLK_N, aud_ts.n); + intel_de_write(display, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); + drm_dbg_kms(display->drm, "aud_ts_cdclk set to M=%u, N=%u\n", + aud_ts.m, aud_ts.n); } } @@ -943,7 +953,7 @@ static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, return drm_atomic_commit(&state->base); } -static void glk_force_audio_cdclk(struct drm_i915_private *i915, +static void glk_force_audio_cdclk(struct intel_display *display, bool enable) { struct drm_modeset_acquire_ctx ctx; @@ -951,13 +961,13 @@ static void glk_force_audio_cdclk(struct drm_i915_private *i915, struct intel_crtc *crtc; int ret; - crtc = intel_first_crtc(i915); + crtc = intel_first_crtc(display); if (!crtc) return; drm_modeset_acquire_init(&ctx, 0); - state = drm_atomic_state_alloc(&i915->drm); - if (drm_WARN_ON(&i915->drm, !state)) + state = drm_atomic_state_alloc(display->drm); + if (drm_WARN_ON(display->drm, !state)) return; state->acquire_ctx = &ctx; @@ -972,7 +982,7 @@ retry: goto retry; } - drm_WARN_ON(&i915->drm, ret); + drm_WARN_ON(display->drm, ret); drm_atomic_state_put(state); @@ -983,7 +993,6 @@ retry: int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - struct drm_i915_private *dev_priv = to_i915(display->drm); int min_cdclk = 0; if (!crtc_state->has_audio) @@ -1000,7 +1009,7 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state) if (DISPLAY_VER(display) == 10) { /* Display WA #1145: glk */ min_cdclk = max(min_cdclk, 316800); - } else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) { + } else if (DISPLAY_VER(display) == 9 || display->platform.broadwell) { /* Display WA #1144: skl,bxt */ min_cdclk = max(min_cdclk, 432000); } @@ -1020,99 +1029,95 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state) * 270 | 320 or higher * 162 | 200 or higher" */ - if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + if ((display->platform.valleyview || display->platform.cherryview) && intel_crtc_has_dp_encoder(crtc_state)) min_cdclk = max(min_cdclk, crtc_state->port_clock); return min_cdclk; } -static unsigned long i915_audio_component_get_power(struct device *kdev) +static unsigned long intel_audio_component_get_power(struct device *kdev) { struct intel_display *display = to_intel_display(kdev); - struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref; /* Catch potential impedance mismatches before they occur! */ BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); - wakeref = intel_display_power_get(i915, POWER_DOMAIN_AUDIO_PLAYBACK); + wakeref = intel_display_power_get(display, POWER_DOMAIN_AUDIO_PLAYBACK); - if (i915->display.audio.power_refcount++ == 0) { - if (DISPLAY_VER(i915) >= 9) { - intel_de_write(i915, AUD_FREQ_CNTRL, - i915->display.audio.freq_cntrl); - drm_dbg_kms(&i915->drm, + if (display->audio.power_refcount++ == 0) { + if (DISPLAY_VER(display) >= 9) { + intel_de_write(display, AUD_FREQ_CNTRL, + display->audio.freq_cntrl); + drm_dbg_kms(display->drm, "restored AUD_FREQ_CNTRL to 0x%x\n", - i915->display.audio.freq_cntrl); + display->audio.freq_cntrl); } /* Force CDCLK to 2*BCLK as long as we need audio powered. */ - if (IS_GEMINILAKE(i915)) - glk_force_audio_cdclk(i915, true); + if (display->platform.geminilake) + glk_force_audio_cdclk(display, true); - if (DISPLAY_VER(i915) >= 10) - intel_de_rmw(i915, AUD_PIN_BUF_CTL, + if (DISPLAY_VER(display) >= 10) + intel_de_rmw(display, AUD_PIN_BUF_CTL, 0, AUD_PIN_BUF_ENABLE); } return (unsigned long)wakeref; } -static void i915_audio_component_put_power(struct device *kdev, - unsigned long cookie) +static void intel_audio_component_put_power(struct device *kdev, + unsigned long cookie) { struct intel_display *display = to_intel_display(kdev); - struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref = (intel_wakeref_t)cookie; /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ - if (--i915->display.audio.power_refcount == 0) - if (IS_GEMINILAKE(i915)) - glk_force_audio_cdclk(i915, false); + if (--display->audio.power_refcount == 0) + if (display->platform.geminilake) + glk_force_audio_cdclk(display, false); - intel_display_power_put(i915, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref); + intel_display_power_put(display, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref); } -static void i915_audio_component_codec_wake_override(struct device *kdev, - bool enable) +static void intel_audio_component_codec_wake_override(struct device *kdev, + bool enable) { struct intel_display *display = to_intel_display(kdev); - struct drm_i915_private *i915 = to_i915(display->drm); unsigned long cookie; - if (DISPLAY_VER(i915) < 9) + if (DISPLAY_VER(display) < 9) return; - cookie = i915_audio_component_get_power(kdev); + cookie = intel_audio_component_get_power(kdev); /* * Enable/disable generating the codec wake signal, overriding the * internal logic to generate the codec wake to controller. */ - intel_de_rmw(i915, HSW_AUD_CHICKENBIT, + intel_de_rmw(display, HSW_AUD_CHICKENBIT, SKL_AUD_CODEC_WAKE_SIGNAL, 0); usleep_range(1000, 1500); if (enable) { - intel_de_rmw(i915, HSW_AUD_CHICKENBIT, + intel_de_rmw(display, HSW_AUD_CHICKENBIT, 0, SKL_AUD_CODEC_WAKE_SIGNAL); usleep_range(1000, 1500); } - i915_audio_component_put_power(kdev, cookie); + intel_audio_component_put_power(kdev, cookie); } /* Get CDCLK in kHz */ -static int i915_audio_component_get_cdclk_freq(struct device *kdev) +static int intel_audio_component_get_cdclk_freq(struct device *kdev) { struct intel_display *display = to_intel_display(kdev); - struct drm_i915_private *i915 = to_i915(display->drm); - if (drm_WARN_ON_ONCE(&i915->drm, !HAS_DDI(i915))) + if (drm_WARN_ON_ONCE(display->drm, !HAS_DDI(display))) return -ENODEV; - return i915->display.cdclk.hw.cdclk; + return display->cdclk.hw.cdclk; } /* @@ -1124,7 +1129,7 @@ static int i915_audio_component_get_cdclk_freq(struct device *kdev) * will get the right intel_encoder with port matched * Non-MST & (cpu_transcoder < 0): get the right intel_encoder with port matched */ -static struct intel_audio_state *find_audio_state(struct drm_i915_private *i915, +static struct intel_audio_state *find_audio_state(struct intel_display *display, int port, int cpu_transcoder) { /* MST */ @@ -1132,11 +1137,11 @@ static struct intel_audio_state *find_audio_state(struct drm_i915_private *i915, struct intel_audio_state *audio_state; struct intel_encoder *encoder; - if (drm_WARN_ON(&i915->drm, - cpu_transcoder >= ARRAY_SIZE(i915->display.audio.state))) + if (drm_WARN_ON(display->drm, + cpu_transcoder >= ARRAY_SIZE(display->audio.state))) return NULL; - audio_state = &i915->display.audio.state[cpu_transcoder]; + audio_state = &display->audio.state[cpu_transcoder]; encoder = audio_state->encoder; if (encoder && encoder->port == port && @@ -1148,11 +1153,11 @@ static struct intel_audio_state *find_audio_state(struct drm_i915_private *i915, if (cpu_transcoder > 0) return NULL; - for_each_cpu_transcoder(i915, cpu_transcoder) { + for_each_cpu_transcoder(display, cpu_transcoder) { struct intel_audio_state *audio_state; struct intel_encoder *encoder; - audio_state = &i915->display.audio.state[cpu_transcoder]; + audio_state = &display->audio.state[cpu_transcoder]; encoder = audio_state->encoder; if (encoder && encoder->port == port && @@ -1163,27 +1168,27 @@ static struct intel_audio_state *find_audio_state(struct drm_i915_private *i915, return NULL; } -static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, - int cpu_transcoder, int rate) +static int intel_audio_component_sync_audio_rate(struct device *kdev, int port, + int cpu_transcoder, int rate) { struct intel_display *display = to_intel_display(kdev); - struct drm_i915_private *i915 = to_i915(display->drm); - struct i915_audio_component *acomp = i915->display.audio.component; + struct i915_audio_component *acomp = display->audio.component; const struct intel_audio_state *audio_state; struct intel_encoder *encoder; struct intel_crtc *crtc; unsigned long cookie; int err = 0; - if (!HAS_DDI(i915)) + if (!HAS_DDI(display)) return 0; - cookie = i915_audio_component_get_power(kdev); - mutex_lock(&i915->display.audio.mutex); + cookie = intel_audio_component_get_power(kdev); + mutex_lock(&display->audio.mutex); - audio_state = find_audio_state(i915, port, cpu_transcoder); + audio_state = find_audio_state(display, port, cpu_transcoder); if (!audio_state) { - drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port)); + drm_dbg_kms(display->drm, "Not valid for port %c\n", + port_name(port)); err = -ENODEV; goto unlock; } @@ -1200,26 +1205,26 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, hsw_audio_config_update(encoder, crtc->config); unlock: - mutex_unlock(&i915->display.audio.mutex); - i915_audio_component_put_power(kdev, cookie); + mutex_unlock(&display->audio.mutex); + intel_audio_component_put_power(kdev, cookie); return err; } -static int i915_audio_component_get_eld(struct device *kdev, int port, - int cpu_transcoder, bool *enabled, - unsigned char *buf, int max_bytes) +static int intel_audio_component_get_eld(struct device *kdev, int port, + int cpu_transcoder, bool *enabled, + unsigned char *buf, int max_bytes) { struct intel_display *display = to_intel_display(kdev); - struct drm_i915_private *i915 = to_i915(display->drm); const struct intel_audio_state *audio_state; int ret = 0; - mutex_lock(&i915->display.audio.mutex); + mutex_lock(&display->audio.mutex); - audio_state = find_audio_state(i915, port, cpu_transcoder); + audio_state = find_audio_state(display, port, cpu_transcoder); if (!audio_state) { - drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port)); - mutex_unlock(&i915->display.audio.mutex); + drm_dbg_kms(display->drm, "Not valid for port %c\n", + port_name(port)); + mutex_unlock(&display->audio.mutex); return -EINVAL; } @@ -1231,71 +1236,70 @@ static int i915_audio_component_get_eld(struct device *kdev, int port, memcpy(buf, eld, min(max_bytes, ret)); } - mutex_unlock(&i915->display.audio.mutex); + mutex_unlock(&display->audio.mutex); return ret; } -static const struct drm_audio_component_ops i915_audio_component_ops = { - .owner = THIS_MODULE, - .get_power = i915_audio_component_get_power, - .put_power = i915_audio_component_put_power, - .codec_wake_override = i915_audio_component_codec_wake_override, - .get_cdclk_freq = i915_audio_component_get_cdclk_freq, - .sync_audio_rate = i915_audio_component_sync_audio_rate, - .get_eld = i915_audio_component_get_eld, +static const struct drm_audio_component_ops intel_audio_component_ops = { + .owner = THIS_MODULE, + .get_power = intel_audio_component_get_power, + .put_power = intel_audio_component_put_power, + .codec_wake_override = intel_audio_component_codec_wake_override, + .get_cdclk_freq = intel_audio_component_get_cdclk_freq, + .sync_audio_rate = intel_audio_component_sync_audio_rate, + .get_eld = intel_audio_component_get_eld, }; -static int i915_audio_component_bind(struct device *drv_kdev, - struct device *hda_kdev, void *data) +static int intel_audio_component_bind(struct device *drv_kdev, + struct device *hda_kdev, void *data) { struct intel_display *display = to_intel_display(drv_kdev); - struct drm_i915_private *i915 = to_i915(display->drm); struct i915_audio_component *acomp = data; int i; - if (drm_WARN_ON(&i915->drm, acomp->base.ops || acomp->base.dev)) + if (drm_WARN_ON(display->drm, acomp->base.ops || acomp->base.dev)) return -EEXIST; - if (drm_WARN_ON(&i915->drm, + if (drm_WARN_ON(display->drm, !device_link_add(hda_kdev, drv_kdev, DL_FLAG_STATELESS))) return -ENOMEM; - drm_modeset_lock_all(&i915->drm); - acomp->base.ops = &i915_audio_component_ops; + drm_modeset_lock_all(display->drm); + acomp->base.ops = &intel_audio_component_ops; acomp->base.dev = drv_kdev; BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) acomp->aud_sample_rate[i] = 0; - i915->display.audio.component = acomp; - drm_modeset_unlock_all(&i915->drm); + display->audio.component = acomp; + drm_modeset_unlock_all(display->drm); return 0; } -static void i915_audio_component_unbind(struct device *drv_kdev, - struct device *hda_kdev, void *data) +static void intel_audio_component_unbind(struct device *drv_kdev, + struct device *hda_kdev, void *data) { struct intel_display *display = to_intel_display(drv_kdev); - struct drm_i915_private *i915 = to_i915(display->drm); struct i915_audio_component *acomp = data; - drm_modeset_lock_all(&i915->drm); + drm_modeset_lock_all(display->drm); acomp->base.ops = NULL; acomp->base.dev = NULL; - i915->display.audio.component = NULL; - drm_modeset_unlock_all(&i915->drm); + display->audio.component = NULL; + drm_modeset_unlock_all(display->drm); device_link_remove(hda_kdev, drv_kdev); - if (i915->display.audio.power_refcount) - drm_err(&i915->drm, "audio power refcount %d after unbind\n", - i915->display.audio.power_refcount); + if (display->audio.power_refcount) + drm_err(display->drm, + "audio power refcount %d after unbind\n", + display->audio.power_refcount); } -static const struct component_ops i915_audio_component_bind_ops = { - .bind = i915_audio_component_bind, - .unbind = i915_audio_component_unbind, +static const struct component_ops intel_audio_component_bind_ops = { + .bind = intel_audio_component_bind, + .unbind = intel_audio_component_unbind, }; #define AUD_FREQ_TMODE_SHIFT 14 @@ -1308,8 +1312,8 @@ static const struct component_ops i915_audio_component_bind_ops = { #define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M) /** - * i915_audio_component_init - initialize and register the audio component - * @i915: i915 device instance + * intel_audio_component_init - initialize and register the audio component + * @display: display device * * This will register with the component framework a child component which * will bind dynamically to the snd_hda_intel driver's corresponding master @@ -1323,93 +1327,93 @@ static const struct component_ops i915_audio_component_bind_ops = { * We ignore any error during registration and continue with reduced * functionality (i.e. without HDMI audio). */ -static void i915_audio_component_init(struct drm_i915_private *i915) +static void intel_audio_component_init(struct intel_display *display) { u32 aud_freq, aud_freq_init; - if (DISPLAY_VER(i915) >= 9) { - aud_freq_init = intel_de_read(i915, AUD_FREQ_CNTRL); + if (DISPLAY_VER(display) >= 9) { + aud_freq_init = intel_de_read(display, AUD_FREQ_CNTRL); - if (DISPLAY_VER(i915) >= 12) + if (DISPLAY_VER(display) >= 12) aud_freq = AUD_FREQ_GEN12; else aud_freq = aud_freq_init; /* use BIOS provided value for TGL and RKL unless it is a known bad value */ - if ((IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) && + if ((display->platform.tigerlake || display->platform.rocketlake) && aud_freq_init != AUD_FREQ_TGL_BROKEN) aud_freq = aud_freq_init; - drm_dbg_kms(&i915->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", + drm_dbg_kms(display->drm, + "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n", aud_freq, aud_freq_init); - i915->display.audio.freq_cntrl = aud_freq; + display->audio.freq_cntrl = aud_freq; } /* init with current cdclk */ - intel_audio_cdclk_change_post(i915); + intel_audio_cdclk_change_post(display); } -static void i915_audio_component_register(struct drm_i915_private *i915) +static void intel_audio_component_register(struct intel_display *display) { int ret; - ret = component_add_typed(i915->drm.dev, - &i915_audio_component_bind_ops, + ret = component_add_typed(display->drm->dev, + &intel_audio_component_bind_ops, I915_COMPONENT_AUDIO); if (ret < 0) { - drm_err(&i915->drm, + drm_err(display->drm, "failed to add audio component (%d)\n", ret); /* continue with reduced functionality */ return; } - i915->display.audio.component_registered = true; + display->audio.component_registered = true; } /** - * i915_audio_component_cleanup - deregister the audio component - * @i915: i915 device instance + * intel_audio_component_cleanup - deregister the audio component + * @display: display device * * Deregisters the audio component, breaking any existing binding to the * corresponding snd_hda_intel driver's master component. */ -static void i915_audio_component_cleanup(struct drm_i915_private *i915) +static void intel_audio_component_cleanup(struct intel_display *display) { - if (!i915->display.audio.component_registered) + if (!display->audio.component_registered) return; - component_del(i915->drm.dev, &i915_audio_component_bind_ops); - i915->display.audio.component_registered = false; + component_del(display->drm->dev, &intel_audio_component_bind_ops); + display->audio.component_registered = false; } /** * intel_audio_init() - Initialize the audio driver either using * component framework or using lpe audio bridge - * @i915: the i915 drm device private data + * @display: display device * */ -void intel_audio_init(struct drm_i915_private *i915) +void intel_audio_init(struct intel_display *display) { - if (intel_lpe_audio_init(i915) < 0) - i915_audio_component_init(i915); + if (intel_lpe_audio_init(display) < 0) + intel_audio_component_init(display); } -void intel_audio_register(struct drm_i915_private *i915) +void intel_audio_register(struct intel_display *display) { - if (!i915->display.audio.lpe.platdev) - i915_audio_component_register(i915); + if (!display->audio.lpe.platdev) + intel_audio_component_register(display); } /** * intel_audio_deinit() - deinitialize the audio driver - * @i915: the i915 drm device private data - * + * @display: display device */ -void intel_audio_deinit(struct drm_i915_private *i915) +void intel_audio_deinit(struct intel_display *display) { - if (i915->display.audio.lpe.platdev != NULL) - intel_lpe_audio_teardown(i915); + if (display->audio.lpe.platdev) + intel_lpe_audio_teardown(display); else - i915_audio_component_cleanup(i915); + intel_audio_component_cleanup(display); } diff --git a/drivers/gpu/drm/i915/display/intel_audio.h b/drivers/gpu/drm/i915/display/intel_audio.h index 1bafc155434a..ad49eefa7182 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.h +++ b/drivers/gpu/drm/i915/display/intel_audio.h @@ -9,11 +9,11 @@ #include <linux/types.h> struct drm_connector_state; -struct drm_i915_private; struct intel_crtc_state; +struct intel_display; struct intel_encoder; -void intel_audio_hooks_init(struct drm_i915_private *dev_priv); +void intel_audio_hooks_init(struct intel_display *display); bool intel_audio_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state); @@ -25,12 +25,12 @@ void intel_audio_codec_disable(struct intel_encoder *encoder, const struct drm_connector_state *old_conn_state); void intel_audio_codec_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state); -void intel_audio_cdclk_change_pre(struct drm_i915_private *dev_priv); -void intel_audio_cdclk_change_post(struct drm_i915_private *dev_priv); +void intel_audio_cdclk_change_pre(struct intel_display *display); +void intel_audio_cdclk_change_post(struct intel_display *display); int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state); -void intel_audio_init(struct drm_i915_private *dev_priv); -void intel_audio_register(struct drm_i915_private *i915); -void intel_audio_deinit(struct drm_i915_private *dev_priv); +void intel_audio_init(struct intel_display *display); +void intel_audio_register(struct intel_display *display); +void intel_audio_deinit(struct intel_display *display); void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_AUDIO_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c index fc1e517e074a..178dc6c8de80 100644 --- a/drivers/gpu/drm/i915/display/intel_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_backlight.c @@ -41,8 +41,9 @@ static u32 scale(u32 source_val, { u64 target_val; - WARN_ON(source_min > source_max); - WARN_ON(target_min > target_max); + if (WARN_ON(source_min >= source_max) || + WARN_ON(target_min > target_max)) + return target_min; /* defensive */ source_val = clamp(source_val, source_min, source_max); @@ -103,20 +104,20 @@ u32 intel_backlight_invert_pwm_level(struct intel_connector *connector, u32 val) void intel_backlight_set_pwm_level(const struct drm_connector_state *conn_state, u32 val) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] set backlight PWM = %d\n", + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] set backlight PWM = %d\n", connector->base.base.id, connector->base.name, val); panel->backlight.pwm_funcs->set(conn_state, val); } u32 intel_backlight_level_to_pwm(struct intel_connector *connector, u32 val) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; - drm_WARN_ON_ONCE(&i915->drm, + drm_WARN_ON_ONCE(display->drm, panel->backlight.max == 0 || panel->backlight.pwm_level_max == 0); val = scale(val, panel->backlight.min, panel->backlight.max, @@ -144,32 +145,33 @@ u32 intel_backlight_level_from_pwm(struct intel_connector *connector, u32 val) static u32 lpt_get_backlight(struct intel_connector *connector, enum pipe unused) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); - return intel_de_read(i915, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; + return intel_de_read(display, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; } static u32 pch_get_backlight(struct intel_connector *connector, enum pipe unused) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); - return intel_de_read(i915, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; + return intel_de_read(display, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; } static u32 i9xx_get_backlight(struct intel_connector *connector, enum pipe unused) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 val; - val = intel_de_read(i915, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; - if (DISPLAY_VER(i915) < 4) + val = intel_de_read(display, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; + if (DISPLAY_VER(display) < 4) val >>= 1; if (panel->backlight.combination_mode) { + struct pci_dev *pdev = to_pci_dev(display->drm->dev); u8 lbpc; - pci_read_config_byte(to_pci_dev(i915->drm.dev), LBPC, &lbpc); + pci_read_config_byte(pdev, LBPC, &lbpc); val *= lbpc; } @@ -178,20 +180,20 @@ static u32 i9xx_get_backlight(struct intel_connector *connector, enum pipe unuse static u32 vlv_get_backlight(struct intel_connector *connector, enum pipe pipe) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); - if (drm_WARN_ON(&i915->drm, pipe != PIPE_A && pipe != PIPE_B)) + if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B)) return 0; - return intel_de_read(i915, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; + return intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; } static u32 bxt_get_backlight(struct intel_connector *connector, enum pipe unused) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; - return intel_de_read(i915, BXT_BLC_PWM_DUTY(panel->backlight.controller)); + return intel_de_read(display, BXT_BLC_PWM_DUTY(panel->backlight.controller)); } static u32 ext_pwm_get_backlight(struct intel_connector *connector, enum pipe unused) @@ -206,69 +208,70 @@ static u32 ext_pwm_get_backlight(struct intel_connector *connector, enum pipe un static void lpt_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); u32 val; - val = intel_de_read(i915, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; - intel_de_write(i915, BLC_PWM_PCH_CTL2, val | level); + val = intel_de_read(display, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; + intel_de_write(display, BLC_PWM_PCH_CTL2, val | level); } static void pch_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); u32 tmp; - tmp = intel_de_read(i915, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; - intel_de_write(i915, BLC_PWM_CPU_CTL, tmp | level); + tmp = intel_de_read(display, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; + intel_de_write(display, BLC_PWM_CPU_CTL, tmp | level); } static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 tmp, mask; - drm_WARN_ON(&i915->drm, panel->backlight.pwm_level_max == 0); + drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0); if (panel->backlight.combination_mode) { + struct pci_dev *pdev = to_pci_dev(display->drm->dev); u8 lbpc; lbpc = level * 0xfe / panel->backlight.pwm_level_max + 1; level /= lbpc; - pci_write_config_byte(to_pci_dev(i915->drm.dev), LBPC, lbpc); + pci_write_config_byte(pdev, LBPC, lbpc); } - if (DISPLAY_VER(i915) == 4) { + if (DISPLAY_VER(display) == 4) { mask = BACKLIGHT_DUTY_CYCLE_MASK; } else { level <<= 1; mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV; } - tmp = intel_de_read(i915, BLC_PWM_CTL) & ~mask; - intel_de_write(i915, BLC_PWM_CTL, tmp | level); + tmp = intel_de_read(display, BLC_PWM_CTL) & ~mask; + intel_de_write(display, BLC_PWM_CTL, tmp | level); } static void vlv_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); enum pipe pipe = to_intel_crtc(conn_state->crtc)->pipe; u32 tmp; - tmp = intel_de_read(i915, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; - intel_de_write(i915, VLV_BLC_PWM_CTL(pipe), tmp | level); + tmp = intel_de_read(display, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; + intel_de_write(display, VLV_BLC_PWM_CTL(pipe), tmp | level); } static void bxt_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; - intel_de_write(i915, BXT_BLC_PWM_DUTY(panel->backlight.controller), level); + intel_de_write(display, BXT_BLC_PWM_DUTY(panel->backlight.controller), level); } static void ext_pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level) @@ -283,10 +286,10 @@ static void intel_panel_actually_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] set backlight level = %d\n", + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] set backlight level = %d\n", connector->base.base.id, connector->base.name, level); panel->backlight.funcs->set(conn_state, level); @@ -299,7 +302,7 @@ void intel_backlight_set_acpi(const struct drm_connector_state *conn_state, u32 user_level, u32 user_max) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 hw_level; @@ -312,9 +315,9 @@ void intel_backlight_set_acpi(const struct drm_connector_state *conn_state, if (!panel->backlight.present || !conn_state->crtc) return; - mutex_lock(&i915->display.backlight.lock); + mutex_lock(&display->backlight.lock); - drm_WARN_ON(&i915->drm, panel->backlight.max == 0); + drm_WARN_ON(display->drm, panel->backlight.max == 0); hw_level = clamp_user_to_hw(connector, user_level, user_max); panel->backlight.level = hw_level; @@ -328,13 +331,13 @@ void intel_backlight_set_acpi(const struct drm_connector_state *conn_state, if (panel->backlight.enabled) intel_panel_actually_set_backlight(conn_state, hw_level); - mutex_unlock(&i915->display.backlight.lock); + mutex_unlock(&display->backlight.lock); } static void lpt_disable_backlight(const struct drm_connector_state *old_conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(old_conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); u32 tmp; intel_backlight_set_pwm_level(old_conn_state, level); @@ -347,26 +350,26 @@ static void lpt_disable_backlight(const struct drm_connector_state *old_conn_sta * This needs rework if we need to add support for CPU PWM on PCH split * platforms. */ - tmp = intel_de_read(i915, BLC_PWM_CPU_CTL2); + tmp = intel_de_read(display, BLC_PWM_CPU_CTL2); if (tmp & BLM_PWM_ENABLE) { - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] CPU backlight was enabled, disabling\n", + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] CPU backlight was enabled, disabling\n", connector->base.base.id, connector->base.name); - intel_de_write(i915, BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); + intel_de_write(display, BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); } - intel_de_rmw(i915, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0); + intel_de_rmw(display, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0); } static void pch_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val) { struct intel_connector *connector = to_intel_connector(old_conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); intel_backlight_set_pwm_level(old_conn_state, val); - intel_de_rmw(i915, BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE, 0); + intel_de_rmw(display, BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE, 0); - intel_de_rmw(i915, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0); + intel_de_rmw(display, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0); } static void i9xx_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val) @@ -376,48 +379,49 @@ static void i9xx_disable_backlight(const struct drm_connector_state *old_conn_st static void i965_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val) { - struct drm_i915_private *i915 = to_i915(old_conn_state->connector->dev); + struct intel_connector *connector = to_intel_connector(old_conn_state->connector); + struct intel_display *display = to_intel_display(connector); intel_backlight_set_pwm_level(old_conn_state, val); - intel_de_rmw(i915, BLC_PWM_CTL2, BLM_PWM_ENABLE, 0); + intel_de_rmw(display, BLC_PWM_CTL2, BLM_PWM_ENABLE, 0); } static void vlv_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val) { struct intel_connector *connector = to_intel_connector(old_conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); enum pipe pipe = to_intel_crtc(old_conn_state->crtc)->pipe; intel_backlight_set_pwm_level(old_conn_state, val); - intel_de_rmw(i915, VLV_BLC_PWM_CTL2(pipe), BLM_PWM_ENABLE, 0); + intel_de_rmw(display, VLV_BLC_PWM_CTL2(pipe), BLM_PWM_ENABLE, 0); } static void bxt_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val) { struct intel_connector *connector = to_intel_connector(old_conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; intel_backlight_set_pwm_level(old_conn_state, val); - intel_de_rmw(i915, BXT_BLC_PWM_CTL(panel->backlight.controller), + intel_de_rmw(display, BXT_BLC_PWM_CTL(panel->backlight.controller), BXT_BLC_PWM_ENABLE, 0); if (panel->backlight.controller == 1) - intel_de_rmw(i915, UTIL_PIN_CTL, UTIL_PIN_ENABLE, 0); + intel_de_rmw(display, UTIL_PIN_CTL, UTIL_PIN_ENABLE, 0); } static void cnp_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val) { struct intel_connector *connector = to_intel_connector(old_conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; intel_backlight_set_pwm_level(old_conn_state, val); - intel_de_rmw(i915, BXT_BLC_PWM_CTL(panel->backlight.controller), + intel_de_rmw(display, BXT_BLC_PWM_CTL(panel->backlight.controller), BXT_BLC_PWM_ENABLE, 0); } @@ -435,7 +439,7 @@ static void ext_pwm_disable_backlight(const struct drm_connector_state *old_conn void intel_backlight_disable(const struct drm_connector_state *old_conn_state) { struct intel_connector *connector = to_intel_connector(old_conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; if (!panel->backlight.present) @@ -447,49 +451,51 @@ void intel_backlight_disable(const struct drm_connector_state *old_conn_state) * backlight. This will leave the backlight on unnecessarily when * another client is not activated. */ - if (i915->drm.switch_power_state == DRM_SWITCH_POWER_CHANGING) { - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Skipping backlight disable on vga switch\n", + if (display->drm->switch_power_state == DRM_SWITCH_POWER_CHANGING) { + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Skipping backlight disable on vga switch\n", connector->base.base.id, connector->base.name); return; } - mutex_lock(&i915->display.backlight.lock); + mutex_lock(&display->backlight.lock); if (panel->backlight.device) panel->backlight.device->props.power = BACKLIGHT_POWER_OFF; panel->backlight.enabled = false; panel->backlight.funcs->disable(old_conn_state, 0); - mutex_unlock(&i915->display.backlight.lock); + mutex_unlock(&display->backlight.lock); } static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct intel_display *display = to_intel_display(connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_panel *panel = &connector->panel; u32 pch_ctl1, pch_ctl2; - pch_ctl1 = intel_de_read(i915, BLC_PWM_PCH_CTL1); + pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1); if (pch_ctl1 & BLM_PCH_PWM_ENABLE) { - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] PCH backlight already enabled\n", + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] PCH backlight already enabled\n", connector->base.base.id, connector->base.name); pch_ctl1 &= ~BLM_PCH_PWM_ENABLE; - intel_de_write(i915, BLC_PWM_PCH_CTL1, pch_ctl1); + intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1); } if (HAS_PCH_LPT(i915)) - intel_de_rmw(i915, SOUTH_CHICKEN2, LPT_PWM_GRANULARITY, + intel_de_rmw(display, SOUTH_CHICKEN2, LPT_PWM_GRANULARITY, panel->backlight.alternate_pwm_increment ? LPT_PWM_GRANULARITY : 0); else - intel_de_rmw(i915, SOUTH_CHICKEN1, SPT_PWM_GRANULARITY, + intel_de_rmw(display, SOUTH_CHICKEN1, SPT_PWM_GRANULARITY, panel->backlight.alternate_pwm_increment ? SPT_PWM_GRANULARITY : 0); pch_ctl2 = panel->backlight.pwm_level_max << 16; - intel_de_write(i915, BLC_PWM_PCH_CTL2, pch_ctl2); + intel_de_write(display, BLC_PWM_PCH_CTL2, pch_ctl2); pch_ctl1 = 0; if (panel->backlight.active_low_pwm) @@ -499,9 +505,9 @@ static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state, if (HAS_PCH_LPT(i915)) pch_ctl1 |= BLM_PCH_OVERRIDE_ENABLE; - intel_de_write(i915, BLC_PWM_PCH_CTL1, pch_ctl1); - intel_de_posting_read(i915, BLC_PWM_PCH_CTL1); - intel_de_write(i915, BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); + intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1); + intel_de_posting_read(display, BLC_PWM_PCH_CTL1); + intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); /* This won't stick until the above enable. */ intel_backlight_set_pwm_level(conn_state, level); @@ -511,63 +517,66 @@ static void pch_enable_backlight(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 cpu_ctl2, pch_ctl1, pch_ctl2; - cpu_ctl2 = intel_de_read(i915, BLC_PWM_CPU_CTL2); + cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2); if (cpu_ctl2 & BLM_PWM_ENABLE) { - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] CPU backlight already enabled\n", + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] CPU backlight already enabled\n", connector->base.base.id, connector->base.name); cpu_ctl2 &= ~BLM_PWM_ENABLE; - intel_de_write(i915, BLC_PWM_CPU_CTL2, cpu_ctl2); + intel_de_write(display, BLC_PWM_CPU_CTL2, cpu_ctl2); } - pch_ctl1 = intel_de_read(i915, BLC_PWM_PCH_CTL1); + pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1); if (pch_ctl1 & BLM_PCH_PWM_ENABLE) { - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] PCH backlight already enabled\n", + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] PCH backlight already enabled\n", connector->base.base.id, connector->base.name); pch_ctl1 &= ~BLM_PCH_PWM_ENABLE; - intel_de_write(i915, BLC_PWM_PCH_CTL1, pch_ctl1); + intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1); } if (cpu_transcoder == TRANSCODER_EDP) cpu_ctl2 = BLM_TRANSCODER_EDP; else cpu_ctl2 = BLM_PIPE(cpu_transcoder); - intel_de_write(i915, BLC_PWM_CPU_CTL2, cpu_ctl2); - intel_de_posting_read(i915, BLC_PWM_CPU_CTL2); - intel_de_write(i915, BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE); + intel_de_write(display, BLC_PWM_CPU_CTL2, cpu_ctl2); + intel_de_posting_read(display, BLC_PWM_CPU_CTL2); + intel_de_write(display, BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE); /* This won't stick until the above enable. */ intel_backlight_set_pwm_level(conn_state, level); pch_ctl2 = panel->backlight.pwm_level_max << 16; - intel_de_write(i915, BLC_PWM_PCH_CTL2, pch_ctl2); + intel_de_write(display, BLC_PWM_PCH_CTL2, pch_ctl2); pch_ctl1 = 0; if (panel->backlight.active_low_pwm) pch_ctl1 |= BLM_PCH_POLARITY; - intel_de_write(i915, BLC_PWM_PCH_CTL1, pch_ctl1); - intel_de_posting_read(i915, BLC_PWM_PCH_CTL1); - intel_de_write(i915, BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); + intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1); + intel_de_posting_read(display, BLC_PWM_PCH_CTL1); + intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); } static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 ctl, freq; - ctl = intel_de_read(i915, BLC_PWM_CTL); + ctl = intel_de_read(display, BLC_PWM_CTL); if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) { - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] backlight already enabled\n", + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] backlight already enabled\n", connector->base.base.id, connector->base.name); - intel_de_write(i915, BLC_PWM_CTL, 0); + intel_de_write(display, BLC_PWM_CTL, 0); } freq = panel->backlight.pwm_level_max; @@ -577,11 +586,11 @@ static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state, ctl = freq << 17; if (panel->backlight.combination_mode) ctl |= BLM_LEGACY_MODE; - if (IS_PINEVIEW(i915) && panel->backlight.active_low_pwm) + if (display->platform.pineview && panel->backlight.active_low_pwm) ctl |= BLM_POLARITY_PNV; - intel_de_write(i915, BLC_PWM_CTL, ctl); - intel_de_posting_read(i915, BLC_PWM_CTL); + intel_de_write(display, BLC_PWM_CTL, ctl); + intel_de_posting_read(display, BLC_PWM_CTL); /* XXX: combine this into above write? */ intel_backlight_set_pwm_level(conn_state, level); @@ -591,25 +600,26 @@ static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state, * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2 * that has backlight. */ - if (DISPLAY_VER(i915) == 2) - intel_de_write(i915, BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); + if (DISPLAY_VER(display) == 2) + intel_de_write(display, BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); } static void i965_enable_backlight(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; enum pipe pipe = to_intel_crtc(conn_state->crtc)->pipe; u32 ctl, ctl2, freq; - ctl2 = intel_de_read(i915, BLC_PWM_CTL2); + ctl2 = intel_de_read(display, BLC_PWM_CTL2); if (ctl2 & BLM_PWM_ENABLE) { - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] backlight already enabled\n", + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] backlight already enabled\n", connector->base.base.id, connector->base.name); ctl2 &= ~BLM_PWM_ENABLE; - intel_de_write(i915, BLC_PWM_CTL2, ctl2); + intel_de_write(display, BLC_PWM_CTL2, ctl2); } freq = panel->backlight.pwm_level_max; @@ -617,16 +627,16 @@ static void i965_enable_backlight(const struct intel_crtc_state *crtc_state, freq /= 0xff; ctl = freq << 16; - intel_de_write(i915, BLC_PWM_CTL, ctl); + intel_de_write(display, BLC_PWM_CTL, ctl); ctl2 = BLM_PIPE(pipe); if (panel->backlight.combination_mode) ctl2 |= BLM_COMBINATION_MODE; if (panel->backlight.active_low_pwm) ctl2 |= BLM_POLARITY_I965; - intel_de_write(i915, BLC_PWM_CTL2, ctl2); - intel_de_posting_read(i915, BLC_PWM_CTL2); - intel_de_write(i915, BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); + intel_de_write(display, BLC_PWM_CTL2, ctl2); + intel_de_posting_read(display, BLC_PWM_CTL2); + intel_de_write(display, BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); intel_backlight_set_pwm_level(conn_state, level); } @@ -635,21 +645,22 @@ static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; u32 ctl, ctl2; - ctl2 = intel_de_read(i915, VLV_BLC_PWM_CTL2(pipe)); + ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe)); if (ctl2 & BLM_PWM_ENABLE) { - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] backlight already enabled\n", + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] backlight already enabled\n", connector->base.base.id, connector->base.name); ctl2 &= ~BLM_PWM_ENABLE; - intel_de_write(i915, VLV_BLC_PWM_CTL2(pipe), ctl2); + intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2); } ctl = panel->backlight.pwm_level_max << 16; - intel_de_write(i915, VLV_BLC_PWM_CTL(pipe), ctl); + intel_de_write(display, VLV_BLC_PWM_CTL(pipe), ctl); /* XXX: combine this into above write? */ intel_backlight_set_pwm_level(conn_state, level); @@ -657,47 +668,49 @@ static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state, ctl2 = 0; if (panel->backlight.active_low_pwm) ctl2 |= BLM_POLARITY_I965; - intel_de_write(i915, VLV_BLC_PWM_CTL2(pipe), ctl2); - intel_de_posting_read(i915, VLV_BLC_PWM_CTL2(pipe)); - intel_de_write(i915, VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE); + intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2); + intel_de_posting_read(display, VLV_BLC_PWM_CTL2(pipe)); + intel_de_write(display, VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE); } static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; u32 pwm_ctl, val; /* Controller 1 uses the utility pin. */ if (panel->backlight.controller == 1) { - val = intel_de_read(i915, UTIL_PIN_CTL); + val = intel_de_read(display, UTIL_PIN_CTL); if (val & UTIL_PIN_ENABLE) { - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] utility pin already enabled\n", + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] utility pin already enabled\n", connector->base.base.id, connector->base.name); val &= ~UTIL_PIN_ENABLE; - intel_de_write(i915, UTIL_PIN_CTL, val); + intel_de_write(display, UTIL_PIN_CTL, val); } val = 0; if (panel->backlight.util_pin_active_low) val |= UTIL_PIN_POLARITY; - intel_de_write(i915, UTIL_PIN_CTL, + intel_de_write(display, UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) | UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE); } - pwm_ctl = intel_de_read(i915, BXT_BLC_PWM_CTL(panel->backlight.controller)); + pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller)); if (pwm_ctl & BXT_BLC_PWM_ENABLE) { - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] backlight already enabled\n", + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] backlight already enabled\n", connector->base.base.id, connector->base.name); pwm_ctl &= ~BXT_BLC_PWM_ENABLE; - intel_de_write(i915, BXT_BLC_PWM_CTL(panel->backlight.controller), + intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl); } - intel_de_write(i915, BXT_BLC_PWM_FREQ(panel->backlight.controller), + intel_de_write(display, BXT_BLC_PWM_FREQ(panel->backlight.controller), panel->backlight.pwm_level_max); intel_backlight_set_pwm_level(conn_state, level); @@ -706,9 +719,9 @@ static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state, if (panel->backlight.active_low_pwm) pwm_ctl |= BXT_BLC_PWM_POLARITY; - intel_de_write(i915, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl); - intel_de_posting_read(i915, BXT_BLC_PWM_CTL(panel->backlight.controller)); - intel_de_write(i915, BXT_BLC_PWM_CTL(panel->backlight.controller), + intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl); + intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller)); + intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl | BXT_BLC_PWM_ENABLE); } @@ -716,19 +729,19 @@ static void cnp_enable_backlight(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 pwm_ctl; - pwm_ctl = intel_de_read(i915, BXT_BLC_PWM_CTL(panel->backlight.controller)); + pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller)); if (pwm_ctl & BXT_BLC_PWM_ENABLE) { - drm_dbg_kms(&i915->drm, "backlight already enabled\n"); + drm_dbg_kms(display->drm, "backlight already enabled\n"); pwm_ctl &= ~BXT_BLC_PWM_ENABLE; - intel_de_write(i915, BXT_BLC_PWM_CTL(panel->backlight.controller), + intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl); } - intel_de_write(i915, BXT_BLC_PWM_FREQ(panel->backlight.controller), + intel_de_write(display, BXT_BLC_PWM_FREQ(panel->backlight.controller), panel->backlight.pwm_level_max); intel_backlight_set_pwm_level(conn_state, level); @@ -737,9 +750,9 @@ static void cnp_enable_backlight(const struct intel_crtc_state *crtc_state, if (panel->backlight.active_low_pwm) pwm_ctl |= BXT_BLC_PWM_POLARITY; - intel_de_write(i915, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl); - intel_de_posting_read(i915, BXT_BLC_PWM_CTL(panel->backlight.controller)); - intel_de_write(i915, BXT_BLC_PWM_CTL(panel->backlight.controller), + intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl); + intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller)); + intel_de_write(display, BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl | BXT_BLC_PWM_ENABLE); } @@ -781,37 +794,37 @@ void intel_backlight_enable(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; if (!panel->backlight.present) return; - drm_dbg_kms(&i915->drm, "pipe %c\n", pipe_name(pipe)); + drm_dbg_kms(display->drm, "pipe %c\n", pipe_name(pipe)); - mutex_lock(&i915->display.backlight.lock); + mutex_lock(&display->backlight.lock); __intel_backlight_enable(crtc_state, conn_state); - mutex_unlock(&i915->display.backlight.lock); + mutex_unlock(&display->backlight.lock); } #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) static u32 intel_panel_get_backlight(struct intel_connector *connector) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 val = 0; - mutex_lock(&i915->display.backlight.lock); + mutex_lock(&display->backlight.lock); if (panel->backlight.enabled) val = panel->backlight.funcs->get(connector, intel_connector_get_pipe(connector)); - mutex_unlock(&i915->display.backlight.lock); + mutex_unlock(&display->backlight.lock); - drm_dbg_kms(&i915->drm, "get backlight PWM = %d\n", val); + drm_dbg_kms(display->drm, "get backlight PWM = %d\n", val); return val; } @@ -830,16 +843,16 @@ static void intel_panel_set_backlight(const struct drm_connector_state *conn_sta u32 user_level, u32 user_max) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 hw_level; if (!panel->backlight.present) return; - mutex_lock(&i915->display.backlight.lock); + mutex_lock(&display->backlight.lock); - drm_WARN_ON(&i915->drm, panel->backlight.max == 0); + drm_WARN_ON(display->drm, panel->backlight.max == 0); hw_level = scale_user_to_hw(connector, user_level, user_max); panel->backlight.level = hw_level; @@ -847,18 +860,18 @@ static void intel_panel_set_backlight(const struct drm_connector_state *conn_sta if (panel->backlight.enabled) intel_panel_actually_set_backlight(conn_state, hw_level); - mutex_unlock(&i915->display.backlight.lock); + mutex_unlock(&display->backlight.lock); } static int intel_backlight_device_update_status(struct backlight_device *bd) { struct intel_connector *connector = bl_get_data(bd); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; - drm_modeset_lock(&i915->drm.mode_config.connection_mutex, NULL); + drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL); - drm_dbg_kms(&i915->drm, "updating intel_backlight, brightness=%d/%d\n", + drm_dbg_kms(display->drm, "updating intel_backlight, brightness=%d/%d\n", bd->props.brightness, bd->props.max_brightness); intel_panel_set_backlight(connector->base.state, bd->props.brightness, bd->props.max_brightness); @@ -879,7 +892,7 @@ static int intel_backlight_device_update_status(struct backlight_device *bd) bd->props.power = BACKLIGHT_POWER_OFF; } - drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + drm_modeset_unlock(&display->drm->mode_config.connection_mutex); return 0; } @@ -887,6 +900,7 @@ static int intel_backlight_device_update_status(struct backlight_device *bd) static int intel_backlight_device_get_brightness(struct backlight_device *bd) { struct intel_connector *connector = bl_get_data(bd); + struct intel_display *display = to_intel_display(connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); intel_wakeref_t wakeref; int ret = 0; @@ -894,13 +908,13 @@ static int intel_backlight_device_get_brightness(struct backlight_device *bd) with_intel_runtime_pm(&i915->runtime_pm, wakeref) { u32 hw_level; - drm_modeset_lock(&i915->drm.mode_config.connection_mutex, NULL); + drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL); hw_level = intel_panel_get_backlight(connector); ret = scale_hw_to_user(connector, hw_level, bd->props.max_brightness); - drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + drm_modeset_unlock(&display->drm->mode_config.connection_mutex); } return ret; @@ -913,7 +927,7 @@ static const struct backlight_ops intel_backlight_device_ops = { int intel_backlight_device_register(struct intel_connector *connector) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; struct backlight_properties props; struct backlight_device *bd; @@ -929,7 +943,8 @@ int intel_backlight_device_register(struct intel_connector *connector) WARN_ON(panel->backlight.max == 0); if (!acpi_video_backlight_use_native()) { - drm_info(&i915->drm, "Skipping intel_backlight registration\n"); + drm_info(display->drm, + "Skipping intel_backlight registration\n"); return 0; } @@ -966,7 +981,8 @@ int intel_backlight_device_register(struct intel_connector *connector) */ kfree(name); name = kasprintf(GFP_KERNEL, "card%d-%s-backlight", - i915->drm.primary->index, connector->base.name); + display->drm->primary->index, + connector->base.name); if (!name) return -ENOMEM; } @@ -974,7 +990,7 @@ int intel_backlight_device_register(struct intel_connector *connector) &intel_backlight_device_ops, &props); if (IS_ERR(bd)) { - drm_err(&i915->drm, + drm_err(display->drm, "[CONNECTOR:%d:%s] backlight device %s register failed: %ld\n", connector->base.base.id, connector->base.name, name, PTR_ERR(bd)); ret = PTR_ERR(bd); @@ -983,7 +999,7 @@ int intel_backlight_device_register(struct intel_connector *connector) panel->backlight.device = bd; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] backlight device %s registered\n", connector->base.base.id, connector->base.name, name); @@ -1010,9 +1026,9 @@ void intel_backlight_device_unregister(struct intel_connector *connector) */ static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); - return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq), + return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq), pwm_freq_hz); } @@ -1072,9 +1088,9 @@ static u32 lpt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) */ static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); - return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq), + return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq), pwm_freq_hz * 128); } @@ -1088,13 +1104,13 @@ static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) */ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); int clock; - if (IS_PINEVIEW(i915)) - clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq); + if (display->platform.pineview) + clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq); else - clock = KHz(i915->display.cdclk.hw.cdclk); + clock = KHz(display->cdclk.hw.cdclk); return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 32); } @@ -1106,13 +1122,13 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) */ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); int clock; - if (IS_G4X(i915)) - clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq); + if (display->platform.g4x) + clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq); else - clock = KHz(i915->display.cdclk.hw.cdclk); + clock = KHz(display->cdclk.hw.cdclk); return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 128); } @@ -1124,17 +1140,17 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) */ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); int mul, clock; - if ((intel_de_read(i915, CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) { - if (IS_CHERRYVIEW(i915)) + if ((intel_de_read(display, CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) { + if (display->platform.cherryview) clock = KHz(19200); else clock = MHz(25); mul = 16; } else { - clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq); + clock = KHz(DISPLAY_RUNTIME_INFO(display)->rawclk_freq); mul = 128; } @@ -1143,16 +1159,16 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) static u16 get_vbt_pwm_freq(struct intel_connector *connector) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); u16 pwm_freq_hz = connector->panel.vbt.backlight.pwm_freq_hz; if (pwm_freq_hz) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "VBT defined backlight frequency %u Hz\n", pwm_freq_hz); } else { pwm_freq_hz = 200; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "default backlight frequency %u Hz\n", pwm_freq_hz); } @@ -1162,20 +1178,20 @@ static u16 get_vbt_pwm_freq(struct intel_connector *connector) static u32 get_backlight_max_vbt(struct intel_connector *connector) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u16 pwm_freq_hz = get_vbt_pwm_freq(connector); u32 pwm; if (!panel->backlight.pwm_funcs->hz_to_pwm) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "backlight frequency conversion not supported\n"); return 0; } pwm = panel->backlight.pwm_funcs->hz_to_pwm(connector, pwm_freq_hz); if (!pwm) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "backlight frequency conversion failed\n"); return 0; } @@ -1188,11 +1204,11 @@ static u32 get_backlight_max_vbt(struct intel_connector *connector) */ static u32 get_backlight_min_vbt(struct intel_connector *connector) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; int min; - drm_WARN_ON(&i915->drm, panel->backlight.pwm_level_max == 0); + drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0); /* * XXX: If the vbt value is 255, it makes min equal to max, which leads @@ -1203,7 +1219,7 @@ static u32 get_backlight_min_vbt(struct intel_connector *connector) */ min = clamp_t(int, connector->panel.vbt.backlight.min_brightness, 0, 64); if (min != connector->panel.vbt.backlight.min_brightness) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "clamping VBT min backlight %d/255 to %d/255\n", connector->panel.vbt.backlight.min_brightness, min); } @@ -1214,24 +1230,25 @@ static u32 get_backlight_min_vbt(struct intel_connector *connector) static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unused) { + struct intel_display *display = to_intel_display(connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_panel *panel = &connector->panel; u32 cpu_ctl2, pch_ctl1, pch_ctl2, val; bool alt, cpu_mode; if (HAS_PCH_LPT(i915)) - alt = intel_de_read(i915, SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY; + alt = intel_de_read(display, SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY; else - alt = intel_de_read(i915, SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY; + alt = intel_de_read(display, SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY; panel->backlight.alternate_pwm_increment = alt; - pch_ctl1 = intel_de_read(i915, BLC_PWM_PCH_CTL1); + pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1); panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY; - pch_ctl2 = intel_de_read(i915, BLC_PWM_PCH_CTL2); + pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2); panel->backlight.pwm_level_max = pch_ctl2 >> 16; - cpu_ctl2 = intel_de_read(i915, BLC_PWM_CPU_CTL2); + cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2); if (!panel->backlight.pwm_level_max) panel->backlight.pwm_level_max = get_backlight_max_vbt(connector); @@ -1250,19 +1267,19 @@ static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unus if (cpu_mode) { val = pch_get_backlight(connector, unused); - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "CPU backlight register was enabled, switching to PCH override\n"); /* Write converted CPU PWM value to PCH override register */ lpt_set_backlight(connector->base.state, val); - intel_de_write(i915, BLC_PWM_PCH_CTL1, + intel_de_write(display, BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_OVERRIDE_ENABLE); - intel_de_write(i915, BLC_PWM_CPU_CTL2, + intel_de_write(display, BLC_PWM_CPU_CTL2, cpu_ctl2 & ~BLM_PWM_ENABLE); } - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Using native PCH PWM for backlight control\n", connector->base.base.id, connector->base.name); @@ -1271,14 +1288,14 @@ static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unus static int pch_setup_backlight(struct intel_connector *connector, enum pipe unused) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 cpu_ctl2, pch_ctl1, pch_ctl2; - pch_ctl1 = intel_de_read(i915, BLC_PWM_PCH_CTL1); + pch_ctl1 = intel_de_read(display, BLC_PWM_PCH_CTL1); panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY; - pch_ctl2 = intel_de_read(i915, BLC_PWM_PCH_CTL2); + pch_ctl2 = intel_de_read(display, BLC_PWM_PCH_CTL2); panel->backlight.pwm_level_max = pch_ctl2 >> 16; if (!panel->backlight.pwm_level_max) @@ -1289,11 +1306,11 @@ static int pch_setup_backlight(struct intel_connector *connector, enum pipe unus panel->backlight.pwm_level_min = get_backlight_min_vbt(connector); - cpu_ctl2 = intel_de_read(i915, BLC_PWM_CPU_CTL2); + cpu_ctl2 = intel_de_read(display, BLC_PWM_CPU_CTL2); panel->backlight.pwm_enabled = (cpu_ctl2 & BLM_PWM_ENABLE) && (pch_ctl1 & BLM_PCH_PWM_ENABLE); - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Using native PCH PWM for backlight control\n", connector->base.base.id, connector->base.name); @@ -1302,16 +1319,16 @@ static int pch_setup_backlight(struct intel_connector *connector, enum pipe unus static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unused) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 ctl, val; - ctl = intel_de_read(i915, BLC_PWM_CTL); + ctl = intel_de_read(display, BLC_PWM_CTL); - if (DISPLAY_VER(i915) == 2 || IS_I915GM(i915) || IS_I945GM(i915)) + if (DISPLAY_VER(display) == 2 || display->platform.i915gm || display->platform.i945gm) panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE; - if (IS_PINEVIEW(i915)) + if (display->platform.pineview) panel->backlight.active_low_pwm = ctl & BLM_POLARITY_PNV; panel->backlight.pwm_level_max = ctl >> 17; @@ -1335,7 +1352,7 @@ static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unu panel->backlight.pwm_enabled = val != 0; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Using native PWM for backlight control\n", connector->base.base.id, connector->base.name); @@ -1344,15 +1361,15 @@ static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unu static int i965_setup_backlight(struct intel_connector *connector, enum pipe unused) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 ctl, ctl2; - ctl2 = intel_de_read(i915, BLC_PWM_CTL2); + ctl2 = intel_de_read(display, BLC_PWM_CTL2); panel->backlight.combination_mode = ctl2 & BLM_COMBINATION_MODE; panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; - ctl = intel_de_read(i915, BLC_PWM_CTL); + ctl = intel_de_read(display, BLC_PWM_CTL); panel->backlight.pwm_level_max = ctl >> 16; if (!panel->backlight.pwm_level_max) @@ -1368,7 +1385,7 @@ static int i965_setup_backlight(struct intel_connector *connector, enum pipe unu panel->backlight.pwm_enabled = ctl2 & BLM_PWM_ENABLE; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Using native PWM for backlight control\n", connector->base.base.id, connector->base.name); @@ -1377,17 +1394,17 @@ static int i965_setup_backlight(struct intel_connector *connector, enum pipe unu static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 ctl, ctl2; - if (drm_WARN_ON(&i915->drm, pipe != PIPE_A && pipe != PIPE_B)) + if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B)) return -ENODEV; - ctl2 = intel_de_read(i915, VLV_BLC_PWM_CTL2(pipe)); + ctl2 = intel_de_read(display, VLV_BLC_PWM_CTL2(pipe)); panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; - ctl = intel_de_read(i915, VLV_BLC_PWM_CTL(pipe)); + ctl = intel_de_read(display, VLV_BLC_PWM_CTL(pipe)); panel->backlight.pwm_level_max = ctl >> 16; if (!panel->backlight.pwm_level_max) @@ -1400,7 +1417,7 @@ static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe panel->backlight.pwm_enabled = ctl2 & BLM_PWM_ENABLE; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Using native PWM for backlight control (on pipe %c)\n", connector->base.base.id, connector->base.name, pipe_name(pipe)); @@ -1410,25 +1427,25 @@ static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe static int bxt_setup_backlight(struct intel_connector *connector, enum pipe unused) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 pwm_ctl, val; panel->backlight.controller = connector->panel.vbt.backlight.controller; - pwm_ctl = intel_de_read(i915, + pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller)); /* Controller 1 uses the utility pin. */ if (panel->backlight.controller == 1) { - val = intel_de_read(i915, UTIL_PIN_CTL); + val = intel_de_read(display, UTIL_PIN_CTL); panel->backlight.util_pin_active_low = val & UTIL_PIN_POLARITY; } panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY; panel->backlight.pwm_level_max = - intel_de_read(i915, BXT_BLC_PWM_FREQ(panel->backlight.controller)); + intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller)); if (!panel->backlight.pwm_level_max) panel->backlight.pwm_level_max = get_backlight_max_vbt(connector); @@ -1440,7 +1457,7 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused) panel->backlight.pwm_enabled = pwm_ctl & BXT_BLC_PWM_ENABLE; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Using native PWM for backlight control (controller=%d)\n", connector->base.base.id, connector->base.name, panel->backlight.controller); @@ -1448,8 +1465,10 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused) return 0; } -static int cnp_num_backlight_controllers(struct drm_i915_private *i915) +static int cnp_num_backlight_controllers(struct intel_display *display) { + struct drm_i915_private *i915 = to_i915(display->drm); + if (INTEL_PCH_TYPE(i915) >= PCH_MTL) return 2; @@ -1462,15 +1481,17 @@ static int cnp_num_backlight_controllers(struct drm_i915_private *i915) return 1; } -static bool cnp_backlight_controller_is_valid(struct drm_i915_private *i915, int controller) +static bool cnp_backlight_controller_is_valid(struct intel_display *display, int controller) { - if (controller < 0 || controller >= cnp_num_backlight_controllers(i915)) + struct drm_i915_private *i915 = to_i915(display->drm); + + if (controller < 0 || controller >= cnp_num_backlight_controllers(display)) return false; if (controller == 1 && INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_ADP) - return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT; + return intel_de_read(display, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT; return true; } @@ -1478,7 +1499,7 @@ static bool cnp_backlight_controller_is_valid(struct drm_i915_private *i915, int static int cnp_setup_backlight(struct intel_connector *connector, enum pipe unused) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; u32 pwm_ctl; @@ -1487,19 +1508,20 @@ cnp_setup_backlight(struct intel_connector *connector, enum pipe unused) * controller. ICP+ can have two controllers, depending on pin muxing. */ panel->backlight.controller = connector->panel.vbt.backlight.controller; - if (!cnp_backlight_controller_is_valid(i915, panel->backlight.controller)) { - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Invalid backlight controller %d, assuming 0\n", + if (!cnp_backlight_controller_is_valid(display, panel->backlight.controller)) { + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] Invalid backlight controller %d, assuming 0\n", connector->base.base.id, connector->base.name, panel->backlight.controller); panel->backlight.controller = 0; } - pwm_ctl = intel_de_read(i915, + pwm_ctl = intel_de_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller)); panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY; panel->backlight.pwm_level_max = - intel_de_read(i915, BXT_BLC_PWM_FREQ(panel->backlight.controller)); + intel_de_read(display, BXT_BLC_PWM_FREQ(panel->backlight.controller)); if (!panel->backlight.pwm_level_max) panel->backlight.pwm_level_max = get_backlight_max_vbt(connector); @@ -1511,7 +1533,7 @@ cnp_setup_backlight(struct intel_connector *connector, enum pipe unused) panel->backlight.pwm_enabled = pwm_ctl & BXT_BLC_PWM_ENABLE; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Using native PCH PWM for backlight control (controller=%d)\n", connector->base.base.id, connector->base.name, panel->backlight.controller); @@ -1522,22 +1544,25 @@ cnp_setup_backlight(struct intel_connector *connector, enum pipe unused) static int ext_pwm_setup_backlight(struct intel_connector *connector, enum pipe pipe) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; const char *desc; u32 level; /* Get the right PWM chip for DSI backlight according to VBT */ if (connector->panel.vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { - panel->backlight.pwm = pwm_get(i915->drm.dev, "pwm_pmic_backlight"); + panel->backlight.pwm = pwm_get(display->drm->dev, + "pwm_pmic_backlight"); desc = "PMIC"; } else { - panel->backlight.pwm = pwm_get(i915->drm.dev, "pwm_soc_backlight"); + panel->backlight.pwm = pwm_get(display->drm->dev, + "pwm_soc_backlight"); desc = "SoC"; } if (IS_ERR(panel->backlight.pwm)) { - drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to get the %s PWM chip\n", + drm_err(display->drm, + "[CONNECTOR:%d:%s] Failed to get the %s PWM chip\n", connector->base.base.id, connector->base.name, desc); panel->backlight.pwm = NULL; return -ENODEV; @@ -1555,7 +1580,8 @@ static int ext_pwm_setup_backlight(struct intel_connector *connector, level = intel_backlight_invert_pwm_level(connector, level); panel->backlight.pwm_enabled = true; - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] PWM already enabled at freq %ld, VBT freq %d, level %d\n", + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] PWM already enabled at freq %ld, VBT freq %d, level %d\n", connector->base.base.id, connector->base.name, NSEC_PER_SEC / (unsigned long)panel->backlight.pwm_state.period, get_vbt_pwm_freq(connector), level); @@ -1565,7 +1591,7 @@ static int ext_pwm_setup_backlight(struct intel_connector *connector, NSEC_PER_SEC / get_vbt_pwm_freq(connector); } - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Using %s PWM for backlight control\n", connector->base.base.id, connector->base.name, desc); @@ -1631,17 +1657,17 @@ void intel_backlight_update(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_panel *panel = &connector->panel; if (!panel->backlight.present) return; - mutex_lock(&i915->display.backlight.lock); + mutex_lock(&display->backlight.lock); if (!panel->backlight.enabled) __intel_backlight_enable(crtc_state, conn_state); - mutex_unlock(&i915->display.backlight.lock); + mutex_unlock(&display->backlight.lock); } int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe) @@ -1792,30 +1818,31 @@ void intel_backlight_init_funcs(struct intel_panel *panel) { struct intel_connector *connector = container_of(panel, struct intel_connector, panel); + struct intel_display *display = to_intel_display(connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI && intel_dsi_dcs_init_backlight_funcs(connector) == 0) return; - if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { + if (display->platform.geminilake || display->platform.broxton) { panel->backlight.pwm_funcs = &bxt_pwm_funcs; } else if (INTEL_PCH_TYPE(i915) >= PCH_CNP) { panel->backlight.pwm_funcs = &cnp_pwm_funcs; - } else if (INTEL_PCH_TYPE(i915) >= PCH_LPT) { + } else if (INTEL_PCH_TYPE(i915) >= PCH_LPT_H) { if (HAS_PCH_LPT(i915)) panel->backlight.pwm_funcs = &lpt_pwm_funcs; else panel->backlight.pwm_funcs = &spt_pwm_funcs; } else if (HAS_PCH_SPLIT(i915)) { panel->backlight.pwm_funcs = &pch_pwm_funcs; - } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { + } else if (display->platform.valleyview || display->platform.cherryview) { if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI) { panel->backlight.pwm_funcs = &ext_pwm_funcs; } else { panel->backlight.pwm_funcs = &vlv_pwm_funcs; } - } else if (DISPLAY_VER(i915) == 4) { + } else if (DISPLAY_VER(display) == 4) { panel->backlight.pwm_funcs = &i965_pwm_funcs; } else { panel->backlight.pwm_funcs = &i9xx_pwm_funcs; @@ -1825,7 +1852,7 @@ void intel_backlight_init_funcs(struct intel_panel *panel) if (intel_dp_aux_init_backlight_funcs(connector) == 0) return; - if (!intel_has_quirk(&i915->display, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK)) + if (!intel_has_quirk(display, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK)) connector->panel.backlight.power = intel_pps_backlight_power; } diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index e0e4e9b62d8d..a8d08d7d82b3 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2902,7 +2902,6 @@ init_vbt_panel_defaults(struct intel_panel *panel) static void init_vbt_missing_defaults(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); unsigned int ports = DISPLAY_RUNTIME_INFO(display)->port_mask; enum port port; @@ -2912,13 +2911,13 @@ init_vbt_missing_defaults(struct intel_display *display) for_each_port_masked(port, ports) { struct intel_bios_encoder_data *devdata; struct child_device_config *child; - enum phy phy = intel_port_to_phy(i915, port); + enum phy phy = intel_port_to_phy(display, port); /* * VBT has the TypeC mode (native,TBT/USB) and we don't want * to detect it. */ - if (intel_phy_is_tc(i915, phy)) + if (intel_phy_is_tc(display, phy)) continue; /* Create fake child device config */ diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 23edc81741de..98b898a1de8f 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -244,6 +244,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, qi->deinterleave = 4; break; case INTEL_DRAM_GDDR: + case INTEL_DRAM_GDDR_ECC: qi->channel_width = 32; break; default: @@ -398,6 +399,12 @@ static const struct intel_sa_info xe2_hpd_sa_info = { /* Other values not used by simplified algorithm */ }; +static const struct intel_sa_info xe2_hpd_ecc_sa_info = { + .derating = 45, + .deprogbwlimit = 53, + /* Other values not used by simplified algorithm */ +}; + static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) { struct intel_qgv_info qi = {}; @@ -740,10 +747,15 @@ static unsigned int icl_qgv_bw(struct drm_i915_private *i915, void intel_bw_init_hw(struct drm_i915_private *dev_priv) { + const struct dram_info *dram_info = &dev_priv->dram_info; + if (!HAS_DISPLAY(dev_priv)) return; - if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv)) + if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv) && + dram_info->type == INTEL_DRAM_GDDR_ECC) + xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_ecc_sa_info); + else if (DISPLAY_VERx100(dev_priv) >= 1401 && IS_DGFX(dev_priv)) xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info); else if (DISPLAY_VER(dev_priv) >= 14) tgl_get_bw_info(dev_priv, &mtl_sa_info); @@ -806,24 +818,6 @@ static int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state) return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512); } -void intel_bw_crtc_update(struct intel_bw_state *bw_state, - const struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); - - bw_state->data_rate[crtc->pipe] = - intel_bw_crtc_data_rate(crtc_state); - bw_state->num_active_planes[crtc->pipe] = - intel_bw_crtc_num_active_planes(crtc_state); - bw_state->force_check_qgv = true; - - drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n", - pipe_name(crtc->pipe), - bw_state->data_rate[crtc->pipe], - bw_state->num_active_planes[crtc->pipe]); -} - static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv, const struct intel_bw_state *bw_state) { @@ -1422,6 +1416,62 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) return 0; } +static void intel_bw_crtc_update(struct intel_bw_state *bw_state, + const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + + bw_state->data_rate[crtc->pipe] = + intel_bw_crtc_data_rate(crtc_state); + bw_state->num_active_planes[crtc->pipe] = + intel_bw_crtc_num_active_planes(crtc_state); + bw_state->force_check_qgv = true; + + drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n", + pipe_name(crtc->pipe), + bw_state->data_rate[crtc->pipe], + bw_state->num_active_planes[crtc->pipe]); +} + +void intel_bw_update_hw_state(struct intel_display *display) +{ + struct intel_bw_state *bw_state = + to_intel_bw_state(display->bw.obj.state); + struct intel_crtc *crtc; + + if (DISPLAY_VER(display) < 9) + return; + + bw_state->active_pipes = 0; + + for_each_intel_crtc(display->drm, crtc) { + const struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); + enum pipe pipe = crtc->pipe; + + if (crtc_state->hw.active) + bw_state->active_pipes |= BIT(pipe); + + if (DISPLAY_VER(display) >= 11) + intel_bw_crtc_update(bw_state, crtc_state); + } +} + +void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(crtc); + struct intel_bw_state *bw_state = + to_intel_bw_state(display->bw.obj.state); + enum pipe pipe = crtc->pipe; + + if (DISPLAY_VER(display) < 9) + return; + + bw_state->data_rate[pipe] = 0; + bw_state->num_active_planes[pipe] = 0; +} + static struct intel_global_state * intel_bw_duplicate_state(struct intel_global_obj *obj) { diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index 161813cca473..3313e4eac4f0 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.h +++ b/drivers/gpu/drm/i915/display/intel_bw.h @@ -14,7 +14,9 @@ struct drm_i915_private; struct intel_atomic_state; +struct intel_crtc; struct intel_crtc_state; +struct intel_display; struct intel_dbuf_bw { unsigned int max_bw[I915_MAX_DBUF_SLICES]; @@ -73,13 +75,13 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state); void intel_bw_init_hw(struct drm_i915_private *dev_priv); int intel_bw_init(struct drm_i915_private *dev_priv); int intel_bw_atomic_check(struct intel_atomic_state *state); -void intel_bw_crtc_update(struct intel_bw_state *bw_state, - const struct intel_crtc_state *crtc_state); int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, u32 points_mask); int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, bool *need_cdclk_calc); int intel_bw_min_cdclk(struct drm_i915_private *i915, const struct intel_bw_state *bw_state); +void intel_bw_update_hw_state(struct intel_display *display); +void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc); #endif /* __INTEL_BW_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index c7a603589412..2a8749a0213e 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -314,27 +314,26 @@ static unsigned int intel_hpll_vco(struct intel_display *display) [4] = 2666667, [5] = 4266667, }; - struct drm_i915_private *dev_priv = to_i915(display->drm); const unsigned int *vco_table; unsigned int vco; u8 tmp = 0; /* FIXME other chipsets? */ - if (IS_GM45(dev_priv)) + if (display->platform.gm45) vco_table = ctg_vco; - else if (IS_G45(dev_priv)) + else if (display->platform.g45) vco_table = elk_vco; - else if (IS_I965GM(dev_priv)) + else if (display->platform.i965gm) vco_table = cl_vco; - else if (IS_PINEVIEW(dev_priv)) + else if (display->platform.pineview) vco_table = pnv_vco; - else if (IS_G33(dev_priv)) + else if (display->platform.g33) vco_table = blb_vco; else return 0; - tmp = intel_de_read(display, - IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); + tmp = intel_de_read(display, display->platform.pineview || + display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO); vco = vco_table[tmp & 0x7]; if (vco == 0) @@ -508,7 +507,6 @@ static void gm45_get_cdclk(struct intel_display *display, static void hsw_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 lcpll = intel_de_read(display, LCPLL_CTL); u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; @@ -518,7 +516,7 @@ static void hsw_get_cdclk(struct intel_display *display, cdclk_config->cdclk = 450000; else if (freq == LCPLL_CLK_FREQ_450) cdclk_config->cdclk = 450000; - else if (IS_HASWELL_ULT(dev_priv)) + else if (display->platform.haswell_ult) cdclk_config->cdclk = 337500; else cdclk_config->cdclk = 540000; @@ -535,7 +533,7 @@ static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) * Not sure what's wrong. For now use 200MHz only when all pipes * are off. */ - if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) + if (display->platform.valleyview && min_cdclk > freq_320) return 400000; else if (min_cdclk > 266667) return freq_320; @@ -549,7 +547,7 @@ static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) { struct drm_i915_private *dev_priv = to_i915(display->drm); - if (IS_VALLEYVIEW(dev_priv)) { + if (display->platform.valleyview) { if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ return 2; else if (cdclk >= 266667) @@ -585,7 +583,7 @@ static void vlv_get_cdclk(struct intel_display *display, vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); - if (IS_VALLEYVIEW(dev_priv)) + if (display->platform.valleyview) cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> DSPFREQGUAR_SHIFT; else @@ -598,14 +596,14 @@ static void vlv_program_pfi_credits(struct intel_display *display) struct drm_i915_private *dev_priv = to_i915(display->drm); unsigned int credits, default_credits; - if (IS_CHERRYVIEW(dev_priv)) + if (display->platform.cherryview) default_credits = PFI_CREDIT(12); else default_credits = PFI_CREDIT(8); if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { /* CHV suggested value is 31 or 63 */ - if (IS_CHERRYVIEW(dev_priv)) + if (display->platform.cherryview) credits = PFI_CREDIT_63; else credits = PFI_CREDIT(15); @@ -658,7 +656,7 @@ static void vlv_set_cdclk(struct intel_display *display, * a system suspend. So grab the display core domain, which covers * the HW blocks needed for the following programming. */ - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); + wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_CCK) | @@ -718,7 +716,7 @@ static void vlv_set_cdclk(struct intel_display *display, vlv_program_pfi_credits(display); - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); } static void chv_set_cdclk(struct intel_display *display, @@ -747,7 +745,7 @@ static void chv_set_cdclk(struct intel_display *display, * a system suspend. So grab the display core domain, which covers * the HW blocks needed for the following programming. */ - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); + wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); vlv_punit_get(dev_priv); val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); @@ -767,7 +765,7 @@ static void chv_set_cdclk(struct intel_display *display, vlv_program_pfi_credits(display); - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); } static int bdw_calc_cdclk(int min_cdclk) @@ -1142,7 +1140,7 @@ static void skl_set_cdclk(struct intel_display *display, * minimum 308MHz CDCLK. */ drm_WARN_ON_ONCE(display->drm, - IS_SKYLAKE(dev_priv) && vco == 8640000); + display->platform.skylake && vco == 8640000); ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, SKL_CDCLK_PREPARE_FOR_CHANGE, @@ -1662,10 +1660,9 @@ static void icl_readout_refclk(struct intel_display *display, static void bxt_de_pll_readout(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 val, ratio; - if (IS_DG2(dev_priv)) + if (display->platform.dg2) cdclk_config->ref = 38400; else if (DISPLAY_VER(display) >= 11) icl_readout_refclk(display, cdclk_config); @@ -2057,11 +2054,9 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *displa static bool pll_enable_wa_needed(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - return (DISPLAY_VERx100(display) == 2000 || DISPLAY_VERx100(display) == 1400 || - IS_DG2(dev_priv)) && + display->platform.dg2) && display->cdclk.hw.vco > 0; } @@ -2069,7 +2064,6 @@ static u32 bxt_cdclk_ctl(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - struct drm_i915_private *i915 = to_i915(display->drm); int cdclk = cdclk_config->cdclk; int vco = cdclk_config->vco; u16 waveform; @@ -2084,7 +2078,7 @@ static u32 bxt_cdclk_ctl(struct intel_display *display, * Disable SSA Precharge when CD clock frequency < 500 MHz, * enable otherwise. */ - if ((IS_GEMINILAKE(i915) || IS_BROXTON(i915)) && + if ((display->platform.geminilake || display->platform.broxton) && cdclk >= 500000) val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; @@ -2144,8 +2138,8 @@ static void bxt_set_cdclk(struct intel_display *display, * mailbox communication, skip * this step. */ - if (DISPLAY_VER(display) >= 14 || IS_DG2(dev_priv)) - /* NOOP */; + if (DISPLAY_VER(display) >= 14 || display->platform.dg2) + ; /* NOOP */ else if (DISPLAY_VER(display) >= 11) ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, SKL_CDCLK_PREPARE_FOR_CHANGE, @@ -2186,7 +2180,7 @@ static void bxt_set_cdclk(struct intel_display *display, * NOOP - No Pcode communication needed for * Display versions 14 and beyond */; - else if (DISPLAY_VER(display) >= 11 && !IS_DG2(dev_priv)) + else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, cdclk_config->voltage_level); if (DISPLAY_VER(display) < 11) { @@ -2250,7 +2244,7 @@ static void bxt_sanitize_cdclk(struct intel_display *display) /* * Let's ignore the pipe field, since BIOS could have configured the - * dividers both synching to an active pipe, or asynchronously + * dividers both syncing to an active pipe, or asynchronously * (PIPE_NONE). */ cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); @@ -2318,9 +2312,7 @@ static void bxt_cdclk_uninit_hw(struct intel_display *display) */ void intel_cdclk_init_hw(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - - if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915)) + if (DISPLAY_VER(display) >= 10 || display->platform.broxton) bxt_cdclk_init_hw(display); else if (DISPLAY_VER(display) == 9) skl_cdclk_init_hw(display); @@ -2335,9 +2327,7 @@ void intel_cdclk_init_hw(struct intel_display *display) */ void intel_cdclk_uninit_hw(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - - if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915)) + if (DISPLAY_VER(display) >= 10 || display->platform.broxton) bxt_cdclk_uninit_hw(display); else if (DISPLAY_VER(display) == 9) skl_cdclk_uninit_hw(display); @@ -2438,10 +2428,8 @@ static bool intel_cdclk_can_cd2x_update(struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - /* Older hw doesn't have the capability */ - if (DISPLAY_VER(display) < 10 && !IS_BROXTON(dev_priv)) + if (DISPLAY_VER(display) < 10 && !display->platform.broxton) return false; /* @@ -2495,7 +2483,7 @@ static void intel_pcode_notify(struct intel_display *display, int ret; u32 update_mask = 0; - if (!IS_DG2(i915)) + if (!display->platform.dg2) return; update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); @@ -2521,7 +2509,6 @@ static void intel_set_cdclk(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe, const char *context) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *encoder; if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) @@ -2538,7 +2525,7 @@ static void intel_set_cdclk(struct intel_display *display, intel_psr_pause(intel_dp); } - intel_audio_cdclk_change_pre(dev_priv); + intel_audio_cdclk_change_pre(display); /* * Lock aux/gmbus while we change cdclk in case those @@ -2568,7 +2555,7 @@ static void intel_set_cdclk(struct intel_display *display, intel_psr_resume(intel_dp); } - intel_audio_cdclk_change_post(dev_priv); + intel_audio_cdclk_change_post(display); if (drm_WARN(display->drm, intel_cdclk_changed(&display->cdclk.hw, cdclk_config), @@ -2682,7 +2669,6 @@ void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *i915 = to_i915(display->drm); const struct intel_cdclk_state *old_cdclk_state = intel_atomic_get_old_cdclk_state(state); const struct intel_cdclk_state *new_cdclk_state = @@ -2694,7 +2680,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) &new_cdclk_state->actual)) return; - if (IS_DG2(i915)) + if (display->platform.dg2) intel_cdclk_pcode_pre_notify(state); if (new_cdclk_state->disable_pipes) { @@ -2736,7 +2722,6 @@ void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *i915 = to_i915(display->drm); const struct intel_cdclk_state *old_cdclk_state = intel_atomic_get_old_cdclk_state(state); const struct intel_cdclk_state *new_cdclk_state = @@ -2747,7 +2732,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) &new_cdclk_state->actual)) return; - if (IS_DG2(i915)) + if (display->platform.dg2) intel_cdclk_pcode_post_notify(state); if (!new_cdclk_state->disable_pipes && @@ -2771,12 +2756,10 @@ static int intel_cdclk_ppc(struct intel_display *display, bool double_wide) /* max pixel rate as % of CDCLK (not accounting for PPC) */ static int intel_cdclk_guardband(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - if (DISPLAY_VER(display) >= 9 || - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + display->platform.broadwell || display->platform.haswell) return 100; - else if (IS_CHERRYVIEW(dev_priv)) + else if (display->platform.cherryview) return 95; else return 90; @@ -2805,7 +2788,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) return min_cdclk; } -int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) +static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) { int min_cdclk; @@ -2879,7 +2862,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) * by changing the cd2x divider (see glk_cdclk_table[]) and * thus a full modeset won't be needed then. */ - if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && + if (display->platform.geminilake && cdclk_state->active_pipes && !is_power_of_2(cdclk_state->active_pipes)) min_cdclk = max(min_cdclk, 2 * 96000); @@ -3233,7 +3216,6 @@ static bool intel_cdclk_need_serialize(struct intel_display *display, const struct intel_cdclk_state *old_cdclk_state, const struct intel_cdclk_state *new_cdclk_state) { - struct drm_i915_private *i915 = to_i915(display->drm); bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != hweight8(new_cdclk_state->active_pipes); bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, @@ -3242,7 +3224,7 @@ static bool intel_cdclk_need_serialize(struct intel_display *display, * We need to poke hw for gen >= 12, because we notify PCode if * pipe power well count changes. */ - return cdclk_changed || (IS_DG2(i915) && power_well_cnt_changed); + return cdclk_changed || (display->platform.dg2 && power_well_cnt_changed); } int intel_modeset_calc_cdclk(struct intel_atomic_state *state) @@ -3358,6 +3340,34 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) return 0; } +void intel_cdclk_update_hw_state(struct intel_display *display) +{ + struct intel_cdclk_state *cdclk_state = + to_intel_cdclk_state(display->cdclk.obj.state); + struct intel_crtc *crtc; + + cdclk_state->active_pipes = 0; + + for_each_intel_crtc(display->drm, crtc) { + const struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); + enum pipe pipe = crtc->pipe; + + if (crtc_state->hw.active) + cdclk_state->active_pipes |= BIT(pipe); + + cdclk_state->min_cdclk[pipe] = intel_crtc_compute_min_cdclk(crtc_state); + cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level; + } +} + +void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(crtc); + + intel_cdclk_update_hw_state(display); +} + static int intel_compute_max_dotclk(struct intel_display *display) { int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); @@ -3377,11 +3387,9 @@ static int intel_compute_max_dotclk(struct intel_display *display) */ void intel_update_max_cdclk(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - if (DISPLAY_VER(display) >= 30) { display->cdclk.max_cdclk_freq = 691200; - } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { + } else if (display->platform.jasperlake || display->platform.elkhartlake) { if (display->cdclk.hw.ref == 24000) display->cdclk.max_cdclk_freq = 552000; else @@ -3391,9 +3399,9 @@ void intel_update_max_cdclk(struct intel_display *display) display->cdclk.max_cdclk_freq = 648000; else display->cdclk.max_cdclk_freq = 652800; - } else if (IS_GEMINILAKE(dev_priv)) { + } else if (display->platform.geminilake) { display->cdclk.max_cdclk_freq = 316800; - } else if (IS_BROXTON(dev_priv)) { + } else if (display->platform.broxton) { display->cdclk.max_cdclk_freq = 624000; } else if (DISPLAY_VER(display) == 9) { u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; @@ -3417,7 +3425,7 @@ void intel_update_max_cdclk(struct intel_display *display) max_cdclk = 308571; display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); - } else if (IS_BROADWELL(dev_priv)) { + } else if (display->platform.broadwell) { /* * FIXME with extra cooling we can allow * 540 MHz for ULX and 675 Mhz for ULT. @@ -3426,15 +3434,15 @@ void intel_update_max_cdclk(struct intel_display *display) */ if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) display->cdclk.max_cdclk_freq = 450000; - else if (IS_BROADWELL_ULX(dev_priv)) + else if (display->platform.broadwell_ulx) display->cdclk.max_cdclk_freq = 450000; - else if (IS_BROADWELL_ULT(dev_priv)) + else if (display->platform.broadwell_ult) display->cdclk.max_cdclk_freq = 540000; else display->cdclk.max_cdclk_freq = 675000; - } else if (IS_CHERRYVIEW(dev_priv)) { + } else if (display->platform.cherryview) { display->cdclk.max_cdclk_freq = 320000; - } else if (IS_VALLEYVIEW(dev_priv)) { + } else if (display->platform.valleyview) { display->cdclk.max_cdclk_freq = 400000; } else { /* otherwise assume cdclk is fixed */ @@ -3458,8 +3466,6 @@ void intel_update_max_cdclk(struct intel_display *display) */ void intel_update_cdclk(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - intel_cdclk_get_cdclk(display, &display->cdclk.hw); /* @@ -3468,7 +3474,7 @@ void intel_update_cdclk(struct intel_display *display) * of cdclk that generates 4MHz reference clock freq which is used to * generate GMBus clock. This will vary with the cdclk freq. */ - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + if (display->platform.valleyview || display->platform.cherryview) intel_de_write(display, GMBUSFREQ_VLV, DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); } @@ -3562,7 +3568,7 @@ u32 intel_read_rawclk(struct intel_display *display) freq = cnp_rawclk(display); else if (HAS_PCH_SPLIT(dev_priv)) freq = pch_rawclk(display); - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + else if (display->platform.valleyview || display->platform.cherryview) freq = vlv_hrawclk(display); else if (DISPLAY_VER(display) >= 3) freq = i9xx_hrawclk(display); @@ -3743,8 +3749,6 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = { */ void intel_init_cdclk_hooks(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - if (DISPLAY_VER(display) >= 30) { display->funcs.cdclk = &xe3lpd_cdclk_funcs; display->cdclk.table = xe3lpd_cdclk_table; @@ -3757,80 +3761,80 @@ void intel_init_cdclk_hooks(struct intel_display *display) } else if (DISPLAY_VER(display) >= 14) { display->funcs.cdclk = &rplu_cdclk_funcs; display->cdclk.table = mtl_cdclk_table; - } else if (IS_DG2(dev_priv)) { + } else if (display->platform.dg2) { display->funcs.cdclk = &tgl_cdclk_funcs; display->cdclk.table = dg2_cdclk_table; - } else if (IS_ALDERLAKE_P(dev_priv)) { + } else if (display->platform.alderlake_p) { /* Wa_22011320316:adl-p[a0] */ - if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { + if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) { display->cdclk.table = adlp_a_step_cdclk_table; display->funcs.cdclk = &tgl_cdclk_funcs; - } else if (IS_RAPTORLAKE_U(dev_priv)) { + } else if (display->platform.alderlake_p_raptorlake_u) { display->cdclk.table = rplu_cdclk_table; display->funcs.cdclk = &rplu_cdclk_funcs; } else { display->cdclk.table = adlp_cdclk_table; display->funcs.cdclk = &tgl_cdclk_funcs; } - } else if (IS_ROCKETLAKE(dev_priv)) { + } else if (display->platform.rocketlake) { display->funcs.cdclk = &tgl_cdclk_funcs; display->cdclk.table = rkl_cdclk_table; } else if (DISPLAY_VER(display) >= 12) { display->funcs.cdclk = &tgl_cdclk_funcs; display->cdclk.table = icl_cdclk_table; - } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { + } else if (display->platform.jasperlake || display->platform.elkhartlake) { display->funcs.cdclk = &ehl_cdclk_funcs; display->cdclk.table = icl_cdclk_table; } else if (DISPLAY_VER(display) >= 11) { display->funcs.cdclk = &icl_cdclk_funcs; display->cdclk.table = icl_cdclk_table; - } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { + } else if (display->platform.geminilake || display->platform.broxton) { display->funcs.cdclk = &bxt_cdclk_funcs; - if (IS_GEMINILAKE(dev_priv)) + if (display->platform.geminilake) display->cdclk.table = glk_cdclk_table; else display->cdclk.table = bxt_cdclk_table; } else if (DISPLAY_VER(display) == 9) { display->funcs.cdclk = &skl_cdclk_funcs; - } else if (IS_BROADWELL(dev_priv)) { + } else if (display->platform.broadwell) { display->funcs.cdclk = &bdw_cdclk_funcs; - } else if (IS_HASWELL(dev_priv)) { + } else if (display->platform.haswell) { display->funcs.cdclk = &hsw_cdclk_funcs; - } else if (IS_CHERRYVIEW(dev_priv)) { + } else if (display->platform.cherryview) { display->funcs.cdclk = &chv_cdclk_funcs; - } else if (IS_VALLEYVIEW(dev_priv)) { + } else if (display->platform.valleyview) { display->funcs.cdclk = &vlv_cdclk_funcs; - } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { + } else if (display->platform.sandybridge || display->platform.ivybridge) { display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; - } else if (IS_IRONLAKE(dev_priv)) { + } else if (display->platform.ironlake) { display->funcs.cdclk = &ilk_cdclk_funcs; - } else if (IS_GM45(dev_priv)) { + } else if (display->platform.gm45) { display->funcs.cdclk = &gm45_cdclk_funcs; - } else if (IS_G45(dev_priv)) { + } else if (display->platform.g45) { display->funcs.cdclk = &g33_cdclk_funcs; - } else if (IS_I965GM(dev_priv)) { + } else if (display->platform.i965gm) { display->funcs.cdclk = &i965gm_cdclk_funcs; - } else if (IS_I965G(dev_priv)) { + } else if (display->platform.i965g) { display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; - } else if (IS_PINEVIEW(dev_priv)) { + } else if (display->platform.pineview) { display->funcs.cdclk = &pnv_cdclk_funcs; - } else if (IS_G33(dev_priv)) { + } else if (display->platform.g33) { display->funcs.cdclk = &g33_cdclk_funcs; - } else if (IS_I945GM(dev_priv)) { + } else if (display->platform.i945gm) { display->funcs.cdclk = &i945gm_cdclk_funcs; - } else if (IS_I945G(dev_priv)) { + } else if (display->platform.i945g) { display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; - } else if (IS_I915GM(dev_priv)) { + } else if (display->platform.i915gm) { display->funcs.cdclk = &i915gm_cdclk_funcs; - } else if (IS_I915G(dev_priv)) { + } else if (display->platform.i915g) { display->funcs.cdclk = &i915g_cdclk_funcs; - } else if (IS_I865G(dev_priv)) { + } else if (display->platform.i865g) { display->funcs.cdclk = &i865g_cdclk_funcs; - } else if (IS_I85X(dev_priv)) { + } else if (display->platform.i85x) { display->funcs.cdclk = &i85x_cdclk_funcs; - } else if (IS_I845G(dev_priv)) { + } else if (display->platform.i845g) { display->funcs.cdclk = &i845g_cdclk_funcs; - } else if (IS_I830(dev_priv)) { + } else if (display->platform.i830) { display->funcs.cdclk = &i830_cdclk_funcs; } diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index 6b0e7a41eba3..a1cefd455d92 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -12,6 +12,7 @@ #include "intel_global_state.h" struct intel_atomic_state; +struct intel_crtc; struct intel_crtc_state; struct intel_display; @@ -58,7 +59,6 @@ struct intel_cdclk_state { bool disable_pipes; }; -int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); void intel_cdclk_init_hw(struct intel_display *display); void intel_cdclk_uninit_hw(struct intel_display *display); void intel_init_cdclk_hooks(struct intel_display *display); @@ -83,6 +83,8 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state, int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus); struct intel_cdclk_state * intel_atomic_get_cdclk_state(struct intel_atomic_state *state); +void intel_cdclk_update_hw_state(struct intel_display *display); +void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc); #define to_intel_cdclk_state(global_state) \ container_of_const((global_state), struct intel_cdclk_state, base) diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c new file mode 100644 index 000000000000..07d7f4e8f60f --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2025 Intel Corporation + */ + +#include <linux/string_choices.h> +#include <linux/types.h> + +#include <drm/drm_device.h> +#include <drm/drm_print.h> + +#include "i915_drv.h" +#include "i915_reg.h" +#include "intel_crtc.h" +#include "intel_cmtg.h" +#include "intel_cmtg_regs.h" +#include "intel_de.h" +#include "intel_display_device.h" +#include "intel_display_power.h" + +/** + * DOC: Common Primary Timing Generator (CMTG) + * + * The CMTG is a timing generator that runs in parallel to transcoders timing + * generators (TG) to provide a synchronization mechanism where CMTG acts as + * primary and transcoders TGs act as secondary to the CMTG. The CMTG outputs + * its TG start and frame sync signals to the transcoders that are configured + * as secondary, which use those signals to synchronize their own timing with + * the CMTG's. + * + * The CMTG can be used only with eDP or MIPI command mode and supports the + * following use cases: + * + * - Dual eDP: The CMTG can be used to keep two eDP TGs in sync when on a + * dual eDP configuration (with or without PSR/PSR2 enabled). + * + * - Single eDP as secondary: It is also possible to use a single eDP + * configuration with the transcoder TG as secondary to the CMTG. That would + * allow a flow that would not require a modeset on the existing eDP when a + * new eDP is added for a dual eDP configuration with CMTG. + * + * - DC6v: In DC6v, the transcoder might be off but the CMTG keeps running to + * maintain frame timings. When exiting DC6v, the transcoder TG then is + * synced back the CMTG. + * + * Currently, the driver does not use the CMTG, but we need to make sure that + * we disable it in case we inherit a display configuration with it enabled. + */ + +/* + * We describe here only the minimum data required to allow us to properly + * disable the CMTG if necessary. + */ +struct intel_cmtg_config { + bool cmtg_a_enable; + /* + * Xe2_LPD adds a second CMTG that can be used for dual eDP async mode. + */ + bool cmtg_b_enable; + bool trans_a_secondary; + bool trans_b_secondary; +}; + +static bool intel_cmtg_has_cmtg_b(struct intel_display *display) +{ + return DISPLAY_VER(display) >= 20; +} + +static bool intel_cmtg_has_clock_sel(struct intel_display *display) +{ + return DISPLAY_VER(display) >= 14; +} + +static void intel_cmtg_dump_config(struct intel_display *display, + struct intel_cmtg_config *cmtg_config) +{ + drm_dbg_kms(display->drm, + "CMTG readout: CMTG A: %s, CMTG B: %s, Transcoder A secondary: %s, Transcoder B secondary: %s\n", + str_enabled_disabled(cmtg_config->cmtg_a_enable), + intel_cmtg_has_cmtg_b(display) ? str_enabled_disabled(cmtg_config->cmtg_b_enable) : "n/a", + str_yes_no(cmtg_config->trans_a_secondary), + str_yes_no(cmtg_config->trans_b_secondary)); +} + +static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display, + enum transcoder trans) +{ + enum intel_display_power_domain power_domain; + intel_wakeref_t wakeref; + u32 val = 0; + + if (!HAS_TRANSCODER(display, trans)) + return false; + + power_domain = POWER_DOMAIN_TRANSCODER(trans); + + with_intel_display_power_if_enabled(display, power_domain, wakeref) + val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans)); + + return val & CMTG_SECONDARY_MODE; +} + +static void intel_cmtg_get_config(struct intel_display *display, + struct intel_cmtg_config *cmtg_config) +{ + u32 val; + + val = intel_de_read(display, TRANS_CMTG_CTL_A); + cmtg_config->cmtg_a_enable = val & CMTG_ENABLE; + + if (intel_cmtg_has_cmtg_b(display)) { + val = intel_de_read(display, TRANS_CMTG_CTL_B); + cmtg_config->cmtg_b_enable = val & CMTG_ENABLE; + } + + cmtg_config->trans_a_secondary = intel_cmtg_transcoder_is_secondary(display, TRANSCODER_A); + cmtg_config->trans_b_secondary = intel_cmtg_transcoder_is_secondary(display, TRANSCODER_B); +} + +static bool intel_cmtg_disable_requires_modeset(struct intel_display *display, + struct intel_cmtg_config *cmtg_config) +{ + if (DISPLAY_VER(display) >= 20) + return false; + + return cmtg_config->trans_a_secondary || cmtg_config->trans_b_secondary; +} + +static void intel_cmtg_disable(struct intel_display *display, + struct intel_cmtg_config *cmtg_config) +{ + u32 clk_sel_clr = 0; + u32 clk_sel_set = 0; + + if (cmtg_config->trans_a_secondary) + intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_A), + CMTG_SECONDARY_MODE, 0); + + if (cmtg_config->trans_b_secondary) + intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_B), + CMTG_SECONDARY_MODE, 0); + + if (cmtg_config->cmtg_a_enable) { + drm_dbg_kms(display->drm, "Disabling CMTG A\n"); + intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE, 0); + clk_sel_clr |= CMTG_CLK_SEL_A_MASK; + clk_sel_set |= CMTG_CLK_SEL_A_DISABLED; + } + + if (cmtg_config->cmtg_b_enable) { + drm_dbg_kms(display->drm, "Disabling CMTG B\n"); + intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE, 0); + clk_sel_clr |= CMTG_CLK_SEL_B_MASK; + clk_sel_set |= CMTG_CLK_SEL_B_DISABLED; + } + + if (intel_cmtg_has_clock_sel(display) && clk_sel_clr) + intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set); +} + +/* + * Read out CMTG configuration and, on platforms that allow disabling it without + * a modeset, do it. + * + * This function must be called before any port PLL is disabled in the general + * sanitization process, because we need whatever port PLL that is providing the + * clock for CMTG to be on before accessing CMTG registers. + */ +void intel_cmtg_sanitize(struct intel_display *display) +{ + struct intel_cmtg_config cmtg_config = {}; + + if (!HAS_CMTG(display)) + return; + + intel_cmtg_get_config(display, &cmtg_config); + intel_cmtg_dump_config(display, &cmtg_config); + + /* + * FIXME: The driver is not prepared to handle cases where a modeset is + * required for disabling the CMTG: we need a proper way of tracking + * CMTG state and do the right syncronization with respect to triggering + * the modeset as part of the disable sequence. + */ + if (intel_cmtg_disable_requires_modeset(display, &cmtg_config)) + return; + + intel_cmtg_disable(display, &cmtg_config); +} diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h new file mode 100644 index 000000000000..ba62199adaa2 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2025 Intel Corporation + */ + +#ifndef __INTEL_CMTG_H__ +#define __INTEL_CMTG_H__ + +struct intel_display; + +void intel_cmtg_sanitize(struct intel_display *display); + +#endif /* __INTEL_CMTG_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h new file mode 100644 index 000000000000..668e41d65e86 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2025 Intel Corporation + */ + +#ifndef __INTEL_CMTG_REGS_H__ +#define __INTEL_CMTG_REGS_H__ + +#include "i915_reg_defs.h" + +#define CMTG_CLK_SEL _MMIO(0x46160) +#define CMTG_CLK_SEL_A_MASK REG_GENMASK(31, 29) +#define CMTG_CLK_SEL_A_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0) +#define CMTG_CLK_SEL_B_MASK REG_GENMASK(15, 13) +#define CMTG_CLK_SEL_B_DISABLED REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0) + +#define TRANS_CMTG_CTL_A _MMIO(0x6fa88) +#define TRANS_CMTG_CTL_B _MMIO(0x6fb88) +#define CMTG_ENABLE REG_BIT(31) + +#endif /* __INTEL_CMTG_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 2f51eccdb27a..cfe14162231d 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -29,6 +29,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_dsb.h" +#include "intel_vrr.h" struct intel_color_funcs { int (*color_check)(struct intel_atomic_state *state, @@ -998,7 +999,7 @@ static void skl_color_commit_noarm(struct intel_dsb *dsb, * output all black (until CSC_MODE is rearmed and properly latched). * Once PSR exit (and proper register latching) has occurred the * danger is over. Thus when PSR is enabled the CSC coeff/offset - * register programming will be peformed from skl_color_commit_arm() + * register programming will be performed from skl_color_commit_arm() * which is called after PSR exit. */ if (!crtc_state->has_psr) @@ -1987,8 +1988,12 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, display->funcs.color->load_luts(crtc_state); - intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color_vblank); - intel_dsb_interrupt(crtc_state->dsb_color_vblank); + if (crtc_state->use_dsb) { + intel_vrr_send_push(crtc_state->dsb_color_vblank, crtc_state); + intel_dsb_wait_vblank_delay(state, crtc_state->dsb_color_vblank); + intel_vrr_check_push_sent(crtc_state->dsb_color_vblank, crtc_state); + intel_dsb_interrupt(crtc_state->dsb_color_vblank); + } intel_dsb_finish(crtc_state->dsb_color_vblank); } diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 4fbe2e3542ca..17eea244cc83 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -3,20 +3,20 @@ * Copyright © 2018 Intel Corporation */ -#include "i915_drv.h" #include "i915_reg.h" +#include "i915_utils.h" #include "intel_combo_phy.h" #include "intel_combo_phy_regs.h" #include "intel_de.h" #include "intel_display_types.h" -#define for_each_combo_phy(__dev_priv, __phy) \ +#define for_each_combo_phy(__display, __phy) \ for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ - for_each_if(intel_phy_is_combo(__dev_priv, __phy)) + for_each_if(intel_phy_is_combo(__display, __phy)) -#define for_each_combo_phy_reverse(__dev_priv, __phy) \ +#define for_each_combo_phy_reverse(__display, __phy) \ for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \ - for_each_if(intel_phy_is_combo(__dev_priv, __phy)) + for_each_if(intel_phy_is_combo(__display, __phy)) enum { PROCMON_0_85V_DOT_0, @@ -53,11 +53,11 @@ static const struct icl_procmon { }; static const struct icl_procmon * -icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) +icl_get_procmon_ref_values(struct intel_display *display, enum phy phy) { u32 val; - val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); + val = intel_de_read(display, ICL_PORT_COMP_DW3(phy)); switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { default: MISSING_CASE(val); @@ -75,57 +75,57 @@ icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) } } -static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv, +static void icl_set_procmon_ref_values(struct intel_display *display, enum phy phy) { const struct icl_procmon *procmon; - procmon = icl_get_procmon_ref_values(dev_priv, phy); + procmon = icl_get_procmon_ref_values(display, phy); - intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy), + intel_de_rmw(display, ICL_PORT_COMP_DW1(phy), (0xff << 16) | 0xff, procmon->dw1); - intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); - intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); + intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9); + intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10); } -static bool check_phy_reg(struct drm_i915_private *dev_priv, +static bool check_phy_reg(struct intel_display *display, enum phy phy, i915_reg_t reg, u32 mask, u32 expected_val) { - u32 val = intel_de_read(dev_priv, reg); + u32 val = intel_de_read(display, reg); if ((val & mask) != expected_val) { - drm_dbg(&dev_priv->drm, - "Combo PHY %c reg %08x state mismatch: " - "current %08x mask %08x expected %08x\n", - phy_name(phy), - reg.reg, val, mask, expected_val); + drm_dbg_kms(display->drm, + "Combo PHY %c reg %08x state mismatch: " + "current %08x mask %08x expected %08x\n", + phy_name(phy), + reg.reg, val, mask, expected_val); return false; } return true; } -static bool icl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, +static bool icl_verify_procmon_ref_values(struct intel_display *display, enum phy phy) { const struct icl_procmon *procmon; bool ret; - procmon = icl_get_procmon_ref_values(dev_priv, phy); + procmon = icl_get_procmon_ref_values(display, phy); - ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), + ret = check_phy_reg(display, phy, ICL_PORT_COMP_DW1(phy), (0xff << 16) | 0xff, procmon->dw1); - ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), + ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW9(phy), -1U, procmon->dw9); - ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), + ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW10(phy), -1U, procmon->dw10); return ret; } -static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) +static bool has_phy_misc(struct intel_display *display, enum phy phy) { /* * Some platforms only expect PHY_MISC to be programmed for PHY-A and @@ -136,32 +136,30 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) * that we program it for PHY A. */ - if (IS_ALDERLAKE_S(i915)) + if (display->platform.alderlake_s) return phy == PHY_A; - else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) || - IS_ROCKETLAKE(i915) || - IS_DG1(i915)) + else if ((display->platform.jasperlake || display->platform.elkhartlake) || + display->platform.rocketlake || + display->platform.dg1) return phy < PHY_C; return true; } -static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, +static bool icl_combo_phy_enabled(struct intel_display *display, enum phy phy) { /* The PHY C added by EHL has no PHY_MISC register */ - if (!has_phy_misc(dev_priv, phy)) - return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; + if (!has_phy_misc(display, phy)) + return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; else - return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & + return !(intel_de_read(display, ICL_PHY_MISC(phy)) & ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) && - (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); + (intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); } -static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915) +static bool ehl_vbt_ddi_d_present(struct intel_display *display) { - struct intel_display *display = &i915->display; - bool ddi_a_present = intel_bios_is_port_present(display, PORT_A); bool ddi_d_present = intel_bios_is_port_present(display, PORT_D); bool dsi_present = intel_bios_is_dsi_present(display, NULL); @@ -181,13 +179,13 @@ static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915) * in the log and let the internal display win. */ if (ddi_d_present) - drm_err(&i915->drm, + drm_err(display->drm, "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n"); return false; } -static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) +static bool phy_is_master(struct intel_display *display, enum phy phy) { /* * Certain PHYs are connected to compensation resistors and act @@ -207,64 +205,64 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) */ if (phy == PHY_A) return true; - else if (IS_ALDERLAKE_S(dev_priv)) + else if (display->platform.alderlake_s) return phy == PHY_D; - else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) + else if (display->platform.dg1 || display->platform.rocketlake) return phy == PHY_C; return false; } -static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, +static bool icl_combo_phy_verify_state(struct intel_display *display, enum phy phy) { bool ret = true; u32 expected_val = 0; - if (!icl_combo_phy_enabled(dev_priv, phy)) + if (!icl_combo_phy_enabled(display, phy)) return false; - if (DISPLAY_VER(dev_priv) >= 12) { - ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy), + if (DISPLAY_VER(display) >= 12) { + ret &= check_phy_reg(display, phy, ICL_PORT_TX_DW8_LN(0, phy), ICL_PORT_TX_DW8_ODCC_CLK_SEL | ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, ICL_PORT_TX_DW8_ODCC_CLK_SEL | ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2); - ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy), + ret &= check_phy_reg(display, phy, ICL_PORT_PCS_DW1_LN(0, phy), DCC_MODE_SELECT_MASK, RUN_DCC_ONCE); } - ret &= icl_verify_procmon_ref_values(dev_priv, phy); + ret &= icl_verify_procmon_ref_values(display, phy); - if (phy_is_master(dev_priv, phy)) { - ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), + if (phy_is_master(display, phy)) { + ret &= check_phy_reg(display, phy, ICL_PORT_COMP_DW8(phy), IREFGEN, IREFGEN); - if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { - if (ehl_vbt_ddi_d_present(dev_priv)) + if (display->platform.jasperlake || display->platform.elkhartlake) { + if (ehl_vbt_ddi_d_present(display)) expected_val = ICL_PHY_MISC_MUX_DDID; - ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy), + ret &= check_phy_reg(display, phy, ICL_PHY_MISC(phy), ICL_PHY_MISC_MUX_DDID, expected_val); } } - ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), + ret &= check_phy_reg(display, phy, ICL_PORT_CL_DW5(phy), CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); return ret; } -void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, +void intel_combo_phy_power_up_lanes(struct intel_display *display, enum phy phy, bool is_dsi, int lane_count, bool lane_reversal) { u8 lane_mask; if (is_dsi) { - drm_WARN_ON(&dev_priv->drm, lane_reversal); + drm_WARN_ON(display->drm, lane_reversal); switch (lane_count) { case 1: @@ -302,28 +300,28 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, } } - intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), + intel_de_rmw(display, ICL_PORT_CL_DW10(phy), PWR_DOWN_LN_MASK, lane_mask); } -static void icl_combo_phys_init(struct drm_i915_private *dev_priv) +static void icl_combo_phys_init(struct intel_display *display) { enum phy phy; - for_each_combo_phy(dev_priv, phy) { + for_each_combo_phy(display, phy) { const struct icl_procmon *procmon; u32 val; - if (icl_combo_phy_verify_state(dev_priv, phy)) + if (icl_combo_phy_verify_state(display, phy)) continue; - procmon = icl_get_procmon_ref_values(dev_priv, phy); + procmon = icl_get_procmon_ref_values(display, phy); - drm_dbg(&dev_priv->drm, - "Initializing combo PHY %c (Voltage/Process Info : %s)\n", - phy_name(phy), procmon->name); + drm_dbg_kms(display->drm, + "Initializing combo PHY %c (Voltage/Process Info : %s)\n", + phy_name(phy), procmon->name); - if (!has_phy_misc(dev_priv, phy)) + if (!has_phy_misc(display, phy)) goto skip_phy_misc; /* @@ -334,84 +332,84 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) * based on whether our VBT indicates the presence of any * "internal" child devices. */ - val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); - if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && + val = intel_de_read(display, ICL_PHY_MISC(phy)); + if ((display->platform.jasperlake || display->platform.elkhartlake) && phy == PHY_A) { val &= ~ICL_PHY_MISC_MUX_DDID; - if (ehl_vbt_ddi_d_present(dev_priv)) + if (ehl_vbt_ddi_d_present(display)) val |= ICL_PHY_MISC_MUX_DDID; } val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; - intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); + intel_de_write(display, ICL_PHY_MISC(phy), val); skip_phy_misc: - if (DISPLAY_VER(dev_priv) >= 12) { - val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy)); + if (DISPLAY_VER(display) >= 12) { + val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy)); val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK; val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL; val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2; - intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); + intel_de_write(display, ICL_PORT_TX_DW8_GRP(phy), val); - val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); + val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); val &= ~DCC_MODE_SELECT_MASK; val |= RUN_DCC_ONCE; - intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); + intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); } - icl_set_procmon_ref_values(dev_priv, phy); + icl_set_procmon_ref_values(display, phy); - if (phy_is_master(dev_priv, phy)) - intel_de_rmw(dev_priv, ICL_PORT_COMP_DW8(phy), + if (phy_is_master(display, phy)) + intel_de_rmw(display, ICL_PORT_COMP_DW8(phy), 0, IREFGEN); - intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT); - intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), + intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT); + intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0, CL_POWER_DOWN_ENABLE); } } -static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) +static void icl_combo_phys_uninit(struct intel_display *display) { enum phy phy; - for_each_combo_phy_reverse(dev_priv, phy) { + for_each_combo_phy_reverse(display, phy) { if (phy == PHY_A && - !icl_combo_phy_verify_state(dev_priv, phy)) { - if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) { + !icl_combo_phy_verify_state(display, phy)) { + if (display->platform.tigerlake || display->platform.dg1) { /* * A known problem with old ifwi: * https://gitlab.freedesktop.org/drm/intel/-/issues/2411 * Suppress the warning for CI. Remove ASAP! */ - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Combo PHY %c HW state changed unexpectedly\n", phy_name(phy)); } else { - drm_warn(&dev_priv->drm, + drm_warn(display->drm, "Combo PHY %c HW state changed unexpectedly\n", phy_name(phy)); } } - if (!has_phy_misc(dev_priv, phy)) + if (!has_phy_misc(display, phy)) goto skip_phy_misc; - intel_de_rmw(dev_priv, ICL_PHY_MISC(phy), 0, + intel_de_rmw(display, ICL_PHY_MISC(phy), 0, ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN); skip_phy_misc: - intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0); + intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0); } } -void intel_combo_phy_init(struct drm_i915_private *i915) +void intel_combo_phy_init(struct intel_display *display) { - icl_combo_phys_init(i915); + icl_combo_phys_init(display); } -void intel_combo_phy_uninit(struct drm_i915_private *i915) +void intel_combo_phy_uninit(struct intel_display *display) { - icl_combo_phys_uninit(i915); + icl_combo_phys_uninit(display); } diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.h b/drivers/gpu/drm/i915/display/intel_combo_phy.h index 660886f86c59..3f5dba78e533 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.h +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.h @@ -8,12 +8,12 @@ #include <linux/types.h> -struct drm_i915_private; enum phy; +struct intel_display; -void intel_combo_phy_init(struct drm_i915_private *dev_priv); -void intel_combo_phy_uninit(struct drm_i915_private *dev_priv); -void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, +void intel_combo_phy_init(struct intel_display *display); +void intel_combo_phy_uninit(struct intel_display *display); +void intel_combo_phy_power_up_lanes(struct intel_display *display, enum phy phy, bool is_dsi, int lane_count, bool lane_reversal); diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h index 0964e392d02c..ee41acdccf4e 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_combo_phy_regs.h @@ -133,6 +133,8 @@ #define TX_TRAINING_EN REG_BIT(31) #define TAP2_DISABLE REG_BIT(30) #define TAP3_DISABLE REG_BIT(29) +#define CURSOR_PROGRAM REG_BIT(26) +#define COEFF_POLARITY REG_BIT(25) #define SCALING_MODE_SEL_MASK REG_GENMASK(20, 18) #define SCALING_MODE_SEL(x) REG_FIELD_PREP(SCALING_MODE_SEL_MASK, (x)) #define RTERM_SELECT_MASK REG_GENMASK(5, 3) diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c index c65887870ddc..e42357bd9e80 100644 --- a/drivers/gpu/drm/i915/display/intel_connector.c +++ b/drivers/gpu/drm/i915/display/intel_connector.c @@ -28,6 +28,7 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_edid.h> +#include <drm/drm_probe_helper.h> #include "i915_drv.h" #include "intel_backlight.h" @@ -37,6 +38,44 @@ #include "intel_hdcp.h" #include "intel_panel.h" +static void intel_connector_modeset_retry_work_fn(struct work_struct *work) +{ + struct intel_connector *connector = container_of(work, typeof(*connector), + modeset_retry_work); + struct intel_display *display = to_intel_display(connector); + + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.base.id, + connector->base.name); + + /* Grab the locks before changing connector property*/ + mutex_lock(&display->drm->mode_config.mutex); + /* Set connector link status to BAD and send a Uevent to notify + * userspace to do a modeset. + */ + drm_connector_set_link_status_property(&connector->base, + DRM_MODE_LINK_STATUS_BAD); + mutex_unlock(&display->drm->mode_config.mutex); + /* Send Hotplug uevent so userspace can reprobe */ + drm_kms_helper_connector_hotplug_event(&connector->base); + + drm_connector_put(&connector->base); +} + +void intel_connector_queue_modeset_retry_work(struct intel_connector *connector) +{ + struct drm_i915_private *i915 = to_i915(connector->base.dev); + + drm_connector_get(&connector->base); + if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work)) + drm_connector_put(&connector->base); +} + +void intel_connector_cancel_modeset_retry_work(struct intel_connector *connector) +{ + if (cancel_work_sync(&connector->modeset_retry_work)) + drm_connector_put(&connector->base); +} + int intel_connector_init(struct intel_connector *connector) { struct intel_digital_connector_state *conn_state; @@ -56,6 +95,9 @@ int intel_connector_init(struct intel_connector *connector) intel_panel_init_alloc(connector); + INIT_WORK(&connector->modeset_retry_work, + intel_connector_modeset_retry_work_fn); + return 0; } @@ -103,8 +145,8 @@ void intel_connector_destroy(struct drm_connector *connector) drm_connector_cleanup(connector); - if (intel_connector->port) - drm_dp_mst_put_port_malloc(intel_connector->port); + if (intel_connector->mst.port) + drm_dp_mst_put_port_malloc(intel_connector->mst.port); kfree(connector); } diff --git a/drivers/gpu/drm/i915/display/intel_connector.h b/drivers/gpu/drm/i915/display/intel_connector.h index bafde3f11ff4..aafb25a814fa 100644 --- a/drivers/gpu/drm/i915/display/intel_connector.h +++ b/drivers/gpu/drm/i915/display/intel_connector.h @@ -33,5 +33,7 @@ void intel_attach_aspect_ratio_property(struct drm_connector *connector); void intel_attach_hdmi_colorspace_property(struct drm_connector *connector); void intel_attach_dp_colorspace_property(struct drm_connector *connector); void intel_attach_scaling_mode_property(struct drm_connector *connector); +void intel_connector_queue_modeset_retry_work(struct intel_connector *connector); +void intel_connector_cancel_modeset_retry_work(struct intel_connector *connector); #endif /* __INTEL_CONNECTOR_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 4634d3fd9f20..76ffb3f8467c 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -54,6 +54,7 @@ #include "intel_load_detect.h" #include "intel_pch_display.h" #include "intel_pch_refclk.h" +#include "intel_pfit.h" /* Here's the desired hotplug mode */ #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_ENABLE | \ @@ -108,19 +109,18 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crt *crt = intel_encoder_to_crt(encoder); intel_wakeref_t wakeref; bool ret; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe); - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } @@ -251,11 +251,10 @@ static void hsw_disable_crt(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); + intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); } static void hsw_post_disable_crt(struct intel_atomic_state *state, @@ -265,7 +264,6 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); intel_crtc_vblank_off(old_crtc_state); @@ -285,7 +283,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state, drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); + intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); } static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state, @@ -294,11 +292,10 @@ static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); + intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); } static void hsw_pre_enable_crt(struct intel_atomic_state *state, @@ -307,13 +304,12 @@ static void hsw_pre_enable_crt(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum pipe pipe = crtc->pipe; drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); + intel_set_cpu_fifo_underrun_reporting(display, pipe, false); hsw_fdi_link_train(encoder, crtc_state); @@ -326,7 +322,6 @@ static void hsw_enable_crt(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum pipe pipe = crtc->pipe; @@ -344,8 +339,8 @@ static void hsw_enable_crt(struct intel_atomic_state *state, intel_crtc_wait_for_next_vblank(crtc); intel_crtc_wait_for_next_vblank(crtc); - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); + intel_set_cpu_fifo_underrun_reporting(display, pipe, true); + intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); } static void intel_enable_crt(struct intel_atomic_state *state, @@ -358,7 +353,7 @@ static void intel_enable_crt(struct intel_atomic_state *state, static enum drm_mode_status intel_crt_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { struct intel_display *display = to_intel_display(connector->dev); struct drm_i915_private *dev_priv = to_i915(connector->dev); @@ -366,7 +361,7 @@ intel_crt_mode_valid(struct drm_connector *connector, enum drm_mode_status status; int max_clock; - status = intel_cpu_transcoder_mode_valid(dev_priv, mode); + status = intel_cpu_transcoder_mode_valid(display, mode); if (status != MODE_OK) return status; @@ -745,8 +740,10 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) transconf | TRANSCONF_FORCE_BORDER); intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); - /* Wait for next Vblank to substitue - * border color for Color info */ + /* + * Wait for next Vblank to substitute + * border color for Color info. + */ intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); st00 = intel_de_read8(display, _VGA_MSR_WRITE); status = ((st00 & (1 << 4)) != 0) ? @@ -856,7 +853,6 @@ intel_crt_detect(struct drm_connector *connector, bool force) { struct intel_display *display = to_intel_display(connector->dev); - struct drm_i915_private *dev_priv = to_i915(connector->dev); struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); struct intel_encoder *encoder = &crt->base; struct drm_atomic_state *state; @@ -874,7 +870,7 @@ intel_crt_detect(struct drm_connector *connector, return connector->status; if (display->params.load_detect_test) { - wakeref = intel_display_power_get(dev_priv, encoder->power_domain); + wakeref = intel_display_power_get(display, encoder->power_domain); goto load_detect; } @@ -882,7 +878,7 @@ intel_crt_detect(struct drm_connector *connector, if (dmi_check_system(intel_spurious_crt_detect)) return connector_status_disconnected; - wakeref = intel_display_power_get(dev_priv, encoder->power_domain); + wakeref = intel_display_power_get(display, encoder->power_domain); if (I915_HAS_HOTPLUG(display)) { /* We can not rely on the HPD pin always being correctly wired @@ -939,7 +935,7 @@ load_detect: } out: - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return status; } @@ -957,7 +953,7 @@ static int intel_crt_get_modes(struct drm_connector *connector) if (!intel_display_driver_check_access(display)) return drm_edid_connector_add_modes(connector); - wakeref = intel_display_power_get(dev_priv, encoder->power_domain); + wakeref = intel_display_power_get(display, encoder->power_domain); ret = intel_crt_ddc_get_modes(connector, connector->ddc); if (ret || !IS_G4X(dev_priv)) @@ -968,7 +964,7 @@ static int intel_crt_get_modes(struct drm_connector *connector) ret = intel_crt_ddc_get_modes(connector, ddc); out: - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } @@ -1099,7 +1095,7 @@ void intel_crt_init(struct intel_display *display) connector->base.polled = connector->polled; if (HAS_DDI(display)) { - assert_port_valid(dev_priv, PORT_E); + assert_port_valid(display, PORT_E); crt->base.port = PORT_E; crt->base.get_config = hsw_crt_get_config; diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index c910168602d2..5b2603ef2ff7 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -45,9 +45,9 @@ static void assert_vblank_disabled(struct drm_crtc *crtc) drm_crtc_vblank_put(crtc); } -struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915) +struct intel_crtc *intel_first_crtc(struct intel_display *display) { - return to_intel_crtc(drm_crtc_from_index(&i915->drm, 0)); + return to_intel_crtc(drm_crtc_from_index(display->drm, 0)); } struct intel_crtc *intel_crtc_for_pipe(struct intel_display *display, @@ -68,10 +68,9 @@ void intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc) drm_crtc_wait_one_vblank(&crtc->base); } -void intel_wait_for_vblank_if_active(struct drm_i915_private *i915, +void intel_wait_for_vblank_if_active(struct intel_display *display, enum pipe pipe) { - struct intel_display *display = &i915->display; struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); if (crtc->active) @@ -93,10 +92,10 @@ u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); /* - * From Gen 11, In case of dsi cmd mode, frame counter wouldnt + * From Gen 11, in case of dsi cmd mode, frame counter wouldn't * have updated at the beginning of TE, if we want to use * the hw counter, then we would find it updated in only * the next TE, hence switching to sw counter. @@ -109,13 +108,13 @@ u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state) * On i965gm the hardware frame counter reads * zero when the TV encoder is enabled :( */ - if (IS_I965GM(dev_priv) && + if (display->platform.i965gm && (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT))) return 0; - if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) return 0xffffffff; /* full 32 bit counter */ - else if (DISPLAY_VER(dev_priv) >= 3) + else if (DISPLAY_VER(display) >= 3) return 0xffffff; /* only 24 bits of frame count */ else return 0; /* Gen2 doesn't have a hardware frame counter */ @@ -142,8 +141,8 @@ void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state) void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_display *display = to_intel_display(crtc); /* * Should really happen exactly when we disable the pipe @@ -304,8 +303,9 @@ static const struct drm_crtc_funcs i8xx_crtc_funcs = { .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, }; -int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) +int intel_crtc_init(struct intel_display *display, enum pipe pipe) { + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_plane *primary, *cursor; const struct drm_crtc_funcs *funcs; struct intel_crtc *crtc; @@ -316,27 +316,27 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) return PTR_ERR(crtc); crtc->pipe = pipe; - crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe]; + crtc->num_scalers = DISPLAY_RUNTIME_INFO(display)->num_scalers[pipe]; - if (DISPLAY_VER(dev_priv) >= 9) - primary = skl_universal_plane_create(dev_priv, pipe, PLANE_1); + if (DISPLAY_VER(display) >= 9) + primary = skl_universal_plane_create(display, pipe, PLANE_1); else - primary = intel_primary_plane_create(dev_priv, pipe); + primary = intel_primary_plane_create(display, pipe); if (IS_ERR(primary)) { ret = PTR_ERR(primary); goto fail; } crtc->plane_ids_mask |= BIT(primary->id); - intel_init_fifo_underrun_reporting(dev_priv, crtc, false); + intel_init_fifo_underrun_reporting(display, crtc, false); - for_each_sprite(dev_priv, pipe, sprite) { + for_each_sprite(display, pipe, sprite) { struct intel_plane *plane; if (DISPLAY_VER(dev_priv) >= 9) - plane = skl_universal_plane_create(dev_priv, pipe, PLANE_2 + sprite); + plane = skl_universal_plane_create(display, pipe, PLANE_2 + sprite); else - plane = intel_sprite_plane_create(dev_priv, pipe, sprite); + plane = intel_sprite_plane_create(display, pipe, sprite); if (IS_ERR(plane)) { ret = PTR_ERR(plane); goto fail; @@ -344,39 +344,41 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) crtc->plane_ids_mask |= BIT(plane->id); } - cursor = intel_cursor_plane_create(dev_priv, pipe); + cursor = intel_cursor_plane_create(display, pipe); if (IS_ERR(cursor)) { ret = PTR_ERR(cursor); goto fail; } crtc->plane_ids_mask |= BIT(cursor->id); - if (HAS_GMCH(dev_priv)) { - if (IS_CHERRYVIEW(dev_priv) || - IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv)) + if (HAS_GMCH(display)) { + if (display->platform.cherryview || + display->platform.valleyview || + display->platform.g4x) funcs = &g4x_crtc_funcs; - else if (DISPLAY_VER(dev_priv) == 4) + else if (DISPLAY_VER(display) == 4) funcs = &i965_crtc_funcs; - else if (IS_I945GM(dev_priv) || IS_I915GM(dev_priv)) + else if (display->platform.i945gm || + display->platform.i915gm) funcs = &i915gm_crtc_funcs; - else if (DISPLAY_VER(dev_priv) == 3) + else if (DISPLAY_VER(display) == 3) funcs = &i915_crtc_funcs; else funcs = &i8xx_crtc_funcs; } else { - if (DISPLAY_VER(dev_priv) >= 8) + if (DISPLAY_VER(display) >= 8) funcs = &bdw_crtc_funcs; else funcs = &ilk_crtc_funcs; } - ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base, + ret = drm_crtc_init_with_planes(display->drm, &crtc->base, &primary->base, &cursor->base, funcs, "pipe %c", pipe_name(pipe)); if (ret) goto fail; - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) drm_crtc_create_scaling_filter_property(&crtc->base, BIT(DRM_SCALING_FILTER_DEFAULT) | BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); @@ -387,7 +389,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) cpu_latency_qos_add_request(&crtc->vblank_pm_qos, PM_QOS_DEFAULT_VALUE); - drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe); + drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe); return 0; @@ -512,7 +514,7 @@ int intel_scanlines_to_usecs(const struct drm_display_mode *adjusted_mode, void intel_pipe_update_start(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); struct intel_crtc_state *new_crtc_state = @@ -520,6 +522,8 @@ void intel_pipe_update_start(struct intel_atomic_state *state, struct intel_vblank_evade_ctx evade; int scanline; + drm_WARN_ON(display->drm, new_crtc_state->use_dsb); + intel_psr_lock(new_crtc_state); if (new_crtc_state->do_async_flip) { @@ -546,7 +550,7 @@ void intel_pipe_update_start(struct intel_atomic_state *state, intel_vblank_evade_init(old_crtc_state, new_crtc_state, &evade); - if (drm_WARN_ON(&dev_priv->drm, drm_crtc_vblank_get(&crtc->base))) + if (drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) goto irq_disable; /* @@ -649,6 +653,7 @@ void intel_crtc_prepare_vblank_event(struct intel_crtc_state *crtc_state, void intel_pipe_update_end(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; @@ -657,6 +662,8 @@ void intel_pipe_update_end(struct intel_atomic_state *state, ktime_t end_vbl_time = ktime_get(); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + drm_WARN_ON(display->drm, new_crtc_state->use_dsb); + if (new_crtc_state->do_async_flip) goto out; @@ -666,7 +673,7 @@ void intel_pipe_update_end(struct intel_atomic_state *state, * Incase of mipi dsi command mode, we need to set frame update * request for every commit. */ - if (DISPLAY_VER(dev_priv) >= 11 && + if (DISPLAY_VER(display) >= 11 && intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) icl_dsi_frame_update(new_crtc_state); @@ -714,7 +721,8 @@ void intel_pipe_update_end(struct intel_atomic_state *state, * which would cause the next frame to terminate already at vmin * vblank start instead of vmax vblank start. */ - intel_vrr_send_push(new_crtc_state); + if (!state->base.legacy_cursor_update) + intel_vrr_send_push(NULL, new_crtc_state); local_irq_enable(); @@ -723,7 +731,7 @@ void intel_pipe_update_end(struct intel_atomic_state *state, if (crtc->debug.start_vbl_count && crtc->debug.start_vbl_count != end_vbl_count) { - drm_err(&dev_priv->drm, + drm_err(display->drm, "Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", pipe_name(pipe), crtc->debug.start_vbl_count, end_vbl_count, diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h index de54ae1deedf..8c14ff8b391e 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.h +++ b/drivers/gpu/drm/i915/display/intel_crtc.h @@ -13,7 +13,6 @@ enum pipe; struct drm_device; struct drm_display_mode; struct drm_file; -struct drm_i915_private; struct drm_pending_vblank_event; struct intel_atomic_state; struct intel_crtc; @@ -38,7 +37,7 @@ void intel_crtc_arm_vblank_event(struct intel_crtc_state *crtc_state); void intel_crtc_prepare_vblank_event(struct intel_crtc_state *crtc_state, struct drm_pending_vblank_event **event); u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state); -int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe); +int intel_crtc_init(struct intel_display *display, enum pipe pipe); int intel_crtc_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc); @@ -52,10 +51,10 @@ void intel_pipe_update_start(struct intel_atomic_state *state, void intel_pipe_update_end(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_wait_for_vblank_workers(struct intel_atomic_state *state); -struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915); +struct intel_crtc *intel_first_crtc(struct intel_display *display); struct intel_crtc *intel_crtc_for_pipe(struct intel_display *display, enum pipe pipe); -void intel_wait_for_vblank_if_active(struct drm_i915_private *i915, +void intel_wait_for_vblank_if_active(struct intel_display *display, enum pipe pipe); void intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc); diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 1faef60be472..599ddce96371 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -10,6 +10,7 @@ #include "intel_crtc_state_dump.h" #include "intel_display_types.h" #include "intel_hdmi.h" +#include "intel_vblank.h" #include "intel_vdsc.h" #include "intel_vrr.h" @@ -175,6 +176,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, struct intel_atomic_state *state, const char *context) { + struct intel_display *display = to_intel_display(pipe_config); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); const struct intel_plane_state *plane_state; @@ -248,11 +250,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, str_enabled_disabled(pipe_config->has_sel_update), str_enabled_disabled(pipe_config->has_panel_replay), str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); + drm_printf(&p, "minimum HBlank: %d\n", pipe_config->min_hblank); } - drm_printf(&p, "framestart delay: %d, MSA timing delay: %d\n", - pipe_config->framestart_delay, pipe_config->msa_timing_delay); - drm_printf(&p, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", pipe_config->has_audio, pipe_config->has_infoframe, pipe_config->infoframes.enable); @@ -286,13 +286,23 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, drm_print_hex_dump(&p, "ELD: ", pipe_config->eld, drm_eld_size(pipe_config->eld)); - drm_printf(&p, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", + drm_printf(&p, "scanline offset: %d\n", + intel_crtc_scanline_offset(pipe_config)); + + drm_printf(&p, "vblank delay: %d, framestart delay: %d, MSA timing delay: %d\n", + pipe_config->hw.adjusted_mode.crtc_vblank_start - + pipe_config->hw.adjusted_mode.crtc_vdisplay, + pipe_config->framestart_delay, pipe_config->msa_timing_delay); + + drm_printf(&p, "vrr: %s, vmin: %d, vmax: %d, flipline: %d, pipeline full: %d, guardband: %d vsync start: %d, vsync end: %d\n", str_yes_no(pipe_config->vrr.enable), - pipe_config->vrr.vmin, pipe_config->vrr.vmax, + pipe_config->vrr.vmin, pipe_config->vrr.vmax, pipe_config->vrr.flipline, pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband, - pipe_config->vrr.flipline, - intel_vrr_vmin_vblank_start(pipe_config), - intel_vrr_vmax_vblank_start(pipe_config)); + pipe_config->vrr.vsync_start, pipe_config->vrr.vsync_end); + + drm_printf(&p, "vrr: vmin vblank: %d, vmax vblank: %d, vmin vtotal: %d, vmax vtotal: %d\n", + intel_vrr_vmin_vblank_start(pipe_config), intel_vrr_vmax_vblank_start(pipe_config), + intel_vrr_vmin_vtotal(pipe_config), intel_vrr_vmax_vtotal(pipe_config)); drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n", DRM_MODE_ARG(&pipe_config->hw.mode)); @@ -331,7 +341,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, pipe_config->ips_enabled, pipe_config->double_wide, pipe_config->has_drrs); - intel_dpll_dump_hw_state(i915, &p, &pipe_config->dpll_hw_state); + intel_dpll_dump_hw_state(display, &p, &pipe_config->dpll_hw_state); if (IS_CHERRYVIEW(i915)) drm_printf(&p, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 57cf8f46a458..3276a5b4a9b0 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -35,11 +35,10 @@ static const u32 intel_cursor_formats[] = { static u32 intel_cursor_base(const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); u32 base; - if (DISPLAY_INFO(dev_priv)->cursor_needs_physical) + if (DISPLAY_INFO(display)->cursor_needs_physical) base = plane_state->phys_dma_addr; else base = intel_plane_ggtt_offset(plane_state); @@ -92,8 +91,8 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) static int intel_cursor_check_surface(struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); unsigned int rotation = plane_state->hw.rotation; int src_x, src_y; u32 offset; @@ -114,8 +113,9 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state) plane_state, 0); if (src_x != 0 || src_y != 0) { - drm_dbg_kms(&dev_priv->drm, - "Arbitrary cursor panning not supported\n"); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] arbitrary cursor panning not supported\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -127,7 +127,7 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state) src_x << 16, src_y << 16); /* ILK+ do this automagically in hardware */ - if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) { + if (HAS_GMCH(display) && rotation & DRM_MODE_ROTATE_180) { const struct drm_framebuffer *fb = plane_state->hw.fb; int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; @@ -145,14 +145,16 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state) static int intel_check_cursor(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct drm_framebuffer *fb = plane_state->hw.fb; - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); const struct drm_rect src = plane_state->uapi.src; const struct drm_rect dst = plane_state->uapi.dst; int ret; if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { - drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n"); + drm_dbg_kms(display->drm, "[PLANE:%d:%s] cursor cannot be tiled\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -233,8 +235,9 @@ static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) static int i845_check_cursor(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct drm_framebuffer *fb = plane_state->hw.fb; - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); int ret; ret = intel_check_cursor(crtc_state, plane_state); @@ -247,14 +250,15 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state, /* Check for which cursor types we support */ if (!i845_cursor_size_ok(plane_state)) { - drm_dbg_kms(&i915->drm, - "Cursor dimension %dx%d not supported\n", + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] cursor dimension %dx%d not supported\n", + plane->base.base.id, plane->base.name, drm_rect_width(&plane_state->uapi.dst), drm_rect_height(&plane_state->uapi.dst)); return -EINVAL; } - drm_WARN_ON(&i915->drm, plane_state->uapi.visible && + drm_WARN_ON(display->drm, plane_state->uapi.visible && plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); switch (fb->pitches[0]) { @@ -264,7 +268,8 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state, case 2048: break; default: - drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n", + drm_dbg_kms(display->drm, "[PLANE:%d:%s] invalid cursor stride (%u)\n", + plane->base.base.id, plane->base.name, fb->pitches[0]); return -EINVAL; } @@ -280,7 +285,7 @@ static void i845_cursor_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); u32 cntl = 0, base = 0, pos = 0, size = 0; if (plane_state && plane_state->uapi.visible) { @@ -302,17 +307,17 @@ static void i845_cursor_update_arm(struct intel_dsb *dsb, if (plane->cursor.base != base || plane->cursor.size != size || plane->cursor.cntl != cntl) { - intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0); - intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base); - intel_de_write_fw(dev_priv, CURSIZE(dev_priv, PIPE_A), size); - intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos); - intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl); + intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0); + intel_de_write_fw(display, CURBASE(display, PIPE_A), base); + intel_de_write_fw(display, CURSIZE(display, PIPE_A), size); + intel_de_write_fw(display, CURPOS(display, PIPE_A), pos); + intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl); plane->cursor.base = base; plane->cursor.size = size; plane->cursor.cntl = cntl; } else { - intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos); + intel_de_write_fw(display, CURPOS(display, PIPE_A), pos); } } @@ -326,21 +331,21 @@ static void i845_cursor_disable_arm(struct intel_dsb *dsb, static bool i845_cursor_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; bool ret; power_domain = POWER_DOMAIN_PIPE(PIPE_A); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; - ret = intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & CURSOR_ENABLE; + ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE; *pipe = PIPE_A; - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } @@ -372,16 +377,21 @@ static unsigned int i9xx_cursor_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { + struct intel_display *display = to_intel_display(plane); + + if (intel_scanout_needs_vtd_wa(display)) + return 64 * 1024; + return 4 * 1024; /* physical for i915/i945 */ } static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 cntl = 0; - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) return cntl; if (crtc_state->gamma_enable) @@ -390,7 +400,7 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) if (crtc_state->csc_enable) cntl |= MCURSOR_PIPE_CSC_ENABLE; - if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) + if (DISPLAY_VER(display) < 5 && !display->platform.g4x) cntl |= MCURSOR_PIPE_SEL(crtc->pipe); return cntl; @@ -399,11 +409,10 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); u32 cntl = 0; - if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) + if (display->platform.sandybridge || display->platform.ivybridge) cntl |= MCURSOR_TRICKLE_FEED_DISABLE; switch (drm_rect_width(&plane_state->uapi.dst)) { @@ -425,7 +434,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, cntl |= MCURSOR_ROTATE_180; /* Wa_22012358565:adl-p */ - if (DISPLAY_VER(dev_priv) == 13) + if (DISPLAY_VER(display) == 13) cntl |= MCURSOR_ARB_SLOTS(1); return cntl; @@ -433,8 +442,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); int width = drm_rect_width(&plane_state->uapi.dst); int height = drm_rect_height(&plane_state->uapi.dst); @@ -457,7 +465,7 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) * cursor is not rotated. Everything else requires square * cursors. */ - if (HAS_CUR_FBC(dev_priv) && + if (HAS_CUR_FBC(display) && plane_state->hw.rotation & DRM_MODE_ROTATE_0) { if (height < 8 || height > width) return false; @@ -472,8 +480,8 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum pipe pipe = plane->pipe; int ret; @@ -488,22 +496,23 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, /* Check for which cursor types we support */ if (!i9xx_cursor_size_ok(plane_state)) { - drm_dbg(&dev_priv->drm, - "Cursor dimension %dx%d not supported\n", - drm_rect_width(&plane_state->uapi.dst), - drm_rect_height(&plane_state->uapi.dst)); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] cursor dimension %dx%d not supported\n", + plane->base.base.id, plane->base.name, + drm_rect_width(&plane_state->uapi.dst), + drm_rect_height(&plane_state->uapi.dst)); return -EINVAL; } - drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && + drm_WARN_ON(display->drm, plane_state->uapi.visible && plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]); if (fb->pitches[0] != drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { - drm_dbg_kms(&dev_priv->drm, - "Invalid cursor stride (%u) (cursor width %d)\n", - fb->pitches[0], - drm_rect_width(&plane_state->uapi.dst)); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] invalid cursor stride (%u) (cursor width %d)\n", + plane->base.base.id, plane->base.name, + fb->pitches[0], drm_rect_width(&plane_state->uapi.dst)); return -EINVAL; } @@ -517,10 +526,11 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, * display power well must be turned off and on again. * Refuse the put the cursor into that compromised position. */ - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && + if (display->platform.cherryview && pipe == PIPE_C && plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { - drm_dbg_kms(&dev_priv->drm, - "CHV cursor C not allowed to straddle the left screen edge\n"); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] cursor not allowed to straddle the left screen edge\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -533,7 +543,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; if (!crtc_state->enable_psr2_sel_fetch) @@ -547,8 +557,7 @@ static void wa_16021440873(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); u32 ctl = plane_state->ctl; int et_y_position = drm_rect_height(&crtc_state->pipe_src) + 1; enum pipe pipe = plane->pipe; @@ -558,7 +567,7 @@ static void wa_16021440873(struct intel_dsb *dsb, intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), ctl); - intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(dev_priv, pipe), + intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), CURSOR_POS_Y(et_y_position)); } @@ -567,8 +576,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; if (!crtc_state->enable_psr2_sel_fetch) @@ -579,7 +587,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_dsb *dsb, u32 val = intel_cursor_position(crtc_state, plane_state, true); - intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(dev_priv, pipe), val); + intel_de_write_dsb(display, dsb, CURPOS_ERLY_TPT(display, pipe), val); } intel_de_write_dsb(display, dsb, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl); @@ -653,8 +661,7 @@ static void i9xx_cursor_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; @@ -680,7 +687,7 @@ static void i9xx_cursor_update_arm(struct intel_dsb *dsb, * CURPOS. * * On other platforms CURPOS always requires the - * CURBASE write to arm the update. Additonally + * CURBASE write to arm the update. Additionally * a write to any of the cursor register will cancel * an already armed cursor update. Thus leaving out * the CURBASE write after CURPOS could lead to a @@ -692,7 +699,7 @@ static void i9xx_cursor_update_arm(struct intel_dsb *dsb, * the CURCNTR write arms the update. */ - if (DISPLAY_VER(dev_priv) >= 9) + if (DISPLAY_VER(display) >= 9) skl_write_cursor_wm(dsb, plane, crtc_state); if (plane_state) @@ -703,18 +710,18 @@ static void i9xx_cursor_update_arm(struct intel_dsb *dsb, if (plane->cursor.base != base || plane->cursor.size != fbc_ctl || plane->cursor.cntl != cntl) { - if (HAS_CUR_FBC(dev_priv)) - intel_de_write_dsb(display, dsb, CUR_FBC_CTL(dev_priv, pipe), fbc_ctl); - intel_de_write_dsb(display, dsb, CURCNTR(dev_priv, pipe), cntl); - intel_de_write_dsb(display, dsb, CURPOS(dev_priv, pipe), pos); - intel_de_write_dsb(display, dsb, CURBASE(dev_priv, pipe), base); + if (HAS_CUR_FBC(display)) + intel_de_write_dsb(display, dsb, CUR_FBC_CTL(display, pipe), fbc_ctl); + intel_de_write_dsb(display, dsb, CURCNTR(display, pipe), cntl); + intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos); + intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base); plane->cursor.base = base; plane->cursor.size = fbc_ctl; plane->cursor.cntl = cntl; } else { - intel_de_write_dsb(display, dsb, CURPOS(dev_priv, pipe), pos); - intel_de_write_dsb(display, dsb, CURBASE(dev_priv, pipe), base); + intel_de_write_dsb(display, dsb, CURPOS(display, pipe), pos); + intel_de_write_dsb(display, dsb, CURBASE(display, pipe), base); } } @@ -728,7 +735,7 @@ static void i9xx_cursor_disable_arm(struct intel_dsb *dsb, static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; bool ret; @@ -740,24 +747,45 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, * display power wells. */ power_domain = POWER_DOMAIN_PIPE(plane->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; - val = intel_de_read(dev_priv, CURCNTR(dev_priv, plane->pipe)); + val = intel_de_read(display, CURCNTR(display, plane->pipe)); ret = val & MCURSOR_MODE_MASK; - if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) *pipe = plane->pipe; else *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val); - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } +static void g4x_cursor_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + + error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe)); + error->surf = intel_de_read(display, CURBASE(display, crtc->pipe)); + error->surflive = intel_de_read(display, CURSURFLIVE(display, crtc->pipe)); +} + +static void i9xx_cursor_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + + error->ctl = intel_de_read(display, CURCNTR(display, crtc->pipe)); + error->surf = intel_de_read(display, CURBASE(display, crtc->pipe)); +} + static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, u32 format, u64 modifier) { @@ -790,7 +818,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane, { struct intel_plane *plane = to_intel_plane(_plane); struct intel_crtc *crtc = to_intel_crtc(_crtc); - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); struct intel_plane_state *old_plane_state = to_intel_plane_state(plane->base.state); struct intel_plane_state *new_plane_state; @@ -865,7 +893,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane, if (ret) goto out_free; - ret = intel_plane_pin_fb(new_plane_state); + ret = intel_plane_pin_fb(new_plane_state, old_plane_state); if (ret) goto out_free; @@ -894,7 +922,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane, intel_psr_lock(crtc_state); - if (!drm_WARN_ON(&i915->drm, drm_crtc_vblank_get(&crtc->base))) { + if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) { /* * TODO: maybe check if we're still in PSR * and skip the vblank evasion entirely? @@ -960,8 +988,8 @@ static const struct drm_plane_funcs intel_cursor_plane_funcs = { static void intel_cursor_add_size_hints_property(struct intel_plane *plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); - const struct drm_mode_config *config = &i915->drm.mode_config; + struct intel_display *display = to_intel_display(plane); + const struct drm_mode_config *config = &display->drm->mode_config; struct drm_plane_size_hint hints[4]; int size, max_size, num_hints = 0; @@ -969,7 +997,7 @@ static void intel_cursor_add_size_hints_property(struct intel_plane *plane) /* for simplicity only enumerate the supported square+POT sizes */ for (size = 64; size <= max_size; size *= 2) { - if (drm_WARN_ON(&i915->drm, num_hints >= ARRAY_SIZE(hints))) + if (drm_WARN_ON(display->drm, num_hints >= ARRAY_SIZE(hints))) break; hints[num_hints].width = size; @@ -981,7 +1009,7 @@ static void intel_cursor_add_size_hints_property(struct intel_plane *plane) } struct intel_plane * -intel_cursor_plane_create(struct drm_i915_private *dev_priv, +intel_cursor_plane_create(struct intel_display *display, enum pipe pipe) { struct intel_plane *cursor; @@ -997,7 +1025,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, cursor->id = PLANE_CURSOR; cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id); - if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { + if (display->platform.i845g || display->platform.i865g) { cursor->max_stride = i845_cursor_max_stride; cursor->min_alignment = i845_cursor_min_alignment; cursor->update_arm = i845_cursor_update_arm; @@ -1007,28 +1035,36 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, } else { cursor->max_stride = i9xx_cursor_max_stride; - if (IS_I830(dev_priv)) + if (display->platform.i830) cursor->min_alignment = i830_cursor_min_alignment; - else if (IS_I85X(dev_priv)) + else if (display->platform.i85x) cursor->min_alignment = i85x_cursor_min_alignment; else cursor->min_alignment = i9xx_cursor_min_alignment; + if (intel_scanout_needs_vtd_wa(display)) + cursor->vtd_guard = 2; + cursor->update_arm = i9xx_cursor_update_arm; cursor->disable_arm = i9xx_cursor_disable_arm; cursor->get_hw_state = i9xx_cursor_get_hw_state; cursor->check_plane = i9xx_check_cursor; } + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) + cursor->capture_error = g4x_cursor_capture_error; + else + cursor->capture_error = i9xx_cursor_capture_error; + cursor->cursor.base = ~0; cursor->cursor.cntl = ~0; - if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) + if (display->platform.i845g || display->platform.i865g || HAS_CUR_FBC(display)) cursor->cursor.size = ~0; - modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE); + modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_NONE); - ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, + ret = drm_universal_plane_init(display->drm, &cursor->base, 0, &intel_cursor_plane_funcs, intel_cursor_formats, ARRAY_SIZE(intel_cursor_formats), @@ -1041,7 +1077,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, if (ret) goto fail; - if (DISPLAY_VER(dev_priv) >= 4) + if (DISPLAY_VER(display) >= 4) drm_plane_create_rotation_property(&cursor->base, DRM_MODE_ROTATE_0, DRM_MODE_ROTATE_0 | @@ -1049,10 +1085,10 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, intel_cursor_add_size_hints_property(cursor); - zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1; + zpos = DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + 1; drm_plane_create_zpos_immutable_property(&cursor->base, zpos); - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) drm_plane_enable_fb_damage_clips(&cursor->base); intel_plane_helper_add(cursor); diff --git a/drivers/gpu/drm/i915/display/intel_cursor.h b/drivers/gpu/drm/i915/display/intel_cursor.h index e2d9ec710a86..65a9e7eb88c2 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.h +++ b/drivers/gpu/drm/i915/display/intel_cursor.h @@ -7,12 +7,12 @@ #define _INTEL_CURSOR_H_ enum pipe; -struct drm_i915_private; +struct intel_display; struct intel_plane; struct kthread_work; struct intel_plane * -intel_cursor_plane_create(struct drm_i915_private *dev_priv, +intel_cursor_plane_create(struct intel_display *display, enum pipe pipe); void intel_cursor_unpin_work(struct kthread_work *base); diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index e768dc6a15b3..22595766eac5 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -18,6 +18,7 @@ #include "intel_hdmi.h" #include "intel_panel.h" #include "intel_psr.h" +#include "intel_snps_hdmi_pll.h" #include "intel_tc.h" #define MB_WRITE_COMMITTED true @@ -33,13 +34,13 @@ bool intel_encoder_is_c10phy(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - if (IS_PANTHERLAKE(i915) && phy == PHY_A) + if (display->platform.pantherlake && phy == PHY_A) return true; - if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C) + if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C) return true; return false; @@ -72,10 +73,9 @@ static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder) static void assert_dc_off(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); bool enabled; - enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF); + enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF); drm_WARN_ON(display->drm, !enabled); } @@ -102,12 +102,12 @@ static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder) */ static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder) { - intel_wakeref_t wakeref; - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + intel_wakeref_t wakeref; intel_psr_pause(intel_dp); - wakeref = intel_display_power_get(i915, POWER_DOMAIN_DC_OFF); + wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); intel_cx0_program_msgbus_timer(encoder); return wakeref; @@ -115,11 +115,11 @@ static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *enc static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); intel_psr_resume(intel_dp); - intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref); } static void intel_clear_response_ready_flag(struct intel_encoder *encoder, @@ -2003,19 +2003,6 @@ static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = { NULL, }; -static int intel_c10_phy_check_hdmi_link_rate(int clock) -{ - const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables; - int i; - - for (i = 0; tables[i]; i++) { - if (clock == tables[i]->clock) - return MODE_OK; - } - - return MODE_CLOCK_RANGE; -} - static const struct intel_c10pll_state * const * intel_c10pll_tables_get(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) @@ -2033,21 +2020,25 @@ intel_c10pll_tables_get(struct intel_crtc_state *crtc_state, return NULL; } -static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state, - struct intel_encoder *encoder) +static void intel_cx0pll_update_ssc(struct intel_encoder *encoder, + struct intel_cx0pll_state *pll_state, bool is_dp) { struct intel_display *display = to_intel_display(encoder); - struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll; - int i; - if (intel_crtc_has_dp_encoder(crtc_state)) { + if (is_dp) { if (intel_panel_use_ssc(display)) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - pll_state->ssc_enabled = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5); } } +} + +static void intel_c10pll_update_pll(struct intel_encoder *encoder, + struct intel_cx0pll_state *pll_state) +{ + struct intel_display *display = to_intel_display(encoder); + int i; if (pll_state->ssc_enabled) return; @@ -2057,27 +2048,53 @@ static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state, pll_state->c10.pll[i] = 0; } +static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder, + const struct intel_c10pll_state * const *tables, + bool is_dp, int port_clock, + struct intel_cx0pll_state *pll_state) +{ + int i; + + for (i = 0; tables[i]; i++) { + if (port_clock == tables[i]->clock) { + pll_state->c10 = *tables[i]; + intel_cx0pll_update_ssc(encoder, pll_state, is_dp); + intel_c10pll_update_pll(encoder, pll_state); + pll_state->use_c10 = true; + + return 0; + } + } + + return -EINVAL; +} + static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { const struct intel_c10pll_state * const *tables; - int i; + int err; tables = intel_c10pll_tables_get(crtc_state, encoder); if (!tables) return -EINVAL; - for (i = 0; tables[i]; i++) { - if (crtc_state->port_clock == tables[i]->clock) { - crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i]; - intel_c10pll_update_pll(crtc_state, encoder); - crtc_state->dpll_hw_state.cx0pll.use_c10 = true; + err = intel_c10pll_calc_state_from_table(encoder, tables, + intel_crtc_has_dp_encoder(crtc_state), + crtc_state->port_clock, + &crtc_state->dpll_hw_state.cx0pll); - return 0; - } - } + if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return err; - return -EINVAL; + /* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed tables */ + intel_snps_hdmi_pll_compute_c10pll(&crtc_state->dpll_hw_state.cx0pll.c10, + crtc_state->port_clock); + intel_c10pll_update_pll(encoder, + &crtc_state->dpll_hw_state.cx0pll); + crtc_state->dpll_hw_state.cx0pll.use_c10 = true; + + return 0; } static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, @@ -2107,10 +2124,9 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, } static void intel_c10_pll_program(struct intel_display *display, - const struct intel_crtc_state *crtc_state, - struct intel_encoder *encoder) + struct intel_encoder *encoder, + const struct intel_c10pll_state *pll_state) { - const struct intel_c10pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c10; int i; intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), @@ -2173,9 +2189,47 @@ static void intel_c10pll_dump_hw_state(struct intel_display *display, i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); } -static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state) +/* + * Some ARLs SoCs have the same drm PCI IDs, so need a helper to differentiate based + * on the host bridge device ID to get the correct txx_mics value. + */ +static bool is_arrowlake_s_by_host_bridge(void) +{ + struct pci_dev *pdev = NULL; + u16 host_bridge_pci_dev_id; + + while ((pdev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, pdev))) + host_bridge_pci_dev_id = pdev->device; + + return pdev && IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(host_bridge_pci_dev_id); +} + +static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); + u16 tx_misc; + u16 tx_dcc_cal_dac_ctrl_range = 8; + u16 tx_term_ctrl = 2; + + if (DISPLAY_VER(display) >= 20) { + tx_misc = 5; + tx_term_ctrl = 4; + } else if (display->platform.battlemage) { + tx_misc = 0; + } else if (display->platform.meteorlake_u || + is_arrowlake_s_by_host_bridge()) { + tx_misc = 3; + } else { + tx_misc = 7; + } + + return (C20_PHY_TX_MISC(tx_misc) | + C20_PHY_TX_DCC_CAL_RANGE(tx_dcc_cal_dac_ctrl_range) | + C20_PHY_TX_DCC_BYPASS | C20_PHY_TX_TERM_CTL(tx_term_ctrl)); +} + +static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state) +{ struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; u64 datarate; u64 mpll_tx_clk_div; @@ -2185,7 +2239,6 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state) u64 mpll_multiplier; u64 mpll_fracn_quot; u64 mpll_fracn_rem; - u16 tx_misc; u8 mpllb_ana_freq_vco; u8 mpll_div_multiplier; @@ -2205,11 +2258,6 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state) mpll_div_multiplier = min_t(u8, div64_u64((vco_freq * 16 + (datarate >> 1)), datarate), 255); - if (DISPLAY_VER(display) >= 20) - tx_misc = 0x5; - else - tx_misc = 0x0; - if (vco_freq <= DATARATE_3000000000) mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_3; else if (vco_freq <= DATARATE_3500000000) @@ -2221,7 +2269,7 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state) pll_state->clock = crtc_state->port_clock; pll_state->tx[0] = 0xbe88; - pll_state->tx[1] = 0x9800 | C20_PHY_TX_MISC(tx_misc); + pll_state->tx[1] = intel_c20_hdmi_tmds_tx_cgf_1(crtc_state); pll_state->tx[2] = 0x0000; pll_state->cmn[0] = 0x0500; pll_state->cmn[1] = 0x0005; @@ -2249,31 +2297,6 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state) return 0; } -static int intel_c20_phy_check_hdmi_link_rate(int clock) -{ - const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables; - int i; - - for (i = 0; tables[i]; i++) { - if (clock == tables[i]->clock) - return MODE_OK; - } - - if (clock >= 25175 && clock <= 594000) - return MODE_OK; - - return MODE_CLOCK_RANGE; -} - -int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock) -{ - struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi); - - if (intel_encoder_is_c10phy(&dig_port->base)) - return intel_c10_phy_check_hdmi_link_rate(clock); - return intel_c20_phy_check_hdmi_link_rate(clock); -} - static const struct intel_c20pll_state * const * intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) @@ -2322,6 +2345,9 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state, for (i = 0; tables[i]; i++) { if (crtc_state->port_clock == tables[i]->clock) { crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i]; + intel_cx0pll_update_ssc(encoder, + &crtc_state->dpll_hw_state.cx0pll, + intel_crtc_has_dp_encoder(crtc_state)); crtc_state->dpll_hw_state.cx0pll.use_c10 = false; return 0; } @@ -2587,19 +2613,14 @@ static int intel_get_c20_custom_width(u32 clock, bool dp) } static void intel_c20_pll_program(struct intel_display *display, - const struct intel_crtc_state *crtc_state, - struct intel_encoder *encoder) + struct intel_encoder *encoder, + const struct intel_c20pll_state *pll_state, + bool is_dp, int port_clock) { - const struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; - bool dp = false; u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); - u32 clock = crtc_state->port_clock; bool cntx; int i; - if (intel_crtc_has_dp_encoder(crtc_state)) - dp = true; - /* 1. Read current context selection */ cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0); @@ -2667,23 +2688,23 @@ static void intel_c20_pll_program(struct intel_display *display, /* 4. Program custom width to match the link protocol */ intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH, PHY_C20_CUSTOM_WIDTH_MASK, - PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock, dp)), + PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(port_clock, is_dp)), MB_WRITE_COMMITTED); /* 5. For DP or 6. For HDMI */ - if (dp) { + if (is_dp) { intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(6) | PHY_C20_CUSTOM_SERDES_MASK, - BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)), + BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(port_clock)), MB_WRITE_COMMITTED); } else { intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(7) | PHY_C20_CUSTOM_SERDES_MASK, - is_hdmi_frl(clock) ? BIT(7) : 0, + is_hdmi_frl(port_clock) ? BIT(7) : 0, MB_WRITE_COMMITTED); intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE, - intel_c20_get_hdmi_rate(clock), + intel_c20_get_hdmi_rate(port_clock), MB_WRITE_COMMITTED); } @@ -2723,7 +2744,8 @@ static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, } static void intel_program_port_clock_ctl(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, + const struct intel_cx0pll_state *pll_state, + bool is_dp, int port_clock, bool lane_reversal) { struct intel_display *display = to_intel_display(encoder); @@ -2738,18 +2760,17 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder, val |= XELPDP_FORWARD_CLOCK_UNGATE; - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && - is_hdmi_frl(crtc_state->port_clock)) + if (!is_dp && is_hdmi_frl(port_clock)) val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK); else val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK); /* TODO: HDMI FRL */ /* DP2.0 10G and 20G rates enable MPLLA*/ - if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) - val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; + if (port_clock == 1000000 || port_clock == 2000000) + val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; else - val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; + val |= pll_state->ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE | @@ -2979,8 +3000,9 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask) return val; } -static void intel_cx0pll_enable(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static void __intel_cx0pll_enable(struct intel_encoder *encoder, + const struct intel_cx0pll_state *pll_state, + bool is_dp, int port_clock, int lane_count) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); @@ -2994,7 +3016,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder, * 1. Program PORT_CLOCK_CTL REGISTER to configure * clock muxes, gating and SSC */ - intel_program_port_clock_ctl(encoder, crtc_state, lane_reversal); + intel_program_port_clock_ctl(encoder, pll_state, is_dp, port_clock, lane_reversal); /* 2. Bring PHY out of reset. */ intel_cx0_phy_lane_reset(encoder, lane_reversal); @@ -3014,15 +3036,15 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder, /* 5. Program PHY internal PLL internal registers. */ if (intel_encoder_is_c10phy(encoder)) - intel_c10_pll_program(display, crtc_state, encoder); + intel_c10_pll_program(display, encoder, &pll_state->c10); else - intel_c20_pll_program(display, crtc_state, encoder); + intel_c20_pll_program(display, encoder, &pll_state->c20, is_dp, port_clock); /* * 6. Program the enabled and disabled owned PHY lane * transmitters over message bus */ - intel_cx0_program_phy_lane(encoder, crtc_state->lane_count, lane_reversal); + intel_cx0_program_phy_lane(encoder, lane_count, lane_reversal); /* * 7. Follow the Display Voltage Frequency Switching - Sequence @@ -3033,8 +3055,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder, * 8. Program DDI_CLK_VALFREQ to match intended DDI * clock frequency. */ - intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), - crtc_state->port_clock); + intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), port_clock); /* * 9. Set PORT_CLOCK_CTL register PCLK PLL Request @@ -3061,6 +3082,14 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder, intel_cx0_phy_transaction_end(encoder, wakeref); } +static void intel_cx0pll_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + __intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll, + intel_crtc_has_dp_encoder(crtc_state), + crtc_state->port_clock, crtc_state->lane_count); +} + int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); @@ -3203,12 +3232,11 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder, static u8 cx0_power_control_disable_val(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *i915 = to_i915(encoder->base.dev); if (intel_encoder_is_c10phy(encoder)) return CX0_P2PG_STATE_DISABLE; - if ((IS_BATTLEMAGE(i915) && encoder->port == PORT_A) || + if ((display->platform.battlemage && encoder->port == PORT_A) || (DISPLAY_VER(display) >= 30 && encoder->type == INTEL_OUTPUT_EDP)) return CX0_P2PG_STATE_DISABLE; @@ -3266,6 +3294,16 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder) intel_cx0_phy_transaction_end(encoder, wakeref); } +static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder) +{ + struct intel_display *display = to_intel_display(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + u8 lane = dig_port->lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0; + + return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) & + intel_cx0_get_pclk_pll_request(lane); +} + static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); @@ -3527,3 +3565,54 @@ void intel_cx0pll_state_verify(struct intel_atomic_state *state, else intel_c20pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c20); } + +/* + * WA 14022081154 + * The dedicated display PHYs reset to a power state that blocks S0ix, increasing idle + * system power. After a system reset (cold boot, S3/4/5, warm reset) if a dedicated + * PHY is not being brought up shortly, use these steps to move the PHY to the lowest + * power state to save power. For PTL the workaround is needed only for port A. Port B + * is not connected. + * + * 1. Follow the PLL Enable Sequence, using any valid frequency such as DP 1.62 GHz. + * This brings lanes out of reset and enables the PLL to allow powerdown to be moved + * to the Disable state. + * 2. Follow PLL Disable Sequence. This moves powerdown to the Disable state and disables the PLL. + */ +void intel_cx0_pll_power_save_wa(struct intel_display *display) +{ + struct intel_encoder *encoder; + + if (DISPLAY_VER(display) != 30) + return; + + for_each_intel_encoder(display->drm, encoder) { + struct intel_cx0pll_state pll_state = {}; + int port_clock = 162000; + + if (!intel_encoder_is_dig_port(encoder)) + continue; + + if (!intel_encoder_is_c10phy(encoder)) + continue; + + if (intel_cx0_pll_is_enabled(encoder)) + continue; + + if (intel_c10pll_calc_state_from_table(encoder, + mtl_c10_edp_tables, + true, port_clock, + &pll_state) < 0) { + drm_WARN_ON(display->drm, + "Unable to calc C10 state from the tables\n"); + continue; + } + + drm_dbg_kms(display->drm, + "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n", + encoder->base.base.id, encoder->base.name); + + __intel_cx0pll_enable(encoder, &pll_state, true, port_clock, 4); + intel_cx0pll_disable(encoder); + } +} diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h index 711168882684..a8f811ca5e7b 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h @@ -41,7 +41,7 @@ bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a, const struct intel_cx0pll_state *b); void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); -int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock); int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder); +void intel_cx0_pll_power_save_wa(struct intel_display *display); #endif /* __INTEL_CX0_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index da154ff26b96..960f7f778fb8 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -110,7 +110,8 @@ #define XELPDP_TCSS_POWER_REQUEST REG_BIT(5) #define XELPDP_TCSS_POWER_STATE REG_BIT(4) #define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1) -#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val) +#define XELPDP_PORT_WIDTH(width) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, \ + ((width) == 3 ? 4 : (width) - 1)) #define _XELPDP_PORT_BUF_CTL2(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ _XELPDP_PORT_BUF_CTL1_LN0_A, \ @@ -218,10 +219,34 @@ /* C10 Vendor Registers */ #define PHY_C10_VDR_PLL(idx) (0xC00 + (idx)) +#define C10_PLL0_SSC_EN REG_BIT8(0) +#define C10_PLL0_DIVCLK_EN REG_BIT8(1) +#define C10_PLL0_DIV5CLK_EN REG_BIT8(2) +#define C10_PLL0_WORDDIV2_EN REG_BIT8(3) #define C10_PLL0_FRACEN REG_BIT8(4) +#define C10_PLL0_PMIX_EN REG_BIT8(5) +#define C10_PLL0_ANA_FREQ_VCO_MASK REG_GENMASK8(7, 6) +#define C10_PLL1_DIV_MULTIPLIER_MASK REG_GENMASK8(7, 0) +#define C10_PLL2_MULTIPLIERL_MASK REG_GENMASK8(7, 0) #define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0) +#define C10_PLL8_SSC_UP_SPREAD REG_BIT8(5) +#define C10_PLL9_FRACN_DENL_MASK REG_GENMASK8(7, 0) +#define C10_PLL10_FRACN_DENH_MASK REG_GENMASK8(7, 0) +#define C10_PLL11_FRACN_QUOT_L_MASK REG_GENMASK8(7, 0) +#define C10_PLL12_FRACN_QUOT_H_MASK REG_GENMASK8(7, 0) +#define C10_PLL13_FRACN_REM_L_MASK REG_GENMASK8(7, 0) +#define C10_PLL14_FRACN_REM_H_MASK REG_GENMASK8(7, 0) #define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0) #define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3) +#define C10_PLL15_PIXELCLKDIV_MASK REG_GENMASK8(7, 6) +#define C10_PLL16_ANA_CPINT REG_GENMASK8(6, 0) +#define C10_PLL16_ANA_CPINTGS_L REG_BIT8(7) +#define C10_PLL17_ANA_CPINTGS_H_MASK REG_GENMASK8(5, 0) +#define C10_PLL17_ANA_CPPROP_L_MASK REG_GENMASK8(7, 6) +#define C10_PLL18_ANA_CPPROP_H_MASK REG_GENMASK8(4, 0) +#define C10_PLL18_ANA_CPPROPGS_L_MASK REG_GENMASK8(7, 5) +#define C10_PLL19_ANA_CPPROPGS_H_MASK REG_GENMASK8(3, 0) +#define C10_PLL19_ANA_V2I_MASK REG_GENMASK8(5, 4) #define PHY_C10_VDR_CMN(idx) (0xC20 + (idx)) #define C10_CMN0_REF_RANGE REG_FIELD_PREP(REG_GENMASK(4, 0), 1) @@ -298,6 +323,12 @@ #define C20_PHY_TX_RATE REG_GENMASK(2, 0) #define C20_PHY_TX_MISC_MASK REG_GENMASK16(7, 0) #define C20_PHY_TX_MISC(val) REG_FIELD_PREP16(C20_PHY_TX_MISC_MASK, (val)) +#define C20_PHY_TX_DCC_CAL_RANGE_MASK REG_GENMASK16(11, 8) +#define C20_PHY_TX_DCC_CAL_RANGE(val) \ + REG_FIELD_PREP16(C20_PHY_TX_DCC_CAL_RANGE_MASK, (val)) +#define C20_PHY_TX_DCC_BYPASS REG_BIT(12) +#define C20_PHY_TX_TERM_CTL_MASK REG_GENMASK16(15, 13) +#define C20_PHY_TX_TERM_CTL(val) REG_FIELD_PREP16(C20_PHY_TX_TERM_CTL_MASK, (val)) #define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : _MTL_C20_A_CMN_CNTX_CFG) - (idx)) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index acb986bc1f33..f38c998935b9 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -70,6 +70,7 @@ #include "intel_lspcon.h" #include "intel_mg_phy_regs.h" #include "intel_modeset_lock.h" +#include "intel_pfit.h" #include "intel_pps.h" #include "intel_psr.h" #include "intel_quirks.h" @@ -177,69 +178,60 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, trans->entries[level].hsw.trans2); } -static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port) +static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) { - int ret; + struct drm_i915_private *i915 = to_i915(display->drm); - /* FIXME: find out why Bspec's 100us timeout is too short */ - ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) & - XELPDP_PORT_BUF_PHY_IDLE), 10000); - if (ret) - drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", - port_name(port)); + if (DISPLAY_VER(display) >= 14) + return XELPDP_PORT_BUF_CTL1(i915, port); + else + return DDI_BUF_CTL(port); } -void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, - enum port port) +void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port) { - if (IS_BROXTON(dev_priv)) { + /* + * Bspec's platform specific timeouts: + * MTL+ : 100 us + * BXT : fixed 16 us + * HSW-ADL: 8 us + * + * FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short + */ + if (display->platform.broxton) { udelay(16); return; } - if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & - DDI_BUF_IS_IDLE), 8)) - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", + static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); + if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port), + DDI_BUF_IS_IDLE, 10)) + drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n", port_name(port)); } static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - int timeout_us; - int ret; - /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ - if (DISPLAY_VER(dev_priv) < 10) { + /* + * Bspec's platform specific timeouts: + * MTL+ : 10000 us + * DG2 : 1200 us + * TGL-ADL combo PHY: 1000 us + * TGL-ADL TypeC PHY: 3000 us + * HSW-ICL : fixed 518 us + */ + if (DISPLAY_VER(display) < 10) { usleep_range(518, 1000); return; } - if (DISPLAY_VER(dev_priv) >= 14) { - timeout_us = 10000; - } else if (IS_DG2(dev_priv)) { - timeout_us = 1200; - } else if (DISPLAY_VER(dev_priv) >= 12) { - if (intel_encoder_is_tc(encoder)) - timeout_us = 3000; - else - timeout_us = 1000; - } else { - timeout_us = 500; - } - - if (DISPLAY_VER(dev_priv) >= 14) - ret = _wait_for(!(intel_de_read(dev_priv, - XELPDP_PORT_BUF_CTL1(dev_priv, port)) & - XELPDP_PORT_BUF_PHY_IDLE), - timeout_us, 10, 10); - else - ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), - timeout_us, 10, 10); - - if (ret) - drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", + static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE); + if (intel_de_wait_for_clear(display, intel_ddi_buf_status_reg(display, port), + DDI_BUF_IS_IDLE, 10)) + drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n", port_name(port)); } @@ -328,9 +320,32 @@ static u32 ddi_buf_phy_link_rate(int port_clock) } } +static int dp_phy_lane_stagger_delay(int port_clock) +{ + /* + * Return the number of symbol clocks delay used to stagger the + * assertion/desassertion of the port lane enables. The target delay + * time is 100 ns or greater, return the number of symbols specific to + * the provided port_clock (aka link clock) corresponding to this delay + * time, i.e. so that + * + * number_of_symbols * duration_of_one_symbol >= 100 ns + * + * The delay must be applied only on TypeC DP outputs, for everything else + * the delay must be set to 0. + * + * Return the number of link symbols per 100 ns: + * port_clock (10 kHz) -> bits / 100 us + * / symbol_size -> symbols / 100 us + * / 1000 -> symbols / 100 ns + */ + return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); +} + static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); @@ -356,12 +371,18 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, if (!intel_tc_port_in_tbt_alt_mode(dig_port)) intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; } + + if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) { + int delay = dp_phy_lane_stagger_delay(crtc_state->port_clock); + + intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay); + } } -static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, +static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port) { - u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; + u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; switch (val) { case DDI_CLK_SEL_NONE: @@ -658,7 +679,6 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); u32 ctl; if (DISPLAY_VER(dev_priv) >= 11) @@ -678,8 +698,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK); if (DISPLAY_VER(dev_priv) >= 12) { - if (!intel_dp_mst_is_master_trans(crtc_state) || - (!is_mst && intel_dp_is_uhbr(crtc_state))) { + if (!intel_dp_mst_is_master_trans(crtc_state)) { ctl &= ~(TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); } @@ -705,19 +724,20 @@ int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, enum transcoder cpu_transcoder, bool enable, u32 hdcp_mask) { + struct intel_display *display = to_intel_display(intel_encoder); struct drm_device *dev = intel_encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); intel_wakeref_t wakeref; int ret = 0; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, intel_encoder->power_domain); if (drm_WARN_ON(dev, !wakeref)) return -ENXIO; intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), hdcp_mask, enable ? hdcp_mask : 0); - intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); + intel_display_power_put(display, intel_encoder->power_domain, wakeref); return ret; } @@ -734,7 +754,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) u32 ddi_mode; bool ret; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; @@ -775,7 +795,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) } out: - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } @@ -794,7 +814,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, *pipe_mask = 0; *is_dp_mst = false; - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return; @@ -831,7 +851,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, u32 port_mask, ddi_select, ddi_mode; intel_wakeref_t trans_wakeref; - trans_wakeref = intel_display_power_get_if_enabled(dev_priv, + trans_wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder)); if (!trans_wakeref) continue; @@ -846,7 +866,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); - intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), + intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder), trans_wakeref); if ((tmp & port_mask) != ddi_select) @@ -868,7 +888,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, encoder->base.base.id, encoder->base.name); if (!mst_pipe_mask && dp128b132b_pipe_mask) { - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); /* * If we don't have 8b/10b MST, but have more than one @@ -880,7 +900,8 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, * we don't expect MST to have been enabled at that point, and * can assume it's SST. */ - if (hweight8(dp128b132b_pipe_mask) > 1 || intel_dp->is_mst) + if (hweight8(dp128b132b_pipe_mask) > 1 || + intel_dp_mst_encoder_active_links(dig_port)) mst_pipe_mask = dp128b132b_pipe_mask; } @@ -911,7 +932,7 @@ out: encoder->base.base.id, encoder->base.name, tmp); } - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); } bool intel_ddi_get_hw_state(struct intel_encoder *encoder, @@ -934,7 +955,7 @@ static enum intel_display_power_domain intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); /* * ICL+ HW requires corresponding AUX IOs to be powered up for PSR with @@ -950,8 +971,8 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port, * extra wells. */ if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) - return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); - else if (DISPLAY_VER(i915) < 14 && + return intel_display_power_aux_io_domain(display, dig_port->aux_ch); + else if (DISPLAY_VER(display) < 14 && (intel_crtc_has_dp_encoder(crtc_state) || intel_encoder_is_tc(&dig_port->base))) return intel_aux_power_domain(dig_port); @@ -963,23 +984,23 @@ static void main_link_aux_power_domain_get(struct intel_digital_port *dig_port, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); enum intel_display_power_domain domain = intel_ddi_main_link_aux_domain(dig_port, crtc_state); - drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); + drm_WARN_ON(display->drm, dig_port->aux_wakeref); if (domain == POWER_DOMAIN_INVALID) return; - dig_port->aux_wakeref = intel_display_power_get(i915, domain); + dig_port->aux_wakeref = intel_display_power_get(display, domain); } static void main_link_aux_power_domain_put(struct intel_digital_port *dig_port, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); enum intel_display_power_domain domain = intel_ddi_main_link_aux_domain(dig_port, crtc_state); intel_wakeref_t wf; @@ -988,13 +1009,13 @@ main_link_aux_power_domain_put(struct intel_digital_port *dig_port, if (!wf) return; - intel_display_power_put(i915, domain, wf); + intel_display_power_put(display, domain, wf); } static void intel_ddi_get_power_domains(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port; /* @@ -1002,15 +1023,15 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, * happen since fake-MST encoders don't set their get_power_domains() * hook. */ - if (drm_WARN_ON(&dev_priv->drm, + if (drm_WARN_ON(display->drm, intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) return; dig_port = enc_to_dig_port(encoder); if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { - drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); - dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, + drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref); + dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); } @@ -1172,7 +1193,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, /* Set PORT_TX_DW5 */ val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | - TAP2_DISABLE | TAP3_DISABLE); + COEFF_POLARITY | CURSOR_PROGRAM | + TAP2_DISABLE | TAP3_DISABLE); val |= SCALING_MODE_SEL(0x2); val |= RTERM_SELECT(0x6); val |= TAP3_DISABLE; @@ -1366,7 +1388,7 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum tc_port tc_port = intel_encoder_to_tc(encoder); const struct intel_ddi_buf_trans *trans; int n_entries, ln; @@ -1375,17 +1397,17 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, return; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return; for (ln = 0; ln < 2; ln++) { int level; - intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); + intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); level = intel_ddi_level(encoder, crtc_state, 2*ln+0); - intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln), + intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln), DKL_TX_PRESHOOT_COEFF_MASK | DKL_TX_DE_EMPAHSIS_COEFF_MASK | DKL_TX_VSWING_CONTROL_MASK, @@ -1395,7 +1417,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, level = intel_ddi_level(encoder, crtc_state, 2*ln+1); - intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln), + intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln), DKL_TX_PRESHOOT_COEFF_MASK | DKL_TX_DE_EMPAHSIS_COEFF_MASK | DKL_TX_VSWING_CONTROL_MASK, @@ -1403,10 +1425,10 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); - intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), + intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), DKL_TX_DP20BITMODE, 0); - if (IS_ALDERLAKE_P(dev_priv)) { + if (display->platform.alderlake_p) { u32 val; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { @@ -1422,7 +1444,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0); } - intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln), + intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln), DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK | DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK, val); @@ -1550,14 +1572,14 @@ static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t } static struct intel_shared_dpll * -_icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg, +_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, u32 clk_sel_mask, u32 clk_sel_shift) { enum intel_dpll_id id; - id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; + id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift; - return intel_get_shared_dpll_by_id(i915, id); + return intel_get_shared_dpll_by_id(display, id); } static void adls_ddi_enable_clock(struct intel_encoder *encoder, @@ -1596,10 +1618,10 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy), + return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy), ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy), ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)); } @@ -1640,10 +1662,10 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, + return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); } @@ -1693,12 +1715,12 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); enum intel_dpll_id id; u32 val; - val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)); + val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy)); val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); id = val; @@ -1711,7 +1733,7 @@ static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) if (phy >= PHY_C) id += DPLL_ID_DG1_DPLL2; - return intel_get_shared_dpll_by_id(i915, id); + return intel_get_shared_dpll_by_id(display, id); } static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, @@ -1750,10 +1772,10 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0, + return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0, ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy), ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)); } @@ -1858,13 +1880,13 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum tc_port tc_port = intel_encoder_to_tc(encoder); enum port port = encoder->port; enum intel_dpll_id id; u32 tmp; - tmp = intel_de_read(i915, DDI_CLK_SEL(port)); + tmp = intel_de_read(display, DDI_CLK_SEL(port)); switch (tmp & DDI_CLK_SEL_MASK) { case DDI_CLK_SEL_TBT_162: @@ -1883,12 +1905,12 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode return NULL; } - return intel_get_shared_dpll_by_id(i915, id); + return intel_get_shared_dpll_by_id(display, id); } static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder->base.dev); enum intel_dpll_id id; switch (encoder->port) { @@ -1906,7 +1928,7 @@ static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) return NULL; } - return intel_get_shared_dpll_by_id(i915, id); + return intel_get_shared_dpll_by_id(display, id); } static void skl_ddi_enable_clock(struct intel_encoder *encoder, @@ -1957,12 +1979,12 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; enum intel_dpll_id id; u32 tmp; - tmp = intel_de_read(i915, DPLL_CTRL2); + tmp = intel_de_read(display, DPLL_CTRL2); /* * FIXME Not sure if the override affects both @@ -1974,7 +1996,7 @@ static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); - return intel_get_shared_dpll_by_id(i915, id); + return intel_get_shared_dpll_by_id(display, id); } void hsw_ddi_enable_clock(struct intel_encoder *encoder, @@ -2008,12 +2030,12 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; enum intel_dpll_id id; u32 tmp; - tmp = intel_de_read(i915, PORT_CLK_SEL(port)); + tmp = intel_de_read(display, PORT_CLK_SEL(port)); switch (tmp & PORT_CLK_SEL_MASK) { case PORT_CLK_SEL_WRPLL1: @@ -2041,7 +2063,7 @@ static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) return NULL; } - return intel_get_shared_dpll_by_id(i915, id); + return intel_get_shared_dpll_by_id(display, id); } void intel_ddi_enable_clock(struct intel_encoder *encoder, @@ -2121,27 +2143,37 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) } static void +tgl_dkl_phy_check_and_rewrite(struct intel_display *display, + enum tc_port tc_port, u32 ln0, u32 ln1) +{ + if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0))) + intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); + if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1))) + intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); +} + +static void icl_program_mg_dp_mode(struct intel_digital_port *dig_port, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); u32 ln0, ln1, pin_assignment; u8 width; - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER(display) >= 14) return; if (!intel_encoder_is_tc(&dig_port->base) || intel_tc_port_in_tbt_alt_mode(dig_port)) return; - if (DISPLAY_VER(dev_priv) >= 12) { - ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)); - ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)); + if (DISPLAY_VER(display) >= 12) { + ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)); + ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)); } else { - ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); - ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); + ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port)); + ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port)); } ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE); @@ -2153,7 +2185,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, switch (pin_assignment) { case 0x0: - drm_WARN_ON(&dev_priv->drm, + drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port)); if (width == 1) { ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; @@ -2198,12 +2230,16 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, MISSING_CASE(pin_assignment); } - if (DISPLAY_VER(dev_priv) >= 12) { - intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0); - intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1); + if (DISPLAY_VER(display) >= 12) { + intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); + intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); + /* WA_14018221282 */ + if (IS_DISPLAY_VER(display, 12, 13)) + tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1); + } else { - intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); - intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); + intel_de_write(display, MG_DP_MODE(0, tc_port), ln0); + intel_de_write(display, MG_DP_MODE(1, tc_port), ln1); } } @@ -2422,13 +2458,13 @@ static void intel_ddi_disable_fec(struct intel_encoder *encoder, static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); if (intel_encoder_is_combo(encoder)) { enum phy phy = intel_encoder_to_phy(encoder); - intel_combo_phy_power_up_lanes(i915, phy, false, + intel_combo_phy_power_up_lanes(display, phy, false, crtc_state->lane_count, dig_port->lane_reversal); } @@ -2510,23 +2546,6 @@ static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) OVERLAP_PIXELS_MASK, dss1); } -static u8 mtl_get_port_width(u8 lane_count) -{ - switch (lane_count) { - case 1: - return 0; - case 2: - return 1; - case 3: - return 4; - case 4: - return 3; - default: - MISSING_CASE(lane_count); - return 4; - } -} - static void mtl_ddi_enable_d2d(struct intel_encoder *encoder) { @@ -2535,6 +2554,9 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder) i915_reg_t reg; u32 set_bits, wait_bits; + if (DISPLAY_VER(dev_priv) < 14) + return; + if (DISPLAY_VER(dev_priv) >= 20) { reg = DDI_BUF_CTL(port); set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; @@ -2560,7 +2582,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder, enum port port = encoder->port; u32 val = 0; - val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); + val |= XELPDP_PORT_WIDTH(crtc_state->lane_count); if (intel_dp_is_uhbr(crtc_state)) val |= XELPDP_PORT_BUF_PORT_DATA_40BIT; @@ -2594,6 +2616,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); + bool transparent_mode; int ret; intel_dp_set_link_params(intel_dp, @@ -2645,6 +2668,9 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, if (!is_mst) intel_dp_set_power(intel_dp, DP_SET_POWER_D0); + transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp); + drm_dp_lttpr_wake_timeout_setup(&intel_dp->aux, transparent_mode); + intel_dp_configure_protocol_converter(intel_dp, crtc_state); if (!is_mst) intel_dp_sink_enable_decompression(state, @@ -2706,6 +2732,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); @@ -2752,7 +2779,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); - dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, + dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); } @@ -2853,6 +2880,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; @@ -2881,7 +2909,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); - dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, + dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); } @@ -2927,8 +2955,7 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, crtc_state); /* Panel replay has to be enabled in sink dpcd before link training. */ - if (crtc_state->has_panel_replay) - intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); + intel_psr_panel_replay_enable_sink(enc_to_intel_dp(encoder)); if (DISPLAY_VER(display) >= 14) mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); @@ -2949,6 +2976,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &dig_port->hdmi; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); @@ -2957,7 +2985,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, intel_ddi_enable_clock(encoder, crtc_state); drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); - dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, + dig_port->ddi_io_wakeref = intel_display_power_get(display, dig_port->ddi_io_power_domain); icl_program_mg_dp_mode(dig_port, crtc_state); @@ -2985,20 +3013,21 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, * - crtc_state will be the state of the first stream to be activated on this * port, and it may not be the same stream that will be deactivated last, but * each stream should have a state that is identical when it comes to the DP - * link parameteres + * link parameters. */ static void intel_ddi_pre_enable(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); + intel_set_cpu_fifo_underrun_reporting(display, pipe, true); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, @@ -3011,7 +3040,7 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, /* FIXME precompute everything properly */ /* FIXME how do we turn infoframes off again? */ - if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) + if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) dig_port->set_infoframes(encoder, crtc_state->has_infoframe, crtc_state, conn_state); @@ -3019,13 +3048,16 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state, } static void -mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) +mtl_ddi_disable_d2d(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; i915_reg_t reg; u32 clr_bits, wait_bits; + if (DISPLAY_VER(dev_priv) < 14) + return; + if (DISPLAY_VER(dev_priv) >= 20) { reg = DDI_BUF_CTL(port); clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; @@ -3042,71 +3074,40 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder) port_name(port)); } -static void mtl_disable_ddi_buf(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - u32 val; - /* 3.b Clear DDI_CTL_DE Enable to 0. */ - val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); - if (val & DDI_BUF_CTL_ENABLE) { - val &= ~DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(port), val); - - /* 3.c Poll for PORT_BUF_CTL Idle Status == 1, timeout after 100us */ - mtl_wait_ddi_buf_idle(dev_priv, port); - } - - /* 3.d Disable D2D Link */ - mtl_ddi_disable_d2d_link(encoder); + intel_de_write(display, DDI_BUF_CTL(port), buf_ctl | DDI_BUF_CTL_ENABLE); + intel_de_posting_read(display, DDI_BUF_CTL(port)); - /* 3.e Disable DP_TP_CTL */ - if (intel_crtc_has_dp_encoder(crtc_state)) { - intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), - DP_TP_CTL_ENABLE, 0); - } + intel_wait_ddi_buf_active(encoder); } -static void disable_ddi_buf(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static void intel_ddi_buf_disable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum port port = encoder->port; - bool wait = false; - u32 val; - val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); - if (val & DDI_BUF_CTL_ENABLE) { - val &= ~DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(port), val); - wait = true; - } + intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0); + + if (DISPLAY_VER(display) >= 14) + intel_wait_ddi_buf_idle(display, port); - if (intel_crtc_has_dp_encoder(crtc_state)) + mtl_ddi_disable_d2d(encoder); + + if (intel_crtc_has_dp_encoder(crtc_state)) { intel_de_rmw(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), DP_TP_CTL_ENABLE, 0); + } intel_ddi_disable_fec(encoder, crtc_state); - if (wait) - intel_wait_ddi_buf_idle(dev_priv, port); -} - -static void intel_disable_ddi_buf(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - - if (DISPLAY_VER(dev_priv) >= 14) { - mtl_disable_ddi_buf(encoder, crtc_state); - - /* 3.f Disable DP_TP_CTL FEC Enable if it is needed */ - intel_ddi_disable_fec(encoder, crtc_state); - } else { - disable_ddi_buf(encoder, crtc_state); - } + if (DISPLAY_VER(display) < 14) + intel_wait_ddi_buf_idle(display, port); intel_ddi_wait_for_fec_status(encoder, crtc_state, false); } @@ -3116,6 +3117,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_dp *intel_dp = &dig_port->dp; @@ -3134,7 +3136,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, intel_dp_set_power(intel_dp, DP_SET_POWER_D3); if (DISPLAY_VER(dev_priv) >= 12) { - if (is_mst) { + if (is_mst || intel_dp_is_uhbr(old_crtc_state)) { enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; intel_de_rmw(dev_priv, @@ -3147,7 +3149,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, intel_ddi_disable_transcoder_clock(old_crtc_state); } - intel_disable_ddi_buf(encoder, old_crtc_state); + intel_ddi_buf_disable(encoder, old_crtc_state); intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); @@ -3167,7 +3169,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); if (wakeref) - intel_display_power_put(dev_priv, + intel_display_power_put(display, dig_port->ddi_io_power_domain, wakeref); @@ -3184,6 +3186,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *old_conn_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &dig_port->hdmi; @@ -3195,14 +3198,14 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, if (DISPLAY_VER(dev_priv) < 12) intel_ddi_disable_transcoder_clock(old_crtc_state); - intel_disable_ddi_buf(encoder, old_crtc_state); + intel_ddi_buf_disable(encoder, old_crtc_state); if (DISPLAY_VER(dev_priv) >= 12) intel_ddi_disable_transcoder_clock(old_crtc_state); wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); if (wakeref) - intel_display_power_put(dev_priv, + intel_display_power_put(display, dig_port->ddi_io_power_domain, wakeref); @@ -3285,7 +3288,7 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state, * be deactivated on this port, and it may not be the same * stream that was activated last, but each stream * should have a state that is identical when it comes to - * the DP link parameteres + * the DP link parameters */ if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) @@ -3367,7 +3370,7 @@ static void intel_ddi_enable_dp(struct intel_atomic_state *state, drm_connector_update_privacy_screen(conn_state); intel_edp_backlight_on(crtc_state, conn_state); - if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) + if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(&dig_port->dp)) intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); trans_port_sync_stop_link_train(state, encoder, crtc_state); @@ -3402,7 +3405,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_connector *connector = conn_state->connector; enum port port = encoder->port; - u32 buf_ctl; + u32 buf_ctl = 0; if (!intel_hdmi_handle_sink_scrambling(encoder, connector, crtc_state->hdmi_high_tmds_clock_ratio, @@ -3415,8 +3418,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); /* e. Enable D2D Link for C10/C20 Phy */ - if (DISPLAY_VER(dev_priv) >= 14) - mtl_ddi_enable_d2d(encoder); + mtl_ddi_enable_d2d(encoder); encoder->set_signal_levels(encoder, crtc_state); @@ -3468,18 +3470,15 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, * is filled with lane count, already set in the crtc_state. * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. */ - buf_ctl = DDI_BUF_CTL_ENABLE; - if (dig_port->lane_reversal) buf_ctl |= DDI_BUF_PORT_REVERSAL; if (dig_port->ddi_a_4_lanes) buf_ctl |= DDI_A_4_LANES; if (DISPLAY_VER(dev_priv) >= 14) { - u8 lane_count = mtl_get_port_width(crtc_state->lane_count); u32 port_buf = 0; - port_buf |= XELPDP_PORT_WIDTH(lane_count); + port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count); if (dig_port->lane_reversal) port_buf |= XELPDP_PORT_REVERSAL; @@ -3487,7 +3486,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf); - buf_ctl |= DDI_PORT_WIDTH(lane_count); + buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); if (DISPLAY_VER(dev_priv) >= 20) buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; @@ -3496,9 +3495,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; } - intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl); - - intel_wait_ddi_buf_active(encoder); + intel_ddi_buf_enable(encoder, buf_ctl); } static void intel_ddi_enable(struct intel_atomic_state *state, @@ -3707,12 +3704,13 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum tc_port tc_port = intel_encoder_to_tc(encoder); int ln; for (ln = 0; ln < 2; ln++) - intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0); + intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln), + DKL_PCS_DW5_CORE_SOFTRESET, 0); } static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, @@ -3721,7 +3719,6 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, struct intel_display *display = to_intel_display(crtc_state); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; - enum port port = encoder->port; u32 dp_tp_ctl; /* @@ -3729,8 +3726,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, * necessary disable and enable port */ dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)); - if (dp_tp_ctl & DP_TP_CTL_ENABLE) - mtl_disable_ddi_buf(encoder, crtc_state); + + drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); /* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */ dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; @@ -3755,44 +3752,25 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp, mtl_port_buf_ctl_program(encoder, crtc_state); /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */ - intel_dp->DP |= DDI_BUF_CTL_ENABLE; if (DISPLAY_VER(display) >= 20) intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; - intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); - intel_de_posting_read(display, DDI_BUF_CTL(port)); - - /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */ - intel_wait_ddi_buf_active(encoder); + intel_ddi_buf_enable(encoder, intel_dp->DP); + intel_dp->DP |= DDI_BUF_CTL_ENABLE; } static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; - u32 dp_tp_ctl, ddi_buf_ctl; - bool wait = false; + u32 dp_tp_ctl; dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); - if (dp_tp_ctl & DP_TP_CTL_ENABLE) { - ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); - if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { - intel_de_write(dev_priv, DDI_BUF_CTL(port), - ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); - wait = true; - } - - dp_tp_ctl &= ~DP_TP_CTL_ENABLE; - intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); - intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); - - if (wait) - intel_wait_ddi_buf_idle(dev_priv, port); - } + drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE); dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) || @@ -3810,11 +3788,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) adlp_tbt_to_dp_alt_switch_wa(encoder); + intel_ddi_buf_enable(encoder, intel_dp->DP); intel_dp->DP |= DDI_BUF_CTL_ENABLE; - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); - intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); - - intel_wait_ddi_buf_active(encoder); } static void intel_ddi_set_link_train(struct intel_dp *intel_dp, @@ -3879,10 +3854,12 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { + struct intel_display *display = &dev_priv->display; + if (cpu_transcoder == TRANSCODER_EDP) return false; - if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) + if (!intel_display_power_is_enabled(display, POWER_DOMAIN_AUDIO_MMIO)) return false; return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & @@ -3958,6 +3935,7 @@ static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *de static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_D); @@ -3971,7 +3949,7 @@ static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) intel_wakeref_t trans_wakeref; power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); - trans_wakeref = intel_display_power_get_if_enabled(dev_priv, + trans_wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!trans_wakeref) @@ -3981,7 +3959,7 @@ static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) crtc_state->cpu_transcoder) crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); - intel_display_power_put(dev_priv, power_domain, trans_wakeref); + intel_display_power_put(display, power_domain, trans_wakeref); } drm_WARN_ON(&dev_priv->drm, @@ -4068,7 +4046,7 @@ static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; - if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) + if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(&dig_port->dp)) crtc_state->infoframes.enable |= intel_lspcon_infoframes_enabled(encoder, crtc_state); else @@ -4153,13 +4131,13 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) { intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); /* * If this is true, we know we're being called from mst stream * encoder's ->get_config(). */ - if (intel_dp->is_mst) + if (intel_dp_mst_encoder_active_links(dig_port)) intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); else intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); @@ -4230,21 +4208,21 @@ void intel_ddi_get_clock(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct intel_shared_dpll *pll) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; bool pll_active; - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; port_dpll->pll = pll; - pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); - drm_WARN_ON(&i915->drm, !pll_active); + pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); + drm_WARN_ON(display->drm, !pll_active); icl_set_active_port_dpll(crtc_state, port_dpll_id); - crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, &crtc_state->dpll_hw_state); } @@ -4333,12 +4311,12 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct intel_shared_dpll *pll) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum icl_port_dpll_id port_dpll_id; struct icl_port_dpll *port_dpll; bool pll_active; - if (drm_WARN_ON(&i915->drm, !pll)) + if (drm_WARN_ON(display->drm, !pll)) return; if (icl_ddi_tc_pll_is_tbt(pll)) @@ -4349,15 +4327,15 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; port_dpll->pll = pll; - pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); - drm_WARN_ON(&i915->drm, !pll_active); + pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); + drm_WARN_ON(display->drm, !pll_active); icl_set_active_port_dpll(crtc_state, port_dpll_id); if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) - crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); + crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port); else - crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll, &crtc_state->dpll_hw_state); } @@ -4596,16 +4574,16 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder, static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->dev); + struct intel_display *display = to_intel_display(encoder->dev); struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); intel_dp_encoder_flush_work(encoder); if (intel_encoder_is_tc(&dig_port->base)) intel_tc_port_cleanup(dig_port); - intel_display_power_flush_work(i915); + intel_display_power_flush_work(display); drm_encoder_cleanup(encoder); - kfree(dig_port->hdcp_port_data.streams); + kfree(dig_port->hdcp.port_data.streams); kfree(dig_port); } @@ -4683,6 +4661,7 @@ static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) static int intel_hdmi_reset_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); struct intel_connector *connector = hdmi->attached_connector; @@ -4749,7 +4728,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, * would be perfectly happy if were to just reconfigure * the SCDC settings on the fly. */ - return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); + return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx); } static void intel_ddi_link_check(struct intel_encoder *encoder) @@ -5105,7 +5084,7 @@ void intel_ddi_init(struct intel_display *display, return; } - if (!assert_port_valid(dev_priv, port)) + if (!assert_port_valid(display, port)) return; if (port_in_use(dev_priv, port)) { @@ -5123,7 +5102,7 @@ void intel_ddi_init(struct intel_display *display, return; } - phy = intel_port_to_phy(dev_priv, port); + phy = intel_port_to_phy(display, port); /* * On platforms with HTI (aka HDPORT), if it's enabled at boot it may @@ -5160,7 +5139,7 @@ void intel_ddi_init(struct intel_display *display, return; } - if (intel_phy_is_snps(dev_priv, phy) && + if (intel_phy_is_snps(display, phy) && dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { drm_dbg_kms(&dev_priv->drm, "SNPS PHY %c failed to calibrate, proceeding anyway\n", @@ -5183,7 +5162,7 @@ void intel_ddi_init(struct intel_display *display, port_name(port - PORT_D_XELPD + PORT_D), phy_name(phy)); } else if (DISPLAY_VER(dev_priv) >= 12) { - enum tc_port tc_port = intel_port_to_tc(dev_priv, port); + enum tc_port tc_port = intel_port_to_tc(display, port); drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, @@ -5193,7 +5172,7 @@ void intel_ddi_init(struct intel_display *display, tc_port != TC_PORT_NONE ? "TC" : "", tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); } else if (DISPLAY_VER(dev_priv) >= 11) { - enum tc_port tc_port = intel_port_to_tc(dev_priv, port); + enum tc_port tc_port = intel_port_to_tc(display, port); drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, @@ -5210,8 +5189,8 @@ void intel_ddi_init(struct intel_display *display, intel_encoder_link_check_init(encoder, intel_ddi_link_check); - mutex_init(&dig_port->hdcp_mutex); - dig_port->num_hdcp_streams = 0; + mutex_init(&dig_port->hdcp.mutex); + dig_port->hdcp.num_streams = 0; encoder->hotplug = intel_ddi_hotplug; encoder->compute_output_type = intel_ddi_compute_output_type; @@ -5234,7 +5213,7 @@ void intel_ddi_init(struct intel_display *display, encoder->get_power_domains = intel_ddi_get_power_domains; encoder->type = INTEL_OUTPUT_DDI; - encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); + encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port); encoder->port = port; encoder->cloneable = 0; encoder->pipe_mask = ~0; @@ -5341,7 +5320,7 @@ void intel_ddi_init(struct intel_display *display, else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) encoder->hpd_pin = skl_hpd_pin(dev_priv, port); else - encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); + encoder->hpd_pin = intel_hpd_pin_default(port); ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); @@ -5385,7 +5364,7 @@ void intel_ddi_init(struct intel_display *display, } drm_WARN_ON(&dev_priv->drm, port > PORT_I); - dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); + dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port); if (DISPLAY_VER(dev_priv) >= 11) { if (intel_encoder_is_tc(encoder)) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 2faadd1441e2..353eb04079e9 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -9,7 +9,6 @@ #include "i915_reg_defs.h" struct drm_connector_state; -struct drm_i915_private; struct intel_atomic_state; struct intel_bios_encoder_data; struct intel_connector; @@ -54,8 +53,7 @@ void hsw_ddi_get_config(struct intel_encoder *encoder, struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder); void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); -void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, - enum port port); +void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port); void intel_ddi_init(struct intel_display *display, const struct intel_bios_encoder_data *devdata); bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 9389b295036e..a238be5bc455 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -3,13 +3,13 @@ * Copyright © 2020 Intel Corporation */ -#include "i915_drv.h" +#include "i915_utils.h" +#include "intel_cx0_phy.h" #include "intel_ddi.h" #include "intel_ddi_buf_trans.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_dp.h" -#include "intel_cx0_phy.h" /* HDMI/DVI modes ignore everything but the last 2 items. So we share * them for both DP and FDI transports, allowing those ports to @@ -1407,10 +1407,10 @@ tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, int *n_entries) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); if (crtc_state->port_clock > 270000) { - if (IS_TIGERLAKE_UY(dev_priv)) { + if (display->platform.tigerlake_uy) { return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2, n_entries); } else { @@ -1709,59 +1709,67 @@ mtl_get_c20_buf_trans(struct intel_encoder *encoder, void intel_ddi_buf_trans_init(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); - if (DISPLAY_VER(i915) >= 14) { + if (DISPLAY_VER(display) >= 14) { if (intel_encoder_is_c10phy(encoder)) encoder->get_buf_trans = mtl_get_c10_buf_trans; else encoder->get_buf_trans = mtl_get_c20_buf_trans; - } else if (IS_DG2(i915)) { + } else if (display->platform.dg2) { encoder->get_buf_trans = dg2_get_snps_buf_trans; - } else if (IS_ALDERLAKE_P(i915)) { + } else if (display->platform.alderlake_p) { if (intel_encoder_is_combo(encoder)) encoder->get_buf_trans = adlp_get_combo_buf_trans; else encoder->get_buf_trans = adlp_get_dkl_buf_trans; - } else if (IS_ALDERLAKE_S(i915)) { + } else if (display->platform.alderlake_s) { encoder->get_buf_trans = adls_get_combo_buf_trans; - } else if (IS_ROCKETLAKE(i915)) { + } else if (display->platform.rocketlake) { encoder->get_buf_trans = rkl_get_combo_buf_trans; - } else if (IS_DG1(i915)) { + } else if (display->platform.dg1) { encoder->get_buf_trans = dg1_get_combo_buf_trans; - } else if (DISPLAY_VER(i915) >= 12) { + } else if (DISPLAY_VER(display) >= 12) { if (intel_encoder_is_combo(encoder)) encoder->get_buf_trans = tgl_get_combo_buf_trans; else encoder->get_buf_trans = tgl_get_dkl_buf_trans; - } else if (DISPLAY_VER(i915) == 11) { - if (IS_JASPERLAKE(i915)) + } else if (DISPLAY_VER(display) == 11) { + if (display->platform.jasperlake) encoder->get_buf_trans = jsl_get_combo_buf_trans; - else if (IS_ELKHARTLAKE(i915)) + else if (display->platform.elkhartlake) encoder->get_buf_trans = ehl_get_combo_buf_trans; else if (intel_encoder_is_combo(encoder)) encoder->get_buf_trans = icl_get_combo_buf_trans; else encoder->get_buf_trans = icl_get_mg_buf_trans; - } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { + } else if (display->platform.geminilake || display->platform.broxton) { encoder->get_buf_trans = bxt_get_buf_trans; - } else if (IS_COMETLAKE_ULX(i915) || IS_COFFEELAKE_ULX(i915) || IS_KABYLAKE_ULX(i915)) { + } else if (display->platform.cometlake_ulx || + display->platform.coffeelake_ulx || + display->platform.kabylake_ulx) { encoder->get_buf_trans = kbl_y_get_buf_trans; - } else if (IS_COMETLAKE_ULT(i915) || IS_COFFEELAKE_ULT(i915) || IS_KABYLAKE_ULT(i915)) { + } else if (display->platform.cometlake_ult || + display->platform.coffeelake_ult || + display->platform.kabylake_ult) { encoder->get_buf_trans = kbl_u_get_buf_trans; - } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) { + } else if (display->platform.cometlake || + display->platform.coffeelake || + display->platform.kabylake) { encoder->get_buf_trans = kbl_get_buf_trans; - } else if (IS_SKYLAKE_ULX(i915)) { + } else if (display->platform.skylake_ulx) { encoder->get_buf_trans = skl_y_get_buf_trans; - } else if (IS_SKYLAKE_ULT(i915)) { + } else if (display->platform.skylake_ult) { encoder->get_buf_trans = skl_u_get_buf_trans; - } else if (IS_SKYLAKE(i915)) { + } else if (display->platform.skylake) { encoder->get_buf_trans = skl_get_buf_trans; - } else if (IS_BROADWELL(i915)) { + } else if (display->platform.broadwell) { encoder->get_buf_trans = bdw_get_buf_trans; - } else if (IS_HASWELL(i915)) { + } else if (display->platform.haswell) { encoder->get_buf_trans = hsw_get_buf_trans; } else { - MISSING_CASE(INTEL_INFO(i915)->platform); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); + + MISSING_CASE(pdev->device); } } diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h index 2133984a572b..29a190390192 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h @@ -8,7 +8,6 @@ #include <linux/types.h> -struct drm_i915_private; struct intel_encoder; struct intel_crtc_state; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4271da219b41..3b509c70fb58 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -104,6 +104,7 @@ #include "intel_pch_display.h" #include "intel_pch_refclk.h" #include "intel_pcode.h" +#include "intel_pfit.h" #include "intel_pipe_crc.h" #include "intel_plane_initial.h" #include "intel_pmdemand.h" @@ -123,7 +124,6 @@ #include "intel_wm.h" #include "skl_scaler.h" #include "skl_universal_plane.h" -#include "skl_universal_plane_regs.h" #include "skl_watermark.h" #include "vlv_dpio_phy_regs.h" #include "vlv_dsi.h" @@ -182,16 +182,17 @@ int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, return hpll; } -void intel_update_czclk(struct drm_i915_private *dev_priv) +void intel_update_czclk(struct intel_display *display) { - if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) + struct drm_i915_private *dev_priv = to_i915(display->drm); + + if (!display->platform.valleyview && !display->platform.cherryview) return; dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", CCK_CZ_CLOCK_CONTROL); - drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", - dev_priv->czclk_freq); + drm_dbg_kms(display->drm, "CZ clock rate: %d kHz\n", dev_priv->czclk_freq); } static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) @@ -202,29 +203,29 @@ static bool is_hdr_mode(const struct intel_crtc_state *crtc_state) /* WA Display #0827: Gen9:all */ static void -skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) +skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable) { - intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), + intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), DUPS1_GATING_DIS | DUPS2_GATING_DIS, enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0); } /* Wa_2006604312:icl,ehl */ static void -icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, +icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe, bool enable) { - intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), + intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, enable ? DPFR_GATING_DIS : 0); } /* Wa_1604331009:icl,jsl,ehl */ static void -icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, +icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe, bool enable) { - intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), + intel_de_rmw(display, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS, enable ? CURSOR_GATING_DIS : 0); } @@ -404,41 +405,40 @@ struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state) static void intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) { + struct intel_display *display = to_intel_display(old_crtc_state); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - if (DISPLAY_VER(dev_priv) >= 4) { + if (DISPLAY_VER(display) >= 4) { enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; /* Wait for the Pipe State to go off */ - if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), + if (intel_de_wait_for_clear(display, TRANSCONF(display, cpu_transcoder), TRANSCONF_STATE_ENABLE, 100)) - drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); + drm_WARN(display->drm, 1, "pipe_off wait timed out\n"); } else { intel_wait_for_pipe_scanline_stopped(crtc); } } -void assert_transcoder(struct drm_i915_private *dev_priv, +void assert_transcoder(struct intel_display *display, enum transcoder cpu_transcoder, bool state) { - struct intel_display *display = &dev_priv->display; bool cur_state; enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; /* we keep both pipes enabled on 830 */ - if (IS_I830(dev_priv)) + if (display->platform.i830) state = true; power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (wakeref) { - u32 val = intel_de_read(dev_priv, - TRANSCONF(dev_priv, cpu_transcoder)); + u32 val = intel_de_read(display, + TRANSCONF(display, cpu_transcoder)); cur_state = !!(val & TRANSCONF_ENABLE); - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); } else { cur_state = false; } @@ -468,57 +468,22 @@ static void assert_plane(struct intel_plane *plane, bool state) static void assert_planes_disabled(struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_plane *plane; - for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) + for_each_intel_plane_on_crtc(display->drm, crtc, plane) assert_plane_disabled(plane); } -void vlv_wait_port_ready(struct intel_display *display, - struct intel_digital_port *dig_port, - unsigned int expected_mask) -{ - u32 port_mask; - i915_reg_t dpll_reg; - - switch (dig_port->base.port) { - default: - MISSING_CASE(dig_port->base.port); - fallthrough; - case PORT_B: - port_mask = DPLL_PORTB_READY_MASK; - dpll_reg = DPLL(display, 0); - break; - case PORT_C: - port_mask = DPLL_PORTC_READY_MASK; - dpll_reg = DPLL(display, 0); - expected_mask <<= 4; - break; - case PORT_D: - port_mask = DPLL_PORTD_READY_MASK; - dpll_reg = DPIO_PHY_STATUS; - break; - } - - if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000)) - drm_WARN(display->drm, 1, - "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", - dig_port->base.base.base.id, dig_port->base.base.name, - intel_de_read(display, dpll_reg) & port_mask, - expected_mask); -} - void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) { struct intel_display *display = to_intel_display(new_crtc_state); struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; enum pipe pipe = crtc->pipe; u32 val; - drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); + drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe)); assert_planes_disabled(crtc); @@ -527,56 +492,56 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) * a plane. On ILK+ the pipe PLLs are integrated, so we don't * need the check. */ - if (HAS_GMCH(dev_priv)) { + if (HAS_GMCH(display)) { if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) - assert_dsi_pll_enabled(dev_priv); + assert_dsi_pll_enabled(display); else - assert_pll_enabled(dev_priv, pipe); + assert_pll_enabled(display, pipe); } else { if (new_crtc_state->has_pch_encoder) { /* if driving the PCH, we need FDI enabled */ - assert_fdi_rx_pll_enabled(dev_priv, + assert_fdi_rx_pll_enabled(display, intel_crtc_pch_transcoder(crtc)); - assert_fdi_tx_pll_enabled(dev_priv, + assert_fdi_tx_pll_enabled(display, (enum pipe) cpu_transcoder); } /* FIXME: assert CPU port conditions for SNB+ */ } /* Wa_22012358565:adl-p */ - if (DISPLAY_VER(dev_priv) == 13) - intel_de_rmw(dev_priv, PIPE_ARB_CTL(dev_priv, pipe), + if (DISPLAY_VER(display) == 13) + intel_de_rmw(display, PIPE_ARB_CTL(display, pipe), 0, PIPE_ARB_USE_PROG_SLOTS); - if (DISPLAY_VER(dev_priv) >= 14) { + if (DISPLAY_VER(display) >= 14) { u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA; u32 set = 0; - if (DISPLAY_VER(dev_priv) == 14) + if (DISPLAY_VER(display) == 14) set |= DP_FEC_BS_JITTER_WA; intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), clear, set); } - val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); + val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); if (val & TRANSCONF_ENABLE) { /* we keep both pipes enabled on 830 */ - drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); + drm_WARN_ON(display->drm, !display->platform.i830); return; } /* Wa_1409098942:adlp+ */ - if (DISPLAY_VER(dev_priv) >= 13 && + if (DISPLAY_VER(display) >= 13 && new_crtc_state->dsc.compression_enable) { val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK, TRANSCONF_PIXEL_COUNT_SCALING_X4); } - intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), + intel_de_write(display, TRANSCONF(display, cpu_transcoder), val | TRANSCONF_ENABLE); - intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); + intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); /* * Until the pipe starts PIPEDSL reads will return a stale value, @@ -593,12 +558,11 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) { struct intel_display *display = to_intel_display(old_crtc_state); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; enum pipe pipe = crtc->pipe; u32 val; - drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); + drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe)); /* * Make sure planes won't keep trying to pump pixels to us, @@ -606,7 +570,7 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) */ assert_planes_disabled(crtc); - val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); + val = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); if ((val & TRANSCONF_ENABLE) == 0) return; @@ -618,17 +582,17 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) val &= ~TRANSCONF_DOUBLE_WIDE; /* Don't disable pipe or pipe PLLs if needed */ - if (!IS_I830(dev_priv)) + if (!display->platform.i830) val &= ~TRANSCONF_ENABLE; /* Wa_1409098942:adlp+ */ - if (DISPLAY_VER(dev_priv) >= 13 && + if (DISPLAY_VER(display) >= 13 && old_crtc_state->dsc.compression_enable) val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; - intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); + intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), FECSTALL_DIS_DPTSTREAM_DPTTG, 0); @@ -636,90 +600,14 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) intel_wait_for_pipe_off(old_crtc_state); } -unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) -{ - unsigned int size = 0; - int i; - - for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) - size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; - - return size; -} - -unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) -{ - unsigned int size = 0; - int i; - - for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { - unsigned int plane_size; - - if (rem_info->plane[i].linear) - plane_size = rem_info->plane[i].size; - else - plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; - - if (plane_size == 0) - continue; - - if (rem_info->plane_alignment) - size = ALIGN(size, rem_info->plane_alignment); - - size += plane_size; - } - - return size; -} - -bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) -{ - struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); - - return DISPLAY_VER(dev_priv) < 4 || - (plane->fbc && !plane_state->no_fbc_reason && - plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); -} - -/* - * Convert the x/y offsets into a linear offset. - * Only valid with 0/180 degree rotation, which is fine since linear - * offset is only used with linear buffers on pre-hsw and tiled buffers - * with gen2/3, and 90/270 degree rotations isn't supported on any of them. - */ -u32 intel_fb_xy_to_linear(int x, int y, - const struct intel_plane_state *state, - int color_plane) -{ - const struct drm_framebuffer *fb = state->hw.fb; - unsigned int cpp = fb->format->cpp[color_plane]; - unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; - - return y * pitch + x * cpp; -} - -/* - * Add the x/y offsets derived from fb->offsets[] to the user - * specified plane src x/y offsets. The resulting x/y offsets - * specify the start of scanout from the beginning of the gtt mapping. - */ -void intel_add_fb_offsets(int *x, int *y, - const struct intel_plane_state *state, - int color_plane) - -{ - *x += state->view.color_plane[color_plane].x; - *y += state->view.color_plane[color_plane].y; -} - -u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, +u32 intel_plane_fb_max_stride(struct drm_device *drm, u32 pixel_format, u64 modifier) { + struct intel_display *display = to_intel_display(drm); struct intel_crtc *crtc; struct intel_plane *plane; - if (!HAS_DISPLAY(dev_priv)) + if (!HAS_DISPLAY(display)) return 0; /* @@ -727,7 +615,7 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, * the highest stride limits of them all, * if in case pipe A is disabled, use the first pipe from pipe_mask. */ - crtc = intel_first_crtc(dev_priv); + crtc = intel_first_crtc(display); if (!crtc) return 0; @@ -753,7 +641,7 @@ void intel_set_plane_visible(struct intel_crtc_state *crtc_state, void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); struct drm_plane *plane; /* @@ -764,7 +652,7 @@ void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) crtc_state->enabled_planes = 0; crtc_state->active_planes = 0; - drm_for_each_plane_mask(plane, &dev_priv->drm, + drm_for_each_plane_mask(plane, display->drm, crtc_state->uapi.plane_mask) { crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id); crtc_state->active_planes |= BIT(to_intel_plane(plane)->id); @@ -774,29 +662,28 @@ void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state) void intel_plane_disable_noatomic(struct intel_crtc *crtc, struct intel_plane *plane) { + struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", plane->base.base.id, plane->base.name, crtc->base.base.id, crtc->base.name); + intel_plane_set_invisible(crtc_state, plane_state); intel_set_plane_visible(crtc_state, plane_state, false); intel_plane_fixup_bitmasks(crtc_state); - crtc_state->data_rate[plane->id] = 0; - crtc_state->data_rate_y[plane->id] = 0; - crtc_state->rel_data_rate[plane->id] = 0; - crtc_state->rel_data_rate_y[plane->id] = 0; - crtc_state->min_cdclk[plane->id] = 0; + + skl_wm_plane_disable_noatomic(crtc, plane); if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && hsw_ips_disable(crtc_state)) { crtc_state->ips_enabled = false; - intel_crtc_wait_for_next_vblank(crtc); + intel_plane_initial_vblank_wait(crtc); } /* @@ -808,19 +695,19 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc, * event which is after the vblank start event, so we need to have a * wait-for-vblank between disabling the plane and the pipe. */ - if (HAS_GMCH(dev_priv) && + if (HAS_GMCH(display) && intel_set_memory_cxsr(dev_priv, false)) - intel_crtc_wait_for_next_vblank(crtc); + intel_plane_initial_vblank_wait(crtc); /* * Gen2 reports pipe underruns whenever all planes are disabled. * So disable underrun reporting before all the planes get disabled. */ - if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes) - intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); + if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes) + intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false); intel_plane_disable_arm(NULL, plane, crtc_state); - intel_crtc_wait_for_next_vblank(crtc); + intel_plane_initial_vblank_wait(crtc); } unsigned int @@ -836,12 +723,12 @@ intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; u32 tmp; - tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); + tmp = intel_de_read(display, PIPE_CHICKEN(pipe)); /* * Display WA #1153: icl @@ -861,24 +748,24 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) * Underrun recovery must always be disabled on display 13+. * DG2 chicken bit meaning is inverted compared to other platforms. */ - if (IS_DG2(dev_priv)) + if (display->platform.dg2) tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2; - else if ((DISPLAY_VER(dev_priv) >= 13) && (DISPLAY_VER(dev_priv) < 30)) + else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30)) tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; /* Wa_14010547955:dg2 */ - if (IS_DG2(dev_priv)) + if (display->platform.dg2) tmp |= DG2_RENDER_CCSTAG_4_3_EN; - intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); + intel_de_write(display, PIPE_CHICKEN(pipe), tmp); } -bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) +bool intel_has_pending_fb_unpin(struct intel_display *display) { struct drm_crtc *crtc; bool cleanup_done; - drm_for_each_crtc(crtc, &dev_priv->drm) { + drm_for_each_crtc(crtc, display->drm) { struct drm_crtc_commit *commit; spin_lock(&crtc->commit_lock); commit = list_first_entry_or_null(&crtc->commit_list, @@ -930,36 +817,6 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state, return encoder; } -static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - const struct drm_rect *dst = &crtc_state->pch_pfit.dst; - enum pipe pipe = crtc->pipe; - int width = drm_rect_width(dst); - int height = drm_rect_height(dst); - int x = dst->x1; - int y = dst->y1; - - if (!crtc_state->pch_pfit.enabled) - return; - - /* Force use of hard-coded filter coefficients - * as some pre-programmed values are broken, - * e.g. x201. - */ - if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) - intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | - PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); - else - intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE | - PF_FILTER_MED_3x3); - intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), - PF_WIN_XPOS(x) | PF_WIN_YPOS(y)); - intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), - PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height)); -} - static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) { if (crtc->overlay) @@ -972,13 +829,13 @@ static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc) static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); if (!crtc_state->nv12_planes) return false; /* WA Display #0827: Gen9:all */ - if (DISPLAY_VER(dev_priv) == 9) + if (DISPLAY_VER(display) == 9) return true; return false; @@ -986,10 +843,10 @@ static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); /* Wa_2006604312:icl,ehl */ - if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11) + if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11) return true; return false; @@ -997,31 +854,31 @@ static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); /* Wa_1604331009:icl,jsl,ehl */ if (is_hdr_mode(crtc_state) && crtc_state->active_planes & BIT(PLANE_CURSOR) && - DISPLAY_VER(dev_priv) == 11) + DISPLAY_VER(display) == 11) return true; return false; } -static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, +static void intel_async_flip_vtd_wa(struct intel_display *display, enum pipe pipe, bool enable) { - if (DISPLAY_VER(i915) == 9) { + if (DISPLAY_VER(display) == 9) { /* - * "Plane N strech max must be programmed to 11b (x1) + * "Plane N stretch max must be programmed to 11b (x1) * when Async flips are enabled on that plane." */ - intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), + intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), SKL_PLANE1_STRETCH_MAX_MASK, enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8); } else { /* Also needed on HSW/BDW albeit undocumented */ - intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe), + intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), HSW_PRI_STRETCH_MAX_MASK, enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8); } @@ -1029,10 +886,12 @@ static void intel_async_flip_vtd_wa(struct drm_i915_private *i915, static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); return crtc_state->uapi.async_flip && i915_vtd_active(i915) && - (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915)); + (DISPLAY_VER(display) == 9 || display->platform.broadwell || + display->platform.haswell); } static void intel_encoders_audio_enable(struct intel_atomic_state *state, @@ -1109,7 +968,9 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin || old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax || old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband || - old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full; + old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full || + old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start || + old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end; } static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, @@ -1181,6 +1042,7 @@ static bool audio_disabling(const struct intel_crtc_state *old_crtc_state, static void intel_post_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); struct drm_i915_private *dev_priv = to_i915(state->base.dev); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); @@ -1199,19 +1061,19 @@ static void intel_post_plane_update(struct intel_atomic_state *state, if (needs_async_flip_vtd_wa(old_crtc_state) && !needs_async_flip_vtd_wa(new_crtc_state)) - intel_async_flip_vtd_wa(dev_priv, pipe, false); + intel_async_flip_vtd_wa(display, pipe, false); if (needs_nv12_wa(old_crtc_state) && !needs_nv12_wa(new_crtc_state)) - skl_wa_827(dev_priv, pipe, false); + skl_wa_827(display, pipe, false); if (needs_scalerclk_wa(old_crtc_state) && !needs_scalerclk_wa(new_crtc_state)) - icl_wa_scalerclkgating(dev_priv, pipe, false); + icl_wa_scalerclkgating(display, pipe, false); if (needs_cursorclk_wa(old_crtc_state) && !needs_cursorclk_wa(new_crtc_state)) - icl_wa_cursorclkgating(dev_priv, pipe, false); + icl_wa_cursorclkgating(display, pipe, false); if (intel_crtc_needs_color_update(new_crtc_state)) intel_color_post_update(new_crtc_state); @@ -1305,6 +1167,7 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, static void intel_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); struct drm_i915_private *dev_priv = to_i915(state->base.dev); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); @@ -1332,22 +1195,22 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, if (!needs_async_flip_vtd_wa(old_crtc_state) && needs_async_flip_vtd_wa(new_crtc_state)) - intel_async_flip_vtd_wa(dev_priv, pipe, true); + intel_async_flip_vtd_wa(display, pipe, true); /* Display WA 827 */ if (!needs_nv12_wa(old_crtc_state) && needs_nv12_wa(new_crtc_state)) - skl_wa_827(dev_priv, pipe, true); + skl_wa_827(display, pipe, true); /* Wa_2006604312:icl,ehl */ if (!needs_scalerclk_wa(old_crtc_state) && needs_scalerclk_wa(new_crtc_state)) - icl_wa_scalerclkgating(dev_priv, pipe, true); + icl_wa_scalerclkgating(display, pipe, true); /* Wa_1604331009:icl,jsl,ehl */ if (!needs_cursorclk_wa(old_crtc_state) && needs_cursorclk_wa(new_crtc_state)) - icl_wa_cursorclkgating(dev_priv, pipe, true); + icl_wa_cursorclkgating(display, pipe, true); /* * Vblank time updates from the shadow to live plane control register @@ -1358,7 +1221,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, * event which is after the vblank start event, so we need to have a * wait-for-vblank between disabling the plane and the pipe. */ - if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active && + if (HAS_GMCH(display) && old_crtc_state->hw.active && new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) intel_crtc_wait_for_next_vblank(crtc); @@ -1369,7 +1232,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, * * WaCxSRDisabledForSpriteScaling:ivb */ - if (!HAS_GMCH(dev_priv) && old_crtc_state->hw.active && + if (!HAS_GMCH(display) && old_crtc_state->hw.active && new_crtc_state->disable_cxsr && ilk_disable_cxsr(dev_priv)) intel_crtc_wait_for_next_vblank(crtc); @@ -1405,8 +1268,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, * chance of catching underruns with the intermediate watermarks * vs. the old plane configuration. */ - if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); + if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state)) + intel_set_cpu_fifo_underrun_reporting(display, pipe, false); /* * WA for platforms where async address update enable bit @@ -1446,7 +1309,7 @@ static void intel_crtc_disable_planes(struct intel_atomic_state *state, static void intel_encoders_update_prepare(struct intel_atomic_state *state) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *new_crtc_state, *old_crtc_state; struct intel_crtc *crtc; int i; @@ -1455,7 +1318,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state) * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits. * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook. */ - if (i915->display.dpll.mgr) { + if (display->dpll.mgr) { for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { if (intel_crtc_needs_modeset(new_crtc_state)) continue; @@ -1645,12 +1508,13 @@ static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta static void ilk_crtc_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(crtc); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (drm_WARN_ON(&dev_priv->drm, crtc->active)) + if (drm_WARN_ON(display->drm, crtc->active)) return; /* @@ -1663,8 +1527,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state, * * Spurious PCH underruns also occur during PCH enabling. */ - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); - intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); + intel_set_cpu_fifo_underrun_reporting(display, pipe, false); + intel_set_pch_fifo_underrun_reporting(display, pipe, false); ilk_configure_cpu_transcoder(new_crtc_state); @@ -1677,8 +1541,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state, if (new_crtc_state->has_pch_encoder) { ilk_pch_pre_enable(state, crtc); } else { - assert_fdi_tx_disabled(dev_priv, pipe); - assert_fdi_rx_disabled(dev_priv, pipe); + assert_fdi_tx_disabled(display, pipe); + assert_fdi_rx_disabled(display, pipe); } ilk_pfit_enable(new_crtc_state); @@ -1712,33 +1576,33 @@ static void ilk_crtc_enable(struct intel_atomic_state *state, intel_crtc_wait_for_next_vblank(crtc); intel_crtc_wait_for_next_vblank(crtc); } - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); - intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); + intel_set_cpu_fifo_underrun_reporting(display, pipe, true); + intel_set_pch_fifo_underrun_reporting(display, pipe, true); } /* Display WA #1180: WaDisableScalarClockGating: glk */ static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); - return DISPLAY_VER(i915) == 10 && crtc_state->pch_pfit.enabled; + return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled; } static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; - intel_de_rmw(i915, CLKGATE_DIS_PSL(crtc->pipe), + intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe), mask, enable ? mask : 0); } static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), + intel_de_write(display, WM_LINETIME(crtc->pipe), HSW_LINETIME(crtc_state->linetime) | HSW_IPS_LINETIME(crtc_state->ips_linetime)); } @@ -1754,8 +1618,8 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; if (crtc_state->has_pch_encoder) { @@ -1769,11 +1633,11 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta } intel_set_transcoder_timings(crtc_state); - if (HAS_VRR(dev_priv)) + if (HAS_VRR(display)) intel_vrr_set_transcoder_timings(crtc_state); if (cpu_transcoder != TRANSCODER_EDP) - intel_de_write(dev_priv, TRANS_MULT(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_MULT(display, cpu_transcoder), crtc_state->pixel_multiplier - 1); hsw_set_frame_start_delay(crtc_state); @@ -1787,12 +1651,11 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; struct intel_crtc *pipe_crtc; int i; - if (drm_WARN_ON(&dev_priv->drm, crtc->active)) + if (drm_WARN_ON(display->drm, crtc->active)) return; for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) intel_dmc_enable_pipe(display, pipe_crtc->pipe); @@ -1815,12 +1678,12 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_dsc_enable(pipe_crtc_state); - if (HAS_UNCOMPRESSED_JOINER(dev_priv)) + if (HAS_UNCOMPRESSED_JOINER(display)) intel_uncompressed_joiner_enable(pipe_crtc_state); intel_set_pipe_src_size(pipe_crtc_state); - if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) + if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) bdw_set_pipe_misc(NULL, pipe_crtc_state); } @@ -1836,7 +1699,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, if (glk_need_scaler_clock_gating_wa(pipe_crtc_state)) glk_pipe_scaler_clock_gating_wa(pipe_crtc, true); - if (DISPLAY_VER(dev_priv) >= 9) + if (DISPLAY_VER(display) >= 9) skl_pfit_enable(pipe_crtc_state); else ilk_pfit_enable(pipe_crtc_state); @@ -1849,7 +1712,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, hsw_set_linetime_wm(pipe_crtc_state); - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) icl_set_pipe_chicken(pipe_crtc_state); intel_initial_watermarks(state, pipe_crtc); @@ -1872,7 +1735,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, * enabling, we need to change the workaround. */ hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe; - if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { + if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) { struct intel_crtc *wa_crtc = intel_crtc_for_pipe(display, hsw_workaround_pipe); @@ -1882,28 +1745,12 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, } } -void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum pipe pipe = crtc->pipe; - - /* To avoid upsetting the power well on haswell only disable the pfit if - * it's in use. The hw state code will make sure we get this right. */ - if (!old_crtc_state->pch_pfit.enabled) - return; - - intel_de_write_fw(dev_priv, PF_CTL(pipe), 0); - intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0); - intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0); -} - static void ilk_crtc_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(crtc); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; /* @@ -1911,8 +1758,8 @@ static void ilk_crtc_disable(struct intel_atomic_state *state, * pipe is already disabled, but FDI RX/TX is still enabled. * Happens at least with VGA+HDMI cloning. Suppress them. */ - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); - intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); + intel_set_cpu_fifo_underrun_reporting(display, pipe, false); + intel_set_pch_fifo_underrun_reporting(display, pipe, false); intel_encoders_disable(state, crtc); @@ -1930,8 +1777,8 @@ static void ilk_crtc_disable(struct intel_atomic_state *state, if (old_crtc_state->has_pch_encoder) ilk_pch_post_disable(state, crtc); - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); - intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); + intel_set_cpu_fifo_underrun_reporting(display, pipe, true); + intel_set_pch_fifo_underrun_reporting(display, pipe, true); intel_disable_shared_dpll(old_crtc_state); } @@ -1965,44 +1812,18 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, intel_dmc_disable_pipe(display, pipe_crtc->pipe); } -static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - - if (!crtc_state->gmch_pfit.control) - return; - - /* - * The panel fitter should only be adjusted whilst the pipe is disabled, - * according to register description and PRM. - */ - drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE); - assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); - - intel_de_write(dev_priv, PFIT_PGM_RATIOS(dev_priv), - crtc_state->gmch_pfit.pgm_ratios); - intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), - crtc_state->gmch_pfit.control); - - /* Border color in case we don't scale up to the full screen. Black by - * default, change to something else for debugging. */ - intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0); -} - /* Prefer intel_encoder_is_combo() */ -bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) +bool intel_phy_is_combo(struct intel_display *display, enum phy phy) { if (phy == PHY_NONE) return false; - else if (IS_ALDERLAKE_S(dev_priv)) + else if (display->platform.alderlake_s) return phy <= PHY_E; - else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) + else if (display->platform.dg1 || display->platform.rocketlake) return phy <= PHY_D; - else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) + else if (display->platform.jasperlake || display->platform.elkhartlake) return phy <= PHY_C; - else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12)) + else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12)) return phy <= PHY_B; else /* @@ -2014,47 +1835,47 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) } /* Prefer intel_encoder_is_tc() */ -bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) +bool intel_phy_is_tc(struct intel_display *display, enum phy phy) { /* * Discrete GPU phy's are not attached to FIA's to support TC * subsystem Legacy or non-legacy, and only support native DP/HDMI */ - if (IS_DGFX(dev_priv)) + if (display->platform.dgfx) return false; - if (DISPLAY_VER(dev_priv) >= 13) + if (DISPLAY_VER(display) >= 13) return phy >= PHY_F && phy <= PHY_I; - else if (IS_TIGERLAKE(dev_priv)) + else if (display->platform.tigerlake) return phy >= PHY_D && phy <= PHY_I; - else if (IS_ICELAKE(dev_priv)) + else if (display->platform.icelake) return phy >= PHY_C && phy <= PHY_F; return false; } /* Prefer intel_encoder_is_snps() */ -bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy) +bool intel_phy_is_snps(struct intel_display *display, enum phy phy) { /* * For DG2, and for DG2 only, all four "combo" ports and the TC1 port * (PHY E) use Synopsis PHYs. See intel_phy_is_tc(). */ - return IS_DG2(dev_priv) && phy > PHY_NONE && phy <= PHY_E; + return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E; } /* Prefer intel_encoder_to_phy() */ -enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) +enum phy intel_port_to_phy(struct intel_display *display, enum port port) { - if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD) + if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) return PHY_D + port - PORT_D_XELPD; - else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1) + else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1) return PHY_F + port - PORT_TC1; - else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1) + else if (display->platform.alderlake_s && port >= PORT_TC1) return PHY_B + port - PORT_TC1; - else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1) + else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1) return PHY_C + port - PORT_TC1; - else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && + else if ((display->platform.jasperlake || display->platform.elkhartlake) && port == PORT_D) return PHY_A; @@ -2062,12 +1883,12 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port) } /* Prefer intel_encoder_to_tc() */ -enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) +enum tc_port intel_port_to_tc(struct intel_display *display, enum port port) { - if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) + if (!intel_phy_is_tc(display, intel_port_to_phy(display, port))) return TC_PORT_NONE; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) return TC_PORT_1 + port - PORT_TC1; else return TC_PORT_1 + port - PORT_C; @@ -2075,55 +1896,55 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port) enum phy intel_encoder_to_phy(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); - return intel_port_to_phy(i915, encoder->port); + return intel_port_to_phy(display, encoder->port); } bool intel_encoder_is_combo(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); - return intel_phy_is_combo(i915, intel_encoder_to_phy(encoder)); + return intel_phy_is_combo(display, intel_encoder_to_phy(encoder)); } bool intel_encoder_is_snps(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); - return intel_phy_is_snps(i915, intel_encoder_to_phy(encoder)); + return intel_phy_is_snps(display, intel_encoder_to_phy(encoder)); } bool intel_encoder_is_tc(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); - return intel_phy_is_tc(i915, intel_encoder_to_phy(encoder)); + return intel_phy_is_tc(display, intel_encoder_to_phy(encoder)); } enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); - return intel_port_to_tc(i915, encoder->port); + return intel_port_to_tc(display, encoder->port); } enum intel_display_power_domain intel_aux_power_domain(struct intel_digital_port *dig_port) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); if (intel_tc_port_in_tbt_alt_mode(dig_port)) - return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch); + return intel_display_power_tbt_aux_domain(display, dig_port->aux_ch); - return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); + return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch); } static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, struct intel_power_domain_mask *mask) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; struct drm_encoder *encoder; enum pipe pipe = crtc->pipe; @@ -2139,14 +1960,14 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, crtc_state->pch_pfit.force_thru) set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits); - drm_for_each_encoder_mask(encoder, &dev_priv->drm, + drm_for_each_encoder_mask(encoder, display->drm, crtc_state->uapi.encoder_mask) { struct intel_encoder *intel_encoder = to_intel_encoder(encoder); set_bit(intel_encoder->power_domain, mask->bits); } - if (HAS_DDI(dev_priv) && crtc_state->has_audio) + if (HAS_DDI(display) && crtc_state->has_audio) set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits); if (crtc_state->shared_dpll) @@ -2159,8 +1980,8 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, struct intel_power_domain_mask *old_domains) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum intel_display_power_domain domain; struct intel_power_domain_mask domains, new_domains; @@ -2176,7 +1997,7 @@ void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, POWER_DOMAIN_NUM); for_each_power_domain(domain, &new_domains) - intel_display_power_get_in_set(dev_priv, + intel_display_power_get_in_set(display, &crtc->enabled_power_domains, domain); } @@ -2184,7 +2005,9 @@ void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, struct intel_power_domain_mask *domains) { - intel_display_power_put_mask_in_set(to_i915(crtc->base.dev), + struct intel_display *display = to_intel_display(crtc); + + intel_display_power_put_mask_in_set(display, &crtc->enabled_power_domains, domains); } @@ -2209,33 +2032,33 @@ static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_st static void valleyview_crtc_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(crtc); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (drm_WARN_ON(&dev_priv->drm, crtc->active)) + if (drm_WARN_ON(display->drm, crtc->active)) return; i9xx_configure_cpu_transcoder(new_crtc_state); intel_set_pipe_src_size(new_crtc_state); - intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0); + intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), 0); - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { - intel_de_write(dev_priv, CHV_BLEND(dev_priv, pipe), + if (display->platform.cherryview && pipe == PIPE_B) { + intel_de_write(display, CHV_BLEND(display, pipe), CHV_BLEND_LEGACY); - intel_de_write(dev_priv, CHV_CANVAS(dev_priv, pipe), 0); + intel_de_write(display, CHV_CANVAS(display, pipe), 0); } crtc->active = true; - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); + intel_set_cpu_fifo_underrun_reporting(display, pipe, true); intel_encoders_pre_pll_enable(state, crtc); - if (IS_CHERRYVIEW(dev_priv)) + if (display->platform.cherryview) chv_enable_pll(new_crtc_state); else vlv_enable_pll(new_crtc_state); @@ -2257,12 +2080,13 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state, static void i9xx_crtc_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(crtc); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (drm_WARN_ON(&dev_priv->drm, crtc->active)) + if (drm_WARN_ON(display->drm, crtc->active)) return; i9xx_configure_cpu_transcoder(new_crtc_state); @@ -2271,8 +2095,8 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state, crtc->active = true; - if (DISPLAY_VER(dev_priv) != 2) - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); + if (DISPLAY_VER(display) != 2) + intel_set_cpu_fifo_underrun_reporting(display, pipe, true); intel_encoders_pre_enable(state, crtc); @@ -2291,25 +2115,10 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state, intel_encoders_enable(state, crtc); /* prevents spurious underruns */ - if (DISPLAY_VER(dev_priv) == 2) + if (DISPLAY_VER(display) == 2) intel_crtc_wait_for_next_vblank(crtc); } -static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - - if (!old_crtc_state->gmch_pfit.control) - return; - - assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); - - drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", - intel_de_read(dev_priv, PFIT_CONTROL(dev_priv))); - intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), 0); -} - static void i9xx_crtc_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -2323,7 +2132,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state, * On gen2 planes are double buffered but the pipe isn't, so we must * wait for planes to fully turn off before disabling the pipe. */ - if (DISPLAY_VER(dev_priv) == 2) + if (DISPLAY_VER(display) == 2) intel_crtc_wait_for_next_vblank(crtc); intel_encoders_disable(state, crtc); @@ -2337,9 +2146,9 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state, intel_encoders_post_disable(state, crtc); if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { - if (IS_CHERRYVIEW(dev_priv)) + if (display->platform.cherryview) chv_disable_pll(dev_priv, pipe); - else if (IS_VALLEYVIEW(dev_priv)) + else if (display->platform.valleyview) vlv_disable_pll(dev_priv, pipe); else i9xx_disable_pll(old_crtc_state); @@ -2347,14 +2156,14 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state, intel_encoders_post_pll_disable(state, crtc); - if (DISPLAY_VER(dev_priv) != 2) - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); + if (DISPLAY_VER(display) != 2) + intel_set_cpu_fifo_underrun_reporting(display, pipe, false); - if (!dev_priv->display.funcs.wm->initial_watermarks) + if (!display->funcs.wm->initial_watermarks) intel_update_watermarks(dev_priv); /* clock the pipe down to 640x480@60 to potentially save power */ - if (IS_I830(dev_priv)) + if (display->platform.i830) i830_enable_pipe(display, pipe); } @@ -2368,11 +2177,11 @@ void intel_encoder_destroy(struct drm_encoder *encoder) static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) { - const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); /* GDG double wide on either pipe, otherwise pipe A only */ - return HAS_DOUBLE_WIDE(dev_priv) && - (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); + return HAS_DOUBLE_WIDE(display) && + (crtc->pipe == PIPE_A || display->platform.i915g); } static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) @@ -2419,9 +2228,9 @@ static void intel_mode_from_crtc_timings(struct drm_display_mode *mode, static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); - if (HAS_GMCH(dev_priv)) + if (HAS_GMCH(display)) /* FIXME calculate proper pipe pixel rate for GMCH pfit */ crtc_state->pixel_rate = crtc_state->hw.pipe_mode.crtc_clock; @@ -2532,6 +2341,7 @@ static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); @@ -2545,7 +2355,7 @@ static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) */ if (drm_rect_width(&crtc_state->pipe_src) & 1) { if (crtc_state->double_wide) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n", crtc->base.base.id, crtc->base.name); return -EINVAL; @@ -2553,7 +2363,7 @@ static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && intel_is_dual_link_lvds(i915)) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n", crtc->base.base.id, crtc->base.name); return -EINVAL; @@ -2565,11 +2375,11 @@ static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode; - int clock_limit = i915->display.cdclk.max_dotclk_freq; + int clock_limit = display->cdclk.max_dotclk_freq; /* * Start with the adjusted_mode crtc timings, which @@ -2584,8 +2394,8 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) intel_joiner_adjust_timings(crtc_state, pipe_mode); intel_mode_from_crtc_timings(pipe_mode, pipe_mode); - if (DISPLAY_VER(i915) < 4) { - clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10; + if (DISPLAY_VER(display) < 4) { + clock_limit = display->cdclk.max_cdclk_freq * 9 / 10; /* * Enable double wide mode when the dot clock @@ -2593,13 +2403,13 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) */ if (intel_crtc_supports_double_wide(crtc) && pipe_mode->crtc_clock > clock_limit) { - clock_limit = i915->display.cdclk.max_dotclk_freq; + clock_limit = display->cdclk.max_dotclk_freq; crtc_state->double_wide = true; } } if (pipe_mode->crtc_clock > clock_limit) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", crtc->base.base.id, crtc->base.name, pipe_mode->crtc_clock, clock_limit, @@ -2610,28 +2420,63 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) return 0; } -static bool intel_crtc_needs_wa_14015401596(struct intel_crtc_state *crtc_state) +static bool intel_crtc_needs_wa_14015401596(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; return intel_vrr_possible(crtc_state) && crtc_state->has_psr && - adjusted_mode->crtc_vblank_start == adjusted_mode->crtc_vdisplay && IS_DISPLAY_VER(display, 13, 14); } -static int intel_crtc_compute_config(struct intel_atomic_state *state, - struct intel_crtc *crtc) +static int intel_crtc_vblank_delay(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + int vblank_delay = 0; + + if (!HAS_DSB(display)) + return 0; + + /* Wa_14015401596 */ + if (intel_crtc_needs_wa_14015401596(crtc_state)) + vblank_delay = max(vblank_delay, 1); + + return vblank_delay; +} + +static int intel_crtc_compute_vblank_delay(struct intel_atomic_state *state, + struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + int vblank_delay, max_vblank_delay; + + vblank_delay = intel_crtc_vblank_delay(crtc_state); + max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1; + + if (vblank_delay > max_vblank_delay) { + drm_dbg_kms(display->drm, "[CRTC:%d:%s] vblank delay (%d) exceeds max (%d)\n", + crtc->base.base.id, crtc->base.name, vblank_delay, max_vblank_delay); + return -EINVAL; + } + + adjusted_mode->crtc_vblank_start += vblank_delay; + + return 0; +} + +static int intel_crtc_compute_config(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); int ret; - /* Wa_14015401596 */ - if (intel_crtc_needs_wa_14015401596(crtc_state)) - adjusted_mode->crtc_vblank_start += 1; + ret = intel_crtc_compute_vblank_delay(state, crtc); + if (ret) + return ret; ret = intel_dpll_crtc_compute_clock(state, crtc); if (ret) @@ -2703,8 +2548,10 @@ intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes, 0x80000); } -void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) +void intel_panel_sanitize_ssc(struct intel_display *display) { + struct drm_i915_private *dev_priv = to_i915(display->drm); + /* * There may be no VBT; and if the BIOS enabled SSC we can * just keep using it to avoid unnecessary flicker. Whereas if the @@ -2712,16 +2559,16 @@ void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) * indicates as much. */ if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { - bool bios_lvds_use_ssc = intel_de_read(dev_priv, + bool bios_lvds_use_ssc = intel_de_read(display, PCH_DREF_CONTROL) & DREF_SSC1_ENABLE; - if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) { - drm_dbg_kms(&dev_priv->drm, + if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) { + drm_dbg_kms(display->drm, "SSC %s by BIOS, overriding VBT which says %s\n", str_enabled_disabled(bios_lvds_use_ssc), - str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc)); - dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc; + str_enabled_disabled(display->vbt.lvds_use_ssc)); + display->vbt.lvds_use_ssc = bios_lvds_use_ssc; } } } @@ -2733,45 +2580,45 @@ void intel_zero_m_n(struct intel_link_m_n *m_n) m_n->tu = 1; } -void intel_set_m_n(struct drm_i915_private *i915, +void intel_set_m_n(struct intel_display *display, const struct intel_link_m_n *m_n, i915_reg_t data_m_reg, i915_reg_t data_n_reg, i915_reg_t link_m_reg, i915_reg_t link_n_reg) { - intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); - intel_de_write(i915, data_n_reg, m_n->data_n); - intel_de_write(i915, link_m_reg, m_n->link_m); + intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); + intel_de_write(display, data_n_reg, m_n->data_n); + intel_de_write(display, link_m_reg, m_n->link_m); /* * On BDW+ writing LINK_N arms the double buffered update * of all the M/N registers, so it must be written last. */ - intel_de_write(i915, link_n_reg, m_n->link_n); + intel_de_write(display, link_n_reg, m_n->link_n); } -bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, +bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, enum transcoder transcoder) { - if (IS_HASWELL(dev_priv)) + if (display->platform.haswell) return transcoder == TRANSCODER_EDP; - return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv); + return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview; } void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, enum transcoder transcoder, const struct intel_link_m_n *m_n) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - if (DISPLAY_VER(dev_priv) >= 5) - intel_set_m_n(dev_priv, m_n, - PIPE_DATA_M1(dev_priv, transcoder), - PIPE_DATA_N1(dev_priv, transcoder), - PIPE_LINK_M1(dev_priv, transcoder), - PIPE_LINK_N1(dev_priv, transcoder)); + if (DISPLAY_VER(display) >= 5) + intel_set_m_n(display, m_n, + PIPE_DATA_M1(display, transcoder), + PIPE_DATA_N1(display, transcoder), + PIPE_LINK_M1(display, transcoder), + PIPE_LINK_N1(display, transcoder)); else - intel_set_m_n(dev_priv, m_n, + intel_set_m_n(display, m_n, PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); } @@ -2780,28 +2627,30 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, enum transcoder transcoder, const struct intel_link_m_n *m_n) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); - if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) + if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) return; - intel_set_m_n(dev_priv, m_n, - PIPE_DATA_M2(dev_priv, transcoder), - PIPE_DATA_N2(dev_priv, transcoder), - PIPE_LINK_M2(dev_priv, transcoder), - PIPE_LINK_N2(dev_priv, transcoder)); + intel_set_m_n(display, m_n, + PIPE_DATA_M2(display, transcoder), + PIPE_DATA_N2(display, transcoder), + PIPE_LINK_M2(display, transcoder), + PIPE_LINK_N2(display, transcoder)); } static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; int vsyncshift = 0; + drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); + /* We need to be careful not to changed the adjusted mode, for otherwise * the hw state checker will get angry at the mismatch. */ crtc_vdisplay = adjusted_mode->crtc_vdisplay; @@ -2827,9 +2676,9 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta * VBLANK_START no longer works on ADL+, instead we must use * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. */ - if (DISPLAY_VER(dev_priv) >= 13) { - intel_de_write(dev_priv, - TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder), + if (DISPLAY_VER(display) >= 13) { + intel_de_write(display, + TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder), crtc_vblank_start - crtc_vdisplay); /* @@ -2839,28 +2688,28 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta crtc_vblank_start = 1; } - if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write(dev_priv, - TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder), + if (DISPLAY_VER(display) >= 4) + intel_de_write(display, + TRANS_VSYNCSHIFT(display, cpu_transcoder), vsyncshift); - intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), HACTIVE(adjusted_mode->crtc_hdisplay - 1) | HTOTAL(adjusted_mode->crtc_htotal - 1)); - intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); - intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); - intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); - intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), VBLANK_START(crtc_vblank_start - 1) | VBLANK_END(crtc_vblank_end - 1)); - intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); @@ -2868,48 +2717,65 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is * documented on the DDI_FUNC_CTL register description, EDP Input Select * bits. */ - if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && + if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP && (pipe == PIPE_B || pipe == PIPE_C)) - intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, pipe), + intel_de_write(display, TRANS_VTOTAL(display, pipe), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); } static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end; + drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)); + crtc_vdisplay = adjusted_mode->crtc_vdisplay; crtc_vtotal = adjusted_mode->crtc_vtotal; crtc_vblank_start = adjusted_mode->crtc_vblank_start; crtc_vblank_end = adjusted_mode->crtc_vblank_end; - drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE); + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { + /* the chip adds 2 halflines automatically */ + crtc_vtotal -= 1; + crtc_vblank_end -= 1; + } + + if (DISPLAY_VER(display) >= 13) { + intel_de_write(display, + TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder), + crtc_vblank_start - crtc_vdisplay); + + /* + * VBLANK_START not used by hw, just clear it + * to make it stand out in register dumps. + */ + crtc_vblank_start = 1; + } /* * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode. * But let's write it anyway to keep the state checker happy. */ - intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), VBLANK_START(crtc_vblank_start - 1) | VBLANK_END(crtc_vblank_end - 1)); /* * The double buffer latch point for TRANS_VTOTAL * is the transcoder's undelayed vblank. */ - intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); } static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); int width = drm_rect_width(&crtc_state->pipe_src); int height = drm_rect_height(&crtc_state->pipe_src); enum pipe pipe = crtc->pipe; @@ -2917,63 +2783,62 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) /* pipesrc controls the size that is scaled from, which should * always be the user's requested size. */ - intel_de_write(dev_priv, PIPESRC(dev_priv, pipe), + intel_de_write(display, PIPESRC(display, pipe), PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); } static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (DISPLAY_VER(dev_priv) == 2) + if (DISPLAY_VER(display) == 2) return false; - if (DISPLAY_VER(dev_priv) >= 9 || - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) - return intel_de_read(dev_priv, - TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; + if (DISPLAY_VER(display) >= 9 || + display->platform.broadwell || display->platform.haswell) + return intel_de_read(display, + TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; else - return intel_de_read(dev_priv, - TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; + return intel_de_read(display, + TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; } static void intel_get_transcoder_timings(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(crtc); enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; u32 tmp; - tmp = intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder)); + tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder)); adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; if (!transcoder_is_dsi(cpu_transcoder)) { - tmp = intel_de_read(dev_priv, - TRANS_HBLANK(dev_priv, cpu_transcoder)); + tmp = intel_de_read(display, + TRANS_HBLANK(display, cpu_transcoder)); adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; } - tmp = intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder)); + tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder)); adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; - tmp = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)); + tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder)); adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; /* FIXME TGL+ DSI transcoders have this! */ if (!transcoder_is_dsi(cpu_transcoder)) { - tmp = intel_de_read(dev_priv, - TRANS_VBLANK(dev_priv, cpu_transcoder)); + tmp = intel_de_read(display, + TRANS_VBLANK(display, cpu_transcoder)); adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; } - tmp = intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder)); + tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder)); adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; @@ -2983,11 +2848,11 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, adjusted_mode->crtc_vblank_end += 1; } - if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder)) + if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(cpu_transcoder)) adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay + - intel_de_read(dev_priv, - TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder)); + intel_de_read(display, + TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)); } static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) @@ -3010,11 +2875,10 @@ static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) static void intel_get_pipe_src_size(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(crtc); u32 tmp; - tmp = intel_de_read(dev_priv, PIPESRC(dev_priv, crtc->pipe)); + tmp = intel_de_read(display, PIPESRC(display, crtc->pipe)); drm_rect_init(&pipe_config->pipe_src, 0, 0, REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, @@ -3025,8 +2889,7 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc, void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 val = 0; @@ -3035,15 +2898,15 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) * - During modeset the pipe is still disabled and must remain so * - During fastset the pipe is already enabled and must remain so */ - if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state)) + if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state)) val |= TRANSCONF_ENABLE; if (crtc_state->double_wide) val |= TRANSCONF_DOUBLE_WIDE; /* only g4x and later have fancy bpc/dither controls */ - if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || - IS_CHERRYVIEW(dev_priv)) { + if (display->platform.g4x || display->platform.valleyview || + display->platform.cherryview) { /* Bspec claims that we can't use dithering for 30bpp pipes. */ if (crtc_state->dither && crtc_state->pipe_bpp != 30) val |= TRANSCONF_DITHER_EN | @@ -3067,7 +2930,7 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) } if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { - if (DISPLAY_VER(dev_priv) < 4 || + if (DISPLAY_VER(display) < 4 || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION; else @@ -3076,8 +2939,8 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) val |= TRANSCONF_INTERLACE_PROGRESSIVE; } - if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && - crtc_state->limited_color_range) + if ((display->platform.valleyview || display->platform.cherryview) && + crtc_state->limited_color_range) val |= TRANSCONF_COLOR_RANGE_SELECT; val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); @@ -3087,54 +2950,17 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); - intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); - intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); -} - -static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) -{ - if (IS_I830(dev_priv)) - return false; - - return DISPLAY_VER(dev_priv) >= 4 || - IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); -} - -static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum pipe pipe; - u32 tmp; - - if (!i9xx_has_pfit(dev_priv)) - return; - - tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)); - if (!(tmp & PFIT_ENABLE)) - return; - - /* Check whether the pfit is attached to our pipe. */ - if (DISPLAY_VER(dev_priv) >= 4) - pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp); - else - pipe = PIPE_B; - - if (pipe != crtc->pipe) - return; - - crtc_state->gmch_pfit.control = tmp; - crtc_state->gmch_pfit.pgm_ratios = - intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv)); + intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); + intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); } static enum intel_output_format bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); u32 tmp; - tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); + tmp = intel_de_read(display, PIPE_MISC(crtc->pipe)); if (tmp & PIPE_MISC_YUV420_ENABLE) { /* @@ -3142,8 +2968,8 @@ bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) * For xe3_lpd+ this is implied in YUV420 Enable bit. * Ensure the same for prior platforms in YUV420 Mode bit. */ - if (DISPLAY_VER(dev_priv) < 30) - drm_WARN_ON(&dev_priv->drm, + if (DISPLAY_VER(display) < 30) + drm_WARN_ON(display->drm, (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); return INTEL_OUTPUT_FORMAT_YCBCR420; @@ -3157,31 +2983,29 @@ bdw_get_pipe_misc_output_format(struct intel_crtc *crtc) static bool i9xx_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); enum intel_display_power_domain power_domain; + enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; intel_wakeref_t wakeref; + bool ret = false; u32 tmp; - bool ret; power_domain = POWER_DOMAIN_PIPE(crtc->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; - pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; - pipe_config->sink_format = pipe_config->output_format; - pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; - pipe_config->shared_dpll = NULL; - - ret = false; - - tmp = intel_de_read(dev_priv, - TRANSCONF(dev_priv, pipe_config->cpu_transcoder)); + tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); if (!(tmp & TRANSCONF_ENABLE)) goto out; - if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || - IS_CHERRYVIEW(dev_priv)) { + pipe_config->cpu_transcoder = cpu_transcoder; + + pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; + pipe_config->sink_format = pipe_config->output_format; + + if (display->platform.g4x || display->platform.valleyview || + display->platform.cherryview) { switch (tmp & TRANSCONF_BPC_MASK) { case TRANSCONF_BPC_6: pipe_config->pipe_bpp = 18; @@ -3198,7 +3022,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, } } - if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + if ((display->platform.valleyview || display->platform.cherryview) && (tmp & TRANSCONF_COLOR_RANGE_SELECT)) pipe_config->limited_color_range = true; @@ -3206,29 +3030,29 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; - if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + if ((display->platform.valleyview || display->platform.cherryview) && (tmp & TRANSCONF_WGC_ENABLE)) pipe_config->wgc_enable = true; intel_color_get_config(pipe_config); - if (HAS_DOUBLE_WIDE(dev_priv)) + if (HAS_DOUBLE_WIDE(display)) pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; intel_get_transcoder_timings(crtc, pipe_config); intel_get_pipe_src_size(crtc, pipe_config); - i9xx_get_pfit_config(pipe_config); + i9xx_pfit_get_config(pipe_config); i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state); - if (DISPLAY_VER(dev_priv) >= 4) { + if (DISPLAY_VER(display) >= 4) { tmp = pipe_config->dpll_hw_state.i9xx.dpll_md; pipe_config->pixel_multiplier = ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; - } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || - IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { + } else if (display->platform.i945g || display->platform.i945gm || + display->platform.g33 || display->platform.pineview) { tmp = pipe_config->dpll_hw_state.i9xx.dpll; pipe_config->pixel_multiplier = ((tmp & SDVO_MULTIPLIER_MASK) @@ -3240,9 +3064,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, pipe_config->pixel_multiplier = 1; } - if (IS_CHERRYVIEW(dev_priv)) + if (display->platform.cherryview) chv_crtc_clock_get(pipe_config); - else if (IS_VALLEYVIEW(dev_priv)) + else if (display->platform.valleyview) vlv_crtc_clock_get(pipe_config); else i9xx_crtc_clock_get(pipe_config); @@ -3258,15 +3082,14 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, ret = true; out: - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 val = 0; @@ -3308,7 +3131,7 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) * This would end up with an odd purple hue over * the entire display. Make sure we don't do it. */ - drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && + drm_WARN_ON(display->drm, crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); if (crtc_state->limited_color_range && @@ -3323,14 +3146,13 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); - intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); - intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); + intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); + intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); } static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 val = 0; @@ -3341,7 +3163,7 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) if (!intel_crtc_needs_modeset(crtc_state)) val |= TRANSCONF_ENABLE; - if (IS_HASWELL(dev_priv) && crtc_state->dither) + if (display->platform.haswell && crtc_state->dither) val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP; if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) @@ -3349,20 +3171,19 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) else val |= TRANSCONF_INTERLACE_PF_PD_ILK; - if (IS_HASWELL(dev_priv) && + if (display->platform.haswell && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; - intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); - intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); + intel_de_write(display, TRANSCONF(display, cpu_transcoder), val); + intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder)); } static void bdw_set_pipe_misc(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_display *display = to_intel_display(crtc->base.dev); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 val = 0; switch (crtc_state->pipe_bpp) { @@ -3377,7 +3198,7 @@ static void bdw_set_pipe_misc(struct intel_dsb *dsb, break; case 36: /* Port output 12BPC defined for ADLP+ */ - if (DISPLAY_VER(dev_priv) >= 13) + if (DISPLAY_VER(display) >= 13) val |= PIPE_MISC_BPC_12_ADLP; break; default: @@ -3396,14 +3217,14 @@ static void bdw_set_pipe_misc(struct intel_dsb *dsb, val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE : PIPE_MISC_YUV420_ENABLE | PIPE_MISC_YUV420_MODE_FULL_BLEND; - if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) + if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state)) val |= PIPE_MISC_HDR_MODE_PRECISION; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; /* allow PSR with sprite enabled */ - if (IS_BROADWELL(dev_priv)) + if (display->platform.broadwell) val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE; intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val); @@ -3411,10 +3232,10 @@ static void bdw_set_pipe_misc(struct intel_dsb *dsb, int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); u32 tmp; - tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); + tmp = intel_de_read(display, PIPE_MISC(crtc->pipe)); switch (tmp & PIPE_MISC_BPC_MASK) { case PIPE_MISC_BPC_6: @@ -3434,7 +3255,7 @@ int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc) * MIPI DSI HW readout. */ case PIPE_MISC_BPC_12_ADLP: - if (DISPLAY_VER(dev_priv) >= 13) + if (DISPLAY_VER(display) >= 13) return 36; fallthrough; default: @@ -3454,33 +3275,33 @@ int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) return DIV_ROUND_UP(bps, link_bw * 8); } -void intel_get_m_n(struct drm_i915_private *i915, +void intel_get_m_n(struct intel_display *display, struct intel_link_m_n *m_n, i915_reg_t data_m_reg, i915_reg_t data_n_reg, i915_reg_t link_m_reg, i915_reg_t link_n_reg) { - m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK; - m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK; - m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK; - m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK; - m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1; + m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK; + m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK; + m_n->data_m = intel_de_read(display, data_m_reg) & DATA_LINK_M_N_MASK; + m_n->data_n = intel_de_read(display, data_n_reg) & DATA_LINK_M_N_MASK; + m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1; } void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, enum transcoder transcoder, struct intel_link_m_n *m_n) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - if (DISPLAY_VER(dev_priv) >= 5) - intel_get_m_n(dev_priv, m_n, - PIPE_DATA_M1(dev_priv, transcoder), - PIPE_DATA_N1(dev_priv, transcoder), - PIPE_LINK_M1(dev_priv, transcoder), - PIPE_LINK_N1(dev_priv, transcoder)); + if (DISPLAY_VER(display) >= 5) + intel_get_m_n(display, m_n, + PIPE_DATA_M1(display, transcoder), + PIPE_DATA_N1(display, transcoder), + PIPE_LINK_M1(display, transcoder), + PIPE_LINK_N1(display, transcoder)); else - intel_get_m_n(dev_priv, m_n, + intel_get_m_n(display, m_n, PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe)); } @@ -3489,77 +3310,39 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, enum transcoder transcoder, struct intel_link_m_n *m_n) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - - if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder)) - return; - - intel_get_m_n(dev_priv, m_n, - PIPE_DATA_M2(dev_priv, transcoder), - PIPE_DATA_N2(dev_priv, transcoder), - PIPE_LINK_M2(dev_priv, transcoder), - PIPE_LINK_N2(dev_priv, transcoder)); -} - -static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 ctl, pos, size; - enum pipe pipe; + struct intel_display *display = to_intel_display(crtc); - ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); - if ((ctl & PF_ENABLE) == 0) + if (!intel_cpu_transcoder_has_m2_n2(display, transcoder)) return; - if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) - pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl); - else - pipe = crtc->pipe; - - crtc_state->pch_pfit.enabled = true; - - pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)); - size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)); - - drm_rect_init(&crtc_state->pch_pfit.dst, - REG_FIELD_GET(PF_WIN_XPOS_MASK, pos), - REG_FIELD_GET(PF_WIN_YPOS_MASK, pos), - REG_FIELD_GET(PF_WIN_XSIZE_MASK, size), - REG_FIELD_GET(PF_WIN_YSIZE_MASK, size)); - - /* - * We currently do not free assignements of panel fitters on - * ivb/hsw (since we don't use the higher upscaling modes which - * differentiates them) so just WARN about this case for now. - */ - drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe); + intel_get_m_n(display, m_n, + PIPE_DATA_M2(display, transcoder), + PIPE_DATA_N2(display, transcoder), + PIPE_LINK_M2(display, transcoder), + PIPE_LINK_N2(display, transcoder)); } static bool ilk_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(crtc); enum intel_display_power_domain power_domain; + enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; intel_wakeref_t wakeref; + bool ret = false; u32 tmp; - bool ret; power_domain = POWER_DOMAIN_PIPE(crtc->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; - pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; - pipe_config->shared_dpll = NULL; - - ret = false; - tmp = intel_de_read(dev_priv, - TRANSCONF(dev_priv, pipe_config->cpu_transcoder)); + tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder)); if (!(tmp & TRANSCONF_ENABLE)) goto out; + pipe_config->cpu_transcoder = cpu_transcoder; + switch (tmp & TRANSCONF_BPC_MASK) { case TRANSCONF_BPC_6: pipe_config->pipe_bpp = 18; @@ -3607,31 +3390,31 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, intel_get_transcoder_timings(crtc, pipe_config); intel_get_pipe_src_size(crtc, pipe_config); - ilk_get_pfit_config(pipe_config); + ilk_pfit_get_config(pipe_config); ret = true; out: - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } -static u8 joiner_pipes(struct drm_i915_private *i915) +static u8 joiner_pipes(struct intel_display *display) { u8 pipes; - if (DISPLAY_VER(i915) >= 12) + if (DISPLAY_VER(display) >= 12) pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); - else if (DISPLAY_VER(i915) >= 11) + else if (DISPLAY_VER(display) >= 11) pipes = BIT(PIPE_B) | BIT(PIPE_C); else pipes = 0; - return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask; + return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask; } -static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, +static bool transcoder_ddi_func_is_enabled(struct intel_display *display, enum transcoder cpu_transcoder) { enum intel_display_power_domain power_domain; @@ -3640,9 +3423,9 @@ static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); - with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) - tmp = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); + with_intel_display_power_if_enabled(display, power_domain, wakeref) + tmp = intel_de_read(display, + TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); return tmp & TRANS_DDI_FUNC_ENABLE; } @@ -3650,7 +3433,6 @@ static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, static void enabled_uncompressed_joiner_pipes(struct intel_display *display, u8 *primary_pipes, u8 *secondary_pipes) { - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_crtc *crtc; *primary_pipes = 0; @@ -3659,14 +3441,14 @@ static void enabled_uncompressed_joiner_pipes(struct intel_display *display, if (!HAS_UNCOMPRESSED_JOINER(display)) return; - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, - joiner_pipes(i915)) { + for_each_intel_crtc_in_pipe_mask(display->drm, crtc, + joiner_pipes(display)) { enum intel_display_power_domain power_domain; enum pipe pipe = crtc->pipe; intel_wakeref_t wakeref; power_domain = POWER_DOMAIN_PIPE(pipe); - with_intel_display_power_if_enabled(i915, power_domain, wakeref) { + with_intel_display_power_if_enabled(display, power_domain, wakeref) { u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); if (tmp & UNCOMPRESSED_JOINER_PRIMARY) @@ -3680,7 +3462,6 @@ static void enabled_uncompressed_joiner_pipes(struct intel_display *display, static void enabled_bigjoiner_pipes(struct intel_display *display, u8 *primary_pipes, u8 *secondary_pipes) { - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_crtc *crtc; *primary_pipes = 0; @@ -3689,14 +3470,14 @@ static void enabled_bigjoiner_pipes(struct intel_display *display, if (!HAS_BIGJOINER(display)) return; - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, - joiner_pipes(i915)) { + for_each_intel_crtc_in_pipe_mask(display->drm, crtc, + joiner_pipes(display)) { enum intel_display_power_domain power_domain; enum pipe pipe = crtc->pipe; intel_wakeref_t wakeref; power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); - with_intel_display_power_if_enabled(i915, power_domain, wakeref) { + with_intel_display_power_if_enabled(display, power_domain, wakeref) { u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); if (!(tmp & BIG_JOINER_ENABLE)) @@ -3748,10 +3529,9 @@ static u8 fixup_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes, return ultrajoiner_secondary_pipes | ultrajoiner_primary_pipes << 3; } -static void enabled_ultrajoiner_pipes(struct drm_i915_private *i915, +static void enabled_ultrajoiner_pipes(struct intel_display *display, u8 *primary_pipes, u8 *secondary_pipes) { - struct intel_display *display = &i915->display; struct intel_crtc *crtc; *primary_pipes = 0; @@ -3760,15 +3540,15 @@ static void enabled_ultrajoiner_pipes(struct drm_i915_private *i915, if (!HAS_ULTRAJOINER(display)) return; - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, - joiner_pipes(i915)) { + for_each_intel_crtc_in_pipe_mask(display->drm, crtc, + joiner_pipes(display)) { enum intel_display_power_domain power_domain; enum pipe pipe = crtc->pipe; intel_wakeref_t wakeref; power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); - with_intel_display_power_if_enabled(i915, power_domain, wakeref) { - u32 tmp = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)); + with_intel_display_power_if_enabled(display, power_domain, wakeref) { + u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); if (!(tmp & ULTRA_JOINER_ENABLE)) continue; @@ -3781,11 +3561,10 @@ static void enabled_ultrajoiner_pipes(struct drm_i915_private *i915, } } -static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, +static void enabled_joiner_pipes(struct intel_display *display, enum pipe pipe, u8 *primary_pipe, u8 *secondary_pipes) { - struct intel_display *display = to_intel_display(&dev_priv->drm); u8 primary_ultrajoiner_pipes; u8 primary_uncompressed_joiner_pipes, primary_bigjoiner_pipes; u8 secondary_ultrajoiner_pipes; @@ -3793,21 +3572,21 @@ static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, u8 ultrajoiner_pipes; u8 uncompressed_joiner_pipes, bigjoiner_pipes; - enabled_ultrajoiner_pipes(dev_priv, &primary_ultrajoiner_pipes, + enabled_ultrajoiner_pipes(display, &primary_ultrajoiner_pipes, &secondary_ultrajoiner_pipes); /* * For some strange reason the last pipe in the set of four * shouldn't have ultrajoiner enable bit set in hardware. * Set the bit anyway to make life easier. */ - drm_WARN_ON(&dev_priv->drm, + drm_WARN_ON(display->drm, expected_secondary_pipes(primary_ultrajoiner_pipes, 3) != secondary_ultrajoiner_pipes); secondary_ultrajoiner_pipes = fixup_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes, secondary_ultrajoiner_pipes); - drm_WARN_ON(&dev_priv->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0); + drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0); enabled_uncompressed_joiner_pipes(display, &primary_uncompressed_joiner_pipes, &secondary_uncompressed_joiner_pipes); @@ -3901,11 +3680,11 @@ static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, } } -static u8 hsw_panel_transcoders(struct drm_i915_private *i915) +static u8 hsw_panel_transcoders(struct intel_display *display) { u8 panel_transcoder_mask = BIT(TRANSCODER_EDP); - if (DISPLAY_VER(i915) >= 11) + if (DISPLAY_VER(display) >= 11) panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1); return panel_transcoder_mask; @@ -3913,9 +3692,8 @@ static u8 hsw_panel_transcoders(struct drm_i915_private *i915) static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); - u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); + struct intel_display *display = to_intel_display(crtc); + u8 panel_transcoder_mask = hsw_panel_transcoders(display); enum transcoder cpu_transcoder; u8 primary_pipe, secondary_pipes; u8 enabled_transcoders = 0; @@ -3924,7 +3702,7 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) * XXX: Do intel_display_power_get_if_enabled before reading this (for * consistency and less surprising code; it's in always on power). */ - for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, + for_each_cpu_transcoder_masked(display, cpu_transcoder, panel_transcoder_mask) { enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; @@ -3932,16 +3710,16 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) u32 tmp = 0; power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); - with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) - tmp = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); + with_intel_display_power_if_enabled(display, power_domain, wakeref) + tmp = intel_de_read(display, + TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); if (!(tmp & TRANS_DDI_FUNC_ENABLE)) continue; switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { default: - drm_WARN(dev, 1, + drm_WARN(display->drm, 1, "unknown pipe linked to transcoder %s\n", transcoder_name(cpu_transcoder)); fallthrough; @@ -3966,14 +3744,14 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) /* single pipe or joiner primary */ cpu_transcoder = (enum transcoder) crtc->pipe; - if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) + if (transcoder_ddi_func_is_enabled(display, cpu_transcoder)) enabled_transcoders |= BIT(cpu_transcoder); /* joiner secondary -> consider the primary pipe's transcoder as well */ - enabled_joiner_pipes(dev_priv, crtc->pipe, &primary_pipe, &secondary_pipes); + enabled_joiner_pipes(display, crtc->pipe, &primary_pipe, &secondary_pipes); if (secondary_pipes & BIT(crtc->pipe)) { cpu_transcoder = (enum transcoder)ffs(primary_pipe) - 1; - if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) + if (transcoder_ddi_func_is_enabled(display, cpu_transcoder)) enabled_transcoders |= BIT(cpu_transcoder); } @@ -3998,17 +3776,17 @@ static bool has_pipe_transcoders(u8 enabled_transcoders) BIT(TRANSCODER_DSI_1)); } -static void assert_enabled_transcoders(struct drm_i915_private *i915, +static void assert_enabled_transcoders(struct intel_display *display, u8 enabled_transcoders) { /* Only one type of transcoder please */ - drm_WARN_ON(&i915->drm, + drm_WARN_ON(display->drm, has_edp_transcoders(enabled_transcoders) + has_dsi_transcoders(enabled_transcoders) + has_pipe_transcoders(enabled_transcoders) > 1); /* Only DSI transcoders can be ganged */ - drm_WARN_ON(&i915->drm, + drm_WARN_ON(display->drm, !has_dsi_transcoders(enabled_transcoders) && !is_power_of_2(enabled_transcoders)); } @@ -4017,8 +3795,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config, struct intel_display_power_domain_set *power_domain_set) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(crtc); unsigned long enabled_transcoders; u32 tmp; @@ -4026,7 +3803,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, if (!enabled_transcoders) return false; - assert_enabled_transcoders(dev_priv, enabled_transcoders); + assert_enabled_transcoders(display, enabled_transcoders); /* * With the exception of DSI we should only ever have @@ -4035,20 +3812,20 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, */ pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1; - if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, + if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) return false; - if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { - tmp = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL(dev_priv, pipe_config->cpu_transcoder)); + if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) { + tmp = intel_de_read(display, + TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder)); if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) pipe_config->pch_pfit.force_thru = true; } - tmp = intel_de_read(dev_priv, - TRANSCONF(dev_priv, pipe_config->cpu_transcoder)); + tmp = intel_de_read(display, + TRANSCONF(display, pipe_config->cpu_transcoder)); return tmp & TRANSCONF_ENABLE; } @@ -4069,7 +3846,7 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, else cpu_transcoder = TRANSCODER_DSI_C; - if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set, + if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set, POWER_DOMAIN_TRANSCODER(cpu_transcoder))) continue; @@ -4101,12 +3878,12 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, static void intel_joiner_get_config(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); u8 primary_pipe, secondary_pipes; enum pipe pipe = crtc->pipe; - enabled_joiner_pipes(i915, pipe, &primary_pipe, &secondary_pipes); + enabled_joiner_pipes(display, pipe, &primary_pipe, &secondary_pipes); if (((primary_pipe | secondary_pipes) & BIT(pipe)) == 0) return; @@ -4118,21 +3895,18 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); bool active; u32 tmp; - if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, + if (!intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, POWER_DOMAIN_PIPE(crtc->pipe))) return false; - pipe_config->shared_dpll = NULL; - active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains); - if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && + if ((display->platform.geminilake || display->platform.broxton) && bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) { - drm_WARN_ON(&dev_priv->drm, active); + drm_WARN_ON(display->drm, active); active = true; } @@ -4143,17 +3917,17 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, intel_dsc_get_config(pipe_config); if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || - DISPLAY_VER(dev_priv) >= 11) + DISPLAY_VER(display) >= 11) intel_get_transcoder_timings(crtc, pipe_config); - if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) + if (HAS_VRR(display) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) intel_vrr_get_config(pipe_config); intel_get_pipe_src_size(crtc, pipe_config); - if (IS_HASWELL(dev_priv)) { - u32 tmp = intel_de_read(dev_priv, - TRANSCONF(dev_priv, pipe_config->cpu_transcoder)); + if (display->platform.haswell) { + u32 tmp = intel_de_read(display, + TRANSCONF(display, pipe_config->cpu_transcoder)); if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; @@ -4168,18 +3942,18 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, intel_color_get_config(pipe_config); - tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); + tmp = intel_de_read(display, WM_LINETIME(crtc->pipe)); pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); - if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + if (display->platform.broadwell || display->platform.haswell) pipe_config->ips_linetime = REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); - if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains, + if (intel_display_power_get_in_set_if_enabled(display, &crtc->hw_readout_power_domains, POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) { - if (DISPLAY_VER(dev_priv) >= 9) + if (DISPLAY_VER(display) >= 9) skl_scaler_get_config(pipe_config); else - ilk_get_pfit_config(pipe_config); + ilk_pfit_get_config(pipe_config); } hsw_ips_get_config(pipe_config); @@ -4187,8 +3961,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, if (pipe_config->cpu_transcoder != TRANSCODER_EDP && !transcoder_is_dsi(pipe_config->cpu_transcoder)) { pipe_config->pixel_multiplier = - intel_de_read(dev_priv, - TRANS_MULT(dev_priv, pipe_config->cpu_transcoder)) + 1; + intel_de_read(display, + TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1; } else { pipe_config->pixel_multiplier = 1; } @@ -4203,17 +3977,17 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, } out: - intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains); + intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains); return active; } bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); - if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state)) + if (!display->funcs.display->get_pipe_config(crtc, crtc_state)) return false; crtc_state->hw.active = true; @@ -4229,7 +4003,7 @@ int intel_dotclock_calculate(int link_freq, /* * The calculation for the data clock -> pixel clock is: * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp - * But we want to avoid losing precison if possible, so: + * But we want to avoid losing precision if possible, so: * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) * * and for link freq (10kbs units) -> pixel clock it is: @@ -4339,137 +4113,6 @@ static bool check_single_encoder_cloning(struct intel_atomic_state *state, return true; } -static int icl_add_linked_planes(struct intel_atomic_state *state) -{ - struct intel_plane *plane, *linked; - struct intel_plane_state *plane_state, *linked_plane_state; - int i; - - for_each_new_intel_plane_in_state(state, plane, plane_state, i) { - linked = plane_state->planar_linked_plane; - - if (!linked) - continue; - - linked_plane_state = intel_atomic_get_plane_state(state, linked); - if (IS_ERR(linked_plane_state)) - return PTR_ERR(linked_plane_state); - - drm_WARN_ON(state->base.dev, - linked_plane_state->planar_linked_plane != plane); - drm_WARN_ON(state->base.dev, - linked_plane_state->planar_slave == plane_state->planar_slave); - } - - return 0; -} - -static int icl_check_nv12_planes(struct intel_atomic_state *state, - struct intel_crtc *crtc) -{ - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct intel_crtc_state *crtc_state = - intel_atomic_get_new_crtc_state(state, crtc); - struct intel_plane *plane, *linked; - struct intel_plane_state *plane_state; - int i; - - if (DISPLAY_VER(dev_priv) < 11) - return 0; - - /* - * Destroy all old plane links and make the slave plane invisible - * in the crtc_state->active_planes mask. - */ - for_each_new_intel_plane_in_state(state, plane, plane_state, i) { - if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) - continue; - - plane_state->planar_linked_plane = NULL; - if (plane_state->planar_slave && !plane_state->uapi.visible) { - crtc_state->enabled_planes &= ~BIT(plane->id); - crtc_state->active_planes &= ~BIT(plane->id); - crtc_state->update_planes |= BIT(plane->id); - crtc_state->data_rate[plane->id] = 0; - crtc_state->rel_data_rate[plane->id] = 0; - } - - plane_state->planar_slave = false; - } - - if (!crtc_state->nv12_planes) - return 0; - - for_each_new_intel_plane_in_state(state, plane, plane_state, i) { - struct intel_plane_state *linked_state = NULL; - - if (plane->pipe != crtc->pipe || - !(crtc_state->nv12_planes & BIT(plane->id))) - continue; - - for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) { - if (!icl_is_nv12_y_plane(dev_priv, linked->id)) - continue; - - if (crtc_state->active_planes & BIT(linked->id)) - continue; - - linked_state = intel_atomic_get_plane_state(state, linked); - if (IS_ERR(linked_state)) - return PTR_ERR(linked_state); - - break; - } - - if (!linked_state) { - drm_dbg_kms(&dev_priv->drm, - "Need %d free Y planes for planar YUV\n", - hweight8(crtc_state->nv12_planes)); - - return -EINVAL; - } - - plane_state->planar_linked_plane = linked; - - linked_state->planar_slave = true; - linked_state->planar_linked_plane = plane; - crtc_state->enabled_planes |= BIT(linked->id); - crtc_state->active_planes |= BIT(linked->id); - crtc_state->update_planes |= BIT(linked->id); - crtc_state->data_rate[linked->id] = - crtc_state->data_rate_y[plane->id]; - crtc_state->rel_data_rate[linked->id] = - crtc_state->rel_data_rate_y[plane->id]; - drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", - linked->base.name, plane->base.name); - - /* Copy parameters to slave plane */ - linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; - linked_state->color_ctl = plane_state->color_ctl; - linked_state->view = plane_state->view; - linked_state->decrypt = plane_state->decrypt; - - intel_plane_copy_hw_state(linked_state, plane_state); - linked_state->uapi.src = plane_state->uapi.src; - linked_state->uapi.dst = plane_state->uapi.dst; - - if (icl_is_hdr_plane(dev_priv, plane->id)) { - if (linked->id == PLANE_7) - plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; - else if (linked->id == PLANE_6) - plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; - else if (linked->id == PLANE_5) - plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; - else if (linked->id == PLANE_4) - plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; - else - MISSING_CASE(linked->id); - } - } - - return 0; -} - static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) { const struct drm_display_mode *pipe_mode = @@ -4503,6 +4146,7 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct drm_display_mode *pipe_mode = @@ -4516,7 +4160,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) crtc_state->pixel_rate); /* Display WA #1135: BXT:ALL GLK:ALL */ - if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && + if ((display->platform.geminilake || display->platform.broxton) && skl_watermark_ipc_enabled(dev_priv)) linetime_wm /= 2; @@ -4526,12 +4170,12 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) static int hsw_compute_linetime_wm(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_cdclk_state *cdclk_state; - if (DISPLAY_VER(dev_priv) >= 9) + if (DISPLAY_VER(display) >= 9) crtc_state->linetime = skl_linetime_wm(crtc_state); else crtc_state->linetime = hsw_linetime_wm(crtc_state); @@ -4553,12 +4197,11 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); int ret; - if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) && + if (DISPLAY_VER(display) < 5 && !display->platform.g4x && intel_crtc_needs_modeset(crtc_state) && !crtc_state->hw.active) crtc_state->update_wm_post = true; @@ -4575,13 +4218,13 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, ret = intel_wm_compute(state, crtc); if (ret) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] watermarks are invalid\n", crtc->base.base.id, crtc->base.name); return ret; } - if (DISPLAY_VER(dev_priv) >= 9) { + if (DISPLAY_VER(display) >= 9) { if (intel_crtc_needs_modeset(crtc_state) || intel_crtc_needs_fastset(crtc_state)) { ret = skl_update_scaler_crtc(crtc_state); @@ -4600,8 +4243,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, return ret; } - if (DISPLAY_VER(dev_priv) >= 9 || - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + if (DISPLAY_VER(display) >= 9 || + display->platform.broadwell || display->platform.haswell) { ret = hsw_compute_linetime_wm(state, crtc); if (ret) return ret; @@ -4619,8 +4262,8 @@ static int compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct drm_connector *connector = conn_state->connector; - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); const struct drm_display_info *info = &connector->display_info; int bpp; @@ -4643,7 +4286,7 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, } if (bpp < crtc_state->pipe_bpp) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] Limiting display bpp to %d " "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n", connector->base.id, connector->name, @@ -4661,17 +4304,17 @@ static int compute_baseline_pipe_bpp(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct drm_connector *connector; struct drm_connector_state *connector_state; int bpp, i; - if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || - IS_CHERRYVIEW(dev_priv))) + if (display->platform.g4x || display->platform.valleyview || + display->platform.cherryview) bpp = 10*3; - else if (DISPLAY_VER(dev_priv) >= 5) + else if (DISPLAY_VER(display) >= 5) bpp = 12*3; else bpp = 8*3; @@ -4695,7 +4338,7 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state, static bool check_digital_port_conflicts(struct intel_atomic_state *state) { - struct drm_device *dev = state->base.dev; + struct intel_display *display = to_intel_display(state); struct drm_connector *connector; struct drm_connector_list_iter conn_iter; unsigned int used_ports = 0; @@ -4706,14 +4349,14 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state) * We're going to peek into connector->state, * hence connection_mutex must be held. */ - drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); + drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex); /* * Walk the connector list instead of the encoder * list to detect the problem on ddi platforms * where there's just one encoder per digital port. */ - drm_connector_list_iter_begin(dev, &conn_iter); + drm_connector_list_iter_begin(display->drm, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { struct drm_connector_state *connector_state; struct intel_encoder *encoder; @@ -4729,11 +4372,11 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state) encoder = to_intel_encoder(connector_state->best_encoder); - drm_WARN_ON(dev, !connector_state->crtc); + drm_WARN_ON(display->drm, !connector_state->crtc); switch (encoder->type) { case INTEL_OUTPUT_DDI: - if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) + if (drm_WARN_ON(display->drm, !HAS_DDI(display))) break; fallthrough; case INTEL_OUTPUT_DP: @@ -4881,9 +4524,9 @@ static int intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_crtc_state *saved_state; saved_state = intel_crtc_state_alloc(crtc); @@ -4908,8 +4551,8 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls, sizeof(saved_state->icl_port_dplls)); saved_state->crc_enabled = crtc_state->crc_enabled; - if (IS_G4X(dev_priv) || - IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + if (display->platform.g4x || + display->platform.valleyview || display->platform.cherryview) saved_state->wm = crtc_state->wm; memcpy(crtc_state, saved_state, sizeof(*crtc_state)); @@ -4925,7 +4568,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state, struct intel_crtc *crtc, const struct intel_link_bw_limits *limits) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct drm_connector *connector; @@ -4958,7 +4601,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state, crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe]; if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n", crtc->base.base.id, crtc->base.name, FXP_Q4_ARGS(crtc_state->max_link_bpp_x16)); @@ -4988,7 +4631,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state, continue; if (!check_single_encoder_cloning(state, crtc, encoder)) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[ENCODER:%d:%s] rejecting invalid cloning configuration\n", encoder->base.base.id, encoder->base.name); return -EINVAL; @@ -5030,7 +4673,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state, if (ret == -EDEADLK) return ret; if (ret < 0) { - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n", + drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n", encoder->base.base.id, encoder->base.name, ret); return ret; } @@ -5046,7 +4689,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state, if (ret == -EDEADLK) return ret; if (ret < 0) { - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n", + drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n", crtc->base.base.id, crtc->base.name, ret); return ret; } @@ -5057,7 +4700,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state, */ crtc_state->dither = (crtc_state->pipe_bpp == 6*3) && !crtc_state->dither_force_disable; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n", crtc->base.base.id, crtc->base.name, base_bpp, crtc_state->pipe_bpp, crtc_state->dither); @@ -5189,7 +4832,7 @@ pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset, const union hdmi_infoframe *a, const union hdmi_infoframe *b) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); const char *loglevel; if (fastset) { @@ -5204,9 +4847,9 @@ pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset, pipe_config_mismatch(p, fastset, crtc, name, "infoframe"); drm_printf(p, "expected:\n"); - hdmi_infoframe_log(loglevel, i915->drm.dev, a); + hdmi_infoframe_log(loglevel, display->drm->dev, a); drm_printf(p, "found:\n"); - hdmi_infoframe_log(loglevel, i915->drm.dev, b); + hdmi_infoframe_log(loglevel, display->drm->dev, b); } static void @@ -5275,14 +4918,14 @@ pipe_config_pll_mismatch(struct drm_printer *p, bool fastset, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */ drm_printf(p, "expected:\n"); - intel_dpll_dump_hw_state(i915, p, a); + intel_dpll_dump_hw_state(display, p, a); drm_printf(p, "found:\n"); - intel_dpll_dump_hw_state(i915, p, b); + intel_dpll_dump_hw_state(display, p, b); } static void @@ -5303,21 +4946,34 @@ pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset, intel_cx0pll_dump_hw_state(display, b); } +static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state) +{ + struct intel_display *display = to_intel_display(old_crtc_state); + + /* + * Allow fastboot to fix up vblank delay (handled via LRR + * codepaths), a bit dodgy as the registers aren't + * double buffered but seems to be working more or less... + */ + return HAS_LRR(display) && old_crtc_state->inherited && + !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI); +} + bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, const struct intel_crtc_state *pipe_config, bool fastset) { struct intel_display *display = to_intel_display(current_config); - struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct drm_printer p; + u32 exclude_infoframes = 0; bool ret = true; if (fastset) - p = drm_dbg_printer(&dev_priv->drm, DRM_UT_KMS, NULL); + p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL); else - p = drm_err_printer(&dev_priv->drm, NULL); + p = drm_err_printer(display->drm, NULL); #define PIPE_CONF_CHECK_X(name) do { \ if (current_config->name != pipe_config->name) { \ @@ -5408,7 +5064,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, } while (0) #define PIPE_CONF_CHECK_PLL(name) do { \ - if (!intel_dpll_compare_hw_state(dev_priv, ¤t_config->name, \ + if (!intel_dpll_compare_hw_state(display, ¤t_config->name, \ &pipe_config->name)) { \ pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \ ¤t_config->name, \ @@ -5435,7 +5091,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ - PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ + if (!fastset || !allow_vblank_delay_fastset(current_config)) \ + PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ if (!fastset || !pipe_config->update_lrr) { \ @@ -5583,8 +5240,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(output_format); PIPE_CONF_CHECK_BOOL(has_hdmi_sink); - if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || - IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) || + display->platform.valleyview || display->platform.cherryview) PIPE_CONF_CHECK_BOOL(limited_color_range); PIPE_CONF_CHECK_BOOL(hdmi_scrambling); @@ -5600,7 +5257,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_X(gmch_pfit.control); /* pfit ratios are autocomputed by the hw on gen4+ */ - if (DISPLAY_VER(dev_priv) < 4) + if (DISPLAY_VER(display) < 4) PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); @@ -5620,7 +5277,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(pixel_rate); PIPE_CONF_CHECK_X(gamma_mode); - if (IS_CHERRYVIEW(dev_priv)) + if (display->platform.cherryview) PIPE_CONF_CHECK_X(cgm_mode); else PIPE_CONF_CHECK_X(csc_mode); @@ -5638,37 +5295,23 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_CSC(output_csc); } - /* - * Panel replay has to be enabled before link training. PSR doesn't have - * this requirement -> check these only if using panel replay - */ - if (current_config->active_planes && - (current_config->has_panel_replay || - pipe_config->has_panel_replay)) { - PIPE_CONF_CHECK_BOOL(has_psr); - PIPE_CONF_CHECK_BOOL(has_sel_update); - PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); - PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et); - PIPE_CONF_CHECK_BOOL(has_panel_replay); - } - PIPE_CONF_CHECK_BOOL(double_wide); - if (dev_priv->display.dpll.mgr) + if (display->dpll.mgr) PIPE_CONF_CHECK_P(shared_dpll); /* FIXME convert everything over the dpll_mgr */ - if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv)) + if (display->dpll.mgr || HAS_GMCH(display)) PIPE_CONF_CHECK_PLL(dpll_hw_state); /* FIXME convert MTL+ platforms over to dpll_mgr */ - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER(display) >= 14) PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll); PIPE_CONF_CHECK_X(dsi_pll.ctrl); PIPE_CONF_CHECK_X(dsi_pll.div); - if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) + if (display->platform.g4x || DISPLAY_VER(display) >= 5) PIPE_CONF_CHECK_I(pipe_bpp); if (!fastset || !pipe_config->update_m_n) { @@ -5680,19 +5323,21 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(min_voltage_level); if (current_config->has_psr || pipe_config->has_psr) - PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, - ~intel_hdmi_infoframe_enable(DP_SDP_VSC)); - else - PIPE_CONF_CHECK_X(infoframes.enable); + exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_VSC); + if (current_config->vrr.enable || pipe_config->vrr.enable) + exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); + + PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, ~exclude_infoframes); PIPE_CONF_CHECK_X(infoframes.gcp); PIPE_CONF_CHECK_INFOFRAME(avi); PIPE_CONF_CHECK_INFOFRAME(spd); PIPE_CONF_CHECK_INFOFRAME(hdmi); - if (!fastset) + if (!fastset) { PIPE_CONF_CHECK_INFOFRAME(drm); + PIPE_CONF_CHECK_DP_AS_SDP(as_sdp); + } PIPE_CONF_CHECK_DP_VSC_SDP(vsc); - PIPE_CONF_CHECK_DP_AS_SDP(as_sdp); PIPE_CONF_CHECK_X(sync_mode_slaves_mask); PIPE_CONF_CHECK_I(master_transcoder); @@ -5774,7 +5419,7 @@ intel_verify_planes(struct intel_atomic_state *state) for_each_new_intel_plane_in_state(state, plane, plane_state, i) - assert_plane(plane, plane_state->planar_slave || + assert_plane(plane, plane_state->is_y_plane || plane_state->uapi.visible); } @@ -5782,11 +5427,11 @@ static int intel_modeset_pipe(struct intel_atomic_state *state, struct intel_crtc_state *crtc_state, const char *reason) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); int ret; - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Full modeset due to %s\n", + drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n", crtc->base.base.id, crtc->base.name, reason); ret = drm_atomic_add_affected_connectors(&state->base, @@ -5826,10 +5471,10 @@ static int intel_modeset_pipe(struct intel_atomic_state *state, int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, const char *reason, u8 mask) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc *crtc; - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mask) { + for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) { struct intel_crtc_state *crtc_state; int ret; @@ -5873,10 +5518,10 @@ intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state) int intel_modeset_all_pipes_late(struct intel_atomic_state *state, const char *reason) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc *crtc; - for_each_intel_crtc(&dev_priv->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state; int ret; @@ -5902,7 +5547,7 @@ int intel_modeset_all_pipes_late(struct intel_atomic_state *state, return 0; } -int intel_modeset_commit_pipes(struct drm_i915_private *i915, +int intel_modeset_commit_pipes(struct intel_display *display, u8 pipe_mask, struct drm_modeset_acquire_ctx *ctx) { @@ -5910,14 +5555,14 @@ int intel_modeset_commit_pipes(struct drm_i915_private *i915, struct intel_crtc *crtc; int ret; - state = drm_atomic_state_alloc(&i915->drm); + state = drm_atomic_state_alloc(display->drm); if (!state) return -ENOMEM; state->acquire_ctx = ctx; to_intel_atomic_state(state)->internal = true; - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) { + for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) { struct intel_crtc_state *crtc_state = intel_atomic_get_crtc_state(state, crtc); @@ -6016,38 +5661,49 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state, static int intel_modeset_checks(struct intel_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); state->modeset = true; - if (IS_HASWELL(dev_priv)) + if (display->platform.haswell) return hsw_mode_set_planes_workaround(state); return 0; } +static bool lrr_params_changed(const struct drm_display_mode *old_adjusted_mode, + const struct drm_display_mode *new_adjusted_mode) +{ + return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start || + old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end || + old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal; +} + static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, struct intel_crtc_state *new_crtc_state) { + struct intel_display *display = to_intel_display(new_crtc_state); struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); /* only allow LRR when the timings stay within the VRR range */ if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range) new_crtc_state->update_lrr = false; - if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n", + if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) { + drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n", crtc->base.base.id, crtc->base.name); - else + } else { + if (allow_vblank_delay_fastset(old_crtc_state)) + new_crtc_state->update_lrr = true; new_crtc_state->uapi.mode_changed = false; + } if (intel_compare_link_m_n(&old_crtc_state->dp_m_n, &new_crtc_state->dp_m_n)) new_crtc_state->update_m_n = false; - if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal && - old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_end)) + if (!lrr_params_changed(&old_crtc_state->hw.adjusted_mode, + &new_crtc_state->hw.adjusted_mode)) new_crtc_state->update_lrr = false; if (intel_crtc_needs_modeset(new_crtc_state)) @@ -6056,161 +5712,19 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta new_crtc_state->update_pipe = true; } -static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, - struct intel_crtc *crtc, - u8 plane_ids_mask) -{ - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct intel_plane *plane; - - for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { - struct intel_plane_state *plane_state; - - if ((plane_ids_mask & BIT(plane->id)) == 0) - continue; - - plane_state = intel_atomic_get_plane_state(state, plane); - if (IS_ERR(plane_state)) - return PTR_ERR(plane_state); - } - - return 0; -} - -int intel_atomic_add_affected_planes(struct intel_atomic_state *state, - struct intel_crtc *crtc) -{ - const struct intel_crtc_state *old_crtc_state = - intel_atomic_get_old_crtc_state(state, crtc); - const struct intel_crtc_state *new_crtc_state = - intel_atomic_get_new_crtc_state(state, crtc); - - return intel_crtc_add_planes_to_state(state, crtc, - old_crtc_state->enabled_planes | - new_crtc_state->enabled_planes); -} - -static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) -{ - /* See {hsw,vlv,ivb}_plane_ratio() */ - return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) || - IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || - IS_IVYBRIDGE(dev_priv); -} - -static int intel_crtc_add_joiner_planes(struct intel_atomic_state *state, - struct intel_crtc *crtc, - struct intel_crtc *other) -{ - const struct intel_plane_state __maybe_unused *plane_state; - struct intel_plane *plane; - u8 plane_ids = 0; - int i; - - for_each_new_intel_plane_in_state(state, plane, plane_state, i) { - if (plane->pipe == crtc->pipe) - plane_ids |= BIT(plane->id); - } - - return intel_crtc_add_planes_to_state(state, other, plane_ids); -} - -static int intel_joiner_add_affected_planes(struct intel_atomic_state *state) -{ - struct drm_i915_private *i915 = to_i915(state->base.dev); - const struct intel_crtc_state *crtc_state; - struct intel_crtc *crtc; - int i; - - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - struct intel_crtc *other; - - for_each_intel_crtc_in_pipe_mask(&i915->drm, other, - crtc_state->joiner_pipes) { - int ret; - - if (crtc == other) - continue; - - ret = intel_crtc_add_joiner_planes(state, crtc, other); - if (ret) - return ret; - } - } - - return 0; -} - -static int intel_atomic_check_planes(struct intel_atomic_state *state) -{ - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct intel_crtc_state *old_crtc_state, *new_crtc_state; - struct intel_plane_state __maybe_unused *plane_state; - struct intel_plane *plane; - struct intel_crtc *crtc; - int i, ret; - - ret = icl_add_linked_planes(state); - if (ret) - return ret; - - ret = intel_joiner_add_affected_planes(state); - if (ret) - return ret; - - for_each_new_intel_plane_in_state(state, plane, plane_state, i) { - ret = intel_plane_atomic_check(state, plane); - if (ret) { - drm_dbg_atomic(&dev_priv->drm, - "[PLANE:%d:%s] atomic driver check failed\n", - plane->base.base.id, plane->base.name); - return ret; - } - } - - for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, - new_crtc_state, i) { - u8 old_active_planes, new_active_planes; - - ret = icl_check_nv12_planes(state, crtc); - if (ret) - return ret; - - /* - * On some platforms the number of active planes affects - * the planes' minimum cdclk calculation. Add such planes - * to the state before we compute the minimum cdclk. - */ - if (!active_planes_affects_min_cdclk(dev_priv)) - continue; - - old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR); - new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR); - - if (hweight8(old_active_planes) == hweight8(new_active_planes)) - continue; - - ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); - if (ret) - return ret; - } - - return 0; -} - static int intel_atomic_check_crtcs(struct intel_atomic_state *state) { + struct intel_display *display = to_intel_display(state); struct intel_crtc_state __maybe_unused *crtc_state; struct intel_crtc *crtc; int i; for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); int ret; ret = intel_crtc_atomic_check(state, crtc); if (ret) { - drm_dbg_atomic(&i915->drm, + drm_dbg_atomic(display->drm, "[CRTC:%d:%s] atomic driver check failed\n", crtc->base.base.id, crtc->base.name); return ret; @@ -6257,7 +5771,7 @@ static bool intel_pipes_need_modeset(struct intel_atomic_state *state, static int intel_atomic_check_joiner(struct intel_atomic_state *state, struct intel_crtc *primary_crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *primary_crtc_state = intel_atomic_get_new_crtc_state(state, primary_crtc); struct intel_crtc *secondary_crtc; @@ -6266,20 +5780,20 @@ static int intel_atomic_check_joiner(struct intel_atomic_state *state, return 0; /* sanity check */ - if (drm_WARN_ON(&i915->drm, + if (drm_WARN_ON(display->drm, primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state))) return -EINVAL; - if (primary_crtc_state->joiner_pipes & ~joiner_pipes(i915)) { - drm_dbg_kms(&i915->drm, + if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) { + drm_dbg_kms(display->drm, "[CRTC:%d:%s] Cannot act as joiner primary " "(need 0x%x as pipes, only 0x%x possible)\n", primary_crtc->base.base.id, primary_crtc->base.name, - primary_crtc_state->joiner_pipes, joiner_pipes(i915)); + primary_crtc_state->joiner_pipes, joiner_pipes(display)); return -EINVAL; } - for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc, + for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc, intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { struct intel_crtc_state *secondary_crtc_state; int ret; @@ -6290,7 +5804,7 @@ static int intel_atomic_check_joiner(struct intel_atomic_state *state, /* primary being enabled, secondary was already configured? */ if (secondary_crtc_state->uapi.enable) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] secondary is enabled as normal CRTC, but " "[CRTC:%d:%s] claiming this CRTC for joiner.\n", secondary_crtc->base.base.id, secondary_crtc->base.name, @@ -6309,7 +5823,7 @@ static int intel_atomic_check_joiner(struct intel_atomic_state *state, drm_crtc_index(&secondary_crtc->base))) return -EINVAL; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n", secondary_crtc->base.base.id, secondary_crtc->base.name, primary_crtc->base.base.id, primary_crtc->base.name); @@ -6328,12 +5842,12 @@ static int intel_atomic_check_joiner(struct intel_atomic_state *state, static void kill_joiner_secondaries(struct intel_atomic_state *state, struct intel_crtc *primary_crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *primary_crtc_state = intel_atomic_get_new_crtc_state(state, primary_crtc); struct intel_crtc *secondary_crtc; - for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc, + for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc, intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { struct intel_crtc_state *secondary_crtc_state = intel_atomic_get_new_crtc_state(state, secondary_crtc); @@ -6359,7 +5873,7 @@ static void kill_joiner_secondaries(struct intel_atomic_state *state, * the intel_crtc_enable_flip_done() function. * * As soon as the surface address register is written, flip done interrupt is - * generated and the requested events are sent to the usersapce in the interrupt + * generated and the requested events are sent to the userspace in the interrupt * handler itself. The timestamp and sequence sent during the flip done event * correspond to the last vblank and have no relation to the actual time when * the flip done event was sent. @@ -6367,7 +5881,7 @@ static void kill_joiner_secondaries(struct intel_atomic_state *state, static int intel_async_flip_check_uapi(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_plane_state *old_plane_state; @@ -6379,14 +5893,14 @@ static int intel_async_flip_check_uapi(struct intel_atomic_state *state, return 0; if (!new_crtc_state->uapi.active) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] not active\n", crtc->base.base.id, crtc->base.name); return -EINVAL; } if (intel_crtc_needs_modeset(new_crtc_state)) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] modeset required\n", crtc->base.base.id, crtc->base.name); return -EINVAL; @@ -6397,7 +5911,7 @@ static int intel_async_flip_check_uapi(struct intel_atomic_state *state, * Remove this check once the issues are fixed. */ if (new_crtc_state->joiner_pipes) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] async flip disallowed with joiner\n", crtc->base.base.id, crtc->base.name); return -EINVAL; @@ -6416,14 +5930,14 @@ static int intel_async_flip_check_uapi(struct intel_atomic_state *state, * enabled in the atomic IOCTL path. */ if (!plane->async_flip) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] async flip not supported\n", plane->base.base.id, plane->base.name); return -EINVAL; } if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] no old or new framebuffer\n", plane->base.base.id, plane->base.name); return -EINVAL; @@ -6435,7 +5949,7 @@ static int intel_async_flip_check_uapi(struct intel_atomic_state *state, static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *old_crtc_state, *new_crtc_state; const struct intel_plane_state *new_plane_state, *old_plane_state; struct intel_plane *plane; @@ -6448,21 +5962,21 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in return 0; if (!new_crtc_state->hw.active) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] not active\n", crtc->base.base.id, crtc->base.name); return -EINVAL; } if (intel_crtc_needs_modeset(new_crtc_state)) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] modeset required\n", crtc->base.base.id, crtc->base.name); return -EINVAL; } if (old_crtc_state->active_planes != new_crtc_state->active_planes) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] Active planes cannot be in async flip\n", crtc->base.base.id, crtc->base.name); return -EINVAL; @@ -6478,7 +5992,7 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in * if we're really about to ask the hardware to perform * an async flip. We should never get this far otherwise. */ - if (drm_WARN_ON(&i915->drm, + if (drm_WARN_ON(display->drm, new_crtc_state->do_async_flip && !plane->async_flip)) return -EINVAL; @@ -6493,45 +6007,17 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in if (!plane->async_flip) continue; - /* - * FIXME: This check is kept generic for all platforms. - * Need to verify this for all gen9 platforms to enable - * this selectively if required. - */ - switch (new_plane_state->hw.fb->modifier) { - case DRM_FORMAT_MOD_LINEAR: - /* - * FIXME: Async on Linear buffer is supported on ICL as - * but with additional alignment and fbc restrictions - * need to be taken care of. These aren't applicable for - * gen12+. - */ - if (DISPLAY_VER(i915) < 12) { - drm_dbg_kms(&i915->drm, - "[PLANE:%d:%s] Modifier 0x%llx does not support async flip on display ver %d\n", - plane->base.base.id, plane->base.name, - new_plane_state->hw.fb->modifier, DISPLAY_VER(i915)); - return -EINVAL; - } - break; - - case I915_FORMAT_MOD_X_TILED: - case I915_FORMAT_MOD_Y_TILED: - case I915_FORMAT_MOD_Yf_TILED: - case I915_FORMAT_MOD_4_TILED: - case I915_FORMAT_MOD_4_TILED_BMG_CCS: - case I915_FORMAT_MOD_4_TILED_LNL_CCS: - break; - default: - drm_dbg_kms(&i915->drm, + if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->modifier)) { + drm_dbg_kms(display->drm, "[PLANE:%d:%s] Modifier 0x%llx does not support async flip\n", plane->base.base.id, plane->base.name, new_plane_state->hw.fb->modifier); return -EINVAL; } - if (new_plane_state->hw.fb->format->num_planes > 1) { - drm_dbg_kms(&i915->drm, + if (intel_format_info_is_yuv_semiplanar(new_plane_state->hw.fb->format, + new_plane_state->hw.fb->modifier)) { + drm_dbg_kms(display->drm, "[PLANE:%d:%s] Planar formats do not support async flips\n", plane->base.base.id, plane->base.name); return -EINVAL; @@ -6546,7 +6032,7 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in if (old_plane_state->view.color_plane[0].mapping_stride != new_plane_state->view.color_plane[0].mapping_stride) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] Stride cannot be changed in async flip\n", plane->base.base.id, plane->base.name); return -EINVAL; @@ -6554,7 +6040,7 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in if (old_plane_state->hw.fb->modifier != new_plane_state->hw.fb->modifier) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] Modifier cannot be changed in async flip\n", plane->base.base.id, plane->base.name); return -EINVAL; @@ -6562,7 +6048,7 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in if (old_plane_state->hw.fb->format != new_plane_state->hw.fb->format) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n", plane->base.base.id, plane->base.name); return -EINVAL; @@ -6570,22 +6056,30 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in if (old_plane_state->hw.rotation != new_plane_state->hw.rotation) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] Rotation cannot be changed in async flip\n", plane->base.base.id, plane->base.name); return -EINVAL; } + if (skl_plane_aux_dist(old_plane_state, 0) != + skl_plane_aux_dist(new_plane_state, 0)) { + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] AUX_DIST cannot be changed in async flip\n", + plane->base.base.id, plane->base.name); + return -EINVAL; + } + if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) || !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n", plane->base.base.id, plane->base.name); return -EINVAL; } if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n", plane->base.base.id, plane->base.name); return -EINVAL; @@ -6593,21 +6087,21 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in if (old_plane_state->hw.pixel_blend_mode != new_plane_state->hw.pixel_blend_mode) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n", plane->base.base.id, plane->base.name); return -EINVAL; } if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n", plane->base.base.id, plane->base.name); return -EINVAL; } if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] Color range cannot be changed in async flip\n", plane->base.base.id, plane->base.name); return -EINVAL; @@ -6615,7 +6109,7 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in /* plane decryption is allow to change only in synchronous flips */ if (old_plane_state->decrypt != new_plane_state->decrypt) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[PLANE:%d:%s] Decryption cannot be changed in async flip\n", plane->base.base.id, plane->base.name); return -EINVAL; @@ -6627,26 +6121,44 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); + const struct intel_plane_state *plane_state; struct intel_crtc_state *crtc_state; + struct intel_plane *plane; struct intel_crtc *crtc; u8 affected_pipes = 0; u8 modeset_pipes = 0; int i; + /* + * Any plane which is in use by the joiner needs its crtc. + * Pull those in first as this will not have happened yet + * if the plane remains disabled according to uapi. + */ + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + crtc = to_intel_crtc(plane_state->hw.crtc); + if (!crtc) + continue; + + crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + } + + /* Now pull in all joined crtcs */ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { affected_pipes |= crtc_state->joiner_pipes; if (intel_crtc_needs_modeset(crtc_state)) modeset_pipes |= crtc_state->joiner_pipes; } - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { + for_each_intel_crtc_in_pipe_mask(display->drm, crtc, affected_pipes) { crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); if (IS_ERR(crtc_state)) return PTR_ERR(crtc_state); } - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) { + for_each_intel_crtc_in_pipe_mask(display->drm, crtc, modeset_pipes) { int ret; crtc_state = intel_atomic_get_new_crtc_state(state, crtc); @@ -6676,7 +6188,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state, struct intel_link_bw_limits *limits, enum pipe *failed_pipe) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *new_crtc_state; struct intel_crtc *crtc; int ret; @@ -6701,7 +6213,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state, continue; } - if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) + if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) continue; ret = intel_crtc_prepare_cleared_state(state, crtc); @@ -6720,7 +6232,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state, if (!intel_crtc_needs_modeset(new_crtc_state)) continue; - if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) + if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) continue; if (!new_crtc_state->hw.enable) @@ -6785,7 +6297,6 @@ int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *_state) { struct intel_display *display = to_intel_display(dev); - struct drm_i915_private *dev_priv = to_i915(dev); struct intel_atomic_state *state = to_intel_atomic_state(_state); struct intel_crtc_state *old_crtc_state, *new_crtc_state; struct intel_crtc *crtc; @@ -6833,7 +6344,7 @@ int intel_atomic_check(struct drm_device *dev, continue; if (intel_crtc_is_joiner_secondary(new_crtc_state)) { - drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); + drm_WARN_ON(display->drm, new_crtc_state->uapi.enable); continue; } @@ -6904,7 +6415,7 @@ int intel_atomic_check(struct drm_device *dev, } if (any_ms && !check_digital_port_conflicts(state)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "rejecting conflicting digital port configuration\n"); ret = -EINVAL; goto fail; @@ -6960,7 +6471,7 @@ int intel_atomic_check(struct drm_device *dev, goto fail; /* Either full modeset or fastset (or neither), never both */ - drm_WARN_ON(&dev_priv->drm, + drm_WARN_ON(display->drm, intel_crtc_needs_modeset(new_crtc_state) && intel_crtc_needs_fastset(new_crtc_state)); @@ -7004,22 +6515,23 @@ static int intel_atomic_prepare_commit(struct intel_atomic_state *state) void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); - if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes) - intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); + if (DISPLAY_VER(display) != 2 || crtc_state->active_planes) + intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true); if (crtc_state->has_pch_encoder) { enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc); - intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true); + intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, true); } } static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { + struct intel_display *display = to_intel_display(new_crtc_state); struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -7034,7 +6546,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, intel_set_pipe_src_size(new_crtc_state); /* on skylake this is done by detaching scalers */ - if (DISPLAY_VER(dev_priv) >= 9) { + if (DISPLAY_VER(display) >= 9) { if (new_crtc_state->pch_pfit.enabled) skl_pfit_enable(new_crtc_state); } else if (HAS_PCH_SPLIT(dev_priv)) { @@ -7052,8 +6564,8 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, * HSW/BDW only really need this here for fastboot, after * that the value should not change without a full modeset. */ - if (DISPLAY_VER(dev_priv) >= 9 || - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + if (DISPLAY_VER(display) >= 9 || + display->platform.broadwell || display->platform.haswell) hsw_set_linetime_wm(new_crtc_state); if (new_crtc_state->update_m_n) @@ -7067,29 +6579,31 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, static void commit_pipe_pre_planes(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); bool modeset = intel_crtc_needs_modeset(new_crtc_state); + drm_WARN_ON(display->drm, new_crtc_state->use_dsb); + /* * During modesets pipe configuration was programmed as the * CRTC was enabled. */ - if (!modeset && !new_crtc_state->use_dsb) { + if (!modeset) { if (intel_crtc_needs_color_update(new_crtc_state)) intel_color_commit_arm(NULL, new_crtc_state); - if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) + if (DISPLAY_VER(display) >= 9 || display->platform.broadwell) bdw_set_pipe_misc(NULL, new_crtc_state); if (intel_crtc_needs_fastset(new_crtc_state)) intel_pipe_fastset(old_crtc_state, new_crtc_state); } - intel_psr2_program_trans_man_trk_ctl(new_crtc_state); + intel_psr2_program_trans_man_trk_ctl(NULL, new_crtc_state); intel_atomic_update_watermarks(state, crtc); } @@ -7097,18 +6611,20 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state, static void commit_pipe_post_planes(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + drm_WARN_ON(display->drm, new_crtc_state->use_dsb); + /* * Disable the scaler(s) after the plane(s) so that we don't * get a catastrophic underrun even if the two operations * end up happening in two different frames. */ - if (DISPLAY_VER(dev_priv) >= 9 && + if (DISPLAY_VER(display) >= 9 && !intel_crtc_needs_modeset(new_crtc_state)) - skl_detach_scalers(new_crtc_state); + skl_detach_scalers(NULL, new_crtc_state); if (intel_crtc_vrr_enabling(state, crtc)) intel_vrr_enable(new_crtc_state); @@ -7117,7 +6633,7 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, static void intel_enable_crtc(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct intel_crtc *pipe_crtc; @@ -7125,7 +6641,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state, if (!intel_crtc_needs_modeset(new_crtc_state)) return; - for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, + for_each_intel_crtc_in_pipe_mask_reverse(display->drm, pipe_crtc, intel_crtc_joined_pipe_mask(new_crtc_state)) { const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); @@ -7134,7 +6650,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state, intel_crtc_update_active_timings(pipe_crtc_state, false); } - dev_priv->display.funcs.display->crtc_enable(state, crtc); + display->funcs.display->crtc_enable(state, crtc); /* vblanks work again, re-enable pipe CRC. */ intel_crtc_enable_pipe_crc(crtc); @@ -7143,7 +6659,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state, static void intel_pre_update_crtc(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); struct intel_crtc_state *new_crtc_state = @@ -7152,7 +6668,7 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, if (old_crtc_state->inherited || intel_crtc_needs_modeset(new_crtc_state)) { - if (HAS_DPT(i915)) + if (HAS_DPT(display)) intel_dpt_configure(crtc); } @@ -7166,7 +6682,7 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, if (intel_crtc_needs_fastset(new_crtc_state)) intel_encoders_update_pipe(state, crtc); - if (DISPLAY_VER(i915) >= 11 && + if (DISPLAY_VER(display) >= 11 && intel_crtc_needs_fastset(new_crtc_state)) icl_set_pipe_chicken(new_crtc_state); @@ -7177,7 +6693,7 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_fbc_update(state, crtc); - drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF)); + drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF)); if (!modeset && intel_crtc_needs_color_update(new_crtc_state) && @@ -7240,7 +6756,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, static void intel_old_crtc_state_disables(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); struct intel_crtc *pipe_crtc; @@ -7249,13 +6765,13 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state, * We need to disable pipe CRC before disabling the pipe, * or we race against vblank off. */ - for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, + for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, intel_crtc_joined_pipe_mask(old_crtc_state)) intel_crtc_disable_pipe_crc(pipe_crtc); - dev_priv->display.funcs.display->crtc_disable(state, crtc); + display->funcs.display->crtc_disable(state, crtc); - for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, + for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, intel_crtc_joined_pipe_mask(old_crtc_state)) { const struct intel_crtc_state *new_pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); @@ -7270,7 +6786,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state, static void intel_commit_modeset_disables(struct intel_atomic_state *state) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *new_crtc_state, *old_crtc_state; struct intel_crtc *crtc; u8 disable_pipes = 0; @@ -7337,7 +6853,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) disable_pipes &= ~intel_crtc_joined_pipe_mask(old_crtc_state); } - drm_WARN_ON(&i915->drm, disable_pipes); + drm_WARN_ON(display->drm, disable_pipes); } static void intel_commit_modeset_enables(struct intel_atomic_state *state) @@ -7364,7 +6880,7 @@ static void intel_commit_modeset_enables(struct intel_atomic_state *state) static void skl_commit_modeset_enables(struct intel_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc *crtc; struct intel_crtc_state *old_crtc_state, *new_crtc_state; struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; @@ -7506,8 +7022,9 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((update_pipes & BIT(pipe)) == 0) continue; - drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, - entries, I915_MAX_PIPES, pipe)); + drm_WARN_ON(display->drm, + skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, + entries, I915_MAX_PIPES, pipe)); entries[pipe] = new_crtc_state->wm.skl.ddb; update_pipes &= ~BIT(pipe); @@ -7515,8 +7032,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) intel_update_crtc(state, crtc); } - drm_WARN_ON(&dev_priv->drm, modeset_pipes); - drm_WARN_ON(&dev_priv->drm, update_pipes); + drm_WARN_ON(display->drm, modeset_pipes); + drm_WARN_ON(display->drm, update_pipes); } static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) @@ -7561,7 +7078,7 @@ static void intel_atomic_cleanup_work(struct work_struct *work) { struct intel_atomic_state *state = container_of(work, struct intel_atomic_state, cleanup_work); - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *old_crtc_state; struct intel_crtc *crtc; int i; @@ -7569,14 +7086,14 @@ static void intel_atomic_cleanup_work(struct work_struct *work) for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) intel_atomic_dsb_cleanup(old_crtc_state); - drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); + drm_atomic_helper_cleanup_planes(display->drm, &state->base); drm_atomic_helper_commit_cleanup_done(&state->base); drm_atomic_state_put(&state->base); } static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_plane *plane; struct intel_plane_state *plane_state; int i; @@ -7613,21 +7130,14 @@ static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s &plane_state->ccval, sizeof(plane_state->ccval)); /* The above could only fail if the FB obj has an unexpected backing store type. */ - drm_WARN_ON(&i915->drm, ret); + drm_WARN_ON(display->drm, ret); } } static void intel_atomic_dsb_prepare(struct intel_atomic_state *state, struct intel_crtc *crtc) { - intel_color_prepare_commit(state, crtc); -} - -static void intel_atomic_dsb_finish(struct intel_atomic_state *state, - struct intel_crtc *crtc) -{ - const struct intel_crtc_state *old_crtc_state = - intel_atomic_get_old_crtc_state(state, crtc); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); @@ -7639,15 +7149,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, /* FIXME deal with everything */ new_crtc_state->use_dsb = - new_crtc_state->update_planes && - !new_crtc_state->vrr.enable && !new_crtc_state->do_async_flip && - !new_crtc_state->has_psr && - !new_crtc_state->scaler_state.scaler_users && - !old_crtc_state->scaler_state.scaler_users && + (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) && !intel_crtc_needs_modeset(new_crtc_state) && !intel_crtc_needs_fastset(new_crtc_state); + intel_color_prepare_commit(state, crtc); +} + +static void intel_atomic_dsb_finish(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(state); + struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + if (!new_crtc_state->use_dsb && !new_crtc_state->dsb_color_vblank) return; @@ -7671,6 +7187,14 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit, state, crtc); + /* + * Ensure we have "Frame Change" event when PSR state is + * SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank + * evasion hangs as PIPEDSL is reading as 0. + */ + intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit, + state, crtc); + intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit); if (intel_crtc_needs_color_update(new_crtc_state)) @@ -7678,12 +7202,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, new_crtc_state); bdw_set_pipe_misc(new_crtc_state->dsb_commit, new_crtc_state); + intel_psr2_program_trans_man_trk_ctl(new_crtc_state->dsb_commit, + new_crtc_state); intel_crtc_planes_update_arm(new_crtc_state->dsb_commit, state, crtc); + if (DISPLAY_VER(display) >= 9) + skl_detach_scalers(new_crtc_state->dsb_commit, + new_crtc_state); + if (!new_crtc_state->dsb_color_vblank) { intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); + + intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit); + intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state); intel_dsb_interrupt(new_crtc_state->dsb_commit); } } @@ -7697,8 +7230,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, static void intel_atomic_commit_tail(struct intel_atomic_state *state) { - struct drm_device *dev = state->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(state); + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc_state *new_crtc_state, *old_crtc_state; struct intel_crtc *crtc; struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; @@ -7710,11 +7243,14 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_atomic_commit_fence_wait(state); - intel_td_flush(dev_priv); + intel_td_flush(display); intel_atomic_prepare_plane_clear_colors(state); for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) + intel_fbc_prepare_dirty_rect(state, crtc); + + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) intel_atomic_dsb_finish(state, crtc); drm_atomic_helper_wait_for_dependencies(&state->base); @@ -7748,7 +7284,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * the CSC latched register values with the readout (see * skl_read_csc() and skl_color_commit_noarm()). */ - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF); + wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { @@ -7774,7 +7310,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_pmdemand_pre_plane_update(state); if (state->modeset) { - drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); + drm_atomic_helper_update_legacy_modeset_state(display->drm, &state->base); intel_set_cdclk_pre_plane_update(state); @@ -7789,10 +7325,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) /* Complete events for now disable pipes here. */ if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { - spin_lock_irq(&dev->event_lock); + spin_lock_irq(&display->drm->event_lock); drm_crtc_send_vblank_event(&crtc->base, new_crtc_state->uapi.event); - spin_unlock_irq(&dev->event_lock); + spin_unlock_irq(&display->drm->event_lock); new_crtc_state->uapi.event = NULL; } @@ -7808,13 +7344,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) } /* Now enable the clocks, plane, pipe, and connectors that we set up. */ - dev_priv->display.funcs.display->commit_modeset_enables(state); + display->funcs.display->commit_modeset_enables(state); intel_program_dpkgc_latency(state); - if (state->modeset) - intel_set_cdclk_post_plane_update(state); - intel_wait_for_vblank_workers(state); /* FIXME: We should call drm_atomic_helper_commit_hw_done() here @@ -7826,13 +7359,16 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * - switch over to the vblank wait helper in the core after that since * we don't need out special handling any more. */ - drm_atomic_helper_wait_for_flip_done(dev, &state->base); + drm_atomic_helper_wait_for_flip_done(display->drm, &state->base); for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { if (new_crtc_state->do_async_flip) intel_crtc_disable_flip_done(state, crtc); intel_atomic_dsb_wait_commit(new_crtc_state); + + if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb) + intel_vrr_check_push_sent(NULL, new_crtc_state); } /* @@ -7852,8 +7388,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * chance of catching underruns with the intermediate watermarks * vs. the new plane configuration. */ - if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) - intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); + if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state)) + intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, true); intel_optimize_watermarks(state, crtc); } @@ -7881,13 +7417,15 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) } /* Underruns don't always raise interrupts, so check manually */ - intel_check_cpu_fifo_underruns(dev_priv); - intel_check_pch_fifo_underruns(dev_priv); + intel_check_cpu_fifo_underruns(display); + intel_check_pch_fifo_underruns(display); if (state->modeset) intel_verify_planes(state); intel_sagv_post_plane_update(state); + if (state->modeset) + intel_set_cdclk_post_plane_update(state); intel_pmdemand_post_plane_update(state); drm_atomic_helper_commit_hw_done(&state->base); @@ -7906,7 +7444,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * Delay re-enabling DC states by 17 ms to avoid the off->on->off * toggling overhead at and above 60 FPS. */ - intel_display_power_put_async_delay(dev_priv, POWER_DOMAIN_DC_OFF, wakeref, 17); + intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17); intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); /* @@ -7918,7 +7456,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * down. */ INIT_WORK(&state->cleanup_work, intel_atomic_cleanup_work); - queue_work(dev_priv->display.wq.cleanup, &state->cleanup_work); + queue_work(display->wq.cleanup, &state->cleanup_work); } static void intel_atomic_commit_work(struct work_struct *work) @@ -7977,6 +7515,7 @@ static int intel_atomic_swap_state(struct intel_atomic_state *state) int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, bool nonblock) { + struct intel_display *display = to_intel_display(dev); struct intel_atomic_state *state = to_intel_atomic_state(_state); struct drm_i915_private *dev_priv = to_i915(dev); int ret = 0; @@ -8000,7 +7539,7 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, * FIXME doing watermarks and fb cleanup from a vblank worker * (assuming we had any) would solve these problems. */ - if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) { + if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) { struct intel_crtc_state *new_crtc_state; struct intel_crtc *crtc; int i; @@ -8013,7 +7552,7 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, ret = intel_atomic_prepare_commit(state); if (ret) { - drm_dbg_atomic(&dev_priv->drm, + drm_dbg_atomic(display->drm, "Preparing state failed with %i\n", ret); intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); return ret; @@ -8033,38 +7572,25 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); if (nonblock && state->modeset) { - queue_work(dev_priv->display.wq.modeset, &state->base.commit_work); + queue_work(display->wq.modeset, &state->base.commit_work); } else if (nonblock) { - queue_work(dev_priv->display.wq.flip, &state->base.commit_work); + queue_work(display->wq.flip, &state->base.commit_work); } else { if (state->modeset) - flush_workqueue(dev_priv->display.wq.modeset); + flush_workqueue(display->wq.modeset); intel_atomic_commit_tail(state); } return 0; } -/** - * intel_plane_destroy - destroy a plane - * @plane: plane to destroy - * - * Common destruction function for all types of planes (primary, cursor, - * sprite). - */ -void intel_plane_destroy(struct drm_plane *plane) -{ - drm_plane_cleanup(plane); - kfree(to_intel_plane(plane)); -} - static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) { - struct drm_device *dev = encoder->base.dev; + struct intel_display *display = to_intel_display(encoder); struct intel_encoder *source_encoder; u32 possible_clones = 0; - for_each_intel_encoder(dev, source_encoder) { + for_each_intel_encoder(display->drm, source_encoder) { if (encoders_cloneable(encoder, source_encoder)) possible_clones |= drm_encoder_mask(&source_encoder->base); } @@ -8074,76 +7600,78 @@ static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) { - struct drm_device *dev = encoder->base.dev; + struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc; u32 possible_crtcs = 0; - for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) + for_each_intel_crtc_in_pipe_mask(display->drm, crtc, encoder->pipe_mask) possible_crtcs |= drm_crtc_mask(&crtc->base); return possible_crtcs; } -static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) +static bool ilk_has_edp_a(struct intel_display *display) { - if (!IS_MOBILE(dev_priv)) + if (!display->platform.mobile) return false; - if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) + if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0) return false; - if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) + if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE)) return false; return true; } -static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) +static bool intel_ddi_crt_present(struct intel_display *display) { - if (DISPLAY_VER(dev_priv) >= 9) + struct drm_i915_private *dev_priv = to_i915(display->drm); + + if (DISPLAY_VER(display) >= 9) return false; - if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv)) + if (display->platform.haswell_ult || display->platform.broadwell_ult) return false; if (HAS_PCH_LPT_H(dev_priv) && - intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) + intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) return false; /* DDI E can't be used if DDI A requires 4 lanes */ - if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) + if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) return false; - if (!dev_priv->display.vbt.int_crt_support) + if (!display->vbt.int_crt_support) return false; return true; } -bool assert_port_valid(struct drm_i915_private *i915, enum port port) +bool assert_port_valid(struct intel_display *display, enum port port) { - return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)), + return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)), "Platform does not support port %c\n", port_name(port)); } -void intel_setup_outputs(struct drm_i915_private *dev_priv) +void intel_setup_outputs(struct intel_display *display) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *encoder; bool dpd_is_edp = false; intel_pps_unlock_regs_wa(display); - if (!HAS_DISPLAY(dev_priv)) + if (!HAS_DISPLAY(display)) return; - if (HAS_DDI(dev_priv)) { - if (intel_ddi_crt_present(dev_priv)) + if (HAS_DDI(display)) { + if (intel_ddi_crt_present(display)) intel_crt_init(display); intel_bios_for_each_encoder(display, intel_ddi_init); - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) + if (display->platform.geminilake || display->platform.broxton) vlv_dsi_init(dev_priv); } else if (HAS_PCH_SPLIT(dev_priv)) { int found; @@ -8158,33 +7686,33 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv) dpd_is_edp = intel_dp_is_port_edp(display, PORT_D); - if (ilk_has_edp_a(dev_priv)) - g4x_dp_init(dev_priv, DP_A, PORT_A); + if (ilk_has_edp_a(display)) + g4x_dp_init(display, DP_A, PORT_A); - if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { + if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) { /* PCH SDVOB multiplex with HDMIB */ - found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); + found = intel_sdvo_init(display, PCH_SDVOB, PORT_B); if (!found) - g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); - if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) - g4x_dp_init(dev_priv, PCH_DP_B, PORT_B); + g4x_hdmi_init(display, PCH_HDMIB, PORT_B); + if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED)) + g4x_dp_init(display, PCH_DP_B, PORT_B); } - if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) - g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); + if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED) + g4x_hdmi_init(display, PCH_HDMIC, PORT_C); - if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) - g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D); + if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED) + g4x_hdmi_init(display, PCH_HDMID, PORT_D); - if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) - g4x_dp_init(dev_priv, PCH_DP_C, PORT_C); + if (intel_de_read(display, PCH_DP_C) & DP_DETECTED) + g4x_dp_init(display, PCH_DP_C, PORT_C); - if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) - g4x_dp_init(dev_priv, PCH_DP_D, PORT_D); - } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + if (intel_de_read(display, PCH_DP_D) & DP_DETECTED) + g4x_dp_init(display, PCH_DP_D, PORT_D); + } else if (display->platform.valleyview || display->platform.cherryview) { bool has_edp, has_port; - if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support) + if (display->platform.valleyview && display->vbt.int_crt_support) intel_crt_init(display); /* @@ -8204,87 +7732,87 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv) */ has_edp = intel_dp_is_port_edp(display, PORT_B); has_port = intel_bios_is_port_present(display, PORT_B); - if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) - has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B); - if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) - g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); + if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port) + has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B); + if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) + g4x_hdmi_init(display, VLV_HDMIB, PORT_B); has_edp = intel_dp_is_port_edp(display, PORT_C); has_port = intel_bios_is_port_present(display, PORT_C); - if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) - has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C); - if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) - g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); + if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port) + has_edp &= g4x_dp_init(display, VLV_DP_C, PORT_C); + if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) + g4x_hdmi_init(display, VLV_HDMIC, PORT_C); - if (IS_CHERRYVIEW(dev_priv)) { + if (display->platform.cherryview) { /* * eDP not supported on port D, * so no need to worry about it */ has_port = intel_bios_is_port_present(display, PORT_D); - if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) - g4x_dp_init(dev_priv, CHV_DP_D, PORT_D); - if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) - g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D); + if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port) + g4x_dp_init(display, CHV_DP_D, PORT_D); + if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port) + g4x_hdmi_init(display, CHV_HDMID, PORT_D); } vlv_dsi_init(dev_priv); - } else if (IS_PINEVIEW(dev_priv)) { + } else if (display->platform.pineview) { intel_lvds_init(dev_priv); intel_crt_init(display); - } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) { + } else if (IS_DISPLAY_VER(display, 3, 4)) { bool found = false; - if (IS_MOBILE(dev_priv)) + if (display->platform.mobile) intel_lvds_init(dev_priv); intel_crt_init(display); - if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { - drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); - found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); - if (!found && IS_G4X(dev_priv)) { - drm_dbg_kms(&dev_priv->drm, + if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) { + drm_dbg_kms(display->drm, "probing SDVOB\n"); + found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B); + if (!found && display->platform.g4x) { + drm_dbg_kms(display->drm, "probing HDMI on SDVOB\n"); - g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); + g4x_hdmi_init(display, GEN4_HDMIB, PORT_B); } - if (!found && IS_G4X(dev_priv)) - g4x_dp_init(dev_priv, DP_B, PORT_B); + if (!found && display->platform.g4x) + g4x_dp_init(display, DP_B, PORT_B); } /* Before G4X SDVOC doesn't have its own detect register */ - if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { - drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); - found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); + if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) { + drm_dbg_kms(display->drm, "probing SDVOC\n"); + found = intel_sdvo_init(display, GEN3_SDVOC, PORT_C); } - if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { + if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) { - if (IS_G4X(dev_priv)) { - drm_dbg_kms(&dev_priv->drm, + if (display->platform.g4x) { + drm_dbg_kms(display->drm, "probing HDMI on SDVOC\n"); - g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); + g4x_hdmi_init(display, GEN4_HDMIC, PORT_C); } - if (IS_G4X(dev_priv)) - g4x_dp_init(dev_priv, DP_C, PORT_C); + if (display->platform.g4x) + g4x_dp_init(display, DP_C, PORT_C); } - if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) - g4x_dp_init(dev_priv, DP_D, PORT_D); + if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED)) + g4x_dp_init(display, DP_D, PORT_D); - if (SUPPORTS_TV(dev_priv)) + if (SUPPORTS_TV(display)) intel_tv_init(display); - } else if (DISPLAY_VER(dev_priv) == 2) { - if (IS_I85X(dev_priv)) + } else if (DISPLAY_VER(display) == 2) { + if (display->platform.i85x) intel_lvds_init(dev_priv); intel_crt_init(display); intel_dvo_init(dev_priv); } - for_each_intel_encoder(&dev_priv->drm, encoder) { + for_each_intel_encoder(display->drm, encoder) { encoder->base.possible_crtcs = intel_encoder_possible_crtcs(encoder); encoder->base.possible_clones = @@ -8293,12 +7821,11 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv) intel_init_pch_refclk(dev_priv); - drm_helper_move_panel_connectors_to_head(&dev_priv->drm); + drm_helper_move_panel_connectors_to_head(display->drm); } -static int max_dotclock(struct drm_i915_private *i915) +static int max_dotclock(struct intel_display *display) { - struct intel_display *display = &i915->display; int max_dotclock = display->cdclk.max_dotclk_freq; if (HAS_ULTRAJOINER(display)) @@ -8312,7 +7839,7 @@ static int max_dotclock(struct drm_i915_private *i915) enum drm_mode_status intel_mode_valid(struct drm_device *dev, const struct drm_display_mode *mode) { - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(dev); int hdisplay_max, htotal_max; int vdisplay_max, vtotal_max; @@ -8349,22 +7876,22 @@ enum drm_mode_status intel_mode_valid(struct drm_device *dev, * Reject clearly excessive dotclocks early to * avoid having to worry about huge integers later. */ - if (mode->clock > max_dotclock(dev_priv)) + if (mode->clock > max_dotclock(display)) return MODE_CLOCK_HIGH; /* Transcoder timing limits */ - if (DISPLAY_VER(dev_priv) >= 11) { + if (DISPLAY_VER(display) >= 11) { hdisplay_max = 16384; vdisplay_max = 8192; htotal_max = 16384; vtotal_max = 8192; - } else if (DISPLAY_VER(dev_priv) >= 9 || - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + } else if (DISPLAY_VER(display) >= 9 || + display->platform.broadwell || display->platform.haswell) { hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ vdisplay_max = 4096; htotal_max = 8192; vtotal_max = 8192; - } else if (DISPLAY_VER(dev_priv) >= 3) { + } else if (DISPLAY_VER(display) >= 3) { hdisplay_max = 4096; vdisplay_max = 4096; htotal_max = 8192; @@ -8391,14 +7918,14 @@ enum drm_mode_status intel_mode_valid(struct drm_device *dev, return MODE_OK; } -enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *dev_priv, +enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display, const struct drm_display_mode *mode) { /* * Additional transcoder timing limits, * excluding BXT/GLK DSI transcoders. */ - if (DISPLAY_VER(dev_priv) >= 5) { + if (DISPLAY_VER(display) >= 5) { if (mode->hdisplay < 64 || mode->htotal - mode->hdisplay < 32) return MODE_H_ILLEGAL; @@ -8417,7 +7944,7 @@ enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *de * Cantiga+ cannot handle modes with a hsync front porch of 0. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. */ - if ((DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) && + if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) && mode->hsync_start == mode->hdisplay) return MODE_H_ILLEGAL; @@ -8425,7 +7952,7 @@ enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *de } enum drm_mode_status -intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, +intel_mode_valid_max_plane_size(struct intel_display *display, const struct drm_display_mode *mode, int num_joined_pipes) { @@ -8435,7 +7962,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, * intel_mode_valid() should be * sufficient on older platforms. */ - if (DISPLAY_VER(dev_priv) < 9) + if (DISPLAY_VER(display) < 9) return MODE_OK; /* @@ -8443,10 +7970,10 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, * plane so let's not advertize modes that are * too big for that. */ - if (DISPLAY_VER(dev_priv) >= 30) { + if (DISPLAY_VER(display) >= 30) { plane_width_max = 6144 * num_joined_pipes; plane_height_max = 4800; - } else if (DISPLAY_VER(dev_priv) >= 11) { + } else if (DISPLAY_VER(display) >= 11) { plane_width_max = 5120 * num_joined_pipes; plane_height_max = 4320; } else { @@ -8510,32 +8037,34 @@ static const struct intel_display_funcs i9xx_display_funcs = { /** * intel_init_display_hooks - initialize the display modesetting hooks - * @dev_priv: device private + * @display: display device private */ -void intel_init_display_hooks(struct drm_i915_private *dev_priv) +void intel_init_display_hooks(struct intel_display *display) { - if (DISPLAY_VER(dev_priv) >= 9) { - dev_priv->display.funcs.display = &skl_display_funcs; - } else if (HAS_DDI(dev_priv)) { - dev_priv->display.funcs.display = &ddi_display_funcs; + struct drm_i915_private *dev_priv = to_i915(display->drm); + + if (DISPLAY_VER(display) >= 9) { + display->funcs.display = &skl_display_funcs; + } else if (HAS_DDI(display)) { + display->funcs.display = &ddi_display_funcs; } else if (HAS_PCH_SPLIT(dev_priv)) { - dev_priv->display.funcs.display = &pch_split_display_funcs; - } else if (IS_CHERRYVIEW(dev_priv) || - IS_VALLEYVIEW(dev_priv)) { - dev_priv->display.funcs.display = &vlv_display_funcs; + display->funcs.display = &pch_split_display_funcs; + } else if (display->platform.cherryview || + display->platform.valleyview) { + display->funcs.display = &vlv_display_funcs; } else { - dev_priv->display.funcs.display = &i9xx_display_funcs; + display->funcs.display = &i9xx_display_funcs; } } -int intel_initial_commit(struct drm_device *dev) +int intel_initial_commit(struct intel_display *display) { struct drm_atomic_state *state = NULL; struct drm_modeset_acquire_ctx ctx; struct intel_crtc *crtc; int ret = 0; - state = drm_atomic_state_alloc(dev); + state = drm_atomic_state_alloc(display->drm); if (!state) return -ENOMEM; @@ -8545,7 +8074,7 @@ int intel_initial_commit(struct drm_device *dev) to_intel_atomic_state(state)->internal = true; retry: - for_each_intel_crtc(dev, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state = intel_atomic_get_crtc_state(state, crtc); @@ -8569,7 +8098,7 @@ retry: */ crtc_state->uapi.color_mgmt_changed = true; - for_each_intel_encoder_mask(dev, encoder, + for_each_intel_encoder_mask(display->drm, encoder, crtc_state->uapi.encoder_mask) { if (encoder->initial_fastset_check && !encoder->initial_fastset_check(encoder, crtc_state)) { @@ -8707,26 +8236,9 @@ void i830_disable_pipe(struct intel_display *display, enum pipe pipe) intel_de_posting_read(display, DPLL(display, pipe)); } -void intel_hpd_poll_fini(struct drm_i915_private *i915) +bool intel_scanout_needs_vtd_wa(struct intel_display *display) { - struct intel_connector *connector; - struct drm_connector_list_iter conn_iter; - - /* Kill all the work that may have been queued by hpd. */ - drm_connector_list_iter_begin(&i915->drm, &conn_iter); - for_each_intel_connector_iter(connector, &conn_iter) { - if (connector->modeset_retry_work.func && - cancel_work_sync(&connector->modeset_retry_work)) - drm_connector_put(&connector->base); - if (connector->hdcp.shim) { - cancel_delayed_work_sync(&connector->hdcp.check_work); - cancel_work_sync(&connector->hdcp.prop_work); - } - } - drm_connector_list_iter_end(&conn_iter); -} + struct drm_i915_private *i915 = to_i915(display->drm); -bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915) -{ - return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915); + return IS_DISPLAY_VER(display, 6, 11) && i915_vtd_active(i915); } diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 49a246feb1ae..3b54a62c290a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -59,8 +59,6 @@ struct intel_link_m_n; struct intel_plane; struct intel_plane_state; struct intel_power_domain_mask; -struct intel_remapped_info; -struct intel_rotation_info; struct pci_dev; struct work_struct; @@ -413,24 +411,22 @@ enum phy_fia { i) int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); -int intel_atomic_add_affected_planes(struct intel_atomic_state *state, - struct intel_crtc *crtc); u8 intel_calc_active_pipes(struct intel_atomic_state *state, u8 active_pipes); void intel_link_compute_m_n(u16 bpp, int nlanes, int pixel_clock, int link_clock, int bw_overhead, struct intel_link_m_n *m_n); -u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, +u32 intel_plane_fb_max_stride(struct drm_device *drm, u32 pixel_format, u64 modifier); enum drm_mode_status -intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, +intel_mode_valid_max_plane_size(struct intel_display *display, const struct drm_display_mode *mode, int num_joined_pipes); enum drm_mode_status -intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915, +intel_cpu_transcoder_mode_valid(struct intel_display *display, const struct drm_display_mode *mode); -enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); +enum phy intel_port_to_phy(struct intel_display *display, enum port port); bool is_trans_port_sync_mode(const struct intel_crtc_state *state); bool is_trans_port_sync_master(const struct intel_crtc_state *state); u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state); @@ -450,7 +446,6 @@ bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, const struct intel_crtc_state *pipe_config, bool fastset); -void intel_plane_destroy(struct drm_plane *plane); void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); @@ -462,25 +457,16 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv, const char *name, u32 reg, int ref_freq); int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, const char *name, u32 reg); -void intel_init_display_hooks(struct drm_i915_private *dev_priv); -unsigned int intel_fb_xy_to_linear(int x, int y, - const struct intel_plane_state *state, - int plane); -void intel_add_fb_offsets(int *x, int *y, - const struct intel_plane_state *state, int plane); -unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); -unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); -bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv); +bool intel_has_pending_fb_unpin(struct intel_display *display); void intel_encoder_destroy(struct drm_encoder *encoder); struct drm_display_mode * intel_encoder_current_mode(struct intel_encoder *encoder); void intel_encoder_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state); -bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy); -bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy); -bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy); -enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, - enum port port); +bool intel_phy_is_combo(struct intel_display *display, enum phy phy); +bool intel_phy_is_tc(struct intel_display *display, enum phy phy); +bool intel_phy_is_snps(struct intel_display *display, enum phy phy); +enum tc_port intel_port_to_tc(struct intel_display *display, enum port port); enum phy intel_encoder_to_phy(struct intel_encoder *encoder); bool intel_encoder_is_combo(struct intel_encoder *encoder); @@ -489,22 +475,19 @@ bool intel_encoder_is_tc(struct intel_encoder *encoder); enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder); int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); -void vlv_wait_port_ready(struct intel_display *display, - struct intel_digital_port *dig_port, - unsigned int expected_mask); bool intel_fuzzy_clock_check(int clock1, int clock2); void intel_zero_m_n(struct intel_link_m_n *m_n); -void intel_set_m_n(struct drm_i915_private *i915, +void intel_set_m_n(struct intel_display *display, const struct intel_link_m_n *m_n, i915_reg_t data_m_reg, i915_reg_t data_n_reg, i915_reg_t link_m_reg, i915_reg_t link_n_reg); -void intel_get_m_n(struct drm_i915_private *i915, +void intel_get_m_n(struct intel_display *display, struct intel_link_m_n *m_n, i915_reg_t data_m_reg, i915_reg_t data_n_reg, i915_reg_t link_m_reg, i915_reg_t link_n_reg); -bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv, +bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, enum transcoder transcoder); void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, enum transcoder cpu_transcoder, @@ -525,13 +508,9 @@ enum intel_display_power_domain intel_aux_power_domain(struct intel_digital_port *dig_port); void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state); -void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); - int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc); unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); -bool intel_plane_uses_fence(const struct intel_plane_state *plane_state); - struct intel_encoder * intel_get_crtc_new_encoder(const struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state); @@ -542,8 +521,6 @@ void intel_set_plane_visible(struct intel_crtc_state *crtc_state, bool visible); void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state); -void intel_update_watermarks(struct drm_i915_private *i915); - bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, struct intel_crtc *crtc); @@ -552,7 +529,7 @@ int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, const char *reason, u8 pipe_mask); int intel_modeset_all_pipes_late(struct intel_atomic_state *state, const char *reason); -int intel_modeset_commit_pipes(struct drm_i915_private *i915, +int intel_modeset_commit_pipes(struct intel_display *display, u8 pipe_mask, struct drm_modeset_acquire_ctx *ctx); void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, @@ -561,25 +538,23 @@ void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, struct intel_power_domain_mask *domains); /* interface for intel_display_driver.c */ -void intel_setup_outputs(struct drm_i915_private *i915); -int intel_initial_commit(struct drm_device *dev); -void intel_panel_sanitize_ssc(struct drm_i915_private *i915); -void intel_update_czclk(struct drm_i915_private *i915); -void intel_atomic_helper_free_state_worker(struct work_struct *work); +void intel_init_display_hooks(struct intel_display *display); +void intel_setup_outputs(struct intel_display *display); +int intel_initial_commit(struct intel_display *display); +void intel_panel_sanitize_ssc(struct intel_display *display); +void intel_update_czclk(struct intel_display *display); enum drm_mode_status intel_mode_valid(struct drm_device *dev, const struct drm_display_mode *mode); int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, bool nonblock); -void intel_hpd_poll_fini(struct drm_i915_private *i915); - /* modesetting asserts */ -void assert_transcoder(struct drm_i915_private *dev_priv, +void assert_transcoder(struct intel_display *display, enum transcoder cpu_transcoder, bool state); #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true) #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false) -bool assert_port_valid(struct drm_i915_private *i915, enum port port); +bool assert_port_valid(struct intel_display *display, enum port port); /* * Use INTEL_DISPLAY_STATE_WARN(x) (rather than WARN() and WARN_ON()) for hw @@ -596,7 +571,7 @@ bool assert_port_valid(struct drm_i915_private *i915, enum port port); unlikely(__ret_warn_on); \ }) -bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915); +bool intel_scanout_needs_vtd_wa(struct intel_display *display); int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state); #endif diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 554870d2494b..eeb7ae3eaea8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -91,6 +91,7 @@ struct intel_wm_funcs { struct intel_crtc *crtc); int (*compute_global_watermarks)(struct intel_atomic_state *state); void (*get_hw_state)(struct drm_i915_private *i915); + void (*sanitize)(struct drm_i915_private *i915); }; struct intel_audio_state { @@ -386,7 +387,6 @@ struct intel_display { struct { /* list of fbdev register on this device */ struct intel_fbdev *fbdev; - struct work_struct suspend_work; } fbdev; struct { @@ -512,6 +512,8 @@ struct intel_display { /* restore state for suspend/resume and display reset */ struct drm_atomic_state *modeset_state; struct drm_modeset_acquire_ctx reset_ctx; + /* modeset stuck tracking for reset */ + atomic_t pending_fb_pin; u32 saveDSPARB; u32 saveSWF0[16]; u32 saveSWF1[16]; diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index f1d76484025a..fdedf65bee53 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -49,11 +49,6 @@ static struct intel_display *node_to_intel_display(struct drm_info_node *node) return to_intel_display(node->minor->dev); } -static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) -{ - return to_i915(node->minor->dev); -} - static int intel_display_caps(struct seq_file *m, void *data) { struct intel_display *display = node_to_intel_display(m->private); @@ -68,44 +63,45 @@ static int intel_display_caps(struct seq_file *m, void *data) static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) { - struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_display *display = node_to_intel_display(m->private); - spin_lock(&dev_priv->display.fb_tracking.lock); + spin_lock(&display->fb_tracking.lock); seq_printf(m, "FB tracking busy bits: 0x%08x\n", - dev_priv->display.fb_tracking.busy_bits); + display->fb_tracking.busy_bits); seq_printf(m, "FB tracking flip bits: 0x%08x\n", - dev_priv->display.fb_tracking.flip_bits); + display->fb_tracking.flip_bits); - spin_unlock(&dev_priv->display.fb_tracking.lock); + spin_unlock(&display->fb_tracking.lock); return 0; } static int i915_sr_status(struct seq_file *m, void *unused) { - struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_display *display = node_to_intel_display(m->private); + struct drm_i915_private *dev_priv = to_i915(display->drm); intel_wakeref_t wakeref; bool sr_enabled = false; - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); + wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); - if (DISPLAY_VER(dev_priv) >= 9) + if (DISPLAY_VER(display) >= 9) /* no global SR status; inspect per-plane WM */; else if (HAS_PCH_SPLIT(dev_priv)) - sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE; - else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || - IS_I945G(dev_priv) || IS_I945GM(dev_priv)) - sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN; - else if (IS_I915GM(dev_priv)) - sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN; - else if (IS_PINEVIEW(dev_priv)) - sr_enabled = intel_de_read(dev_priv, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN; - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; - - intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); + sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE; + else if (display->platform.i965gm || display->platform.g4x || + display->platform.i945g || display->platform.i945gm) + sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN; + else if (display->platform.i915gm) + sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN; + else if (display->platform.pineview) + sr_enabled = intel_de_read(display, DSPFW3(display)) & PINEVIEW_SELF_REFRESH_EN; + else if (display->platform.valleyview || display->platform.cherryview) + sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; + + intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); seq_printf(m, "self-refresh: %s\n", str_enabled_disabled(sr_enabled)); @@ -114,12 +110,11 @@ static int i915_sr_status(struct seq_file *m, void *unused) static int i915_gem_framebuffer_info(struct seq_file *m, void *data) { - struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_display *display = node_to_intel_display(m->private); struct intel_framebuffer *fbdev_fb = NULL; struct drm_framebuffer *drm_fb; -#ifdef CONFIG_DRM_FBDEV_EMULATION - fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev); + fbdev_fb = intel_fbdev_framebuffer(display->fbdev.fbdev); if (fbdev_fb) { seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", fbdev_fb->base.width, @@ -131,10 +126,9 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data) intel_bo_describe(m, intel_fb_bo(&fbdev_fb->base)); seq_putc(m, '\n'); } -#endif - mutex_lock(&dev_priv->drm.mode_config.fb_lock); - drm_for_each_fb(drm_fb, &dev_priv->drm) { + mutex_lock(&display->drm->mode_config.fb_lock); + drm_for_each_fb(drm_fb, display->drm) { struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); if (fb == fbdev_fb) continue; @@ -149,16 +143,16 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data) intel_bo_describe(m, intel_fb_bo(&fb->base)); seq_putc(m, '\n'); } - mutex_unlock(&dev_priv->drm.mode_config.fb_lock); + mutex_unlock(&display->drm->mode_config.fb_lock); return 0; } static int i915_power_domain_info(struct seq_file *m, void *unused) { - struct drm_i915_private *i915 = node_to_i915(m->private); + struct intel_display *display = node_to_intel_display(m->private); - intel_display_power_debug(i915, m); + intel_display_power_debug(display, m); return 0; } @@ -178,14 +172,14 @@ static void intel_encoder_info(struct seq_file *m, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_display *display = node_to_intel_display(m->private); struct drm_connector_list_iter conn_iter; struct drm_connector *connector; seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n", encoder->base.base.id, encoder->base.name); - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); + drm_connector_list_iter_begin(display->drm, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { const struct drm_connector_state *conn_state = connector->state; @@ -213,38 +207,6 @@ static void intel_panel_info(struct seq_file *m, intel_seq_print_mode(m, 2, fixed_mode); } -static void intel_hdcp_info(struct seq_file *m, - struct intel_connector *intel_connector, - bool remote_req) -{ - bool hdcp_cap = false, hdcp2_cap = false; - - if (!intel_connector->hdcp.shim) { - seq_puts(m, "No Connector Support"); - goto out; - } - - if (remote_req) { - intel_hdcp_get_remote_capability(intel_connector, - &hdcp_cap, - &hdcp2_cap); - } else { - hdcp_cap = intel_hdcp_get_capability(intel_connector); - hdcp2_cap = intel_hdcp2_get_capability(intel_connector); - } - - if (hdcp_cap) - seq_puts(m, "HDCP1.4 "); - if (hdcp2_cap) - seq_puts(m, "HDCP2.2 "); - - if (!hdcp_cap && !hdcp2_cap) - seq_puts(m, "None"); - -out: - seq_puts(m, "\n"); -} - static void intel_dp_info(struct seq_file *m, struct intel_connector *connector) { struct intel_encoder *intel_encoder = intel_attached_encoder(connector); @@ -297,7 +259,7 @@ static void intel_connector_info(struct seq_file *m, switch (connector->connector_type) { case DRM_MODE_CONNECTOR_DisplayPort: case DRM_MODE_CONNECTOR_eDP: - if (intel_connector->mst_port) + if (intel_connector->mst.dp) intel_dp_mst_info(m, intel_connector); else intel_dp_info(m, intel_connector); @@ -309,12 +271,7 @@ static void intel_connector_info(struct seq_file *m, break; } - seq_puts(m, "\tHDCP version: "); - if (intel_connector->mst_port) { - intel_hdcp_info(m, intel_connector, true); - seq_puts(m, "\tMST Hub HDCP version: "); - } - intel_hdcp_info(m, intel_connector, false); + intel_hdcp_info(m, intel_connector); seq_printf(m, "\tmax bpc: %u\n", connector->display_info.bpc); @@ -365,8 +322,8 @@ static const char *plane_visibility(const struct intel_plane_state *plane_state) if (plane_state->uapi.visible) return "visible"; - if (plane_state->planar_slave) - return "planar-slave"; + if (plane_state->is_y_plane) + return "Y plane"; return "hidden"; } @@ -399,7 +356,7 @@ static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane) if (plane_state->planar_linked_plane) seq_printf(m, "\t\tplanar: Linked to [PLANE:%d:%s] as a %s\n", plane_state->planar_linked_plane->base.base.id, plane_state->planar_linked_plane->base.name, - plane_state->planar_slave ? "slave" : "master"); + plane_state->is_y_plane ? "Y plane" : "UV plane"); } static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane) @@ -427,10 +384,10 @@ static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane) static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_display *display = node_to_intel_display(m->private); struct intel_plane *plane; - for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { + for_each_intel_plane_on_crtc(display->drm, crtc, plane) { seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n", plane->base.base.id, plane->base.name, plane_type(plane->base.type)); @@ -573,7 +530,7 @@ static void crtc_updates_add(struct intel_crtc *crtc) static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) { - struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_display *display = node_to_intel_display(m->private); struct drm_printer p = drm_seq_file_printer(m); const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); @@ -607,7 +564,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) intel_vdsc_state_dump(&p, 1, crtc_state); - for_each_intel_encoder_mask(&dev_priv->drm, encoder, + for_each_intel_encoder_mask(display->drm, encoder, crtc_state->uapi.encoder_mask) intel_encoder_info(m, crtc, encoder); @@ -622,7 +579,8 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) static int i915_display_info(struct seq_file *m, void *unused) { - struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_display *display = node_to_intel_display(m->private); + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc *crtc; struct drm_connector *connector; struct drm_connector_list_iter conn_iter; @@ -630,22 +588,22 @@ static int i915_display_info(struct seq_file *m, void *unused) wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); - drm_modeset_lock_all(&dev_priv->drm); + drm_modeset_lock_all(display->drm); seq_printf(m, "CRTC info\n"); seq_printf(m, "---------\n"); - for_each_intel_crtc(&dev_priv->drm, crtc) + for_each_intel_crtc(display->drm, crtc) intel_crtc_info(m, crtc); seq_printf(m, "\n"); seq_printf(m, "Connector info\n"); seq_printf(m, "--------------\n"); - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); + drm_connector_list_iter_begin(display->drm, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) intel_connector_info(m, connector); drm_connector_list_iter_end(&conn_iter); - drm_modeset_unlock_all(&dev_priv->drm); + drm_modeset_unlock_all(display->drm); intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); @@ -654,56 +612,56 @@ static int i915_display_info(struct seq_file *m, void *unused) static int i915_display_capabilities(struct seq_file *m, void *unused) { - struct drm_i915_private *i915 = node_to_i915(m->private); + struct intel_display *display = node_to_intel_display(m->private); struct drm_printer p = drm_seq_file_printer(m); - intel_display_device_info_print(DISPLAY_INFO(i915), - DISPLAY_RUNTIME_INFO(i915), &p); + intel_display_device_info_print(DISPLAY_INFO(display), + DISPLAY_RUNTIME_INFO(display), &p); return 0; } static int i915_shared_dplls_info(struct seq_file *m, void *unused) { - struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_display *display = node_to_intel_display(m->private); struct drm_printer p = drm_seq_file_printer(m); struct intel_shared_dpll *pll; int i; - drm_modeset_lock_all(&dev_priv->drm); + drm_modeset_lock_all(display->drm); drm_printf(&p, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n", - dev_priv->display.dpll.ref_clks.nssc, - dev_priv->display.dpll.ref_clks.ssc); + display->dpll.ref_clks.nssc, + display->dpll.ref_clks.ssc); - for_each_shared_dpll(dev_priv, pll, i) { + for_each_shared_dpll(display, pll, i) { drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index, pll->info->name, pll->info->id); drm_printf(&p, " pipe_mask: 0x%x, active: 0x%x, on: %s\n", pll->state.pipe_mask, pll->active_mask, str_yes_no(pll->on)); drm_printf(&p, " tracked hardware state:\n"); - intel_dpll_dump_hw_state(dev_priv, &p, &pll->state.hw_state); + intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state); } - drm_modeset_unlock_all(&dev_priv->drm); + drm_modeset_unlock_all(display->drm); return 0; } static int i915_ddb_info(struct seq_file *m, void *unused) { - struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_display *display = node_to_intel_display(m->private); struct skl_ddb_entry *entry; struct intel_crtc *crtc; - if (DISPLAY_VER(dev_priv) < 9) + if (DISPLAY_VER(display) < 9) return -ENODEV; - drm_modeset_lock_all(&dev_priv->drm); + drm_modeset_lock_all(display->drm); seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); - for_each_intel_crtc(&dev_priv->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); enum pipe pipe = crtc->pipe; @@ -723,16 +681,16 @@ static int i915_ddb_info(struct seq_file *m, void *unused) entry->end, skl_ddb_entry_size(entry)); } - drm_modeset_unlock_all(&dev_priv->drm); + drm_modeset_unlock_all(display->drm); return 0; } static bool -intel_lpsp_power_well_enabled(struct drm_i915_private *i915, +intel_lpsp_power_well_enabled(struct intel_display *display, enum i915_power_well_id power_well_id) { - struct intel_display *display = &i915->display; + struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref; bool is_enabled; @@ -746,15 +704,15 @@ intel_lpsp_power_well_enabled(struct drm_i915_private *i915, static int i915_lpsp_status(struct seq_file *m, void *unused) { - struct drm_i915_private *i915 = node_to_i915(m->private); + struct intel_display *display = node_to_intel_display(m->private); bool lpsp_enabled = false; - if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) { - lpsp_enabled = !intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2); - } else if (IS_DISPLAY_VER(i915, 11, 12)) { - lpsp_enabled = !intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3); - } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { - lpsp_enabled = !intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL); + if (DISPLAY_VER(display) >= 13 || IS_DISPLAY_VER(display, 9, 10)) { + lpsp_enabled = !intel_lpsp_power_well_enabled(display, SKL_DISP_PW_2); + } else if (IS_DISPLAY_VER(display, 11, 12)) { + lpsp_enabled = !intel_lpsp_power_well_enabled(display, ICL_DISP_PW_3); + } else if (display->platform.haswell || display->platform.broadwell) { + lpsp_enabled = !intel_lpsp_power_well_enabled(display, HSW_DISP_PW_GLOBAL); } else { seq_puts(m, "LPSP: not supported\n"); return 0; @@ -767,13 +725,13 @@ static int i915_lpsp_status(struct seq_file *m, void *unused) static int i915_dp_mst_info(struct seq_file *m, void *unused) { - struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_display *display = node_to_intel_display(m->private); struct intel_encoder *intel_encoder; struct intel_digital_port *dig_port; struct drm_connector *connector; struct drm_connector_list_iter conn_iter; - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); + drm_connector_list_iter_begin(display->drm, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) continue; @@ -789,7 +747,7 @@ static int i915_dp_mst_info(struct seq_file *m, void *unused) seq_printf(m, "MST Source Port [ENCODER:%d:%s]\n", dig_port->base.base.base.id, dig_port->base.base.name); - drm_dp_mst_dump_topology(m, &dig_port->dp.mst_mgr); + drm_dp_mst_dump_topology(m, &dig_port->dp.mst.mgr); } drm_connector_list_iter_end(&conn_iter); @@ -801,7 +759,7 @@ i915_fifo_underrun_reset_write(struct file *filp, const char __user *ubuf, size_t cnt, loff_t *ppos) { - struct drm_i915_private *dev_priv = filp->private_data; + struct intel_display *display = filp->private_data; struct intel_crtc *crtc; int ret; bool reset; @@ -813,7 +771,7 @@ i915_fifo_underrun_reset_write(struct file *filp, if (!reset) return cnt; - for_each_intel_crtc(&dev_priv->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct drm_crtc_commit *commit; struct intel_crtc_state *crtc_state; @@ -830,7 +788,7 @@ i915_fifo_underrun_reset_write(struct file *filp, } if (!ret && crtc_state->hw.active) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Re-arming FIFO underruns on pipe %c\n", pipe_name(crtc->pipe)); @@ -843,7 +801,7 @@ i915_fifo_underrun_reset_write(struct file *filp, return ret; } - intel_fbc_reset_underrun(&dev_priv->display); + intel_fbc_reset_underrun(display); return cnt; } @@ -869,13 +827,13 @@ static const struct drm_info_list intel_display_debugfs_list[] = { {"i915_lpsp_status", i915_lpsp_status, 0}, }; -void intel_display_debugfs_register(struct drm_i915_private *i915) +void intel_display_debugfs_register(struct intel_display *display) { - struct intel_display *display = &i915->display; - struct drm_minor *minor = i915->drm.primary; + struct drm_i915_private *i915 = to_i915(display->drm); + struct drm_minor *minor = display->drm->primary; debugfs_create_file("i915_fifo_underrun_reset", 0644, minor->debugfs_root, - to_i915(minor->dev), &i915_fifo_underrun_reset_ops); + display, &i915_fifo_underrun_reset_ops); drm_debugfs_create_files(intel_display_debugfs_list, ARRAY_SIZE(intel_display_debugfs_list), @@ -893,37 +851,10 @@ void intel_display_debugfs_register(struct drm_i915_private *i915) intel_display_debugfs_params(display); } -static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data) -{ - struct intel_connector *connector = m->private; - struct drm_i915_private *i915 = to_i915(connector->base.dev); - int ret; - - ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); - if (ret) - return ret; - - if (!connector->base.encoder || - connector->base.status != connector_status_connected) { - ret = -ENODEV; - goto out; - } - - seq_printf(m, "%s:%d HDCP version: ", connector->base.name, - connector->base.base.id); - intel_hdcp_info(m, connector, false); - -out: - drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); - - return ret; -} -DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability); - static int i915_lpsp_capability_show(struct seq_file *m, void *data) { struct intel_connector *connector = m->private; - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_encoder *encoder = intel_attached_encoder(connector); int connector_type = connector->base.connector_type; bool lpsp_capable = false; @@ -934,24 +865,24 @@ static int i915_lpsp_capability_show(struct seq_file *m, void *data) if (connector->base.status != connector_status_connected) return -ENODEV; - if (DISPLAY_VER(i915) >= 13) + if (DISPLAY_VER(display) >= 13) lpsp_capable = encoder->port <= PORT_B; - else if (DISPLAY_VER(i915) >= 12) + else if (DISPLAY_VER(display) >= 12) /* * Actually TGL can drive LPSP on port till DDI_C * but there is no physical connected DDI_C on TGL sku's, - * even driver is not initilizing DDI_C port for gen12. + * even driver is not initializing DDI_C port for gen12. */ lpsp_capable = encoder->port <= PORT_B; - else if (DISPLAY_VER(i915) == 11) + else if (DISPLAY_VER(display) == 11) lpsp_capable = (connector_type == DRM_MODE_CONNECTOR_DSI || connector_type == DRM_MODE_CONNECTOR_eDP); - else if (IS_DISPLAY_VER(i915, 9, 10)) + else if (IS_DISPLAY_VER(display, 9, 10)) lpsp_capable = (encoder->port == PORT_A && (connector_type == DRM_MODE_CONNECTOR_DSI || connector_type == DRM_MODE_CONNECTOR_eDP || connector_type == DRM_MODE_CONNECTOR_DisplayPort)); - else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) + else if (display->platform.haswell || display->platform.broadwell) lpsp_capable = connector_type == DRM_MODE_CONNECTOR_eDP; seq_printf(m, "LPSP: %s\n", lpsp_capable ? "capable" : "incapable"); @@ -963,7 +894,7 @@ DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability); static int i915_dsc_fec_support_show(struct seq_file *m, void *data) { struct intel_connector *connector = m->private; - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct drm_crtc *crtc; struct intel_dp *intel_dp; struct drm_modeset_acquire_ctx ctx; @@ -975,7 +906,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) do { try_again = false; - ret = drm_modeset_lock(&i915->drm.mode_config.connection_mutex, + ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex, &ctx); if (ret) { if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) { @@ -1036,7 +967,7 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, { struct seq_file *m = file->private_data; struct intel_connector *connector = m->private; - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_encoder *encoder = intel_attached_encoder(connector); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); bool dsc_enable = false; @@ -1045,14 +976,14 @@ static ssize_t i915_dsc_fec_support_write(struct file *file, if (len == 0) return 0; - drm_dbg(&i915->drm, + drm_dbg(display->drm, "Copied %zu bytes from user to force DSC\n", len); ret = kstrtobool_from_user(ubuf, len, &dsc_enable); if (ret < 0) return ret; - drm_dbg(&i915->drm, "Got %s for DSC Enable\n", + drm_dbg(display->drm, "Got %s for DSC Enable\n", (dsc_enable) ? "true" : "false"); intel_dp->force_dsc_en = dsc_enable; @@ -1079,7 +1010,7 @@ static const struct file_operations i915_dsc_fec_support_fops = { static int i915_dsc_bpc_show(struct seq_file *m, void *data) { struct intel_connector *connector = m->private; - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_encoder *encoder = intel_attached_encoder(connector); struct drm_crtc *crtc; struct intel_crtc_state *crtc_state; @@ -1088,7 +1019,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data) if (!encoder) return -ENODEV; - ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); if (ret) return ret; @@ -1101,7 +1032,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data) crtc_state = to_intel_crtc_state(crtc->state); seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component); -out: drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); +out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex); return ret; } @@ -1145,7 +1076,7 @@ static const struct file_operations i915_dsc_bpc_fops = { static int i915_dsc_output_format_show(struct seq_file *m, void *data) { struct intel_connector *connector = m->private; - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_encoder *encoder = intel_attached_encoder(connector); struct drm_crtc *crtc; struct intel_crtc_state *crtc_state; @@ -1154,7 +1085,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data) if (!encoder) return -ENODEV; - ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); if (ret) return ret; @@ -1168,7 +1099,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data) seq_printf(m, "DSC_Output_Format: %s\n", intel_output_format_name(crtc_state->output_format)); -out: drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); +out: drm_modeset_unlock(&display->drm->mode_config.connection_mutex); return ret; } @@ -1212,7 +1143,7 @@ static const struct file_operations i915_dsc_output_format_fops = { static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data) { struct intel_connector *connector = m->private; - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct intel_encoder *encoder = intel_attached_encoder(connector); struct drm_crtc *crtc; struct intel_dp *intel_dp; @@ -1221,7 +1152,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data) if (!encoder) return -ENODEV; - ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); if (ret) return ret; @@ -1236,7 +1167,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data) str_yes_no(intel_dp->force_dsc_fractional_bpp_en)); out: - drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + drm_modeset_unlock(&display->drm->mode_config.connection_mutex); return ret; } @@ -1247,8 +1178,8 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file, { struct seq_file *m = file->private_data; struct intel_connector *connector = m->private; + struct intel_display *display = to_intel_display(connector); struct intel_encoder *encoder = intel_attached_encoder(connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); bool dsc_fractional_bpp_enable = false; int ret; @@ -1256,14 +1187,14 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file, if (len == 0) return 0; - drm_dbg(&i915->drm, + drm_dbg(display->drm, "Copied %zu bytes from user to force fractional bpp for DSC\n", len); ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable); if (ret < 0) return ret; - drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n", + drm_dbg(display->drm, "Got %s for DSC Fractional BPP Enable\n", (dsc_fractional_bpp_enable) ? "true" : "false"); intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable; @@ -1392,7 +1323,7 @@ static const struct file_operations i915_joiner_fops = { */ void intel_connector_debugfs_add(struct intel_connector *connector) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); struct dentry *root = connector->base.debugfs_entry; int connector_type = connector->base.connector_type; @@ -1401,20 +1332,14 @@ void intel_connector_debugfs_add(struct intel_connector *connector) return; intel_drrs_connector_debugfs_add(connector); + intel_hdcp_connector_debugfs_add(connector); intel_pps_connector_debugfs_add(connector); intel_psr_connector_debugfs_add(connector); intel_alpm_lobf_debugfs_add(connector); intel_dp_link_training_debugfs_add(connector); - if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || - connector_type == DRM_MODE_CONNECTOR_HDMIA || - connector_type == DRM_MODE_CONNECTOR_HDMIB) { - debugfs_create_file("i915_hdcp_sink_capability", 0444, root, - connector, &i915_hdcp_sink_capability_fops); - } - - if (DISPLAY_VER(i915) >= 11 && - ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !connector->mst_port) || + if (DISPLAY_VER(display) >= 11 && + ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !connector->mst.dp) || connector_type == DRM_MODE_CONNECTOR_eDP)) { debugfs_create_file("i915_dsc_fec_support", 0644, root, connector, &i915_dsc_fec_support_fops); diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.h b/drivers/gpu/drm/i915/display/intel_display_debugfs.h index e1f479b7acd1..82af2f608111 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.h +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.h @@ -6,16 +6,16 @@ #ifndef __INTEL_DISPLAY_DEBUGFS_H__ #define __INTEL_DISPLAY_DEBUGFS_H__ -struct drm_i915_private; struct intel_connector; struct intel_crtc; +struct intel_display; #ifdef CONFIG_DEBUG_FS -void intel_display_debugfs_register(struct drm_i915_private *i915); +void intel_display_debugfs_register(struct intel_display *display); void intel_connector_debugfs_add(struct intel_connector *connector); void intel_crtc_debugfs_add(struct intel_crtc *crtc); #else -static inline void intel_display_debugfs_register(struct drm_i915_private *i915) {} +static inline void intel_display_debugfs_register(struct intel_display *display) {} static inline void intel_connector_debugfs_add(struct intel_connector *connector) {} static inline void intel_crtc_debugfs_add(struct intel_crtc *crtc) {} #endif diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 68cb7f9b9ef3..738ae522c8f4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1357,6 +1357,12 @@ static const struct intel_display_device_info xe2_hpd_display = { BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), }; +static const u16 mtl_u_ids[] = { + INTEL_MTL_U_IDS(ID), + INTEL_ARL_U_IDS(ID), + 0 +}; + /* * Do not initialize the .info member of the platform desc for GMD ID based * platforms. Their display will be probed automatically based on the IP version @@ -1364,6 +1370,13 @@ static const struct intel_display_device_info xe2_hpd_display = { */ static const struct platform_desc mtl_desc = { PLATFORM(meteorlake), + .subplatforms = (const struct subplatform_desc[]) { + { + SUBPLATFORM(meteorlake, u), + .pciidlist = mtl_u_ids, + }, + {}, + } }; static const struct platform_desc lnl_desc = { diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 9a333d9e6601..717286981687 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -96,6 +96,7 @@ struct pci_dev; func(dg2_g12) \ /* Display ver 14 (based on GMD ID) */ \ func(meteorlake) \ + func(meteorlake_u) \ /* Display ver 20 (based on GMD ID) */ \ func(lunarlake) \ /* Display ver 14.1 (based on GMD ID) */ \ @@ -145,6 +146,7 @@ struct intel_display_platforms { #define HAS_BIGJOINER(__display) (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display)) #define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl) #define HAS_CDCLK_SQUASH(__display) (DISPLAY_INFO(__display)->has_cdclk_squash) +#define HAS_CMTG(__display) (!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13) #define HAS_CUR_FBC(__display) (!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13)) #define HAS_D12_PLANE_MINIMIZATION(__display) ((__display)->platform.rocketlake || (__display)->platform.alderlake_s) #define HAS_DBUF_OVERLAP_DETECTION(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dbuf_overlap_detection) @@ -161,6 +163,7 @@ struct intel_display_platforms { #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dsc) #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0) +#define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30) #define HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg) #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3) #define HAS_GMBUS_IRQ(__display) (DISPLAY_VER(__display) >= 4) @@ -233,6 +236,17 @@ struct intel_display_platforms { (drm_WARN_ON(__to_intel_display(__display)->drm, INTEL_DISPLAY_STEP(__display) == STEP_NONE), \ INTEL_DISPLAY_STEP(__display) >= (since) && INTEL_DISPLAY_STEP(__display) < (until)) +#define ARLS_HOST_BRIDGE_PCI_ID1 0x7D1C +#define ARLS_HOST_BRIDGE_PCI_ID2 0x7D2D +#define ARLS_HOST_BRIDGE_PCI_ID3 0x7D2E +#define ARLS_HOST_BRIDGE_PCI_ID4 0x7D2F + +#define IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(id) \ + (((id) == ARLS_HOST_BRIDGE_PCI_ID1) || \ + ((id) == ARLS_HOST_BRIDGE_PCI_ID2) || \ + ((id) == ARLS_HOST_BRIDGE_PCI_ID3) || \ + ((id) == ARLS_HOST_BRIDGE_PCI_ID4)) + struct intel_display_runtime_info { struct intel_display_ip_ver { u16 ver; diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index 50ec0c3c7588..31740a677dd8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -194,13 +194,13 @@ void intel_display_driver_early_probe(struct intel_display *display) mutex_init(&display->hdcp.hdcp_mutex); intel_display_irq_init(i915); - intel_dkl_phy_init(i915); + intel_dkl_phy_init(display); intel_color_init_hooks(display); intel_init_cdclk_hooks(display); - intel_audio_hooks_init(i915); + intel_audio_hooks_init(display); intel_dpll_init_clock_hook(i915); - intel_init_display_hooks(i915); - intel_fdi_init_hook(i915); + intel_init_display_hooks(display); + intel_fdi_init_hook(display); intel_dmc_wl_init(display); } @@ -431,7 +431,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display) intel_wm_init(i915); - intel_panel_sanitize_ssc(i915); + intel_panel_sanitize_ssc(display); intel_pps_setup(display); @@ -442,18 +442,18 @@ int intel_display_driver_probe_nogem(struct intel_display *display) INTEL_NUM_PIPES(display) > 1 ? "s" : ""); for_each_pipe(display, pipe) { - ret = intel_crtc_init(i915, pipe); + ret = intel_crtc_init(display, pipe); if (ret) goto err_mode_config; } intel_plane_possible_crtcs_init(display); - intel_shared_dpll_init(i915); - intel_fdi_pll_freq_update(i915); + intel_shared_dpll_init(display); + intel_fdi_pll_freq_update(display); - intel_update_czclk(i915); + intel_update_czclk(display); intel_display_driver_init_hw(display); - intel_dpll_update_ref_clks(i915); + intel_dpll_update_ref_clks(display); if (display->cdclk.max_cdclk_freq == 0) intel_update_max_cdclk(display); @@ -462,7 +462,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display) /* Just disable it once at startup */ intel_vga_disable(display); - intel_setup_outputs(i915); + intel_setup_outputs(display); ret = intel_dp_tunnel_mgr_init(display); if (ret) @@ -517,7 +517,7 @@ int intel_display_driver_probe(struct intel_display *display) * are already calculated and there is no assert_plane warnings * during bootup. */ - ret = intel_initial_commit(display->drm); + ret = intel_initial_commit(display); if (ret) drm_dbg_kms(display->drm, "Initial modeset failed, %d\n", ret); @@ -544,13 +544,13 @@ void intel_display_driver_register(struct intel_display *display) intel_opregion_register(display); intel_acpi_video_register(display); - intel_audio_init(i915); + intel_audio_init(display); intel_display_driver_enable_user_access(display); - intel_audio_register(i915); + intel_audio_register(display); - intel_display_debugfs_register(i915); + intel_display_debugfs_register(display); /* * We need to coordinate the hotplugs with the asynchronous @@ -564,6 +564,8 @@ void intel_display_driver_register(struct intel_display *display) intel_display_device_info_print(DISPLAY_INFO(display), DISPLAY_RUNTIME_INFO(display), &p); + + intel_register_dsm_handler(); } /* part #1: call before irq uninstall */ @@ -636,11 +638,11 @@ void intel_display_driver_remove_nogem(struct intel_display *display) void intel_display_driver_unregister(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (!HAS_DISPLAY(display)) return; + intel_unregister_dsm_handler(); + drm_client_dev_unregister(display->drm); /* @@ -652,7 +654,7 @@ void intel_display_driver_unregister(struct intel_display *display) intel_display_driver_disable_user_access(display); - intel_audio_deinit(i915); + intel_audio_deinit(display); drm_atomic_helper_shutdown(display->drm); diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 069043f9d894..aa23bb817805 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -10,11 +10,13 @@ #include "i915_irq.h" #include "i915_reg.h" #include "icl_dsi_regs.h" +#include "intel_atomic_plane.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_irq.h" #include "intel_display_trace.h" #include "intel_display_types.h" +#include "intel_dmc_wl.h" #include "intel_dp_aux.h" #include "intel_dsb.h" #include "intel_fdi_regs.h" @@ -25,6 +27,92 @@ #include "intel_pmdemand.h" #include "intel_psr.h" #include "intel_psr_regs.h" +#include "intel_uncore.h" + +static void +intel_display_irq_regs_init(struct intel_display *display, struct i915_irq_regs regs, + u32 imr_val, u32 ier_val) +{ + intel_dmc_wl_get(display, regs.imr); + intel_dmc_wl_get(display, regs.ier); + intel_dmc_wl_get(display, regs.iir); + + gen2_irq_init(to_intel_uncore(display->drm), regs, imr_val, ier_val); + + intel_dmc_wl_put(display, regs.iir); + intel_dmc_wl_put(display, regs.ier); + intel_dmc_wl_put(display, regs.imr); +} + +static void +intel_display_irq_regs_reset(struct intel_display *display, struct i915_irq_regs regs) +{ + intel_dmc_wl_get(display, regs.imr); + intel_dmc_wl_get(display, regs.ier); + intel_dmc_wl_get(display, regs.iir); + + gen2_irq_reset(to_intel_uncore(display->drm), regs); + + intel_dmc_wl_put(display, regs.iir); + intel_dmc_wl_put(display, regs.ier); + intel_dmc_wl_put(display, regs.imr); +} + +static void +intel_display_irq_regs_assert_irr_is_zero(struct intel_display *display, i915_reg_t reg) +{ + intel_dmc_wl_get(display, reg); + + gen2_assert_iir_is_zero(to_intel_uncore(display->drm), reg); + + intel_dmc_wl_put(display, reg); +} + +struct pipe_fault_handler { + bool (*handle)(struct intel_crtc *crtc, enum plane_id plane_id); + u32 fault; + enum plane_id plane_id; +}; + +static bool handle_plane_fault(struct intel_crtc *crtc, enum plane_id plane_id) +{ + struct intel_display *display = to_intel_display(crtc); + struct intel_plane_error error = {}; + struct intel_plane *plane; + + plane = intel_crtc_get_plane(crtc, plane_id); + if (!plane || !plane->capture_error) + return false; + + plane->capture_error(crtc, plane, &error); + + drm_err_ratelimited(display->drm, + "[CRTC:%d:%s][PLANE:%d:%s] fault (CTL=0x%x, SURF=0x%x, SURFLIVE=0x%x)\n", + crtc->base.base.id, crtc->base.name, + plane->base.base.id, plane->base.name, + error.ctl, error.surf, error.surflive); + + return true; +} + +static void intel_pipe_fault_irq_handler(struct intel_display *display, + const struct pipe_fault_handler *handlers, + enum pipe pipe, u32 fault_errors) +{ + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); + const struct pipe_fault_handler *handler; + + for (handler = handlers; handler && handler->fault; handler++) { + if ((fault_errors & handler->fault) == 0) + continue; + + if (handler->handle(crtc, handler->plane_id)) + fault_errors &= ~handler->fault; + } + + WARN_ONCE(fault_errors, "[CRTC:%d:%s] unreported faults 0x%x\n", + crtc->base.base.id, crtc->base.name, fault_errors); +} static void intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) @@ -44,6 +132,7 @@ intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) void ilk_update_display_irq(struct drm_i915_private *dev_priv, u32 interrupt_mask, u32 enabled_irq_mask) { + struct intel_display *display = &dev_priv->display; u32 new_val; lockdep_assert_held(&dev_priv->irq_lock); @@ -56,8 +145,8 @@ void ilk_update_display_irq(struct drm_i915_private *dev_priv, if (new_val != dev_priv->irq_mask && !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) { dev_priv->irq_mask = new_val; - intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask); - intel_uncore_posting_read(&dev_priv->uncore, DEIMR); + intel_de_write(display, DEIMR, dev_priv->irq_mask); + intel_de_posting_read(display, DEIMR); } } @@ -80,6 +169,7 @@ void ilk_disable_display_irq(struct drm_i915_private *i915, u32 bits) void bdw_update_port_irq(struct drm_i915_private *dev_priv, u32 interrupt_mask, u32 enabled_irq_mask) { + struct intel_display *display = &dev_priv->display; u32 new_val; u32 old_val; @@ -90,15 +180,15 @@ void bdw_update_port_irq(struct drm_i915_private *dev_priv, if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) return; - old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); + old_val = intel_de_read(display, GEN8_DE_PORT_IMR); new_val = old_val; new_val &= ~interrupt_mask; new_val |= (~enabled_irq_mask & interrupt_mask); if (new_val != old_val) { - intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val); - intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); + intel_de_write(display, GEN8_DE_PORT_IMR, new_val); + intel_de_posting_read(display, GEN8_DE_PORT_IMR); } } @@ -113,6 +203,7 @@ static void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, enum pipe pipe, u32 interrupt_mask, u32 enabled_irq_mask) { + struct intel_display *display = &dev_priv->display; u32 new_val; lockdep_assert_held(&dev_priv->irq_lock); @@ -128,9 +219,8 @@ static void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, if (new_val != dev_priv->display.irq.de_irq_mask[pipe]) { dev_priv->display.irq.de_irq_mask[pipe] = new_val; - intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), - dev_priv->display.irq.de_irq_mask[pipe]); - intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); + intel_de_write(display, GEN8_DE_PIPE_IMR(pipe), display->irq.de_irq_mask[pipe]); + intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe)); } } @@ -156,7 +246,8 @@ void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, u32 interrupt_mask, u32 enabled_irq_mask) { - u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR); + struct intel_display *display = &dev_priv->display; + u32 sdeimr = intel_de_read(display, SDEIMR); sdeimr &= ~interrupt_mask; sdeimr |= (~enabled_irq_mask & interrupt_mask); @@ -168,8 +259,8 @@ void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) return; - intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr); - intel_uncore_posting_read(&dev_priv->uncore, SDEIMR); + intel_de_write(display, SDEIMR, sdeimr); + intel_de_posting_read(display, SDEIMR); } void ibx_enable_display_interrupt(struct drm_i915_private *i915, u32 bits) @@ -182,29 +273,30 @@ void ibx_disable_display_interrupt(struct drm_i915_private *i915, u32 bits) ibx_display_interrupt_update(i915, bits, 0); } -u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, +u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe) { - u32 status_mask = dev_priv->display.irq.pipestat_irq_mask[pipe]; + struct drm_i915_private *dev_priv = to_i915(display->drm); + u32 status_mask = display->irq.pipestat_irq_mask[pipe]; u32 enable_mask = status_mask << 16; lockdep_assert_held(&dev_priv->irq_lock); - if (DISPLAY_VER(dev_priv) < 5) + if (DISPLAY_VER(display) < 5) goto out; /* * On pipe A we don't support the PSR interrupt yet, * on pipe B and C the same bit MBZ. */ - if (drm_WARN_ON_ONCE(&dev_priv->drm, + if (drm_WARN_ON_ONCE(display->drm, status_mask & PIPE_A_PSR_STATUS_VLV)) return 0; /* * On pipe B and C we don't support the PSR interrupt yet, on pipe * A the same bit is for perf counters which we don't use either. */ - if (drm_WARN_ON_ONCE(&dev_priv->drm, + if (drm_WARN_ON_ONCE(display->drm, status_mask & PIPE_B_PSR_STATUS_VLV)) return 0; @@ -217,7 +309,7 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; out: - drm_WARN_ONCE(&dev_priv->drm, + drm_WARN_ONCE(display->drm, enable_mask & ~PIPESTAT_INT_ENABLE_MASK || status_mask & ~PIPESTAT_INT_STATUS_MASK, "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", @@ -229,6 +321,7 @@ out: void i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, u32 status_mask) { + struct intel_display *display = &dev_priv->display; i915_reg_t reg = PIPESTAT(dev_priv, pipe); u32 enable_mask; @@ -243,15 +336,16 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv, return; dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask; - enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); + enable_mask = i915_pipestat_enable_mask(display, pipe); - intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); - intel_uncore_posting_read(&dev_priv->uncore, reg); + intel_de_write(display, reg, enable_mask | status_mask); + intel_de_posting_read(display, reg); } void i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, u32 status_mask) { + struct intel_display *display = &dev_priv->display; i915_reg_t reg = PIPESTAT(dev_priv, pipe); u32 enable_mask; @@ -266,10 +360,10 @@ void i915_disable_pipestat(struct drm_i915_private *dev_priv, return; dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask; - enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); + enable_mask = i915_pipestat_enable_mask(display, pipe); - intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); - intel_uncore_posting_read(&dev_priv->uncore, reg); + intel_de_write(display, reg, enable_mask | status_mask); + intel_de_posting_read(display, reg); } static bool i915_has_legacy_blc_interrupt(struct intel_display *display) @@ -373,55 +467,58 @@ static void flip_done_handler(struct drm_i915_private *i915, static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) { + struct intel_display *display = &dev_priv->display; + display_pipe_crc_irq_handler(dev_priv, pipe, - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_HSW(pipe)), + intel_de_read(display, PIPE_CRC_RES_HSW(pipe)), 0, 0, 0, 0); } static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) { + struct intel_display *display = &dev_priv->display; + display_pipe_crc_irq_handler(dev_priv, pipe, - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); + intel_de_read(display, PIPE_CRC_RES_1_IVB(pipe)), + intel_de_read(display, PIPE_CRC_RES_2_IVB(pipe)), + intel_de_read(display, PIPE_CRC_RES_3_IVB(pipe)), + intel_de_read(display, PIPE_CRC_RES_4_IVB(pipe)), + intel_de_read(display, PIPE_CRC_RES_5_IVB(pipe))); } static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) { + struct intel_display *display = &dev_priv->display; u32 res1, res2; if (DISPLAY_VER(dev_priv) >= 3) - res1 = intel_uncore_read(&dev_priv->uncore, - PIPE_CRC_RES_RES1_I915(dev_priv, pipe)); + res1 = intel_de_read(display, PIPE_CRC_RES_RES1_I915(dev_priv, pipe)); else res1 = 0; if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) - res2 = intel_uncore_read(&dev_priv->uncore, - PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)); + res2 = intel_de_read(display, PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)); else res2 = 0; display_pipe_crc_irq_handler(dev_priv, pipe, - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(dev_priv, pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(dev_priv, pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(dev_priv, pipe)), + intel_de_read(display, PIPE_CRC_RES_RED(dev_priv, pipe)), + intel_de_read(display, PIPE_CRC_RES_GREEN(dev_priv, pipe)), + intel_de_read(display, PIPE_CRC_RES_BLUE(dev_priv, pipe)), res1, res2); } static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) { + struct intel_display *display = &dev_priv->display; enum pipe pipe; for_each_pipe(dev_priv, pipe) { - intel_uncore_write(&dev_priv->uncore, - PIPESTAT(dev_priv, pipe), - PIPESTAT_INT_STATUS_MASK | - PIPE_FIFO_UNDERRUN_STATUS); + intel_de_write(display, + PIPESTAT(dev_priv, pipe), + PIPESTAT_INT_STATUS_MASK | PIPE_FIFO_UNDERRUN_STATUS); dev_priv->display.irq.pipestat_irq_mask[pipe] = 0; } @@ -430,6 +527,7 @@ static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, u32 iir, u32 pipe_stats[I915_MAX_PIPES]) { + struct intel_display *display = &dev_priv->display; enum pipe pipe; spin_lock(&dev_priv->irq_lock); @@ -474,8 +572,8 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, continue; reg = PIPESTAT(dev_priv, pipe); - pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask; - enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); + pipe_stats[pipe] = intel_de_read(display, reg) & status_mask; + enable_mask = i915_pipestat_enable_mask(display, pipe); /* * Clear the PIPE*STAT regs before the IIR @@ -487,8 +585,8 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, * an interrupt is still pending. */ if (pipe_stats[pipe]) { - intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]); - intel_uncore_write(&dev_priv->uncore, reg, enable_mask); + intel_de_write(display, reg, pipe_stats[pipe]); + intel_de_write(display, reg, enable_mask); } } spin_unlock(&dev_priv->irq_lock); @@ -512,7 +610,7 @@ void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv, i9xx_pipe_crc_irq_handler(dev_priv, pipe); if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) - intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); + intel_cpu_fifo_underrun_irq_handler(display, pipe); } if (blc_event || (iir & I915_ASLE_INTERRUPT)) @@ -537,7 +635,7 @@ void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv, i9xx_pipe_crc_irq_handler(dev_priv, pipe); if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) - intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); + intel_cpu_fifo_underrun_irq_handler(display, pipe); } if (blc_event || (iir & I915_ASLE_INTERRUPT)) @@ -564,7 +662,7 @@ void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, i9xx_pipe_crc_irq_handler(dev_priv, pipe); if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) - intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); + intel_cpu_fifo_underrun_irq_handler(display, pipe); } if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) @@ -605,7 +703,7 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) for_each_pipe(dev_priv, pipe) drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", pipe_name(pipe), - intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); + intel_de_read(display, FDI_RX_IIR(pipe))); } if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) @@ -616,23 +714,65 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) "PCH transcoder CRC error interrupt\n"); if (pch_iir & SDE_TRANSA_FIFO_UNDER) - intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); + intel_pch_fifo_underrun_irq_handler(display, PIPE_A); if (pch_iir & SDE_TRANSB_FIFO_UNDER) - intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); + intel_pch_fifo_underrun_irq_handler(display, PIPE_B); +} + +static u32 ivb_err_int_pipe_fault_mask(enum pipe pipe) +{ + switch (pipe) { + case PIPE_A: + return ERR_INT_SPRITE_A_FAULT | + ERR_INT_PRIMARY_A_FAULT | + ERR_INT_CURSOR_A_FAULT; + case PIPE_B: + return ERR_INT_SPRITE_B_FAULT | + ERR_INT_PRIMARY_B_FAULT | + ERR_INT_CURSOR_B_FAULT; + case PIPE_C: + return ERR_INT_SPRITE_C_FAULT | + ERR_INT_PRIMARY_C_FAULT | + ERR_INT_CURSOR_C_FAULT; + default: + return 0; + } } +static const struct pipe_fault_handler ivb_pipe_fault_handlers[] = { + { .fault = ERR_INT_SPRITE_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = ERR_INT_PRIMARY_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = ERR_INT_CURSOR_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + { .fault = ERR_INT_SPRITE_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = ERR_INT_PRIMARY_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = ERR_INT_CURSOR_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + { .fault = ERR_INT_SPRITE_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = ERR_INT_PRIMARY_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = ERR_INT_CURSOR_C_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + static void ivb_err_int_handler(struct drm_i915_private *dev_priv) { - u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT); + struct intel_display *display = &dev_priv->display; + u32 err_int = intel_de_read(display, GEN7_ERR_INT); enum pipe pipe; if (err_int & ERR_INT_POISON) drm_err(&dev_priv->drm, "Poison interrupt\n"); + if (err_int & ERR_INT_INVALID_GTT_PTE) + drm_err_ratelimited(display->drm, "Invalid GTT PTE\n"); + + if (err_int & ERR_INT_INVALID_PTE_DATA) + drm_err_ratelimited(display->drm, "Invalid PTE data\n"); + for_each_pipe(dev_priv, pipe) { + u32 fault_errors; + if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) - intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); + intel_cpu_fifo_underrun_irq_handler(display, pipe); if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { if (IS_IVYBRIDGE(dev_priv)) @@ -640,14 +780,20 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv) else hsw_pipe_crc_irq_handler(dev_priv, pipe); } + + fault_errors = err_int & ivb_err_int_pipe_fault_mask(pipe); + if (fault_errors) + intel_pipe_fault_irq_handler(display, ivb_pipe_fault_handlers, + pipe, fault_errors); } - intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int); + intel_de_write(display, GEN7_ERR_INT, err_int); } static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) { - u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT); + struct intel_display *display = &dev_priv->display; + u32 serr_int = intel_de_read(display, SERR_INT); enum pipe pipe; if (serr_int & SERR_INT_POISON) @@ -655,9 +801,9 @@ static void cpt_serr_int_handler(struct drm_i915_private *dev_priv) for_each_pipe(dev_priv, pipe) if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) - intel_pch_fifo_underrun_irq_handler(dev_priv, pipe); + intel_pch_fifo_underrun_irq_handler(display, pipe); - intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int); + intel_de_write(display, SERR_INT, serr_int); } static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) @@ -691,13 +837,63 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir) for_each_pipe(dev_priv, pipe) drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", pipe_name(pipe), - intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); + intel_de_read(display, FDI_RX_IIR(pipe))); } if (pch_iir & SDE_ERROR_CPT) cpt_serr_int_handler(dev_priv); } +static u32 ilk_gtt_fault_pipe_fault_mask(enum pipe pipe) +{ + switch (pipe) { + case PIPE_A: + return GTT_FAULT_SPRITE_A_FAULT | + GTT_FAULT_PRIMARY_A_FAULT | + GTT_FAULT_CURSOR_A_FAULT; + case PIPE_B: + return GTT_FAULT_SPRITE_B_FAULT | + GTT_FAULT_PRIMARY_B_FAULT | + GTT_FAULT_CURSOR_B_FAULT; + default: + return 0; + } +} + +static const struct pipe_fault_handler ilk_pipe_fault_handlers[] = { + { .fault = GTT_FAULT_SPRITE_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = GTT_FAULT_SPRITE_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = GTT_FAULT_PRIMARY_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = GTT_FAULT_PRIMARY_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = GTT_FAULT_CURSOR_A_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + { .fault = GTT_FAULT_CURSOR_B_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static void ilk_gtt_fault_irq_handler(struct intel_display *display) +{ + enum pipe pipe; + u32 gtt_fault; + + gtt_fault = intel_de_read(display, ILK_GTT_FAULT); + intel_de_write(display, ILK_GTT_FAULT, gtt_fault); + + if (gtt_fault & GTT_FAULT_INVALID_GTT_PTE) + drm_err_ratelimited(display->drm, "Invalid GTT PTE\n"); + + if (gtt_fault & GTT_FAULT_INVALID_PTE_DATA) + drm_err_ratelimited(display->drm, "Invalid PTE data\n"); + + for_each_pipe(display, pipe) { + u32 fault_errors; + + fault_errors = gtt_fault & ilk_gtt_fault_pipe_fault_mask(pipe); + if (fault_errors) + intel_pipe_fault_irq_handler(display, ilk_pipe_fault_handlers, + pipe, fault_errors); + } +} + void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) { struct intel_display *display = &dev_priv->display; @@ -716,6 +912,9 @@ void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) if (de_iir & DE_POISON) drm_err(&dev_priv->drm, "Poison interrupt\n"); + if (de_iir & DE_GTT_FAULT) + ilk_gtt_fault_irq_handler(display); + for_each_pipe(dev_priv, pipe) { if (de_iir & DE_PIPE_VBLANK(pipe)) intel_handle_vblank(dev_priv, pipe); @@ -724,7 +923,7 @@ void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) flip_done_handler(dev_priv, pipe); if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) - intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); + intel_cpu_fifo_underrun_irq_handler(display, pipe); if (de_iir & DE_PIPE_CRC_DONE(pipe)) i9xx_pipe_crc_irq_handler(dev_priv, pipe); @@ -732,7 +931,7 @@ void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) /* check event from PCH */ if (de_iir & DE_PCH_EVENT) { - u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); + u32 pch_iir = intel_de_read(display, SDEIIR); if (HAS_PCH_CPT(dev_priv)) cpt_irq_handler(dev_priv, pch_iir); @@ -740,7 +939,7 @@ void ilk_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) ibx_irq_handler(dev_priv, pch_iir); /* should clear PCH hotplug event before clear CPU irq */ - intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); + intel_de_write(display, SDEIIR, pch_iir); } if (DISPLAY_VER(dev_priv) == 5 && de_iir & DE_PCU_EVENT) @@ -766,8 +965,7 @@ void ivb_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) struct intel_dp *intel_dp = enc_to_intel_dp(encoder); u32 psr_iir; - psr_iir = intel_uncore_rmw(&dev_priv->uncore, - EDP_PSR_IIR, 0, 0); + psr_iir = intel_de_rmw(display, EDP_PSR_IIR, 0, 0); intel_psr_irq_handler(intel_dp, psr_iir); break; } @@ -789,12 +987,12 @@ void ivb_display_irq_handler(struct drm_i915_private *dev_priv, u32 de_iir) /* check event from PCH */ if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) { - u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); + u32 pch_iir = intel_de_read(display, SDEIIR); cpt_irq_handler(dev_priv, pch_iir); /* clear PCH hotplug event before clear CPU irq */ - intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); + intel_de_write(display, SDEIIR, pch_iir); } } @@ -856,7 +1054,7 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) GEN9_PIPE_PLANE3_FAULT | GEN9_PIPE_PLANE2_FAULT | GEN9_PIPE_PLANE1_FAULT; - if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) + else if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) return GEN12_PIPEDMC_FAULT | GEN9_PIPE_CURSOR_FAULT | GEN11_PIPE_PLANE5_FAULT | @@ -895,6 +1093,108 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) GEN8_PIPE_PRIMARY_FAULT; } +static bool handle_plane_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id) +{ + struct intel_display *display = to_intel_display(crtc); + + drm_err_ratelimited(display->drm, + "[CRTC:%d:%s] PLANE ATS fault\n", + crtc->base.base.id, crtc->base.name); + + return true; +} + +static bool handle_pipedmc_ats_fault(struct intel_crtc *crtc, enum plane_id plane_id) +{ + struct intel_display *display = to_intel_display(crtc); + + drm_err_ratelimited(display->drm, + "[CRTC:%d:%s] PIPEDMC ATS fault\n", + crtc->base.base.id, crtc->base.name); + + return true; +} + +static bool handle_pipedmc_fault(struct intel_crtc *crtc, enum plane_id plane_id) +{ + struct intel_display *display = to_intel_display(crtc); + + drm_err_ratelimited(display->drm, + "[CRTC:%d:%s] PIPEDMC fault\n", + crtc->base.base.id, crtc->base.name); + + return true; +} + +static const struct pipe_fault_handler mtl_pipe_fault_handlers[] = { + { .fault = MTL_PLANE_ATS_FAULT, .handle = handle_plane_ats_fault, }, + { .fault = MTL_PIPEDMC_ATS_FAULT, .handle = handle_pipedmc_ats_fault, }, + { .fault = GEN12_PIPEDMC_FAULT, .handle = handle_pipedmc_fault, }, + { .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, }, + { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, + { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, + { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, + { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, + { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static const struct pipe_fault_handler tgl_pipe_fault_handlers[] = { + { .fault = GEN12_PIPEDMC_FAULT, .handle = handle_pipedmc_fault, }, + { .fault = GEN11_PIPE_PLANE7_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_7, }, + { .fault = GEN11_PIPE_PLANE6_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_6, }, + { .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, }, + { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, + { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, + { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, + { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, + { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static const struct pipe_fault_handler icl_pipe_fault_handlers[] = { + { .fault = GEN11_PIPE_PLANE7_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_7, }, + { .fault = GEN11_PIPE_PLANE6_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_6, }, + { .fault = GEN11_PIPE_PLANE5_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_5, }, + { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, + { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, + { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, + { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, + { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static const struct pipe_fault_handler skl_pipe_fault_handlers[] = { + { .fault = GEN9_PIPE_PLANE4_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_4, }, + { .fault = GEN9_PIPE_PLANE3_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_3, }, + { .fault = GEN9_PIPE_PLANE2_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_2, }, + { .fault = GEN9_PIPE_PLANE1_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_1, }, + { .fault = GEN9_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static const struct pipe_fault_handler bdw_pipe_fault_handlers[] = { + { .fault = GEN8_PIPE_SPRITE_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = GEN8_PIPE_PRIMARY_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = GEN8_PIPE_CURSOR_FAULT, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static const struct pipe_fault_handler * +gen8_pipe_fault_handlers(struct intel_display *display) +{ + if (DISPLAY_VER(display) >= 14) + return mtl_pipe_fault_handlers; + else if (DISPLAY_VER(display) >= 12) + return tgl_pipe_fault_handlers; + else if (DISPLAY_VER(display) >= 11) + return icl_pipe_fault_handlers; + else if (DISPLAY_VER(display) >= 9) + return skl_pipe_fault_handlers; + else + return bdw_pipe_fault_handlers; +} + static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv) { wake_up_all(&dev_priv->display.pmdemand.waitqueue); @@ -925,8 +1225,7 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) } if (iir & XELPDP_RM_TIMEOUT) { - u32 val = intel_uncore_read(&dev_priv->uncore, - RM_TIMEOUT_REG_CAPTURE); + u32 val = intel_de_read(display, RM_TIMEOUT_REG_CAPTURE); drm_warn(&dev_priv->drm, "Register Access Timeout = 0x%x\n", val); found = true; } @@ -949,7 +1248,7 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) else iir_reg = EDP_PSR_IIR; - psr_iir = intel_uncore_rmw(&dev_priv->uncore, iir_reg, 0, 0); + psr_iir = intel_de_rmw(display, iir_reg, 0, 0); if (psr_iir) found = true; @@ -969,6 +1268,7 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, u32 te_trigger) { + struct intel_display *display = &dev_priv->display; enum pipe pipe = INVALID_PIPE; enum transcoder dsi_trans; enum port port; @@ -978,8 +1278,7 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, * Incase of dual link, TE comes from DSI_1 * this is to check if dual link is enabled */ - val = intel_uncore_read(&dev_priv->uncore, - TRANS_DDI_FUNC_CTL2(dev_priv, TRANSCODER_DSI_0)); + val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(dev_priv, TRANSCODER_DSI_0)); val &= PORT_SYNC_MODE_ENABLE; /* @@ -991,7 +1290,7 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; /* Check if DSI configured in command mode */ - val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans)); + val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)); val = val & OP_MODE_MASK; if (val != CMD_MODE_NO_GATE && val != CMD_MODE_TE_GATE) { @@ -1000,8 +1299,7 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, } /* Get PIPE for handling VBLANK event */ - val = intel_uncore_read(&dev_priv->uncore, - TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans)); + val = intel_de_read(display, TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans)); switch (val & TRANS_DDI_EDP_INPUT_MASK) { case TRANS_DDI_EDP_INPUT_A_ON: pipe = PIPE_A; @@ -1021,7 +1319,7 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, /* clear TE in dsi IIR */ port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; - intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), 0, 0); + intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0); } static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915) @@ -1034,10 +1332,11 @@ static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915) static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_iir, u32 *pica_iir) { + struct intel_display *display = &i915->display; u32 pica_ier = 0; *pica_iir = 0; - *pch_iir = intel_de_read(i915, SDEIIR); + *pch_iir = intel_de_read(display, SDEIIR); if (!*pch_iir) return; @@ -1049,15 +1348,15 @@ static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_i if (*pch_iir & SDE_PICAINTERRUPT) { drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTL); - pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0); - *pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR); - intel_de_write(i915, PICAINTERRUPT_IIR, *pica_iir); + pica_ier = intel_de_rmw(display, PICAINTERRUPT_IER, ~0, 0); + *pica_iir = intel_de_read(display, PICAINTERRUPT_IIR); + intel_de_write(display, PICAINTERRUPT_IIR, *pica_iir); } - intel_de_write(i915, SDEIIR, *pch_iir); + intel_de_write(display, SDEIIR, *pch_iir); if (pica_ier) - intel_de_write(i915, PICAINTERRUPT_IER, pica_ier); + intel_de_write(display, PICAINTERRUPT_IER, pica_ier); } void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) @@ -1069,9 +1368,9 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); if (master_ctl & GEN8_DE_MISC_IRQ) { - iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR); + iir = intel_de_read(display, GEN8_DE_MISC_IIR); if (iir) { - intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir); + intel_de_write(display, GEN8_DE_MISC_IIR, iir); gen8_de_misc_irq_handler(dev_priv, iir); } else { drm_err_ratelimited(&dev_priv->drm, @@ -1080,9 +1379,9 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) } if (DISPLAY_VER(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) { - iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR); + iir = intel_de_read(display, GEN11_DE_HPD_IIR); if (iir) { - intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir); + intel_de_write(display, GEN11_DE_HPD_IIR, iir); gen11_hpd_irq_handler(dev_priv, iir); } else { drm_err_ratelimited(&dev_priv->drm, @@ -1091,11 +1390,11 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) } if (master_ctl & GEN8_DE_PORT_IRQ) { - iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR); + iir = intel_de_read(display, GEN8_DE_PORT_IIR); if (iir) { bool found = false; - intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir); + intel_de_write(display, GEN8_DE_PORT_IIR, iir); if (iir & gen8_de_port_aux_mask(dev_priv)) { intel_dp_aux_irq_handler(display); @@ -1148,14 +1447,14 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) continue; - iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)); + iir = intel_de_read(display, GEN8_DE_PIPE_IIR(pipe)); if (!iir) { drm_err_ratelimited(&dev_priv->drm, "The master control interrupt lied (DE PIPE)!\n"); continue; } - intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); + intel_de_write(display, GEN8_DE_PIPE_IIR(pipe), iir); if (iir & GEN8_PIPE_VBLANK) intel_handle_vblank(dev_priv, pipe); @@ -1178,14 +1477,13 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) hsw_pipe_crc_irq_handler(dev_priv, pipe); if (iir & GEN8_PIPE_FIFO_UNDERRUN) - intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); + intel_cpu_fifo_underrun_irq_handler(display, pipe); fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv); if (fault_errors) - drm_err_ratelimited(&dev_priv->drm, - "Fault errors on pipe %c: 0x%08x\n", - pipe_name(pipe), - fault_errors); + intel_pipe_fault_irq_handler(display, + gen8_pipe_fault_handlers(display), + pipe, fault_errors); } if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && @@ -1221,14 +1519,15 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl) { + struct intel_display *display = &i915->display; u32 iir; if (!(master_ctl & GEN11_GU_MISC_IRQ)) return 0; - iir = intel_de_read(i915, GEN11_GU_MISC_IIR); + iir = intel_de_read(display, GEN11_GU_MISC_IIR); if (likely(iir)) - intel_de_write(i915, GEN11_GU_MISC_IIR, iir); + intel_de_write(display, GEN11_GU_MISC_IIR, iir); return iir; } @@ -1243,6 +1542,7 @@ void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir) void gen11_display_irq_handler(struct drm_i915_private *i915) { + struct intel_display *display = &i915->display; u32 disp_ctl; disable_rpm_wakeref_asserts(&i915->runtime_pm); @@ -1250,17 +1550,18 @@ void gen11_display_irq_handler(struct drm_i915_private *i915) * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ * for the display related bits. */ - disp_ctl = intel_de_read(i915, GEN11_DISPLAY_INT_CTL); + disp_ctl = intel_de_read(display, GEN11_DISPLAY_INT_CTL); - intel_de_write(i915, GEN11_DISPLAY_INT_CTL, 0); + intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0); gen8_de_irq_handler(i915, disp_ctl); - intel_de_write(i915, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); + intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); enable_rpm_wakeref_asserts(&i915->runtime_pm); } static void i915gm_irq_cstate_wa_enable(struct drm_i915_private *i915) { + struct intel_display *display = &i915->display; lockdep_assert_held(&i915->drm.vblank_time_lock); /* @@ -1270,15 +1571,18 @@ static void i915gm_irq_cstate_wa_enable(struct drm_i915_private *i915) * only when vblank/CRC interrupts are actually enabled. */ if (i915->display.irq.vblank_enabled++ == 0) - intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); + intel_de_write(display, SCPD0, + _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); } static void i915gm_irq_cstate_wa_disable(struct drm_i915_private *i915) { + struct intel_display *display = &i915->display; lockdep_assert_held(&i915->drm.vblank_time_lock); if (--i915->display.irq.vblank_enabled == 0) - intel_uncore_write(&i915->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); + intel_de_write(display, SCPD0, + _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); } void i915gm_irq_cstate_wa(struct drm_i915_private *i915, bool enable) @@ -1398,7 +1702,7 @@ void ilk_disable_vblank(struct drm_crtc *crtc) static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, bool enable) { - struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); + struct intel_display *display = to_intel_display(intel_crtc); enum port port; if (!(intel_crtc->mode_flags & @@ -1411,10 +1715,9 @@ static bool gen11_dsi_configure_te(struct intel_crtc *intel_crtc, else port = PORT_A; - intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_MASK_REG(port), DSI_TE_EVENT, - enable ? 0 : DSI_TE_EVENT); + intel_de_rmw(display, DSI_INTR_MASK_REG(port), DSI_TE_EVENT, enable ? 0 : DSI_TE_EVENT); - intel_uncore_rmw(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), 0, 0); + intel_de_rmw(display, DSI_INTR_IDENT_REG(port), 0, 0); return true; } @@ -1481,21 +1784,132 @@ void bdw_disable_vblank(struct drm_crtc *_crtc) schedule_work(&display->irq.vblank_dc_work); } +static u32 vlv_dpinvgtt_pipe_fault_mask(enum pipe pipe) +{ + switch (pipe) { + case PIPE_A: + return SPRITEB_INVALID_GTT_STATUS | + SPRITEA_INVALID_GTT_STATUS | + PLANEA_INVALID_GTT_STATUS | + CURSORA_INVALID_GTT_STATUS; + case PIPE_B: + return SPRITED_INVALID_GTT_STATUS | + SPRITEC_INVALID_GTT_STATUS | + PLANEB_INVALID_GTT_STATUS | + CURSORB_INVALID_GTT_STATUS; + case PIPE_C: + return SPRITEF_INVALID_GTT_STATUS | + SPRITEE_INVALID_GTT_STATUS | + PLANEC_INVALID_GTT_STATUS | + CURSORC_INVALID_GTT_STATUS; + default: + return 0; + } +} + +static const struct pipe_fault_handler vlv_pipe_fault_handlers[] = { + { .fault = SPRITEB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, }, + { .fault = SPRITEA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = PLANEA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = CURSORA_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + { .fault = SPRITED_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, }, + { .fault = SPRITEC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = PLANEB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = CURSORB_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + { .fault = SPRITEF_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE1, }, + { .fault = SPRITEE_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_SPRITE0, }, + { .fault = PLANEC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_PRIMARY, }, + { .fault = CURSORC_INVALID_GTT_STATUS, .handle = handle_plane_fault, .plane_id = PLANE_CURSOR, }, + {} +}; + +static void vlv_page_table_error_irq_ack(struct intel_display *display, u32 *dpinvgtt) +{ + u32 status, enable, tmp; + + tmp = intel_de_read(display, DPINVGTT); + + enable = tmp >> 16; + status = tmp & 0xffff; + + /* + * Despite what the docs claim, the status bits seem to get + * stuck permanently (similar the old PGTBL_ER register), so + * we have to disable and ignore them once set. They do get + * reset if the display power well goes down, so no need to + * track the enable mask explicitly. + */ + *dpinvgtt = status & enable; + enable &= ~status; + + /* customary ack+disable then re-enable to guarantee an edge */ + intel_de_write(display, DPINVGTT, status); + intel_de_write(display, DPINVGTT, enable << 16); +} + +static void vlv_page_table_error_irq_handler(struct intel_display *display, u32 dpinvgtt) +{ + enum pipe pipe; + + for_each_pipe(display, pipe) { + u32 fault_errors; + + fault_errors = dpinvgtt & vlv_dpinvgtt_pipe_fault_mask(pipe); + if (fault_errors) + intel_pipe_fault_irq_handler(display, vlv_pipe_fault_handlers, + pipe, fault_errors); + } +} + +void vlv_display_error_irq_ack(struct intel_display *display, + u32 *eir, u32 *dpinvgtt) +{ + u32 emr; + + *eir = intel_de_read(display, VLV_EIR); + + if (*eir & VLV_ERROR_PAGE_TABLE) + vlv_page_table_error_irq_ack(display, dpinvgtt); + + intel_de_write(display, VLV_EIR, *eir); + + /* + * Toggle all EMR bits to make sure we get an edge + * in the ISR master error bit if we don't clear + * all the EIR bits. + */ + emr = intel_de_read(display, VLV_EMR); + intel_de_write(display, VLV_EMR, 0xffffffff); + intel_de_write(display, VLV_EMR, emr); +} + +void vlv_display_error_irq_handler(struct intel_display *display, + u32 eir, u32 dpinvgtt) +{ + drm_dbg(display->drm, "Master Error, EIR 0x%08x\n", eir); + + if (eir & VLV_ERROR_PAGE_TABLE) + vlv_page_table_error_irq_handler(display, dpinvgtt); +} + static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv) { - struct intel_uncore *uncore = &dev_priv->uncore; + struct intel_display *display = &dev_priv->display; if (IS_CHERRYVIEW(dev_priv)) - intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV); + intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_CHV); else - intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_VLV); + intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_VLV); + + gen2_error_reset(to_intel_uncore(display->drm), + VLV_ERROR_REGS); i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); - intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT(dev_priv), 0, 0); + intel_de_rmw(display, PORT_HOTPLUG_STAT(dev_priv), 0, 0); i9xx_pipestat_irq_reset(dev_priv); - gen2_irq_reset(uncore, VLV_IRQ_REGS); + intel_display_irq_regs_reset(display, VLV_IRQ_REGS); dev_priv->irq_mask = ~0u; } @@ -1507,19 +1921,25 @@ void vlv_display_irq_reset(struct drm_i915_private *dev_priv) void i9xx_display_irq_reset(struct drm_i915_private *i915) { + struct intel_display *display = &i915->display; + if (I915_HAS_HOTPLUG(i915)) { i915_hotplug_interrupt_update(i915, 0xffffffff, 0); - intel_uncore_rmw(&i915->uncore, - PORT_HOTPLUG_STAT(i915), 0, 0); + intel_de_rmw(display, PORT_HOTPLUG_STAT(i915), 0, 0); } i9xx_pipestat_irq_reset(i915); } -void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) +static u32 vlv_error_mask(void) { - struct intel_uncore *uncore = &dev_priv->uncore; + /* TODO enable other errors too? */ + return VLV_ERROR_PAGE_TABLE; +} +void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) +{ + struct intel_display *display = &dev_priv->display; u32 pipestat_mask; u32 enable_mask; enum pipe pipe; @@ -1527,6 +1947,18 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) if (!dev_priv->display.irq.vlv_display_irqs_enabled) return; + if (IS_CHERRYVIEW(dev_priv)) + intel_de_write(display, DPINVGTT, + DPINVGTT_STATUS_MASK_CHV | + DPINVGTT_EN_MASK_CHV); + else + intel_de_write(display, DPINVGTT, + DPINVGTT_STATUS_MASK_VLV | + DPINVGTT_EN_MASK_VLV); + + gen2_error_init(to_intel_uncore(display->drm), + VLV_ERROR_REGS, ~vlv_error_mask()); + pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); @@ -1537,7 +1969,8 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | I915_LPE_PIPE_A_INTERRUPT | - I915_LPE_PIPE_B_INTERRUPT; + I915_LPE_PIPE_B_INTERRUPT | + I915_MASTER_ERROR_INTERRUPT; if (IS_CHERRYVIEW(dev_priv)) enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT | @@ -1547,32 +1980,32 @@ void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv->irq_mask = ~enable_mask; - gen2_irq_init(uncore, VLV_IRQ_REGS, dev_priv->irq_mask, enable_mask); + intel_display_irq_regs_init(display, VLV_IRQ_REGS, dev_priv->irq_mask, enable_mask); } void gen8_display_irq_reset(struct drm_i915_private *dev_priv) { - struct intel_uncore *uncore = &dev_priv->uncore; + struct intel_display *display = &dev_priv->display; enum pipe pipe; if (!HAS_DISPLAY(dev_priv)) return; - intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); - intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); + intel_de_write(display, EDP_PSR_IMR, 0xffffffff); + intel_de_write(display, EDP_PSR_IIR, 0xffffffff); for_each_pipe(dev_priv, pipe) - if (intel_display_power_is_enabled(dev_priv, + if (intel_display_power_is_enabled(display, POWER_DOMAIN_PIPE(pipe))) - gen2_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe)); + intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); - gen2_irq_reset(uncore, GEN8_DE_PORT_IRQ_REGS); - gen2_irq_reset(uncore, GEN8_DE_MISC_IRQ_REGS); + intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS); + intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS); } void gen11_display_irq_reset(struct drm_i915_private *dev_priv) { - struct intel_uncore *uncore = &dev_priv->uncore; + struct intel_display *display = &dev_priv->display; enum pipe pipe; u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_D); @@ -1580,7 +2013,7 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; - intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0); + intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0); if (DISPLAY_VER(dev_priv) >= 12) { enum transcoder trans; @@ -1589,42 +2022,42 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv) enum intel_display_power_domain domain; domain = POWER_DOMAIN_TRANSCODER(trans); - if (!intel_display_power_is_enabled(dev_priv, domain)) + if (!intel_display_power_is_enabled(display, domain)) continue; - intel_uncore_write(uncore, - TRANS_PSR_IMR(dev_priv, trans), - 0xffffffff); - intel_uncore_write(uncore, - TRANS_PSR_IIR(dev_priv, trans), - 0xffffffff); + intel_de_write(display, + TRANS_PSR_IMR(dev_priv, trans), + 0xffffffff); + intel_de_write(display, + TRANS_PSR_IIR(dev_priv, trans), + 0xffffffff); } } else { - intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); - intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff); + intel_de_write(display, EDP_PSR_IMR, 0xffffffff); + intel_de_write(display, EDP_PSR_IIR, 0xffffffff); } for_each_pipe(dev_priv, pipe) - if (intel_display_power_is_enabled(dev_priv, + if (intel_display_power_is_enabled(display, POWER_DOMAIN_PIPE(pipe))) - gen2_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe)); + intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); - gen2_irq_reset(uncore, GEN8_DE_PORT_IRQ_REGS); - gen2_irq_reset(uncore, GEN8_DE_MISC_IRQ_REGS); + intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS); + intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS); if (DISPLAY_VER(dev_priv) >= 14) - gen2_irq_reset(uncore, PICAINTERRUPT_IRQ_REGS); + intel_display_irq_regs_reset(display, PICAINTERRUPT_IRQ_REGS); else - gen2_irq_reset(uncore, GEN11_DE_HPD_IRQ_REGS); + intel_display_irq_regs_reset(display, GEN11_DE_HPD_IRQ_REGS); if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) - gen2_irq_reset(uncore, SDE_IRQ_REGS); + intel_display_irq_regs_reset(display, SDE_IRQ_REGS); } void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, u8 pipe_mask) { - struct intel_uncore *uncore = &dev_priv->uncore; + struct intel_display *display = &dev_priv->display; u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN | gen8_de_pipe_flip_done_mask(dev_priv); enum pipe pipe; @@ -1637,9 +2070,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, } for_each_pipe_masked(dev_priv, pipe, pipe_mask) - gen2_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe), - dev_priv->display.irq.de_irq_mask[pipe], - ~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier); + intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), + dev_priv->display.irq.de_irq_mask[pipe], + ~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier); spin_unlock_irq(&dev_priv->irq_lock); } @@ -1647,7 +2080,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, u8 pipe_mask) { - struct intel_uncore *uncore = &dev_priv->uncore; + struct intel_display *display = &dev_priv->display; enum pipe pipe; spin_lock_irq(&dev_priv->irq_lock); @@ -1658,7 +2091,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, } for_each_pipe_masked(dev_priv, pipe, pipe_mask) - gen2_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe)); + intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); spin_unlock_irq(&dev_priv->irq_lock); @@ -1679,7 +2112,7 @@ void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, */ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) { - struct intel_uncore *uncore = &dev_priv->uncore; + struct intel_display *display = &dev_priv->display; u32 mask; if (HAS_PCH_NOP(dev_priv)) @@ -1692,7 +2125,7 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv) else mask = SDE_GMBUS_CPT; - gen2_irq_init(uncore, SDE_IRQ_REGS, ~mask, 0xffffffff); + intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); } void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) @@ -1725,7 +2158,7 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) void ilk_de_irq_postinstall(struct drm_i915_private *i915) { - struct intel_uncore *uncore = &i915->uncore; + struct intel_display *display = &i915->display; u32 display_mask, extra_mask; if (DISPLAY_VER(i915) >= 7) { @@ -1738,7 +2171,8 @@ void ilk_de_irq_postinstall(struct drm_i915_private *i915) DE_PLANE_FLIP_DONE_IVB(PLANE_A) | DE_DP_A_HOTPLUG_IVB); } else { - display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | + display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | + DE_PCH_EVENT | DE_GTT_FAULT | DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | DE_POISON); extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | @@ -1749,7 +2183,7 @@ void ilk_de_irq_postinstall(struct drm_i915_private *i915) } if (IS_HASWELL(i915)) { - gen2_assert_iir_is_zero(uncore, EDP_PSR_IIR); + intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR); display_mask |= DE_EDP_PSR_INT_HSW; } @@ -1760,8 +2194,8 @@ void ilk_de_irq_postinstall(struct drm_i915_private *i915) ibx_irq_postinstall(i915); - gen2_irq_init(uncore, DE_IRQ_REGS, i915->irq_mask, - display_mask | extra_mask); + intel_display_irq_regs_init(display, DE_IRQ_REGS, i915->irq_mask, + display_mask | extra_mask); } static void mtp_irq_postinstall(struct drm_i915_private *i915); @@ -1770,7 +2204,6 @@ static void icp_irq_postinstall(struct drm_i915_private *i915); void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) { struct intel_display *display = &dev_priv->display; - struct intel_uncore *uncore = &dev_priv->uncore; u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | GEN8_PIPE_CDCLK_CRC_DONE; @@ -1833,80 +2266,84 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) enum intel_display_power_domain domain; domain = POWER_DOMAIN_TRANSCODER(trans); - if (!intel_display_power_is_enabled(dev_priv, domain)) + if (!intel_display_power_is_enabled(display, domain)) continue; - gen2_assert_iir_is_zero(uncore, - TRANS_PSR_IIR(dev_priv, trans)); + intel_display_irq_regs_assert_irr_is_zero(display, + TRANS_PSR_IIR(dev_priv, trans)); } } else { - gen2_assert_iir_is_zero(uncore, EDP_PSR_IIR); + intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR); } for_each_pipe(dev_priv, pipe) { dev_priv->display.irq.de_irq_mask[pipe] = ~de_pipe_masked; - if (intel_display_power_is_enabled(dev_priv, + if (intel_display_power_is_enabled(display, POWER_DOMAIN_PIPE(pipe))) - gen2_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe), - dev_priv->display.irq.de_irq_mask[pipe], - de_pipe_enables); + intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), + dev_priv->display.irq.de_irq_mask[pipe], + de_pipe_enables); } - gen2_irq_init(uncore, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, de_port_enables); - gen2_irq_init(uncore, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, de_misc_masked); + intel_display_irq_regs_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, + de_port_enables); + intel_display_irq_regs_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, + de_misc_masked); if (IS_DISPLAY_VER(dev_priv, 11, 13)) { u32 de_hpd_masked = 0; u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK; - gen2_irq_init(uncore, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, - de_hpd_enables); + intel_display_irq_regs_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, + de_hpd_enables); } } static void mtp_irq_postinstall(struct drm_i915_private *i915) { - struct intel_uncore *uncore = &i915->uncore; + struct intel_display *display = &i915->display; u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT; u32 de_hpd_mask = XELPDP_AUX_TC_MASK; u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK; - gen2_irq_init(uncore, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, - de_hpd_enables); + intel_display_irq_regs_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, + de_hpd_enables); - gen2_irq_init(uncore, SDE_IRQ_REGS, ~sde_mask, 0xffffffff); + intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff); } static void icp_irq_postinstall(struct drm_i915_private *dev_priv) { - struct intel_uncore *uncore = &dev_priv->uncore; + struct intel_display *display = &dev_priv->display; u32 mask = SDE_GMBUS_ICP; - gen2_irq_init(uncore, SDE_IRQ_REGS, ~mask, 0xffffffff); + intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); } void gen11_de_irq_postinstall(struct drm_i915_private *dev_priv) { + struct intel_display *display = &dev_priv->display; + if (!HAS_DISPLAY(dev_priv)) return; gen8_de_irq_postinstall(dev_priv); - intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, - GEN11_DISPLAY_IRQ_ENABLE); + intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); } void dg1_de_irq_postinstall(struct drm_i915_private *i915) { + struct intel_display *display = &i915->display; + if (!HAS_DISPLAY(i915)) return; gen8_de_irq_postinstall(i915); - intel_uncore_write(&i915->uncore, GEN11_DISPLAY_INT_CTL, - GEN11_DISPLAY_IRQ_ENABLE); + intel_de_write(display, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); } void intel_display_irq_init(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h index b077712b7be1..d9867cd0a220 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.h +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h @@ -11,8 +11,9 @@ #include "intel_display_limits.h" enum pipe; -struct drm_i915_private; struct drm_crtc; +struct drm_i915_private; +struct intel_display; void valleyview_enable_display_irqs(struct drm_i915_private *i915); void valleyview_disable_display_irqs(struct drm_i915_private *i915); @@ -64,7 +65,7 @@ void gen8_de_irq_postinstall(struct drm_i915_private *i915); void gen11_de_irq_postinstall(struct drm_i915_private *i915); void dg1_de_irq_postinstall(struct drm_i915_private *i915); -u32 i915_pipestat_enable_mask(struct drm_i915_private *i915, enum pipe pipe); +u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe); void i915_enable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask); void i915_disable_pipestat(struct drm_i915_private *i915, enum pipe pipe, u32 status_mask); void i915_enable_asle_pipestat(struct drm_i915_private *i915); @@ -75,6 +76,9 @@ void i915_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_ void i965_pipestat_irq_handler(struct drm_i915_private *i915, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); void valleyview_pipestat_irq_handler(struct drm_i915_private *i915, u32 pipe_stats[I915_MAX_PIPES]); +void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt); +void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt); + void intel_display_irq_init(struct drm_i915_private *i915); void i915gm_irq_cstate_wa(struct drm_i915_private *i915, bool enable); diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index f92e4640a613..c4f1ab43fc0c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -130,7 +130,7 @@ intel_display_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400, intel_display_param_named_unsafe(enable_dmc_wl, int, 0400, "Enable DMC wakelock " - "(-1=use per-chip default, 0=disabled, 1=enabled) " + "(-1=use per-chip default, 0=disabled, 1=enabled, 2=match any register, 3=always locked) " "Default: -1"); __maybe_unused diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index d3b8453a1705..f7171e6932dc 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -224,7 +224,7 @@ static bool __intel_display_power_is_enabled(struct intel_display *display, /** * intel_display_power_is_enabled - check for a power domain - * @dev_priv: i915 device instance + * @display: display device instance * @domain: power domain to check * * This function can be used to check the hw power domain state. It is mostly @@ -239,10 +239,9 @@ static bool __intel_display_power_is_enabled(struct intel_display *display, * Returns: * True when the power domain is enabled, false otherwise. */ -bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, +bool intel_display_power_is_enabled(struct intel_display *display, enum intel_display_power_domain domain) { - struct intel_display *display = &dev_priv->display; struct i915_power_domains *power_domains = &display->power.domains; bool ret; @@ -500,7 +499,7 @@ __intel_display_power_get_domain(struct intel_display *display, /** * intel_display_power_get - grab a power domain reference - * @dev_priv: i915 device instance + * @display: display device instance * @domain: power domain to reference * * This function grabs a power domain reference for @domain and ensures that the @@ -510,10 +509,10 @@ __intel_display_power_get_domain(struct intel_display *display, * Any power domain reference obtained by this function must have a symmetric * call to intel_display_power_put() to release the reference again. */ -intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, +intel_wakeref_t intel_display_power_get(struct intel_display *display, enum intel_display_power_domain domain) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); @@ -526,7 +525,7 @@ intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, /** * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain - * @dev_priv: i915 device instance + * @display: display device instance * @domain: power domain to reference * * This function grabs a power domain reference for @domain and ensures that the @@ -537,10 +536,10 @@ intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, * call to intel_display_power_put() to release the reference again. */ intel_wakeref_t -intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, +intel_display_power_get_if_enabled(struct intel_display *display, enum intel_display_power_domain domain) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; intel_wakeref_t wakeref; bool is_enabled; @@ -696,7 +695,7 @@ out_verify: /** * __intel_display_power_put_async - release a power domain reference asynchronously - * @i915: i915 device instance + * @display: display device instance * @domain: power domain to reference * @wakeref: wakeref acquired for the reference that is being released * @delay_ms: delay of powering down the power domain @@ -707,12 +706,12 @@ out_verify: * The power down is delayed by @delay_ms if this is >= 0, or by a default * 100 ms otherwise. */ -void __intel_display_power_put_async(struct drm_i915_private *i915, +void __intel_display_power_put_async(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref, int delay_ms) { - struct intel_display *display = &i915->display; + struct drm_i915_private *i915 = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; struct intel_runtime_pm *rpm = &i915->runtime_pm; intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm); @@ -754,7 +753,7 @@ out_verify: /** * intel_display_power_flush_work - flushes the async display power disabling work - * @i915: i915 device instance + * @display: display device instance * * Flushes any pending work that was scheduled by a preceding * intel_display_power_put_async() call, completing the disabling of the @@ -764,9 +763,9 @@ out_verify: * function returns; to ensure that the work handler isn't running use * intel_display_power_flush_work_sync() instead. */ -void intel_display_power_flush_work(struct drm_i915_private *i915) +void intel_display_power_flush_work(struct intel_display *display) { - struct intel_display *display = &i915->display; + struct drm_i915_private *i915 = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; struct intel_power_domain_mask async_put_mask; intel_wakeref_t work_wakeref; @@ -800,10 +799,9 @@ out_verify: static void intel_display_power_flush_work_sync(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; - intel_display_power_flush_work(i915); + intel_display_power_flush_work(display); cancel_async_put_work(power_domains, true); verify_async_put_domains_state(power_domains); @@ -814,7 +812,7 @@ intel_display_power_flush_work_sync(struct intel_display *display) #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) /** * intel_display_power_put - release a power domain reference - * @dev_priv: i915 device instance + * @display: display device instance * @domain: power domain to reference * @wakeref: wakeref acquired for the reference that is being released * @@ -822,11 +820,11 @@ intel_display_power_flush_work_sync(struct intel_display *display) * intel_display_power_get() and might power down the corresponding hardware * block right away if this is the last reference. */ -void intel_display_power_put(struct drm_i915_private *dev_priv, +void intel_display_power_put(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); __intel_display_power_put(display, domain); intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); @@ -834,7 +832,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, #else /** * intel_display_power_put_unchecked - release an unchecked power domain reference - * @dev_priv: i915 device instance + * @display: display device instance * @domain: power domain to reference * * This function drops the power domain reference obtained by @@ -842,13 +840,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, * block right away if this is the last reference. * * This function is only for the power domain code's internal use to suppress wakeref - * tracking when the correspondig debug kconfig option is disabled, should not + * tracking when the corresponding debug kconfig option is disabled, should not * be used otherwise. */ -void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, +void intel_display_power_put_unchecked(struct intel_display *display, enum intel_display_power_domain domain) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); __intel_display_power_put(display, domain); intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); @@ -856,16 +854,15 @@ void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, #endif void -intel_display_power_get_in_set(struct drm_i915_private *i915, +intel_display_power_get_in_set(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, enum intel_display_power_domain domain) { - struct intel_display *display = &i915->display; intel_wakeref_t __maybe_unused wf; drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); - wf = intel_display_power_get(i915, domain); + wf = intel_display_power_get(display, domain); #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) power_domain_set->wakerefs[domain] = wf; #endif @@ -873,16 +870,15 @@ intel_display_power_get_in_set(struct drm_i915_private *i915, } bool -intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, +intel_display_power_get_in_set_if_enabled(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, enum intel_display_power_domain domain) { - struct intel_display *display = &i915->display; intel_wakeref_t wf; drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); - wf = intel_display_power_get_if_enabled(i915, domain); + wf = intel_display_power_get_if_enabled(display, domain); if (!wf) return false; @@ -895,11 +891,10 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, } void -intel_display_power_put_mask_in_set(struct drm_i915_private *i915, +intel_display_power_put_mask_in_set(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, struct intel_power_domain_mask *mask) { - struct intel_display *display = &i915->display; enum intel_display_power_domain domain; drm_WARN_ON(display->drm, @@ -911,7 +906,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915, #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) wf = fetch_and_zero(&power_domain_set->wakerefs[domain]); #endif - intel_display_power_put(i915, domain, wf); + intel_display_power_put(display, domain, wf); clear_bit(domain, power_domain_set->mask.bits); } } @@ -999,7 +994,7 @@ static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc) * intel_power_domains_init - initializes the power domain structures * @display: display device instance * - * Initializes the power domain structures for @dev_priv depending upon the + * Initializes the power domain structures for @display depending upon the * supported platform. */ int intel_power_domains_init(struct intel_display *display) @@ -1061,10 +1056,9 @@ static void gen9_dbuf_slice_set(struct intel_display *display, slice, str_enable_disable(enable)); } -void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, +void gen9_dbuf_slices_update(struct intel_display *display, u8 req_slices) { - struct intel_display *display = &dev_priv->display; struct i915_power_domains *power_domains = &display->power.domains; u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask; enum dbuf_slice slice; @@ -1095,10 +1089,9 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, static void gen9_dbuf_enable(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u8 slices_mask; - display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); + display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(display); slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices; @@ -1109,14 +1102,12 @@ static void gen9_dbuf_enable(struct intel_display *display) * Just power up at least 1 slice, we will * figure out later which slices we have and what we need. */ - gen9_dbuf_slices_update(dev_priv, slices_mask); + gen9_dbuf_slices_update(display, slices_mask); } static void gen9_dbuf_disable(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - gen9_dbuf_slices_update(dev_priv, 0); + gen9_dbuf_slices_update(display, 0); if (DISPLAY_VER(display) >= 14) intel_pmdemand_program_dbuf(display, 0); @@ -1126,9 +1117,6 @@ static void gen12_dbuf_slices_config(struct intel_display *display) { enum dbuf_slice slice; - if (display->platform.alderlake_p) - return; - for_each_dbuf_slice(display, slice) intel_de_rmw(display, DBUF_CTL_S(slice), DBUF_TRACKER_STATE_SERVICE_MASK, @@ -1663,7 +1651,7 @@ static void icl_display_core_init(struct intel_display *display, return; /* 2. Initialize all combo phys */ - intel_combo_phy_init(dev_priv); + intel_combo_phy_init(display); /* * 3. Enable Power Well 1 (PG1). @@ -1681,7 +1669,7 @@ static void icl_display_core_init(struct intel_display *display, /* 4. Enable CDCLK. */ intel_cdclk_init_hw(display); - if (DISPLAY_VER(display) >= 12) + if (DISPLAY_VER(display) == 12 || display->platform.dg2) gen12_dbuf_slices_config(display); /* 5. Enable DBUF. */ @@ -1696,7 +1684,7 @@ static void icl_display_core_init(struct intel_display *display, /* 8. Ensure PHYs have completed calibration and adaptation */ if (display->platform.dg2) - intel_snps_phy_wait_for_calibration(dev_priv); + intel_snps_phy_wait_for_calibration(display); /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */ if (DISPLAY_VERx100(display) == 1401) @@ -1726,7 +1714,6 @@ static void icl_display_core_init(struct intel_display *display, static void icl_display_core_uninit(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; struct i915_power_well *well; @@ -1736,7 +1723,7 @@ static void icl_display_core_uninit(struct intel_display *display) gen9_disable_dc_states(display); intel_dmc_disable_program(display); - /* 1. Disable all display engine functions -> aready done */ + /* 1. Disable all display engine functions -> already done */ /* 2. Disable DBUF */ gen9_dbuf_disable(display); @@ -1759,7 +1746,7 @@ static void icl_display_core_uninit(struct intel_display *display) mutex_unlock(&power_domains->lock); /* 5. */ - intel_combo_phy_uninit(dev_priv); + intel_combo_phy_uninit(display); } static void chv_phy_control_init(struct intel_display *display) @@ -1966,12 +1953,12 @@ void intel_power_domains_init_hw(struct intel_display *display, bool resume) */ drm_WARN_ON(display->drm, power_domains->init_wakeref); power_domains->init_wakeref = - intel_display_power_get(i915, POWER_DOMAIN_INIT); + intel_display_power_get(display, POWER_DOMAIN_INIT); /* Disable power support if the user asked so. */ if (!display->params.disable_power_well) { drm_WARN_ON(display->drm, power_domains->disable_wakeref); - display->power.domains.disable_wakeref = intel_display_power_get(i915, + display->power.domains.disable_wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); } intel_power_domains_sync_hw(display); @@ -1998,7 +1985,7 @@ void intel_power_domains_driver_remove(struct intel_display *display) /* Remove the refcount we took to keep power well support disabled. */ if (!display->params.disable_power_well) - intel_display_power_put(i915, POWER_DOMAIN_INIT, + intel_display_power_put(display, POWER_DOMAIN_INIT, fetch_and_zero(&display->power.domains.disable_wakeref)); intel_display_power_flush_work_sync(display); @@ -2054,11 +2041,10 @@ void intel_power_domains_sanitize_state(struct intel_display *display) */ void intel_power_domains_enable(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref __maybe_unused = fetch_and_zero(&display->power.domains.init_wakeref); - intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); + intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); intel_power_domains_verify_state(display); } @@ -2071,12 +2057,11 @@ void intel_power_domains_enable(struct intel_display *display) */ void intel_power_domains_disable(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; drm_WARN_ON(display->drm, power_domains->init_wakeref); power_domains->init_wakeref = - intel_display_power_get(i915, POWER_DOMAIN_INIT); + intel_display_power_get(display, POWER_DOMAIN_INIT); intel_power_domains_verify_state(display); } @@ -2094,12 +2079,11 @@ void intel_power_domains_disable(struct intel_display *display) */ void intel_power_domains_suspend(struct intel_display *display, bool s2idle) { - struct drm_i915_private *i915 = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; intel_wakeref_t wakeref __maybe_unused = fetch_and_zero(&power_domains->init_wakeref); - intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); + intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); /* * In case of suspend-to-idle (aka S0ix) on a DMC platform without DC9 @@ -2110,7 +2094,7 @@ void intel_power_domains_suspend(struct intel_display *display, bool s2idle) */ if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle && intel_dmc_has_payload(display)) { - intel_display_power_flush_work(i915); + intel_display_power_flush_work(display); intel_power_domains_verify_state(display); return; } @@ -2120,10 +2104,10 @@ void intel_power_domains_suspend(struct intel_display *display, bool s2idle) * power wells if power domains must be deinitialized for suspend. */ if (!display->params.disable_power_well) - intel_display_power_put(i915, POWER_DOMAIN_INIT, + intel_display_power_put(display, POWER_DOMAIN_INIT, fetch_and_zero(&display->power.domains.disable_wakeref)); - intel_display_power_flush_work(i915); + intel_display_power_flush_work(display); intel_power_domains_verify_state(display); if (DISPLAY_VER(display) >= 11) @@ -2148,7 +2132,6 @@ void intel_power_domains_suspend(struct intel_display *display, bool s2idle) */ void intel_power_domains_resume(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; if (power_domains->display_core_suspended) { @@ -2157,7 +2140,7 @@ void intel_power_domains_resume(struct intel_display *display) } else { drm_WARN_ON(display->drm, power_domains->init_wakeref); power_domains->init_wakeref = - intel_display_power_get(i915, POWER_DOMAIN_INIT); + intel_display_power_get(display, POWER_DOMAIN_INIT); } intel_power_domains_verify_state(display); @@ -2327,14 +2310,16 @@ void intel_display_power_resume(struct intel_display *display) } } -void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m) +void intel_display_power_debug(struct intel_display *display, struct seq_file *m) { - struct intel_display *display = &i915->display; struct i915_power_domains *power_domains = &display->power.domains; int i; mutex_lock(&power_domains->lock); + seq_printf(m, "Runtime power status: %s\n", + str_enabled_disabled(!power_domains->init_wakeref)); + seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); for (i = 0; i < power_domains->power_well_count; i++) { struct i915_power_well *power_well; @@ -2510,9 +2495,8 @@ intel_port_domains_for_port(struct intel_display *display, enum port port) } enum intel_display_power_domain -intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port) +intel_display_power_ddi_io_domain(struct intel_display *display, enum port port) { - struct intel_display *display = &i915->display; const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) @@ -2522,9 +2506,8 @@ intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port) } enum intel_display_power_domain -intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port) +intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port) { - struct intel_display *display = &i915->display; const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) @@ -2549,9 +2532,8 @@ intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch) } enum intel_display_power_domain -intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) +intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch) { - struct intel_display *display = &i915->display; const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) @@ -2561,9 +2543,8 @@ intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux } enum intel_display_power_domain -intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) +intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch) { - struct intel_display *display = &i915->display; const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) @@ -2573,9 +2554,8 @@ intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch } enum intel_display_power_domain -intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) +intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch) { - struct intel_display *display = &i915->display; const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 7b294eec4431..1b53d67f9b60 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -13,7 +13,6 @@ enum aux_ch; enum port; -struct drm_i915_private; struct i915_power_well; struct intel_display; struct intel_encoder; @@ -118,12 +117,13 @@ enum intel_display_power_domain { POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM, }; -#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) +#define POWER_DOMAIN_PIPE(pipe) \ + ((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_A)) #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ - ((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A) + ((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_PANEL_FITTER_A)) #define POWER_DOMAIN_TRANSCODER(tran) \ ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ - (tran) + POWER_DOMAIN_TRANSCODER_A) + (enum intel_display_power_domain)((tran) - TRANSCODER_A + POWER_DOMAIN_TRANSCODER_A)) struct intel_power_domain_mask { DECLARE_BITMAP(bits, POWER_DOMAIN_NUM); @@ -184,102 +184,102 @@ void intel_display_power_resume(struct intel_display *display); void intel_display_power_set_target_dc_state(struct intel_display *display, u32 state); -bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, +bool intel_display_power_is_enabled(struct intel_display *display, enum intel_display_power_domain domain); -intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, +intel_wakeref_t intel_display_power_get(struct intel_display *display, enum intel_display_power_domain domain); intel_wakeref_t -intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, +intel_display_power_get_if_enabled(struct intel_display *display, enum intel_display_power_domain domain); -void __intel_display_power_put_async(struct drm_i915_private *i915, +void __intel_display_power_put_async(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref, int delay_ms); -void intel_display_power_flush_work(struct drm_i915_private *i915); +void intel_display_power_flush_work(struct intel_display *display); #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) -void intel_display_power_put(struct drm_i915_private *dev_priv, +void intel_display_power_put(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref); static inline void -intel_display_power_put_async(struct drm_i915_private *i915, +intel_display_power_put_async(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref) { - __intel_display_power_put_async(i915, domain, wakeref, -1); + __intel_display_power_put_async(display, domain, wakeref, -1); } static inline void -intel_display_power_put_async_delay(struct drm_i915_private *i915, +intel_display_power_put_async_delay(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref, int delay_ms) { - __intel_display_power_put_async(i915, domain, wakeref, delay_ms); + __intel_display_power_put_async(display, domain, wakeref, delay_ms); } #else -void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, +void intel_display_power_put_unchecked(struct intel_display *display, enum intel_display_power_domain domain); static inline void -intel_display_power_put(struct drm_i915_private *i915, +intel_display_power_put(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref) { - intel_display_power_put_unchecked(i915, domain); + intel_display_power_put_unchecked(display, domain); } static inline void -intel_display_power_put_async(struct drm_i915_private *i915, +intel_display_power_put_async(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref) { - __intel_display_power_put_async(i915, domain, INTEL_WAKEREF_DEF, -1); + __intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, -1); } static inline void -intel_display_power_put_async_delay(struct drm_i915_private *i915, +intel_display_power_put_async_delay(struct intel_display *display, enum intel_display_power_domain domain, intel_wakeref_t wakeref, int delay_ms) { - __intel_display_power_put_async(i915, domain, INTEL_WAKEREF_DEF, delay_ms); + __intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, delay_ms); } #endif void -intel_display_power_get_in_set(struct drm_i915_private *i915, +intel_display_power_get_in_set(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, enum intel_display_power_domain domain); bool -intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915, +intel_display_power_get_in_set_if_enabled(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, enum intel_display_power_domain domain); void -intel_display_power_put_mask_in_set(struct drm_i915_private *i915, +intel_display_power_put_mask_in_set(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, struct intel_power_domain_mask *mask); static inline void -intel_display_power_put_all_in_set(struct drm_i915_private *i915, +intel_display_power_put_all_in_set(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set) { - intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask); + intel_display_power_put_mask_in_set(display, power_domain_set, &power_domain_set->mask); } -void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m); +void intel_display_power_debug(struct intel_display *display, struct seq_file *m); enum intel_display_power_domain -intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port); +intel_display_power_ddi_lanes_domain(struct intel_display *display, enum port port); enum intel_display_power_domain -intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port); +intel_display_power_ddi_io_domain(struct intel_display *display, enum port port); enum intel_display_power_domain -intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch); +intel_display_power_aux_io_domain(struct intel_display *display, enum aux_ch aux_ch); enum intel_display_power_domain -intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch); +intel_display_power_legacy_aux_domain(struct intel_display *display, enum aux_ch aux_ch); enum intel_display_power_domain -intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch); +intel_display_power_tbt_aux_domain(struct intel_display *display, enum aux_ch aux_ch); /* * FIXME: We should probably switch this to a 0-based scheme to be consistent @@ -293,15 +293,15 @@ enum dbuf_slice { I915_MAX_DBUF_SLICES }; -void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, +void gen9_dbuf_slices_update(struct intel_display *display, u8 req_slices); -#define with_intel_display_power(i915, domain, wf) \ - for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ - intel_display_power_put_async((i915), (domain), (wf)), (wf) = NULL) +#define with_intel_display_power(display, domain, wf) \ + for ((wf) = intel_display_power_get((display), (domain)); (wf); \ + intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL) -#define with_intel_display_power_if_enabled(i915, domain, wf) \ - for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \ - intel_display_power_put_async((i915), (domain), (wf)), (wf) = NULL) +#define with_intel_display_power_if_enabled(display, domain, wf) \ + for ((wf) = intel_display_power_get_if_enabled((display), (domain)); (wf); \ + intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL) #endif /* __INTEL_DISPLAY_POWER_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c index 0c8ac1af6db7..e80e1fd611ca 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c @@ -3,6 +3,8 @@ * Copyright © 2022 Intel Corporation */ +#include <drm/drm_print.h> + #include "i915_reg.h" #include "intel_display_core.h" #include "intel_display_power_map.h" diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index f45a4f9ba23c..8ec87ffd87d2 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -507,7 +507,6 @@ static void icl_tc_phy_aux_power_well_enable(struct intel_display *display, struct i915_power_well *power_well) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); const struct i915_power_well_regs *regs = power_well->desc->ops->regs; @@ -539,7 +538,7 @@ icl_tc_phy_aux_power_well_enable(struct intel_display *display, tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); - if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) & + if (wait_for(intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)) & DKL_CMN_UC_DW27_UC_HEALTH, 1)) drm_warn(display->drm, "Timeout waiting TC uC health\n"); @@ -550,10 +549,9 @@ static void icl_aux_power_well_enable(struct intel_display *display, struct i915_power_well *power_well) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum phy phy = icl_aux_pw_to_phy(display, power_well); - if (intel_phy_is_tc(dev_priv, phy)) + if (intel_phy_is_tc(display, phy)) return icl_tc_phy_aux_power_well_enable(display, power_well); else if (display->platform.icelake) return icl_combo_phy_aux_power_well_enable(display, @@ -566,10 +564,9 @@ static void icl_aux_power_well_disable(struct intel_display *display, struct i915_power_well *power_well) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum phy phy = icl_aux_pw_to_phy(display, power_well); - if (intel_phy_is_tc(dev_priv, phy)) + if (intel_phy_is_tc(display, phy)) return hsw_power_well_disable(display, power_well); else if (display->platform.icelake) return icl_combo_phy_aux_power_well_disable(display, @@ -962,8 +959,7 @@ static bool gen9_dc_off_power_well_enabled(struct intel_display *display, static void gen9_assert_dbuf_enabled(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv); + u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(display); u8 enabled_dbuf_slices = display->dbuf.enabled_slices; drm_WARN(display->drm, @@ -975,7 +971,6 @@ static void gen9_assert_dbuf_enabled(struct intel_display *display) void gen9_disable_dc_states(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; struct intel_cdclk_config cdclk_config = {}; u32 old_state = power_domains->dc_state; @@ -1015,7 +1010,7 @@ void gen9_disable_dc_states(struct intel_display *display) * PHY's HW context for port B is lost after DC transitions, * so we need to restore it manually. */ - intel_combo_phy_init(dev_priv); + intel_combo_phy_init(display); } static void gen9_dc_off_power_well_enable(struct intel_display *display, @@ -1314,11 +1309,10 @@ static void vlv_dpio_cmn_power_well_enable(struct intel_display *display, static void vlv_dpio_cmn_power_well_disable(struct intel_display *display, struct i915_power_well *power_well) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe; for_each_pipe(display, pipe) - assert_pll_disabled(dev_priv, pipe); + assert_pll_disabled(display, pipe); /* Assert common reset */ intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0); @@ -1500,7 +1494,6 @@ static void chv_dpio_cmn_power_well_enable(struct intel_display *display, static void chv_dpio_cmn_power_well_disable(struct intel_display *display, struct i915_power_well *power_well) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum i915_power_well_id id = i915_power_well_instance(power_well)->id; enum dpio_phy phy; @@ -1510,11 +1503,11 @@ static void chv_dpio_cmn_power_well_disable(struct intel_display *display, if (id == VLV_DISP_PW_DPIO_CMN_BC) { phy = DPIO_PHY0; - assert_pll_disabled(dev_priv, PIPE_A); - assert_pll_disabled(dev_priv, PIPE_B); + assert_pll_disabled(display, PIPE_A); + assert_pll_disabled(display, PIPE_B); } else { phy = DPIO_PHY1; - assert_pll_disabled(dev_priv, PIPE_C); + assert_pll_disabled(display, PIPE_C); } display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); @@ -1834,11 +1827,10 @@ tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display, static void xelpdp_aux_power_well_enable(struct intel_display *display, struct i915_power_well *power_well) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; enum phy phy = icl_aux_pw_to_phy(display, power_well); - if (intel_phy_is_tc(dev_priv, phy)) + if (intel_phy_is_tc(display, phy)) icl_tc_port_assert_ref_held(display, power_well, aux_ch_to_digital_port(display, aux_ch)); diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h index 338379dae44c..ec8e508d0593 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h @@ -60,7 +60,7 @@ struct i915_power_well_instance { /* unique identifier for this power well */ enum i915_power_well_id id; /* - * Arbitraty data associated with this power well. Platform and power + * Arbitrary data associated with this power well. Platform and power * well specific. */ union { @@ -77,7 +77,7 @@ struct i915_power_well_instance { struct { /* * request/status flag index in the power well - * constrol/status registers. + * control/status registers. */ u8 idx; } hsw; diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c index 093b386c95e8..1f2798404f2c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.c +++ b/drivers/gpu/drm/i915/display/intel_display_reset.c @@ -7,51 +7,43 @@ #include "i915_drv.h" #include "intel_clock_gating.h" +#include "intel_cx0_phy.h" #include "intel_display_driver.h" #include "intel_display_reset.h" #include "intel_display_types.h" #include "intel_hotplug.h" #include "intel_pps.h" -static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) +bool intel_display_reset_test(struct intel_display *display) { - return (INTEL_INFO(dev_priv)->gpu_reset_clobbers_display && - intel_has_gpu_reset(to_gt(dev_priv))); + return display->params.force_reset_modeset_test; } -void intel_display_reset_prepare(struct drm_i915_private *dev_priv) +/* returns true if intel_display_reset_finish() needs to be called */ +bool intel_display_reset_prepare(struct intel_display *display, + modeset_stuck_fn modeset_stuck, void *context) { - struct drm_modeset_acquire_ctx *ctx = &dev_priv->display.restore.reset_ctx; + struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx; struct drm_atomic_state *state; int ret; - if (!HAS_DISPLAY(dev_priv)) - return; + if (!HAS_DISPLAY(display)) + return false; - /* reset doesn't touch the display */ - if (!dev_priv->display.params.force_reset_modeset_test && - !gpu_reset_clobbers_display(dev_priv)) - return; - - /* We have a modeset vs reset deadlock, defensively unbreak it. */ - set_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags); - smp_mb__after_atomic(); - wake_up_bit(&to_gt(dev_priv)->reset.flags, I915_RESET_MODESET); - - if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { - drm_dbg_kms(&dev_priv->drm, + if (atomic_read(&display->restore.pending_fb_pin)) { + drm_dbg_kms(display->drm, "Modeset potentially stuck, unbreaking through wedging\n"); - intel_gt_set_wedged(to_gt(dev_priv)); + modeset_stuck(context); } /* * Need mode_config.mutex so that we don't * trample ongoing ->detect() and whatnot. */ - mutex_lock(&dev_priv->drm.mode_config.mutex); + mutex_lock(&display->drm->mode_config.mutex); drm_modeset_acquire_init(ctx, 0); while (1) { - ret = drm_modeset_lock_all_ctx(&dev_priv->drm, ctx); + ret = drm_modeset_lock_all_ctx(display->drm, ctx); if (ret != -EDEADLK) break; @@ -61,38 +53,36 @@ void intel_display_reset_prepare(struct drm_i915_private *dev_priv) * Disabling the crtcs gracefully seems nicer. Also the * g33 docs say we should at least disable all the planes. */ - state = drm_atomic_helper_duplicate_state(&dev_priv->drm, ctx); + state = drm_atomic_helper_duplicate_state(display->drm, ctx); if (IS_ERR(state)) { ret = PTR_ERR(state); - drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", + drm_err(display->drm, "Duplicating state failed with %i\n", ret); - return; + return true; } - ret = drm_atomic_helper_disable_all(&dev_priv->drm, ctx); + ret = drm_atomic_helper_disable_all(display->drm, ctx); if (ret) { - drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", + drm_err(display->drm, "Suspending crtc's failed with %i\n", ret); drm_atomic_state_put(state); - return; + return true; } - dev_priv->display.restore.modeset_state = state; + display->restore.modeset_state = state; state->acquire_ctx = ctx; + + return true; } -void intel_display_reset_finish(struct drm_i915_private *i915) +void intel_display_reset_finish(struct intel_display *display, bool test_only) { - struct intel_display *display = &i915->display; + struct drm_i915_private *i915 = to_i915(display->drm); struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx; struct drm_atomic_state *state; int ret; - if (!HAS_DISPLAY(i915)) - return; - - /* reset doesn't touch the display */ - if (!test_bit(I915_RESET_MODESET, &to_gt(i915)->reset.flags)) + if (!HAS_DISPLAY(display)) return; state = fetch_and_zero(&display->restore.modeset_state); @@ -100,12 +90,12 @@ void intel_display_reset_finish(struct drm_i915_private *i915) goto unlock; /* reset doesn't touch the display */ - if (!gpu_reset_clobbers_display(i915)) { + if (test_only) { /* for testing only restore the display */ ret = drm_atomic_helper_commit_duplicated_state(state, ctx); if (ret) { - drm_WARN_ON(&i915->drm, ret == -EDEADLK); - drm_err(&i915->drm, + drm_WARN_ON(display->drm, ret == -EDEADLK); + drm_err(display->drm, "Restoring old state failed with %i\n", ret); } } else { @@ -116,11 +106,12 @@ void intel_display_reset_finish(struct drm_i915_private *i915) intel_pps_unlock_regs_wa(display); intel_display_driver_init_hw(display); intel_clock_gating_init(i915); + intel_cx0_pll_power_save_wa(display); intel_hpd_init(i915); ret = __intel_display_driver_resume(display, state, ctx); if (ret) - drm_err(&i915->drm, + drm_err(display->drm, "Restoring old state failed with %i\n", ret); intel_hpd_poll_disable(i915); @@ -130,7 +121,5 @@ void intel_display_reset_finish(struct drm_i915_private *i915) unlock: drm_modeset_drop_locks(ctx); drm_modeset_acquire_fini(ctx); - mutex_unlock(&i915->drm.mode_config.mutex); - - clear_bit_unlock(I915_RESET_MODESET, &to_gt(i915)->reset.flags); + mutex_unlock(&display->drm->mode_config.mutex); } diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.h b/drivers/gpu/drm/i915/display/intel_display_reset.h index f06d0d35b86b..8b3bda134454 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.h +++ b/drivers/gpu/drm/i915/display/intel_display_reset.h @@ -6,9 +6,15 @@ #ifndef __INTEL_RESET_H__ #define __INTEL_RESET_H__ -struct drm_i915_private; +#include <linux/types.h> -void intel_display_reset_prepare(struct drm_i915_private *i915); -void intel_display_reset_finish(struct drm_i915_private *i915); +struct intel_display; + +typedef void modeset_stuck_fn(void *context); + +bool intel_display_reset_test(struct intel_display *display); +bool intel_display_reset_prepare(struct intel_display *display, + modeset_stuck_fn modeset_stuck, void *context); +void intel_display_reset_finish(struct intel_display *display, bool test_only); #endif /* __INTEL_RESET_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_rps.c b/drivers/gpu/drm/i915/display/intel_display_rps.c index 918d0327169a..4074a1879828 100644 --- a/drivers/gpu/drm/i915/display/intel_display_rps.c +++ b/drivers/gpu/drm/i915/display/intel_display_rps.c @@ -69,10 +69,12 @@ void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc, add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait); } -void intel_display_rps_mark_interactive(struct drm_i915_private *i915, +void intel_display_rps_mark_interactive(struct intel_display *display, struct intel_atomic_state *state, bool interactive) { + struct drm_i915_private *i915 = to_i915(display->drm); + if (state->rps_interactive == interactive) return; diff --git a/drivers/gpu/drm/i915/display/intel_display_rps.h b/drivers/gpu/drm/i915/display/intel_display_rps.h index e19009c2371a..556891edb2dd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_rps.h +++ b/drivers/gpu/drm/i915/display/intel_display_rps.h @@ -10,12 +10,12 @@ struct dma_fence; struct drm_crtc; -struct drm_i915_private; struct intel_atomic_state; +struct intel_display; void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc, struct dma_fence *fence); -void intel_display_rps_mark_interactive(struct drm_i915_private *i915, +void intel_display_rps_mark_interactive(struct intel_display *display, struct intel_atomic_state *state, bool interactive); diff --git a/drivers/gpu/drm/i915/display/intel_display_trace.h b/drivers/gpu/drm/i915/display/intel_display_trace.h index 338b9f7b20b8..27ebc32cb61a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_trace.h +++ b/drivers/gpu/drm/i915/display/intel_display_trace.h @@ -4,7 +4,11 @@ */ #undef TRACE_SYSTEM +#ifdef I915 #define TRACE_SYSTEM i915 +#else +#define TRACE_SYSTEM xe +#endif #if !defined(__INTEL_DISPLAY_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ) #define __INTEL_DISPLAY_TRACE_H__ @@ -21,6 +25,7 @@ #include "intel_vblank.h" #define __dev_name_display(display) dev_name((display)->drm->dev) +#define __dev_name_drm(obj) dev_name((obj)->dev->dev) #define __dev_name_kms(obj) dev_name((obj)->base.dev->dev) /* @@ -397,23 +402,24 @@ TRACE_EVENT(intel_plane_async_flip, __entry->async_flip = async_flip; ), - TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u, async_flip=%s", + TP_printk("dev %s, pipe %c, %s, frame=%u, scanline=%u, async_flip=%s", __get_str(dev), __entry->pipe_name, __get_str(name), __entry->frame, __entry->scanline, str_yes_no(__entry->async_flip)) ); TRACE_EVENT(intel_plane_update_noarm, - TP_PROTO(struct intel_plane *plane, struct intel_crtc *crtc), - TP_ARGS(plane, crtc), + TP_PROTO(const struct intel_plane_state *plane_state, struct intel_crtc *crtc), + TP_ARGS(plane_state, crtc), TP_STRUCT__entry( - __string(dev, __dev_name_kms(plane)) + __string(dev, __dev_name_drm(plane_state->uapi.plane)) __field(char, pipe_name) __field(u32, frame) __field(u32, scanline) + __field(u32, format) __array(int, src, 4) __array(int, dst, 4) - __string(name, plane->base.name) + __string(name, plane_state->uapi.plane->name) ), TP_fast_assign( @@ -422,29 +428,31 @@ TRACE_EVENT(intel_plane_update_noarm, __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); - memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src)); - memcpy(__entry->dst, &plane->base.state->dst, sizeof(__entry->dst)); + __entry->format = plane_state->hw.fb->format->format; + memcpy(__entry->src, &plane_state->uapi.src, sizeof(__entry->src)); + memcpy(__entry->dst, &plane_state->uapi.dst, sizeof(__entry->dst)); ), - TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT, + TP_printk("dev %s, pipe %c, %s, frame=%u, scanline=%u, format=%p4cc, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT, __get_str(dev), __entry->pipe_name, __get_str(name), - __entry->frame, __entry->scanline, + __entry->frame, __entry->scanline, &__entry->format, DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src), DRM_RECT_ARG((const struct drm_rect *)__entry->dst)) ); TRACE_EVENT(intel_plane_update_arm, - TP_PROTO(struct intel_plane *plane, struct intel_crtc *crtc), - TP_ARGS(plane, crtc), + TP_PROTO(const struct intel_plane_state *plane_state, struct intel_crtc *crtc), + TP_ARGS(plane_state, crtc), TP_STRUCT__entry( - __string(dev, __dev_name_kms(plane)) + __string(dev, __dev_name_drm(plane_state->uapi.plane)) __field(char, pipe_name) __field(u32, frame) __field(u32, scanline) + __field(u32, format) __array(int, src, 4) __array(int, dst, 4) - __string(name, plane->base.name) + __string(name, plane_state->uapi.plane->name) ), TP_fast_assign( @@ -453,13 +461,14 @@ TRACE_EVENT(intel_plane_update_arm, __entry->pipe_name = pipe_name(crtc->pipe); __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); - memcpy(__entry->src, &plane->base.state->src, sizeof(__entry->src)); - memcpy(__entry->dst, &plane->base.state->dst, sizeof(__entry->dst)); + __entry->format = plane_state->hw.fb->format->format; + memcpy(__entry->src, &plane_state->uapi.src, sizeof(__entry->src)); + memcpy(__entry->dst, &plane_state->uapi.dst, sizeof(__entry->dst)); ), - TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT, + TP_printk("dev %s, pipe %c, %s, frame=%u, scanline=%u, format=%p4cc, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT, __get_str(dev), __entry->pipe_name, __get_str(name), - __entry->frame, __entry->scanline, + __entry->frame, __entry->scanline, &__entry->format, DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src), DRM_RECT_ARG((const struct drm_rect *)__entry->dst)) ); @@ -484,11 +493,110 @@ TRACE_EVENT(intel_plane_disable_arm, __entry->scanline = intel_get_crtc_scanline(crtc); ), - TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u", + TP_printk("dev %s, pipe %c, %s, frame=%u, scanline=%u", __get_str(dev), __entry->pipe_name, __get_str(name), __entry->frame, __entry->scanline) ); +TRACE_EVENT(intel_plane_scaler_update_arm, + TP_PROTO(struct intel_plane *plane, + int scaler_id, int x, int y, int w, int h), + TP_ARGS(plane, scaler_id, x, y, w, h), + + TP_STRUCT__entry( + __string(dev, __dev_name_kms(plane)) + __field(char, pipe_name) + __field(int, scaler_id) + __field(u32, frame) + __field(u32, scanline) + __field(int, x) + __field(int, y) + __field(int, w) + __field(int, h) + __string(name, plane->base.name) + ), + + TP_fast_assign( + struct intel_display *display = to_intel_display(plane); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, plane->pipe); + __assign_str(dev); + __assign_str(name); + __entry->pipe_name = pipe_name(crtc->pipe); + __entry->scaler_id = scaler_id; + __entry->frame = intel_crtc_get_vblank_counter(crtc); + __entry->scanline = intel_get_crtc_scanline(crtc); + __entry->x = x; + __entry->y = y; + __entry->w = w; + __entry->h = h; + ), + + TP_printk("dev %s, pipe %c, scaler %d, plane %s, frame=%u, scanline=%u, " DRM_RECT_FMT, + __get_str(dev), __entry->pipe_name, __entry->scaler_id, + __get_str(name), __entry->frame, __entry->scanline, + __entry->w, __entry->h, __entry->x, __entry->y) +); + +TRACE_EVENT(intel_pipe_scaler_update_arm, + TP_PROTO(struct intel_crtc *crtc, int scaler_id, + int x, int y, int w, int h), + TP_ARGS(crtc, scaler_id, x, y, w, h), + + TP_STRUCT__entry( + __string(dev, __dev_name_kms(crtc)) + __field(char, pipe_name) + __field(int, scaler_id) + __field(u32, frame) + __field(u32, scanline) + __field(int, x) + __field(int, y) + __field(int, w) + __field(int, h) + ), + + TP_fast_assign( + __assign_str(dev); + __entry->pipe_name = pipe_name(crtc->pipe); + __entry->scaler_id = scaler_id; + __entry->frame = intel_crtc_get_vblank_counter(crtc); + __entry->scanline = intel_get_crtc_scanline(crtc); + __entry->x = x; + __entry->y = y; + __entry->w = w; + __entry->h = h; + ), + + TP_printk("dev %s, pipe %c, scaler %d frame=%u, scanline=%u, " DRM_RECT_FMT, + __get_str(dev), __entry->pipe_name, __entry->scaler_id, + __entry->frame, __entry->scanline, + __entry->w, __entry->h, __entry->x, __entry->y) +); + +TRACE_EVENT(intel_scaler_disable_arm, + TP_PROTO(struct intel_crtc *crtc, int scaler_id), + TP_ARGS(crtc, scaler_id), + + TP_STRUCT__entry( + __string(dev, __dev_name_kms(crtc)) + __field(char, pipe_name) + __field(int, scaler_id) + __field(u32, frame) + __field(u32, scanline) + ), + + TP_fast_assign( + __assign_str(dev); + __entry->pipe_name = pipe_name(crtc->pipe); + __entry->scaler_id = scaler_id; + __entry->frame = intel_crtc_get_vblank_counter(crtc); + __entry->scanline = intel_get_crtc_scanline(crtc); + ), + + TP_printk("dev %s, pipe %c, scaler %d, frame=%u, scanline=%u", + __get_str(dev), __entry->pipe_name, __entry->scaler_id, + __entry->frame, __entry->scanline) +); + TRACE_EVENT(intel_fbc_activate, TP_PROTO(struct intel_plane *plane), TP_ARGS(plane), @@ -512,7 +620,7 @@ TRACE_EVENT(intel_fbc_activate, __entry->scanline = intel_get_crtc_scanline(crtc); ), - TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u", + TP_printk("dev %s, pipe %c, %s, frame=%u, scanline=%u", __get_str(dev), __entry->pipe_name, __get_str(name), __entry->frame, __entry->scanline) ); @@ -540,7 +648,7 @@ TRACE_EVENT(intel_fbc_deactivate, __entry->scanline = intel_get_crtc_scanline(crtc); ), - TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u", + TP_printk("dev %s, pipe %c, %s, frame=%u, scanline=%u", __get_str(dev), __entry->pipe_name, __get_str(name), __entry->frame, __entry->scanline) ); @@ -568,7 +676,7 @@ TRACE_EVENT(intel_fbc_nuke, __entry->scanline = intel_get_crtc_scanline(crtc); ), - TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u", + TP_printk("dev %s, pipe %c, %s, frame=%u, scanline=%u", __get_str(dev), __entry->pipe_name, __get_str(name), __entry->frame, __entry->scanline) ); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 8271e50e3644..99a6fd2900b9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -40,9 +40,9 @@ #include <drm/drm_rect.h> #include <drm/drm_vblank_work.h> #include <drm/intel/i915_hdcp_interface.h> +#include <uapi/drm/i915_drm.h> -#include "i915_vma.h" -#include "i915_vma_types.h" +#include "i915_gtt_view_types.h" #include "intel_bios.h" #include "intel_display.h" #include "intel_display_conversion.h" @@ -144,6 +144,7 @@ struct intel_framebuffer { struct i915_address_space *dpt_vm; unsigned int min_alignment; + unsigned int vtd_guard; }; enum intel_hotplug_state { @@ -412,6 +413,7 @@ struct intel_panel { union { struct { struct drm_edp_backlight_info info; + bool luminance_control_support; } vesa; struct { bool sdr_uses_aux; @@ -494,6 +496,8 @@ struct intel_hdcp { enum transcoder cpu_transcoder; /* Only used for DP MST stream encryption */ enum transcoder stream_transcoder; + /* Used to force HDCP 1.4 bypassing HDCP 2.x */ + bool force_hdcp14; }; struct intel_connector { @@ -530,10 +534,6 @@ struct intel_connector { state of connector->polled in case hotplug storm detection changes it */ u8 polled; - struct drm_dp_mst_port *port; - - struct intel_dp *mst_port; - int force_joined_pipes; struct { @@ -545,6 +545,11 @@ struct intel_connector { u8 dsc_decompression_enabled:1; } dp; + struct { + struct drm_dp_mst_port *port; + struct intel_dp *dp; + } mst; + /* Work struct to schedule a uevent on link train failure */ struct work_struct modeset_retry_work; @@ -638,6 +643,9 @@ struct intel_plane_state { /* Plane state to display black pixels when pxp is borked */ bool force_black; + /* Acting as Y plane for another UV plane? */ + bool is_y_plane; + /* plane control register */ u32 ctl; @@ -677,16 +685,6 @@ struct intel_plane_state { */ struct intel_plane *planar_linked_plane; - /* - * planar_slave: - * If set don't update use the linked plane's state for updating - * this plane during atomic commit with the update_slave() callback. - * - * It's also used by the watermark code to ignore wm calculations on - * this plane. They're calculated by the linked plane's wm code. - */ - u32 planar_slave; - struct drm_intel_sprite_colorkey ckey; struct drm_rect psr2_sel_fetch_area; @@ -695,6 +693,8 @@ struct intel_plane_state { u64 ccval; const char *no_fbc_reason; + + struct drm_rect damage; }; struct intel_initial_plane_config { @@ -711,6 +711,8 @@ struct intel_initial_plane_config { struct intel_scaler { u32 mode; bool in_use; + int hscale; + int vscale; }; struct intel_crtc_scaler_state { @@ -732,7 +734,7 @@ struct intel_crtc_scaler_state { * * intel_atomic_setup_scalers will setup available scalers to users * requesting scalers. It will gracefully fail if request exceeds - * avilability. + * availability. */ #define SKL_CRTC_INDEX 31 unsigned scaler_users; @@ -1095,6 +1097,7 @@ struct intel_crtc_state { int max_link_bpp_x16; /* in 1/16 bpp units */ int pipe_bpp; /* in 1 bpp units */ + int min_hblank; struct intel_link_m_n dp_m_n; /* m2_n2 for eDP downclock */ @@ -1113,7 +1116,7 @@ struct intel_crtc_state { u16 su_y_granularity; /* - * Frequence the dpll for the port should run at. Differs from the + * Frequency the dpll for the port should run at. Differs from the * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also * already multiplied by pixel_multiplier. */ @@ -1439,12 +1442,17 @@ struct intel_crtc { bool block_dc_for_vblank; }; +struct intel_plane_error { + u32 ctl, surf, surflive; +}; + struct intel_plane { struct drm_plane base; enum i9xx_plane_id i9xx_plane; enum plane_id id; enum pipe pipe; bool need_async_flip_toggle_wa; + u8 vtd_guard; u32 frontbuffer_bit; struct { @@ -1474,6 +1482,7 @@ struct intel_plane { unsigned int (*max_stride)(struct intel_plane *plane, u32 pixel_format, u64 modifier, unsigned int rotation); + bool (*can_async_flip)(u64 modifier); /* Write all non-self arming plane registers */ void (*update_noarm)(struct intel_dsb *dsb, struct intel_plane *plane, @@ -1488,6 +1497,9 @@ struct intel_plane { void (*disable_arm)(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state); + void (*capture_error)(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error); bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); int (*check_plane)(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state); @@ -1715,7 +1727,6 @@ struct intel_dp { struct intel_pps pps; bool is_mst; - int active_mst_links; enum drm_dp_mst_mode mst_detect; /* connector directly attached - won't be use for modeset in mst world */ @@ -1725,9 +1736,11 @@ struct intel_dp { struct drm_dp_tunnel *tunnel; bool tunnel_suspended:1; - /* mst connector list */ - struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; - struct drm_dp_mst_topology_mgr mst_mgr; + struct { + struct intel_dp_mst_encoder *stream_encoders[I915_MAX_PIPES]; + struct drm_dp_mst_topology_mgr mgr; + int active_links; + } mst; u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index); /* @@ -1838,16 +1851,18 @@ struct intel_digital_port { struct intel_tc_port *tc; - /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */ - struct mutex hdcp_mutex; - /* the number of pipes using HDCP signalling out of this port */ - unsigned int num_hdcp_streams; - /* port HDCP auth status */ - bool hdcp_auth_status; - /* HDCP port data need to pass to security f/w */ - struct hdcp_port_data hdcp_port_data; - /* Whether the MST topology supports HDCP Type 1 Content */ - bool hdcp_mst_type1_capable; + struct { + /* protects num_streams reference count, port_data and auth_status */ + struct mutex mutex; + /* the number of pipes using HDCP signalling out of this port */ + unsigned int num_streams; + /* port HDCP auth status */ + bool auth_status; + /* HDCP port data need to pass to security f/w */ + struct hdcp_port_data port_data; + /* Whether the MST topology supports HDCP Type 1 Content */ + bool mst_type1_capable; + } hdcp; void (*write_infoframe)(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, @@ -1946,8 +1961,8 @@ static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder) static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector) { - if (connector->mst_port) - return connector->mst_port; + if (connector->mst.dp) + return connector->mst.dp; else return enc_to_intel_dp(intel_attached_encoder(connector)); } @@ -1979,24 +1994,12 @@ static inline bool intel_encoder_is_hdmi(struct intel_encoder *encoder) } } -static inline struct intel_lspcon * -enc_to_intel_lspcon(struct intel_encoder *encoder) -{ - return &enc_to_dig_port(encoder)->lspcon; -} - static inline struct intel_digital_port * dp_to_dig_port(struct intel_dp *intel_dp) { return container_of(intel_dp, struct intel_digital_port, dp); } -static inline struct intel_lspcon * -dp_to_lspcon(struct intel_dp *intel_dp) -{ - return &dp_to_dig_port(intel_dp)->lspcon; -} - static inline struct intel_digital_port * hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) { @@ -2103,11 +2106,6 @@ intel_crtc_needs_color_update(const struct intel_crtc_state *crtc_state) intel_crtc_needs_modeset(crtc_state); } -static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state) -{ - return i915_ggtt_offset(plane_state->ggtt_vma); -} - static inline struct intel_frontbuffer * to_intel_frontbuffer(struct drm_framebuffer *fb) { diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c index b146b4c46943..0813fb9b5823 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c @@ -3,7 +3,7 @@ * Copyright © 2022 Intel Corporation */ -#include "i915_drv.h" +#include <drm/drm_device.h> #include "intel_de.h" #include "intel_display.h" @@ -12,28 +12,28 @@ /** * intel_dkl_phy_init - initialize Dekel PHY - * @i915: i915 device instance + * @display: display device instance */ -void intel_dkl_phy_init(struct drm_i915_private *i915) +void intel_dkl_phy_init(struct intel_display *display) { - spin_lock_init(&i915->display.dkl.phy_lock); + spin_lock_init(&display->dkl.phy_lock); } static void -dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) +dkl_phy_set_hip_idx(struct intel_display *display, struct intel_dkl_phy_reg reg) { enum tc_port tc_port = DKL_REG_TC_PORT(reg); - drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS); + drm_WARN_ON(display->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS); - intel_de_write(i915, + intel_de_write(display, HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, reg.bank_idx)); } /** * intel_dkl_phy_read - read a Dekel PHY register - * @i915: i915 device instance + * @display: intel_display device instance * @reg: Dekel PHY register * * Read the @reg Dekel PHY register. @@ -41,42 +41,42 @@ dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) * Returns the read value. */ u32 -intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) +intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg) { u32 val; - spin_lock(&i915->display.dkl.phy_lock); + spin_lock(&display->dkl.phy_lock); - dkl_phy_set_hip_idx(i915, reg); - val = intel_de_read(i915, DKL_REG_MMIO(reg)); + dkl_phy_set_hip_idx(display, reg); + val = intel_de_read(display, DKL_REG_MMIO(reg)); - spin_unlock(&i915->display.dkl.phy_lock); + spin_unlock(&display->dkl.phy_lock); return val; } /** * intel_dkl_phy_write - write a Dekel PHY register - * @i915: i915 device instance + * @display: intel_display device instance * @reg: Dekel PHY register * @val: value to write * * Write @val to the @reg Dekel PHY register. */ void -intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val) +intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val) { - spin_lock(&i915->display.dkl.phy_lock); + spin_lock(&display->dkl.phy_lock); - dkl_phy_set_hip_idx(i915, reg); - intel_de_write(i915, DKL_REG_MMIO(reg), val); + dkl_phy_set_hip_idx(display, reg); + intel_de_write(display, DKL_REG_MMIO(reg), val); - spin_unlock(&i915->display.dkl.phy_lock); + spin_unlock(&display->dkl.phy_lock); } /** * intel_dkl_phy_rmw - read-modify-write a Dekel PHY register - * @i915: i915 device instance + * @display: display device instance * @reg: Dekel PHY register * @clear: mask to clear * @set: mask to set @@ -85,30 +85,30 @@ intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, * this value back to the register if the value differs from the read one. */ void -intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set) +intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set) { - spin_lock(&i915->display.dkl.phy_lock); + spin_lock(&display->dkl.phy_lock); - dkl_phy_set_hip_idx(i915, reg); - intel_de_rmw(i915, DKL_REG_MMIO(reg), clear, set); + dkl_phy_set_hip_idx(display, reg); + intel_de_rmw(display, DKL_REG_MMIO(reg), clear, set); - spin_unlock(&i915->display.dkl.phy_lock); + spin_unlock(&display->dkl.phy_lock); } /** * intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register - * @i915: i915 device instance + * @display: display device instance * @reg: Dekel PHY register * * Read the @reg Dekel PHY register without returning the read value. */ void -intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) +intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg) { - spin_lock(&i915->display.dkl.phy_lock); + spin_lock(&display->dkl.phy_lock); - dkl_phy_set_hip_idx(i915, reg); - intel_de_posting_read(i915, DKL_REG_MMIO(reg)); + dkl_phy_set_hip_idx(display, reg); + intel_de_posting_read(display, DKL_REG_MMIO(reg)); - spin_unlock(&i915->display.dkl.phy_lock); + spin_unlock(&display->dkl.phy_lock); } diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.h b/drivers/gpu/drm/i915/display/intel_dkl_phy.h index 5956ec3e940b..ccb445c0022b 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy.h +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.h @@ -10,16 +10,16 @@ #include "intel_dkl_phy_regs.h" -struct drm_i915_private; +struct intel_display; -void intel_dkl_phy_init(struct drm_i915_private *i915); +void intel_dkl_phy_init(struct intel_display *display); u32 -intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg); +intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg); void -intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val); +intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val); void -intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set); +intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set); void -intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg); +intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg); #endif /* __INTEL_DKL_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 221d3abda791..fa6944e55d95 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -992,19 +992,16 @@ static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) static void intel_dmc_runtime_pm_get(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - drm_WARN_ON(display->drm, display->dmc.wakeref); - display->dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); + display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); } static void intel_dmc_runtime_pm_put(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref __maybe_unused = fetch_and_zero(&display->dmc.wakeref); - intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); + intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); } static const char *dmc_fallback_path(struct intel_display *display) diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index 02de3ae15074..7e2ce0c2f6c3 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -10,7 +10,6 @@ #include "i915_drv.h" #include "i915_reg.h" #include "intel_de.h" -#include "intel_dmc.h" #include "intel_dmc_regs.h" #include "intel_dmc_wl.h" @@ -50,12 +49,24 @@ #define DMC_WAKELOCK_CTL_TIMEOUT_US 5000 #define DMC_WAKELOCK_HOLD_TIME 50 +/* + * Possible non-negative values for the enable_dmc_wl param. + */ +enum { + ENABLE_DMC_WL_DISABLED, + ENABLE_DMC_WL_ENABLED, + ENABLE_DMC_WL_ANY_REGISTER, + ENABLE_DMC_WL_ALWAYS_LOCKED, + ENABLE_DMC_WL_MAX, +}; + struct intel_dmc_wl_range { u32 start; u32 end; }; static const struct intel_dmc_wl_range powered_off_ranges[] = { + { .start = 0x44400, .end = 0x4447f }, /* PIPE interrupt registers */ { .start = 0x60000, .end = 0x7ffff }, {}, }; @@ -90,6 +101,7 @@ static const struct intel_dmc_wl_range xe3lpd_dc5_dc6_dmc_ranges[] = { { .start = 0x42088 }, /* CHICKEN_MISC_3 */ { .start = 0x46160 }, /* CMTG_CLK_SEL */ { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */ + { .start = 0x45230 }, /* INITIATE_PM_DMD_REQ */ {}, }; @@ -230,10 +242,15 @@ static bool intel_dmc_wl_reg_in_range(i915_reg_t reg, return false; } -static bool intel_dmc_wl_check_range(i915_reg_t reg, u32 dc_state) +static bool intel_dmc_wl_check_range(struct intel_display *display, + i915_reg_t reg, + u32 dc_state) { const struct intel_dmc_wl_range *ranges; + if (display->params.enable_dmc_wl == ENABLE_DMC_WL_ANY_REGISTER) + return true; + /* * Check that the offset is in one of the ranges for which * registers are powered off during DC states. @@ -265,20 +282,48 @@ static bool intel_dmc_wl_check_range(i915_reg_t reg, u32 dc_state) static bool __intel_dmc_wl_supported(struct intel_display *display) { - return display->params.enable_dmc_wl && intel_dmc_has_payload(display); + return display->params.enable_dmc_wl; } static void intel_dmc_wl_sanitize_param(struct intel_display *display) { - if (!HAS_DMC_WAKELOCK(display)) - display->params.enable_dmc_wl = 0; - else if (display->params.enable_dmc_wl >= 0) - display->params.enable_dmc_wl = !!display->params.enable_dmc_wl; - else - display->params.enable_dmc_wl = DISPLAY_VER(display) >= 30; - - drm_dbg_kms(display->drm, "Sanitized enable_dmc_wl value: %d\n", - display->params.enable_dmc_wl); + const char *desc; + + if (!HAS_DMC_WAKELOCK(display)) { + display->params.enable_dmc_wl = ENABLE_DMC_WL_DISABLED; + } else if (display->params.enable_dmc_wl < 0) { + if (DISPLAY_VER(display) >= 30) + display->params.enable_dmc_wl = ENABLE_DMC_WL_ENABLED; + else + display->params.enable_dmc_wl = ENABLE_DMC_WL_DISABLED; + } else if (display->params.enable_dmc_wl >= ENABLE_DMC_WL_MAX) { + display->params.enable_dmc_wl = ENABLE_DMC_WL_ENABLED; + } + + drm_WARN_ON(display->drm, + display->params.enable_dmc_wl < 0 || + display->params.enable_dmc_wl >= ENABLE_DMC_WL_MAX); + + switch (display->params.enable_dmc_wl) { + case ENABLE_DMC_WL_DISABLED: + desc = "disabled"; + break; + case ENABLE_DMC_WL_ENABLED: + desc = "enabled"; + break; + case ENABLE_DMC_WL_ANY_REGISTER: + desc = "match any register"; + break; + case ENABLE_DMC_WL_ALWAYS_LOCKED: + desc = "always locked"; + break; + default: + desc = "unknown"; + break; + } + + drm_dbg_kms(display->drm, "Sanitized enable_dmc_wl value: %d (%s)\n", + display->params.enable_dmc_wl, desc); } void intel_dmc_wl_init(struct intel_display *display) @@ -292,7 +337,8 @@ void intel_dmc_wl_init(struct intel_display *display) INIT_DELAYED_WORK(&wl->work, intel_dmc_wl_work); spin_lock_init(&wl->lock); - refcount_set(&wl->refcount, 0); + refcount_set(&wl->refcount, + display->params.enable_dmc_wl == ENABLE_DMC_WL_ALWAYS_LOCKED ? 1 : 0); } /* Must only be called as part of enabling dynamic DC states. */ @@ -398,7 +444,8 @@ void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg) spin_lock_irqsave(&wl->lock, flags); - if (i915_mmio_reg_valid(reg) && !intel_dmc_wl_check_range(reg, wl->dc_state)) + if (i915_mmio_reg_valid(reg) && + !intel_dmc_wl_check_range(display, reg, wl->dc_state)) goto out_unlock; if (!wl->enabled) { @@ -430,7 +477,8 @@ void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg) spin_lock_irqsave(&wl->lock, flags); - if (i915_mmio_reg_valid(reg) && !intel_dmc_wl_check_range(reg, wl->dc_state)) + if (i915_mmio_reg_valid(reg) && + !intel_dmc_wl_check_range(display, reg, wl->dc_state)) goto out_unlock; if (WARN_RATELIMIT(!refcount_read(&wl->refcount), diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f1f3b1bb1e89..9476aaa91900 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -172,10 +172,28 @@ int intel_dp_link_symbol_clock(int rate) static int max_dprx_rate(struct intel_dp *intel_dp) { + struct intel_display *display = to_intel_display(intel_dp); + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; + int max_rate; + if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) - return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel); + max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel); + else + max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); - return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); + /* + * Some broken eDP sinks illegally declare support for + * HBR3 without TPS4, and are unable to produce a stable + * output. Reject HBR3 when TPS4 is not available. + */ + if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) { + drm_dbg_kms(display->drm, + "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n", + encoder->base.base.id, encoder->base.name); + max_rate = 540000; + } + + return max_rate; } static int max_dprx_lane_count(struct intel_dp *intel_dp) @@ -1075,7 +1093,7 @@ static bool source_can_output(struct intel_dp *intel_dp, /* * No YCbCr output support on gmch platforms. * Also, ILK doesn't seem capable of DP YCbCr output. - * The displayed image is severly corrupted. SNB+ is fine. + * The displayed image is severely corrupted. SNB+ is fine. */ return !HAS_GMCH(display) && !display->platform.ironlake; @@ -1376,7 +1394,7 @@ bool intel_dp_has_dsc(const struct intel_connector *connector) if (!HAS_DSC(display)) return false; - if (connector->mst_port && !HAS_DSC_MST(display)) + if (connector->mst.dp && !HAS_DSC_MST(display)) return false; if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && @@ -1391,12 +1409,11 @@ bool intel_dp_has_dsc(const struct intel_connector *connector) static enum drm_mode_status intel_dp_mode_valid(struct drm_connector *_connector, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { struct intel_display *display = to_intel_display(_connector->dev); struct intel_connector *connector = to_intel_connector(_connector); struct intel_dp *intel_dp = intel_attached_dp(connector); - struct drm_i915_private *dev_priv = to_i915(connector->base.dev); const struct drm_display_mode *fixed_mode; int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; @@ -1407,7 +1424,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, bool dsc = false; int num_joined_pipes; - status = intel_cpu_transcoder_mode_valid(dev_priv, mode); + status = intel_cpu_transcoder_mode_valid(display, mode); if (status != MODE_OK) return status; @@ -1496,7 +1513,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, if (status != MODE_OK) return status; - return intel_mode_valid_max_plane_size(dev_priv, mode, num_joined_pipes); + return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes); } bool intel_dp_source_supports_tps3(struct intel_display *display) @@ -1791,7 +1808,7 @@ int intel_dp_dsc_max_src_input_bpc(struct intel_display *display) if (DISPLAY_VER(display) == 11) return 10; - return 0; + return intel_dp_dsc_min_src_input_bpc(); } int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, @@ -1926,7 +1943,7 @@ static bool intel_dp_dsc_supports_format(const struct intel_connector *connector return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); } -static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_clock, +static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock, u32 lane_count, u32 mode_clock, enum intel_output_format output_format, int timeslots) @@ -1934,15 +1951,16 @@ static bool is_bw_sufficient_for_dsc_config(u16 compressed_bppx16, u32 link_cloc u32 available_bw, required_bw; available_bw = (link_clock * lane_count * timeslots * 16) / 8; - required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock)); + required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock)); return available_bw > required_bw; } static int dsc_compute_link_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, - struct link_config_limits *limits, - u16 compressed_bppx16, + struct drm_connector_state *conn_state, + const struct link_config_limits *limits, + int dsc_bpp_x16, int timeslots) { const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; @@ -1957,15 +1975,37 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, for (lane_count = limits->min_lane_count; lane_count <= limits->max_lane_count; lane_count <<= 1) { - if (!is_bw_sufficient_for_dsc_config(compressed_bppx16, link_rate, - lane_count, adjusted_mode->clock, - pipe_config->output_format, - timeslots)) - continue; + /* + * FIXME: intel_dp_mtp_tu_compute_config() requires + * ->lane_count and ->port_clock set before we know + * they'll work. If we end up failing altogether, + * they'll remain in crtc state. This shouldn't matter, + * as we'd then bail out from compute config, but it's + * just ugly. + */ pipe_config->lane_count = lane_count; pipe_config->port_clock = link_rate; + if (drm_dp_is_uhbr_rate(link_rate)) { + int ret; + + ret = intel_dp_mtp_tu_compute_config(intel_dp, + pipe_config, + conn_state, + dsc_bpp_x16, + dsc_bpp_x16, + 0, true); + if (ret) + continue; + } else { + if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_rate, + lane_count, adjusted_mode->clock, + pipe_config->output_format, + timeslots)) + continue; + } + return 0; } } @@ -2055,112 +2095,66 @@ static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) } /* - * From a list of valid compressed bpps try different compressed bpp and find a - * suitable link configuration that can support it. + * Note: for pre-13 display you still need to check the validity of each step. */ -static int -icl_dsc_compute_link_config(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, - struct link_config_limits *limits, - int dsc_max_bpp, - int dsc_min_bpp, - int pipe_bpp, - int timeslots) +static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) { - int i, ret; - - /* Compressed BPP should be less than the Input DSC bpp */ - dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); + struct intel_display *display = to_intel_display(connector); + u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); - for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { - if (valid_dsc_bpp[i] < dsc_min_bpp) - continue; - if (valid_dsc_bpp[i] > dsc_max_bpp) - break; + if (DISPLAY_VER(display) < 14 || !incr) + return fxp_q4_from_int(1); - ret = dsc_compute_link_config(intel_dp, - pipe_config, - limits, - valid_dsc_bpp[i] << 4, - timeslots); - if (ret == 0) { - pipe_config->dsc.compressed_bpp_x16 = - fxp_q4_from_int(valid_dsc_bpp[i]); - return 0; - } - } - - return -EINVAL; + /* fxp q4 */ + return fxp_q4_from_int(1) / incr; } -/* - * From XE_LPD onwards we supports compression bpps in steps of 1 up to - * uncompressed bpp-1. So we start from max compressed bpp and see if any - * link configuration is able to support that compressed bpp, if not we - * step down and check for lower compressed bpp. - */ -static int -xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, - const struct intel_connector *connector, - struct intel_crtc_state *pipe_config, - struct link_config_limits *limits, - int dsc_max_bpp, - int dsc_min_bpp, - int pipe_bpp, - int timeslots) +/* Note: This is not universally usable! */ +static bool intel_dp_dsc_valid_bpp(struct intel_dp *intel_dp, int bpp_x16) { struct intel_display *display = to_intel_display(intel_dp); - u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); - u16 compressed_bppx16; - u8 bppx16_step; - int ret; + int i; - if (DISPLAY_VER(display) < 14 || bppx16_incr <= 1) - bppx16_step = 16; - else - bppx16_step = 16 / bppx16_incr; + if (DISPLAY_VER(display) >= 13) { + if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(bpp_x16)) + return false; - /* Compressed BPP should be less than the Input DSC bpp */ - dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step); - dsc_min_bpp = dsc_min_bpp << 4; - - for (compressed_bppx16 = dsc_max_bpp; - compressed_bppx16 >= dsc_min_bpp; - compressed_bppx16 -= bppx16_step) { - if (intel_dp->force_dsc_fractional_bpp_en && - !fxp_q4_to_frac(compressed_bppx16)) - continue; - ret = dsc_compute_link_config(intel_dp, - pipe_config, - limits, - compressed_bppx16, - timeslots); - if (ret == 0) { - pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16; - if (intel_dp->force_dsc_fractional_bpp_en && - fxp_q4_to_frac(compressed_bppx16)) - drm_dbg_kms(display->drm, - "Forcing DSC fractional bpp\n"); + return true; + } - return 0; - } + if (fxp_q4_to_frac(bpp_x16)) + return false; + + for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { + if (fxp_q4_to_int(bpp_x16) == valid_dsc_bpp[i]) + return true; } - return -EINVAL; + + return false; } +/* + * Find the max compressed BPP we can find a link configuration for. The BPPs to + * try depend on the source (platform) and sink. + */ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, - const struct intel_connector *connector, struct intel_crtc_state *pipe_config, - struct link_config_limits *limits, + struct drm_connector_state *conn_state, + const struct link_config_limits *limits, int pipe_bpp, int timeslots) { struct intel_display *display = to_intel_display(intel_dp); + const struct intel_connector *connector = to_intel_connector(conn_state->connector); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; + int output_bpp; int dsc_min_bpp; int dsc_max_bpp; + int min_bpp_x16, max_bpp_x16, bpp_step_x16; int dsc_joiner_max_bpp; int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); + int bpp_x16; + int ret; dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); @@ -2169,11 +2163,38 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, num_joined_pipes); dsc_max_bpp = min(dsc_joiner_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16)); - if (DISPLAY_VER(display) >= 13) - return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits, - dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots); - return icl_dsc_compute_link_config(intel_dp, pipe_config, limits, - dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots); + /* FIXME: remove the round trip via integers */ + min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); + max_bpp_x16 = fxp_q4_from_int(dsc_max_bpp); + + bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); + + /* Compressed BPP should be less than the Input DSC bpp */ + output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); + max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16); + + for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { + if (!intel_dp_dsc_valid_bpp(intel_dp, bpp_x16)) + continue; + + ret = dsc_compute_link_config(intel_dp, + pipe_config, + conn_state, + limits, + bpp_x16, + timeslots); + if (ret == 0) { + pipe_config->dsc.compressed_bpp_x16 = bpp_x16; + if (intel_dp->force_dsc_fractional_bpp_en && + fxp_q4_to_frac(bpp_x16)) + drm_dbg_kms(display->drm, + "Forcing DSC fractional bpp\n"); + + return 0; + } + } + + return -EINVAL; } int intel_dp_dsc_min_src_input_bpc(void) @@ -2183,7 +2204,7 @@ int intel_dp_dsc_min_src_input_bpc(void) } static -bool is_dsc_pipe_bpp_sufficient(struct link_config_limits *limits, +bool is_dsc_pipe_bpp_sufficient(const struct link_config_limits *limits, int pipe_bpp) { return pipe_bpp >= limits->pipe.min_bpp && @@ -2192,7 +2213,7 @@ bool is_dsc_pipe_bpp_sufficient(struct link_config_limits *limits, static int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, - struct link_config_limits *limits) + const struct link_config_limits *limits) { struct intel_display *display = to_intel_display(intel_dp); int forced_bpp; @@ -2218,13 +2239,11 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, - struct link_config_limits *limits, + const struct link_config_limits *limits, int timeslots) { const struct intel_connector *connector = to_intel_connector(conn_state->connector); - int dsc_max_bpp; - int dsc_min_bpp; u8 dsc_bpc[3] = {}; int forced_bpp, pipe_bpp; int num_bpc, i, ret; @@ -2232,7 +2251,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); if (forced_bpp) { - ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, + ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, limits, forced_bpp, timeslots); if (ret == 0) { pipe_config->pipe_bpp = forced_bpp; @@ -2240,9 +2259,6 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, } } - dsc_max_bpp = limits->pipe.max_bpp; - dsc_min_bpp = limits->pipe.min_bpp; - /* * Get the maximum DSC bpc that will be supported by any valid * link configuration and compressed bpp. @@ -2250,11 +2266,10 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); for (i = 0; i < num_bpc; i++) { pipe_bpp = dsc_bpc[i] * 3; - if (pipe_bpp < dsc_min_bpp) - break; - if (pipe_bpp > dsc_max_bpp) + if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp) continue; - ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, + + ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, limits, pipe_bpp, timeslots); if (ret == 0) { pipe_config->pipe_bpp = pipe_bpp; @@ -2268,7 +2283,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, - struct link_config_limits *limits) + const struct link_config_limits *limits) { struct intel_display *display = to_intel_display(intel_dp); struct intel_connector *connector = @@ -2333,9 +2348,8 @@ static void intel_dp_fec_compute_config(struct intel_dp *intel_dp, int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, - struct link_config_limits *limits, - int timeslots, - bool compute_pipe_bpp) + const struct link_config_limits *limits, + int timeslots) { struct intel_display *display = to_intel_display(intel_dp); const struct intel_connector *connector = @@ -2343,6 +2357,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); + bool is_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST); int ret; intel_dp_fec_compute_config(intel_dp, pipe_config); @@ -2351,12 +2366,10 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; /* - * compute pipe bpp is set to false for DP MST DSC case - * and compressed_bpp is calculated same time once - * vpci timeslots are allocated, because overall bpp - * calculation procedure is bit different for MST case. + * Link parameters, pipe bpp and compressed bpp have already been + * figured out for DP MST DSC. */ - if (compute_pipe_bpp) { + if (!is_mst) { if (intel_dp_is_edp(intel_dp)) ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config, conn_state, limits); @@ -2519,9 +2532,6 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp, limits->min_rate = intel_dp_min_link_rate(intel_dp); limits->max_rate = intel_dp_max_link_rate(intel_dp); - /* FIXME 128b/132b SST+DSC support missing */ - if (!is_mst && dsc) - limits->max_rate = min(limits->max_rate, 810000); limits->min_rate = min(limits->min_rate, limits->max_rate); limits->min_lane_count = intel_dp_min_lane_count(intel_dp); @@ -2641,9 +2651,9 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, if (!ret && intel_dp_is_uhbr(pipe_config)) ret = intel_dp_mtp_tu_compute_config(intel_dp, pipe_config, - pipe_config->pipe_bpp, - pipe_config->pipe_bpp, conn_state, + fxp_q4_from_int(pipe_config->pipe_bpp), + fxp_q4_from_int(pipe_config->pipe_bpp), 0, false); if (ret) dsc_needed = true; @@ -2667,7 +2677,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, return -EINVAL; ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, - conn_state, &limits, 64, true); + conn_state, &limits, 64); if (ret < 0) return ret; } @@ -2829,19 +2839,17 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); - /* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */ as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; as_sdp->length = 0x9; as_sdp->duration_incr_ms = 0; + as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state); if (crtc_state->cmrr.enable) { as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED; - as_sdp->vtotal = adjusted_mode->vtotal; as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode); as_sdp->target_rr_divider = true; } else { - as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL; - as_sdp->vtotal = adjusted_mode->vtotal; + as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL; as_sdp->target_rr = 0; } } @@ -2922,7 +2930,7 @@ static bool can_enable_drrs(struct intel_connector *connector, const struct intel_crtc_state *pipe_config, const struct drm_display_mode *downclock_mode) { - struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_display *display = to_intel_display(connector); if (pipe_config->vrr.enable) return false; @@ -2940,7 +2948,7 @@ static bool can_enable_drrs(struct intel_connector *connector, if (pipe_config->has_pch_encoder) return false; - if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder)) + if (!intel_cpu_transcoder_has_drrs(display, pipe_config->cpu_transcoder)) return false; return downclock_mode && @@ -2953,7 +2961,6 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, int link_bpp_x16) { struct intel_display *display = to_intel_display(connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); const struct drm_display_mode *downclock_mode = intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); int pixel_clock; @@ -2966,7 +2973,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, pipe_config->update_m_n = true; if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { - if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) + if (intel_cpu_transcoder_has_m2_n2(display, pipe_config->cpu_transcoder)) intel_zero_m_n(&pipe_config->dp_m2_n2); return; } @@ -3066,15 +3073,6 @@ intel_dp_audio_compute_config(struct intel_encoder *encoder, intel_dp_is_uhbr(pipe_config); } -static void intel_dp_queue_modeset_retry_work(struct intel_connector *connector) -{ - struct drm_i915_private *i915 = to_i915(connector->base.dev); - - drm_connector_get(&connector->base); - if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work)) - drm_connector_put(&connector->base); -} - void intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, struct intel_encoder *encoder, @@ -3091,7 +3089,7 @@ intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, intel_dp->needs_modeset_retry = true; if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { - intel_dp_queue_modeset_retry_work(intel_dp->attached_connector); + intel_connector_queue_modeset_retry_work(intel_dp->attached_connector); return; } @@ -3100,8 +3098,8 @@ intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, if (!conn_state->base.crtc) continue; - if (connector->mst_port == intel_dp) - intel_dp_queue_modeset_retry_work(connector); + if (connector->mst.dp == intel_dp) + intel_connector_queue_modeset_retry_work(connector); } } @@ -3150,7 +3148,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, if ((intel_dp_is_edp(intel_dp) && fixed_mode) || pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { - ret = intel_panel_fitting(pipe_config, conn_state); + ret = intel_pfit_compute_config(pipe_config, conn_state); if (ret) return ret; } @@ -3322,8 +3320,8 @@ intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector, bool enable) { struct intel_display *display = to_intel_display(connector); - struct drm_dp_aux *aux = connector->port ? - connector->port->passthrough_aux : NULL; + struct drm_dp_aux *aux = connector->mst.port ? + connector->mst.port->passthrough_aux : NULL; if (!aux) return; @@ -3350,7 +3348,7 @@ static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state, * On SST the decompression AUX device won't be shared, each connector * uses for this its own AUX targeting the sink device. */ - if (!connector->mst_port) + if (!connector->mst.dp) return connector->dp.dsc_decompression_enabled ? 1 : 0; for_each_oldnew_connector_in_state(&state->base, _connector_iter, @@ -3358,7 +3356,7 @@ static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state, const struct intel_connector * connector_iter = to_intel_connector(_connector_iter); - if (connector_iter->mst_port != connector->mst_port) + if (connector_iter->mst.dp != connector->mst.dp) continue; if (!connector_iter->dp.dsc_decompression_enabled) @@ -3528,9 +3526,9 @@ void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); } else { - struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - lspcon_resume(dp_to_dig_port(intel_dp)); + intel_lspcon_resume(dig_port); /* Write the source OUI as early as possible */ intel_dp_init_source_oui(intel_dp); @@ -3546,8 +3544,8 @@ void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) msleep(1); } - if (ret == 1 && lspcon->active) - lspcon_wait_pcon_mode(lspcon); + if (ret == 1 && intel_lspcon_active(dig_port)) + intel_lspcon_wait_pcon_mode(dig_port); } if (ret != 1) @@ -4190,6 +4188,9 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp) static void intel_edp_set_sink_rates(struct intel_dp *intel_dp) { + struct intel_display *display = to_intel_display(intel_dp); + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; + intel_dp->num_sink_rates = 0; if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { @@ -4200,10 +4201,7 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp) sink_rates, sizeof(sink_rates)); for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { - int val = le16_to_cpu(sink_rates[i]); - - if (val == 0) - break; + int rate; /* Value read multiplied by 200kHz gives the per-lane * link rate in kHz. The source rates are, however, @@ -4211,7 +4209,24 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp) * back to symbols is * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) */ - intel_dp->sink_rates[i] = (val * 200) / 10; + rate = le16_to_cpu(sink_rates[i]) * 200 / 10; + + if (rate == 0) + break; + + /* + * Some broken eDP sinks illegally declare support for + * HBR3 without TPS4, and are unable to produce a stable + * output. Reject HBR3 when TPS4 is not available. + */ + if (rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) { + drm_dbg_kms(display->drm, + "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n", + encoder->base.base.id, encoder->base.name); + break; + } + + intel_dp->sink_rates[i] = rate; } intel_dp->num_sink_rates = i; } @@ -4416,7 +4431,7 @@ intel_dp_mst_configure(struct intel_dp *intel_dp) if (intel_dp->is_mst) intel_dp_mst_prepare_probe(intel_dp); - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); + drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst); /* Avoid stale info on the next detect cycle. */ intel_dp->mst_detect = DRM_DP_SST; @@ -4432,9 +4447,9 @@ intel_dp_mst_disconnect(struct intel_dp *intel_dp) drm_dbg_kms(display->drm, "MST device may have disappeared %d vs %d\n", - intel_dp->is_mst, intel_dp->mst_mgr.mst_state); + intel_dp->is_mst, intel_dp->mst.mgr.mst_state); intel_dp->is_mst = false; - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); + drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst); } static bool @@ -4940,7 +4955,7 @@ intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack) { bool handled = false; - drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled); + drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst.mgr, esi, ack, &handled); if (esi[1] & DP_CP_IRQ) { intel_hdcp_handle_cp_irq(intel_dp->attached_connector); @@ -4989,7 +5004,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) bool link_ok = true; bool reprobe_needed = false; - drm_WARN_ON_ONCE(display->drm, intel_dp->active_mst_links < 0); + drm_WARN_ON_ONCE(display->drm, intel_dp->mst.active_links < 0); for (;;) { u8 esi[4] = {}; @@ -5005,7 +5020,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi); - if (intel_dp->active_mst_links > 0 && link_ok && + if (intel_dp->mst.active_links > 0 && link_ok && esi[3] & LINK_STATUS_CHANGED) { if (!intel_dp_mst_link_status(intel_dp)) link_ok = false; @@ -5028,7 +5043,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) drm_dbg_kms(display->drm, "Failed to ack ESI\n"); if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY)) - drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr); + drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst.mgr); } if (!link_ok || intel_dp->link.force_retrain) @@ -5127,7 +5142,7 @@ bool intel_dp_has_connector(struct intel_dp *intel_dp, /* MST */ for_each_pipe(display, pipe) { - encoder = &intel_dp->mst_encoders[pipe]->base; + encoder = &intel_dp->mst.stream_encoders[pipe]->base; if (conn_state->best_encoder == &encoder->base) return true; } @@ -5213,7 +5228,6 @@ static int intel_dp_retrain_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); u8 pipe_mask; int ret; @@ -5244,7 +5258,7 @@ static int intel_dp_retrain_link(struct intel_encoder *encoder, encoder->base.base.id, encoder->base.name, str_yes_no(intel_dp->link.force_retrain)); - ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx); + ret = intel_modeset_commit_pipes(display, pipe_mask, ctx); if (ret == -EDEADLK) return ret; @@ -5397,7 +5411,7 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp) if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp))) return connector_status_connected; - lspcon_resume(dig_port); + intel_lspcon_resume(dig_port); if (!intel_dp_get_dpcd(intel_dp)) return connector_status_disconnected; @@ -5479,13 +5493,13 @@ void intel_digital_port_unlock(struct intel_encoder *encoder) */ bool intel_digital_port_connected_locked(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port); bool is_connected = false; intel_wakeref_t wakeref; - with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) { + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4); do { @@ -5597,7 +5611,7 @@ intel_dp_update_420(struct intel_dp *intel_dp) intel_dp->downstream_ports); /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ intel_dp->dfp.ycbcr_444_to_420 = - dp_to_dig_port(intel_dp)->lspcon.active || + intel_lspcon_active(dp_to_dig_port(intel_dp)) || drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, intel_dp->downstream_ports); intel_dp->dfp.rgb_to_ycbcr = @@ -5871,7 +5885,6 @@ intel_dp_connector_register(struct drm_connector *connector) struct intel_display *display = to_intel_display(connector->dev); struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - struct intel_lspcon *lspcon = &dig_port->lspcon; int ret; ret = intel_connector_register(connector); @@ -5893,9 +5906,8 @@ intel_dp_connector_register(struct drm_connector *connector) * ToDo: Clean this up to handle lspcon init and resume more * efficiently and streamlined. */ - if (lspcon_init(dig_port)) { - lspcon_detect_hdr_capability(lspcon); - if (lspcon->hdr_supported) + if (intel_lspcon_init(dig_port)) { + if (intel_lspcon_detect_hdr_capability(dig_port)) drm_connector_attach_hdr_output_metadata_property(connector); } @@ -6088,7 +6100,7 @@ static int intel_dp_connector_atomic_check(struct drm_connector *conn, return ret; if (intel_dp_mst_source_support(intel_dp)) { - ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr); + ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst.mgr); if (ret) return ret; } @@ -6497,35 +6509,6 @@ out_vdd_off: return false; } -static void intel_dp_modeset_retry_work_fn(struct work_struct *work) -{ - struct intel_connector *connector = container_of(work, typeof(*connector), - modeset_retry_work); - struct intel_display *display = to_intel_display(connector); - - drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.base.id, - connector->base.name); - - /* Grab the locks before changing connector property*/ - mutex_lock(&display->drm->mode_config.mutex); - /* Set connector link status to BAD and send a Uevent to notify - * userspace to do a modeset. - */ - drm_connector_set_link_status_property(&connector->base, - DRM_MODE_LINK_STATUS_BAD); - mutex_unlock(&display->drm->mode_config.mutex); - /* Send Hotplug uevent so userspace can reprobe */ - drm_kms_helper_connector_hotplug_event(&connector->base); - - drm_connector_put(&connector->base); -} - -void intel_dp_init_modeset_retry_work(struct intel_connector *connector) -{ - INIT_WORK(&connector->modeset_retry_work, - intel_dp_modeset_retry_work_fn); -} - bool intel_dp_init_connector(struct intel_digital_port *dig_port, struct intel_connector *connector) @@ -6534,13 +6517,9 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, struct intel_dp *intel_dp = &dig_port->dp; struct intel_encoder *encoder = &dig_port->base; struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); enum port port = encoder->port; int type; - /* Initialize the work for modeset in case of link train failure */ - intel_dp_init_modeset_retry_work(connector); - if (drm_WARN(dev, dig_port->max_lanes < 1, "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", dig_port->max_lanes, encoder->base.base.id, @@ -6634,7 +6613,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, return true; fail: - intel_display_power_flush_work(dev_priv); + intel_display_power_flush_work(display); drm_connector_cleanup(&connector->base); return false; @@ -6659,7 +6638,7 @@ void intel_dp_mst_suspend(struct intel_display *display) continue; if (intel_dp->is_mst) - drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); + drm_dp_mst_topology_mgr_suspend(&intel_dp->mst.mgr); } } @@ -6682,12 +6661,10 @@ void intel_dp_mst_resume(struct intel_display *display) if (!intel_dp_mst_source_support(intel_dp)) continue; - ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr, - true); + ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst.mgr, true); if (ret) { intel_dp->is_mst = false; - drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, - false); + drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, false); } } } diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index ca49f0a05da5..9189db4c2594 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -75,9 +75,8 @@ int intel_dp_compute_config(struct intel_encoder *encoder, int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, - struct link_config_limits *limits, - int timeslots, - bool recompute_pipe_bpp); + const struct link_config_limits *limits, + int timeslots); void intel_dp_audio_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 40c697476b72..ec27bbd70bcf 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -243,7 +243,6 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); i915_reg_t ch_ctl, ch_data[5]; u32 aux_clock_divider; enum intel_display_power_domain aux_domain; @@ -272,7 +271,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, aux_domain = intel_aux_power_domain(dig_port); - aux_wakeref = intel_display_power_get(i915, aux_domain); + aux_wakeref = intel_display_power_get(display, aux_domain); pps_wakeref = intel_pps_lock(intel_dp); /* @@ -432,7 +431,7 @@ out: intel_pps_vdd_off_unlocked(intel_dp, false); intel_pps_unlock(intel_dp, pps_wakeref); - intel_display_power_put_async(i915, aux_domain, aux_wakeref); + intel_display_power_put_async(display, aux_domain, aux_wakeref); out_unlock: intel_digital_port_unlock(encoder); diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index c846ef4acf5b..8173de8aec63 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -34,6 +34,8 @@ * for some reason. */ +#include <drm/drm_print.h> + #include "i915_utils.h" #include "intel_backlight.h" #include "intel_display_core.h" @@ -451,9 +453,54 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi /* VESA backlight callbacks */ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, enum pipe unused) { + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + struct intel_panel *panel = &connector->panel; + u8 buf[3]; + u32 val = 0; + int ret; + + if (panel->backlight.edp.vesa.luminance_control_support) { + ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_PANEL_TARGET_LUMINANCE_VALUE, buf, + sizeof(buf)); + if (ret < 0) { + drm_err(intel_dp->aux.drm_dev, + "[CONNECTOR:%d:%s] Failed to read Luminance from DPCD\n", + connector->base.base.id, connector->base.name); + return 0; + } + + val |= buf[0] | buf[1] << 8 | buf[2] << 16; + return val / 1000; + } + return connector->panel.backlight.level; } +static int +intel_dp_aux_vesa_set_luminance(struct intel_connector *connector, u32 level) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + u8 buf[3]; + int ret; + + level = level * 1000; + level &= 0xffffff; + buf[0] = (level & 0x0000ff); + buf[1] = (level & 0x00ff00) >> 8; + buf[2] = (level & 0xff0000) >> 16; + + ret = drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_PANEL_TARGET_LUMINANCE_VALUE, + buf, sizeof(buf)); + if (ret != sizeof(buf)) { + drm_err(intel_dp->aux.drm_dev, + "%s: Failed to set VESA Aux Luminance: %d\n", + intel_dp->aux.name, ret); + return -EINVAL; + } else { + return 0; + } +} + static void intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, u32 level) { @@ -461,6 +508,11 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, u3 struct intel_panel *panel = &connector->panel; struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + if (panel->backlight.edp.vesa.luminance_control_support) { + if (!intel_dp_aux_vesa_set_luminance(connector, level)) + return; + } + if (!panel->backlight.edp.vesa.info.aux_set) { const u32 pwm_level = intel_backlight_level_to_pwm(connector, level); @@ -477,6 +529,18 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state, struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_panel *panel = &connector->panel; struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + int ret; + + if (panel->backlight.edp.vesa.luminance_control_support) { + ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, + DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE); + + if (ret == 1) + return; + + if (!intel_dp_aux_vesa_set_luminance(connector, level)) + return; + } if (!panel->backlight.edp.vesa.info.aux_enable) { u32 pwm_level; @@ -500,6 +564,9 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state struct intel_panel *panel = &connector->panel; struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + if (panel->backlight.edp.vesa.luminance_control_support) + return; + drm_edp_backlight_disable(&intel_dp->aux, &panel->backlight.edp.vesa.info); if (!panel->backlight.edp.vesa.info.aux_enable) @@ -510,56 +577,75 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, enum pipe pipe) { struct intel_display *display = to_intel_display(connector); + struct drm_luminance_range_info *luminance_range = + &connector->base.display_info.luminance_range; struct intel_dp *intel_dp = intel_attached_dp(connector); struct intel_panel *panel = &connector->panel; u16 current_level; u8 current_mode; int ret; - ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info, - panel->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd, - ¤t_level, ¤t_mode); - if (ret < 0) - return ret; - - drm_dbg_kms(display->drm, - "[CONNECTOR:%d:%s] AUX VESA backlight enable is controlled through %s\n", - connector->base.base.id, connector->base.name, - dpcd_vs_pwm_str(panel->backlight.edp.vesa.info.aux_enable)); - drm_dbg_kms(display->drm, - "[CONNECTOR:%d:%s] AUX VESA backlight level is controlled through %s\n", - connector->base.base.id, connector->base.name, - dpcd_vs_pwm_str(panel->backlight.edp.vesa.info.aux_set)); - - if (!panel->backlight.edp.vesa.info.aux_set || !panel->backlight.edp.vesa.info.aux_enable) { - ret = panel->backlight.pwm_funcs->setup(connector, pipe); - if (ret < 0) { - drm_err(display->drm, - "[CONNECTOR:%d:%s] Failed to setup PWM backlight controls for eDP backlight: %d\n", - connector->base.base.id, connector->base.name, ret); - return ret; - } - } - - if (panel->backlight.edp.vesa.info.aux_set) { - panel->backlight.max = panel->backlight.edp.vesa.info.max; - panel->backlight.min = 0; - if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) { - panel->backlight.level = current_level; - panel->backlight.enabled = panel->backlight.level != 0; + if (panel->backlight.edp.vesa.luminance_control_support) { + if (luminance_range->max_luminance) { + panel->backlight.max = luminance_range->max_luminance; + panel->backlight.min = luminance_range->min_luminance; } else { - panel->backlight.level = panel->backlight.max; - panel->backlight.enabled = false; + panel->backlight.max = 512; + panel->backlight.min = 0; } + panel->backlight.level = intel_dp_aux_vesa_get_backlight(connector, 0); + panel->backlight.enabled = panel->backlight.level != 0; + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] AUX VESA Nits backlight level is controlled through DPCD\n", + connector->base.base.id, connector->base.name); } else { - panel->backlight.max = panel->backlight.pwm_level_max; - panel->backlight.min = panel->backlight.pwm_level_min; - if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_PWM) { - panel->backlight.level = panel->backlight.pwm_funcs->get(connector, pipe); - panel->backlight.enabled = panel->backlight.pwm_enabled; + ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info, + panel->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd, + ¤t_level, ¤t_mode); + if (ret < 0) + return ret; + + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] AUX VESA backlight enable is controlled through %s\n", + connector->base.base.id, connector->base.name, + dpcd_vs_pwm_str(panel->backlight.edp.vesa.info.aux_enable)); + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] AUX VESA backlight level is controlled through %s\n", + connector->base.base.id, connector->base.name, + dpcd_vs_pwm_str(panel->backlight.edp.vesa.info.aux_set)); + + if (!panel->backlight.edp.vesa.info.aux_set || + !panel->backlight.edp.vesa.info.aux_enable) { + ret = panel->backlight.pwm_funcs->setup(connector, pipe); + if (ret < 0) { + drm_err(display->drm, + "[CONNECTOR:%d:%s] Failed to setup PWM backlight controls for eDP backlight: %d\n", + connector->base.base.id, connector->base.name, ret); + return ret; + } + } + + if (panel->backlight.edp.vesa.info.aux_set) { + panel->backlight.max = panel->backlight.edp.vesa.info.max; + panel->backlight.min = 0; + if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) { + panel->backlight.level = current_level; + panel->backlight.enabled = panel->backlight.level != 0; + } else { + panel->backlight.level = panel->backlight.max; + panel->backlight.enabled = false; + } } else { - panel->backlight.level = panel->backlight.max; - panel->backlight.enabled = false; + panel->backlight.max = panel->backlight.pwm_level_max; + panel->backlight.min = panel->backlight.pwm_level_min; + if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_PWM) { + panel->backlight.level = + panel->backlight.pwm_funcs->get(connector, pipe); + panel->backlight.enabled = panel->backlight.pwm_enabled; + } else { + panel->backlight.level = panel->backlight.max; + panel->backlight.enabled = false; + } } } @@ -575,6 +661,15 @@ intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector) { struct intel_display *display = to_intel_display(connector); struct intel_dp *intel_dp = intel_attached_dp(connector); + struct intel_panel *panel = &connector->panel; + + if ((intel_dp->edp_dpcd[3] & DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE)) { + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] AUX Luminance Based Backlight Control Supported!\n", + connector->base.base.id, connector->base.name); + panel->backlight.edp.vesa.luminance_control_support = true; + return true; + } if (drm_edp_backlight_supported(intel_dp->edp_dpcd)) { drm_dbg_kms(display->drm, @@ -604,6 +699,7 @@ static const struct intel_panel_bl_funcs intel_dp_vesa_bl_funcs = { int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector) { struct intel_display *display = to_intel_display(connector); + struct intel_dp *intel_dp = intel_attached_dp(connector); struct drm_device *dev = connector->base.dev; struct intel_panel *panel = &connector->panel; bool try_intel_interface = false, try_vesa_interface = false; @@ -640,6 +736,10 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector) break; } + /* For eDP 1.5 and above we are supposed to use VESA interface for brightness control */ + if (intel_dp->edp_dpcd[0] >= DP_EDP_15) + try_vesa_interface = true; + /* * Since Intel has their own backlight control interface, the majority of machines out there * using DPCD backlight controls with Intel GPUs will be using this interface as opposed to @@ -653,7 +753,8 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector) * backlight interface at all. This means that the only sensible way for us to detect both * interfaces is to probe for Intel's first, and VESA's second. */ - if (try_intel_interface && intel_dp_aux_supports_hdr_backlight(connector)) { + if (try_intel_interface && intel_dp_aux_supports_hdr_backlight(connector) && + intel_dp->edp_dpcd[0] <= DP_EDP_14b) { drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Using Intel proprietary eDP backlight controls\n", connector->base.base.id, connector->base.name); panel->backlight.funcs = &intel_dp_hdr_bl_funcs; diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c index 00c493cc8a4b..cc312596fb77 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -705,10 +705,10 @@ int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector, *hdcp_capable = false; *hdcp2_capable = false; - if (!connector->mst_port) + if (!connector->mst.dp) return -EINVAL; - aux = &connector->port->aux; + aux = &connector->mst.port->aux; ret = _intel_dp_hdcp2_get_capability(aux, hdcp2_capable); if (ret) drm_dbg_kms(display->drm, @@ -799,7 +799,7 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector, { struct intel_display *display = to_intel_display(connector); struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct intel_hdcp *hdcp = &connector->hdcp; enum transcoder cpu_transcoder = hdcp->stream_transcoder; enum pipe pipe = (enum pipe)cpu_transcoder; @@ -883,7 +883,7 @@ int intel_dp_hdcp_init(struct intel_digital_port *dig_port, if (!is_hdcp_supported(display, port)) return 0; - if (intel_connector->mst_port) + if (intel_connector->mst.dp) return intel_hdcp_init(intel_connector, dig_port, &intel_dp_mst_hdcp_shim); else if (!intel_dp_is_edp(intel_dp)) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 8b1977cfec50..2966f5b39392 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -24,6 +24,7 @@ #include <linux/debugfs.h> #include <drm/display/drm_dp_helper.h> +#include <drm/drm_print.h> #include "i915_utils.h" #include "intel_display_core.h" @@ -119,16 +120,13 @@ intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : DP_PHY_REPEATER_MODE_NON_TRANSPARENT; - if (drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) != 1) - return false; - intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val; return true; } -static bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp) +bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp) { return intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] == @@ -146,6 +144,7 @@ static bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp) static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { int lttpr_count; + int ret; if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) return 0; @@ -172,22 +171,8 @@ static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_ return lttpr_count; } - /* - * See DP Standard v2.0 3.6.6.1. about the explicit disabling of - * non-transparent mode and the disable->enable non-transparent mode - * sequence. - */ - intel_dp_set_lttpr_transparent_mode(intel_dp, true); - - /* - * In case of unsupported number of LTTPRs or failing to switch to - * non-transparent mode fall-back to transparent link training mode, - * still taking into account any LTTPR common lane- rate/count limits. - */ - if (lttpr_count < 0) - goto out_reset_lttpr_count; - - if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { + ret = drm_dp_lttpr_init(&intel_dp->aux, lttpr_count); + if (ret) { lt_dbg(intel_dp, DP_PHY_DPRX, "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); @@ -196,6 +181,8 @@ static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_ goto out_reset_lttpr_count; } + intel_dp_set_lttpr_transparent_mode(intel_dp, false); + return lttpr_count; out_reset_lttpr_count: @@ -783,7 +770,7 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp, /* * WaEdpLinkRateDataReload * - * Parade PS8461E MUX (used on varius TGL+ laptops) needs + * Parade PS8461E MUX (used on various TGL+ laptops) needs * to snoop the link rates reported by the sink when we * use LINK_RATE_SET in order to operate in jitter cleaning * mode (as opposed to redriver mode). Unfortunately it @@ -1563,7 +1550,7 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp, if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n"); - return false; + goto out; } if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) && @@ -1575,6 +1562,19 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp, passed ? "passed" : "failed", crtc_state->port_clock, crtc_state->lane_count); +out: + /* + * Ensure that the training pattern does get set to TPS2 even in case + * of a failure, as is the case at the end of a passing link training + * and what is expected by the transcoder. Leaving TPS1 set (and + * disabling the link train mode in DP_TP_CTL later from TPS1 directly) + * would result in a stuck transcoder HW state and flip-done timeouts + * later in the modeset sequence. + */ + if (!passed) + intel_dp_program_link_training_pattern(intel_dp, crtc_state, + DP_PHY_DPRX, DP_TRAINING_PATTERN_2); + return passed; } @@ -1629,7 +1629,7 @@ void intel_dp_start_link_train(struct intel_atomic_state *state, /* * Ignore the link failure in CI * - * In fixed enviroments like CI, sometimes unexpected long HPDs are + * In fixed environments like CI, sometimes unexpected long HPDs are * generated by the displays. If ignore_long_hpd flag is set, such long * HPDs are ignored. And probably as a consequence of these ignored * long HPDs, subsequent link trainings are failed resulting into CI diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h index 2066b9146762..46614124569f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h @@ -15,6 +15,7 @@ struct intel_dp; int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE]); int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp); +bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp); void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 0c44fc7dd86c..02f95108c637 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -49,6 +49,7 @@ #include "intel_hdcp.h" #include "intel_hotplug.h" #include "intel_link_bw.h" +#include "intel_pfit.h" #include "intel_psr.h" #include "intel_vdsc.h" #include "skl_scaler.h" @@ -111,7 +112,7 @@ static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state, &crtc_state->hw.adjusted_mode; if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc) - return INT_MAX; + return 0; /* * DSC->DPT interface width: @@ -209,22 +210,56 @@ static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connec num_joined_pipes); } +static void intel_dp_mst_compute_min_hblank(struct intel_crtc_state *crtc_state, + int bpp_x16) +{ + struct intel_display *display = to_intel_display(crtc_state); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8; + int hblank; + + if (DISPLAY_VER(display) < 20) + return; + + /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */ + hblank = DIV_ROUND_UP((DIV_ROUND_UP + (adjusted_mode->htotal - adjusted_mode->hdisplay, 4) * bpp_x16), + symbol_size); + + crtc_state->min_hblank = hblank; +} + int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, - int max_bpp, int min_bpp, struct drm_connector_state *conn_state, - int step, bool dsc) + int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc) { struct intel_display *display = to_intel_display(intel_dp); struct drm_atomic_state *state = crtc_state->uapi.state; + struct drm_dp_mst_topology_state *mst_state = NULL; struct intel_connector *connector = to_intel_connector(conn_state->connector); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - fixed20_12 pbn_div; - int bpp, slots = -EINVAL; + bool is_mst = intel_dp->is_mst; + int bpp_x16, slots = -EINVAL; int dsc_slice_count = 0; - int max_dpt_bpp; + int max_dpt_bpp_x16; + + /* shouldn't happen, sanity check */ + drm_WARN_ON(display->drm, !dsc && (fxp_q4_to_frac(min_bpp_x16) || + fxp_q4_to_frac(max_bpp_x16) || + fxp_q4_to_frac(bpp_step_x16))); + + if (is_mst) { + mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst.mgr); + if (IS_ERR(mst_state)) + return PTR_ERR(mst_state); + + mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock, + crtc_state->lane_count); + } if (dsc) { if (!intel_dp_supports_fec(intel_dp, connector, crtc_state)) @@ -233,18 +268,15 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state); } - pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock, - crtc_state->lane_count); - - max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc); - if (max_bpp > max_dpt_bpp) { - drm_dbg_kms(display->drm, "Limiting bpp to max DPT bpp (%d -> %d)\n", - max_bpp, max_dpt_bpp); - max_bpp = max_dpt_bpp; + max_dpt_bpp_x16 = fxp_q4_from_int(intel_dp_mst_max_dpt_bpp(crtc_state, dsc)); + if (max_dpt_bpp_x16 && max_bpp_x16 > max_dpt_bpp_x16) { + drm_dbg_kms(display->drm, "Limiting bpp to max DPT bpp (" FXP_Q4_FMT " -> " FXP_Q4_FMT ")\n", + FXP_Q4_ARGS(max_bpp_x16), FXP_Q4_ARGS(max_dpt_bpp_x16)); + max_bpp_x16 = max_dpt_bpp_x16; } - drm_dbg_kms(display->drm, "Looking for slots in range min bpp %d max bpp %d\n", - min_bpp, max_bpp); + drm_dbg_kms(display->drm, "Looking for slots in range min bpp " FXP_Q4_FMT " max bpp " FXP_Q4_FMT "\n", + FXP_Q4_ARGS(min_bpp_x16), FXP_Q4_ARGS(max_bpp_x16)); if (dsc) { dsc_slice_count = intel_dp_mst_dsc_get_slice_count(connector, crtc_state); @@ -255,23 +287,27 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, } } - for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { + for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { int local_bw_overhead; int link_bpp_x16; - drm_dbg_kms(display->drm, "Trying bpp %d\n", bpp); + drm_dbg_kms(display->drm, "Trying bpp " FXP_Q4_FMT "\n", FXP_Q4_ARGS(bpp_x16)); - link_bpp_x16 = fxp_q4_from_int(dsc ? bpp : - intel_dp_output_bpp(crtc_state->output_format, bpp)); + link_bpp_x16 = dsc ? bpp_x16 : + fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format, + fxp_q4_to_int(bpp_x16))); local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, false, dsc_slice_count, link_bpp_x16); + + intel_dp_mst_compute_min_hblank(crtc_state, link_bpp_x16); + intel_dp_mst_compute_m_n(crtc_state, local_bw_overhead, link_bpp_x16, &crtc_state->dp_m_n); - if (intel_dp->is_mst) { + if (is_mst) { int remote_bw_overhead; int remote_tu; fixed20_12 pbn; @@ -296,7 +332,7 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock, link_bpp_x16, remote_bw_overhead)); - remote_tu = DIV_ROUND_UP(pbn.full, pbn_div.full); + remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full); /* * Aligning the TUs ensures that symbols consisting of multiple @@ -314,13 +350,13 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, * allocated for the whole path and the TUs allocated for the * first branch device's link also applies here. */ - pbn.full = remote_tu * pbn_div.full; + pbn.full = remote_tu * mst_state->pbn_div.full; drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu); crtc_state->dp_m_n.tu = remote_tu; - slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr, - connector->port, + slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst.mgr, + connector->mst.port, dfixed_trunc(pbn)); } else { /* Same as above for remote_tu */ @@ -341,6 +377,10 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, break; } + + /* Allow using zero step to indicate one try */ + if (!bpp_step_x16) + break; } if (slots < 0) { @@ -350,65 +390,42 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, } if (!dsc) - crtc_state->pipe_bpp = bpp; + crtc_state->pipe_bpp = fxp_q4_to_int(bpp_x16); else - crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp); + crtc_state->dsc.compressed_bpp_x16 = bpp_x16; - drm_dbg_kms(display->drm, "Got %d slots for pipe bpp %d dsc %d\n", - slots, bpp, dsc); + drm_dbg_kms(display->drm, "Got %d slots for pipe bpp " FXP_Q4_FMT " dsc %d\n", + slots, FXP_Q4_ARGS(bpp_x16), dsc); return 0; } -static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state, - int max_bpp, int min_bpp, - struct link_config_limits *limits, - struct drm_connector_state *conn_state, - int step, bool dsc) -{ - struct drm_atomic_state *state = crtc_state->uapi.state; - struct drm_dp_mst_topology_state *mst_state; - - mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr); - if (IS_ERR(mst_state)) - return PTR_ERR(mst_state); - - crtc_state->lane_count = limits->max_lane_count; - crtc_state->port_clock = limits->max_rate; - - mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock, - crtc_state->lane_count); - - return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, - max_bpp, min_bpp, - conn_state, step, dsc); -} - static int mst_stream_compute_link_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state, - struct link_config_limits *limits) + const struct link_config_limits *limits) { + crtc_state->lane_count = limits->max_lane_count; + crtc_state->port_clock = limits->max_rate; + /* * FIXME: allocate the BW according to link_bpp, which in the case of * YUV420 is only half of the pipe bpp value. */ - return mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state, - fxp_q4_to_int(limits->link.max_bpp_x16), - fxp_q4_to_int(limits->link.min_bpp_x16), - limits, - conn_state, 2 * 3, false); + return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state, + limits->link.min_bpp_x16, + limits->link.max_bpp_x16, + fxp_q4_from_int(2 * 3), false); } static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state, - struct link_config_limits *limits) + const struct link_config_limits *limits) { struct intel_display *display = to_intel_display(intel_dp); struct intel_connector *connector = to_intel_connector(conn_state->connector); - int i, num_bpc; + int num_bpc; u8 dsc_bpc[3] = {}; int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp; int min_compressed_bpp, max_compressed_bpp; @@ -422,15 +439,8 @@ static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp, drm_dbg_kms(display->drm, "DSC Source supported min bpp %d max bpp %d\n", min_bpp, max_bpp); - sink_max_bpp = dsc_bpc[0] * 3; - sink_min_bpp = sink_max_bpp; - - for (i = 1; i < num_bpc; i++) { - if (sink_min_bpp > dsc_bpc[i] * 3) - sink_min_bpp = dsc_bpc[i] * 3; - if (sink_max_bpp < dsc_bpc[i] * 3) - sink_max_bpp = dsc_bpc[i] * 3; - } + sink_min_bpp = min_array(dsc_bpc, num_bpc) * 3; + sink_max_bpp = max_array(dsc_bpc, num_bpc) * 3; drm_dbg_kms(display->drm, "DSC Sink supported min bpp %d max bpp %d\n", sink_min_bpp, sink_max_bpp); @@ -455,9 +465,13 @@ static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp, min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(display, min_compressed_bpp, crtc_state->pipe_bpp); - return mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state, max_compressed_bpp, - min_compressed_bpp, limits, - conn_state, 1, true); + crtc_state->lane_count = limits->max_lane_count; + crtc_state->port_clock = limits->max_rate; + + return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state, + fxp_q4_from_int(min_compressed_bpp), + fxp_q4_from_int(max_compressed_bpp), + fxp_q4_from_int(1), true); } static int mst_stream_update_slots(struct intel_dp *intel_dp, @@ -465,7 +479,7 @@ static int mst_stream_update_slots(struct intel_dp *intel_dp, struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr; + struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst.mgr; struct drm_dp_mst_topology_state *topology_state; u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ? DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B; @@ -495,8 +509,8 @@ hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector, { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - bool is_uhbr_sink = connector->mst_port && - drm_dp_128b132b_supported(connector->mst_port->dpcd); + bool is_uhbr_sink = connector->mst.dp && + drm_dp_128b132b_supported(connector->mst.dp->dpcd); int hblank_limit = is_uhbr_sink ? 500 : 300; if (!connector->dp.dsc_hblank_expansion_quirk) @@ -679,7 +693,7 @@ static int mst_stream_compute_config(struct intel_encoder *encoder, ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, conn_state, &limits, - pipe_config->dp_m_n.tu, false); + pipe_config->dp_m_n.tu); } if (ret) @@ -727,7 +741,7 @@ intel_dp_mst_transcoder_mask(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state; struct intel_crtc *crtc; - if (connector->mst_port != mst_port || !conn_state->base.crtc) + if (connector->mst.dp != mst_port || !conn_state->base.crtc) continue; crtc = to_intel_crtc(conn_state->base.crtc); @@ -755,12 +769,12 @@ static u8 get_pipes_downstream_of_mst_port(struct intel_atomic_state *state, if (!conn_state->base.crtc) continue; - if (&connector->mst_port->mst_mgr != mst_mgr) + if (&connector->mst.dp->mst.mgr != mst_mgr) continue; - if (connector->port != parent_port && + if (connector->mst.port != parent_port && !drm_dp_mst_port_downstream_of_parent(mst_mgr, - connector->port, + connector->mst.port, parent_port)) continue; @@ -837,7 +851,7 @@ static int intel_dp_mst_check_bw(struct intel_atomic_state *state, * @state must be recomputed with the updated @limits. * * Returns: - * - 0 if the confugration is valid + * - 0 if the configuration is valid * - %-EAGAIN, if the configuration is invalid and @limits got updated * with fallback values with which the configuration of all CRTCs in * @state must be recomputed @@ -911,7 +925,7 @@ mst_connector_atomic_topology_check(struct intel_connector *connector, struct intel_crtc_state *crtc_state; struct intel_crtc *crtc; - if (connector_iter->mst_port != connector->mst_port || + if (connector_iter->mst.dp != connector->mst.dp || connector_iter == connector) continue; @@ -943,33 +957,32 @@ mst_connector_atomic_topology_check(struct intel_connector *connector, } static int -mst_connector_atomic_check(struct drm_connector *connector, +mst_connector_atomic_check(struct drm_connector *_connector, struct drm_atomic_state *_state) { struct intel_atomic_state *state = to_intel_atomic_state(_state); - struct intel_connector *intel_connector = - to_intel_connector(connector); + struct intel_connector *connector = to_intel_connector(_connector); int ret; - ret = intel_digital_connector_atomic_check(connector, &state->base); + ret = intel_digital_connector_atomic_check(&connector->base, &state->base); if (ret) return ret; - ret = mst_connector_atomic_topology_check(intel_connector, state); + ret = mst_connector_atomic_topology_check(connector, state); if (ret) return ret; - if (intel_connector_needs_modeset(state, connector)) { + if (intel_connector_needs_modeset(state, &connector->base)) { ret = intel_dp_tunnel_atomic_check_state(state, - intel_connector->mst_port, - intel_connector); + connector->mst.dp, + connector); if (ret) return ret; } return drm_dp_atomic_release_time_slots(&state->base, - &intel_connector->mst_port->mst_mgr, - intel_connector->port); + &connector->mst.dp->mst.mgr, + connector->mst.port); } static void mst_stream_disable(struct intel_atomic_state *state, @@ -982,16 +995,20 @@ static void mst_stream_disable(struct intel_atomic_state *state, struct intel_dp *intel_dp = to_primary_dp(encoder); struct intel_connector *connector = to_intel_connector(old_conn_state->connector); + enum transcoder trans = old_crtc_state->cpu_transcoder; drm_dbg_kms(display->drm, "active links %d\n", - intel_dp->active_mst_links); + intel_dp->mst.active_links); - if (intel_dp->active_mst_links == 1) + if (intel_dp->mst.active_links == 1) intel_dp->link_trained = false; intel_hdcp_disable(intel_mst->connector); intel_dp_sink_disable_decompression(state, connector, old_crtc_state); + + if (DISPLAY_VER(display) >= 20) + intel_de_write(display, DP_MIN_HBLANK_CTL(trans), 0); } static void mst_stream_post_disable(struct intel_atomic_state *state, @@ -1006,19 +1023,19 @@ static void mst_stream_post_disable(struct intel_atomic_state *state, struct intel_connector *connector = to_intel_connector(old_conn_state->connector); struct drm_dp_mst_topology_state *old_mst_state = - drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst_mgr); + drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst.mgr); struct drm_dp_mst_topology_state *new_mst_state = - drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr); + drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst.mgr); const struct drm_dp_mst_atomic_payload *old_payload = - drm_atomic_get_mst_payload_state(old_mst_state, connector->port); + drm_atomic_get_mst_payload_state(old_mst_state, connector->mst.port); struct drm_dp_mst_atomic_payload *new_payload = - drm_atomic_get_mst_payload_state(new_mst_state, connector->port); + drm_atomic_get_mst_payload_state(new_mst_state, connector->mst.port); struct intel_crtc *pipe_crtc; bool last_mst_stream; int i; - intel_dp->active_mst_links--; - last_mst_stream = intel_dp->active_mst_links == 0; + intel_dp->mst.active_links--; + last_mst_stream = intel_dp->mst.active_links == 0; drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && last_mst_stream && !intel_dp_mst_is_master_trans(old_crtc_state)); @@ -1031,7 +1048,7 @@ static void mst_stream_post_disable(struct intel_atomic_state *state, intel_disable_transcoder(old_crtc_state); - drm_dp_remove_payload_part1(&intel_dp->mst_mgr, new_mst_state, new_payload); + drm_dp_remove_payload_part1(&intel_dp->mst.mgr, new_mst_state, new_payload); intel_ddi_clear_act_sent(encoder, old_crtc_state); @@ -1040,9 +1057,9 @@ static void mst_stream_post_disable(struct intel_atomic_state *state, TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); intel_ddi_wait_for_act_sent(encoder, old_crtc_state); - drm_dp_check_act_status(&intel_dp->mst_mgr); + drm_dp_check_act_status(&intel_dp->mst.mgr); - drm_dp_remove_payload_part2(&intel_dp->mst_mgr, new_mst_state, + drm_dp_remove_payload_part2(&intel_dp->mst.mgr, new_mst_state, old_payload, new_payload); intel_ddi_disable_transcoder_func(old_crtc_state); @@ -1063,7 +1080,7 @@ static void mst_stream_post_disable(struct intel_atomic_state *state, * Power down mst path before disabling the port, otherwise we end * up getting interrupts from the sink upon detecting link loss. */ - drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, + drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, false); /* @@ -1088,7 +1105,7 @@ static void mst_stream_post_disable(struct intel_atomic_state *state, old_crtc_state, NULL); drm_dbg_kms(display->drm, "active links %d\n", - intel_dp->active_mst_links); + intel_dp->mst.active_links); } static void mst_stream_post_pll_disable(struct intel_atomic_state *state, @@ -1099,7 +1116,7 @@ static void mst_stream_post_pll_disable(struct intel_atomic_state *state, struct intel_encoder *primary_encoder = to_primary_encoder(encoder); struct intel_dp *intel_dp = to_primary_dp(encoder); - if (intel_dp->active_mst_links == 0 && + if (intel_dp->mst.active_links == 0 && primary_encoder->post_pll_disable) primary_encoder->post_pll_disable(state, primary_encoder, old_crtc_state, old_conn_state); } @@ -1112,7 +1129,7 @@ static void mst_stream_pre_pll_enable(struct intel_atomic_state *state, struct intel_encoder *primary_encoder = to_primary_encoder(encoder); struct intel_dp *intel_dp = to_primary_dp(encoder); - if (intel_dp->active_mst_links == 0) + if (intel_dp->mst.active_links == 0) primary_encoder->pre_pll_enable(state, primary_encoder, pipe_config, NULL); else @@ -1145,7 +1162,7 @@ static void intel_mst_reprobe_topology(struct intel_dp *intel_dp, crtc_state->port_clock, crtc_state->lane_count)) return; - drm_dp_mst_topology_queue_probe(&intel_dp->mst_mgr); + drm_dp_mst_topology_queue_probe(&intel_dp->mst.mgr); intel_mst_set_probed_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count); @@ -1163,7 +1180,7 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state, struct intel_connector *connector = to_intel_connector(conn_state->connector); struct drm_dp_mst_topology_state *mst_state = - drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr); + drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst.mgr); int ret; bool first_mst_stream; @@ -1172,17 +1189,17 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state, */ connector->encoder = encoder; intel_mst->connector = connector; - first_mst_stream = intel_dp->active_mst_links == 0; + first_mst_stream = intel_dp->mst.active_links == 0; drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && first_mst_stream && !intel_dp_mst_is_master_trans(pipe_config)); drm_dbg_kms(display->drm, "active links %d\n", - intel_dp->active_mst_links); + intel_dp->mst.active_links); if (first_mst_stream) intel_dp_set_power(intel_dp, DP_SET_POWER_D0); - drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true); + drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true); intel_dp_sink_enable_decompression(state, connector, pipe_config); @@ -1193,10 +1210,10 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state, intel_mst_reprobe_topology(intel_dp, pipe_config); } - intel_dp->active_mst_links++; + intel_dp->mst.active_links++; - ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state, - drm_atomic_get_mst_payload_state(mst_state, connector->port)); + ret = drm_dp_add_payload_part1(&intel_dp->mst.mgr, mst_state, + drm_atomic_get_mst_payload_state(mst_state, connector->mst.port)); if (ret < 0) intel_dp_queue_modeset_retry_for_link(state, primary_encoder, pipe_config); @@ -1220,11 +1237,10 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state, static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); u32 clear = 0; u32 set = 0; - if (!IS_ALDERLAKE_P(i915)) + if (!display->platform.alderlake_p) return; if (!IS_DISPLAY_STEP(display, STEP_D0, STEP_FOREVER)) @@ -1261,11 +1277,11 @@ static void mst_stream_enable(struct intel_atomic_state *state, struct intel_dp *intel_dp = to_primary_dp(encoder); struct intel_connector *connector = to_intel_connector(conn_state->connector); struct drm_dp_mst_topology_state *mst_state = - drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr); + drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst.mgr); enum transcoder trans = pipe_config->cpu_transcoder; - bool first_mst_stream = intel_dp->active_mst_links == 1; + bool first_mst_stream = intel_dp->mst.active_links == 1; struct intel_crtc *pipe_crtc; - int ret, i; + int ret, i, min_hblank; drm_WARN_ON(display->drm, pipe_config->has_pch_encoder); @@ -1280,6 +1296,29 @@ static void mst_stream_enable(struct intel_atomic_state *state, TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); } + if (DISPLAY_VER(display) >= 20) { + /* + * adjust the BlankingStart/BlankingEnd framing control from + * the calculated value + */ + min_hblank = pipe_config->min_hblank - 2; + + /* Maximum value to be programmed is limited to 0x10 */ + min_hblank = min(0x10, min_hblank); + + /* + * Minimum hblank accepted for 128b/132b would be 5 and for + * 8b/10b would be 3 symbol count + */ + if (intel_dp_is_uhbr(pipe_config)) + min_hblank = max(min_hblank, 5); + else + min_hblank = max(min_hblank, 3); + + intel_de_write(display, DP_MIN_HBLANK_CTL(trans), + min_hblank); + } + enable_bs_jitter_was(pipe_config); intel_ddi_enable_transcoder_func(encoder, pipe_config); @@ -1290,17 +1329,17 @@ static void mst_stream_enable(struct intel_atomic_state *state, TRANS_DDI_DP_VC_PAYLOAD_ALLOC); drm_dbg_kms(display->drm, "active links %d\n", - intel_dp->active_mst_links); + intel_dp->mst.active_links); intel_ddi_wait_for_act_sent(encoder, pipe_config); - drm_dp_check_act_status(&intel_dp->mst_mgr); + drm_dp_check_act_status(&intel_dp->mst.mgr); if (first_mst_stream) intel_ddi_wait_for_fec_status(encoder, pipe_config, true); - ret = drm_dp_add_payload_part2(&intel_dp->mst_mgr, + ret = drm_dp_add_payload_part2(&intel_dp->mst.mgr, drm_atomic_get_mst_payload_state(mst_state, - connector->port)); + connector->mst.port)); if (ret < 0) intel_dp_queue_modeset_retry_for_link(state, primary_encoder, pipe_config); @@ -1349,23 +1388,23 @@ static bool mst_stream_initial_fastset_check(struct intel_encoder *encoder, return intel_dp_initial_fastset_check(primary_encoder, crtc_state); } -static int mst_connector_get_ddc_modes(struct drm_connector *connector) +static int mst_connector_get_ddc_modes(struct drm_connector *_connector) { - struct intel_display *display = to_intel_display(connector->dev); - struct intel_connector *intel_connector = to_intel_connector(connector); - struct intel_dp *intel_dp = intel_connector->mst_port; + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); + struct intel_dp *intel_dp = connector->mst.dp; const struct drm_edid *drm_edid; int ret; - if (drm_connector_is_unregistered(connector)) - return intel_connector_update_modes(connector, NULL); + if (drm_connector_is_unregistered(&connector->base)) + return intel_connector_update_modes(&connector->base, NULL); if (!intel_display_driver_check_access(display)) - return drm_edid_connector_add_modes(connector); + return drm_edid_connector_add_modes(&connector->base); - drm_edid = drm_dp_mst_edid_read(connector, &intel_dp->mst_mgr, intel_connector->port); + drm_edid = drm_dp_mst_edid_read(&connector->base, &intel_dp->mst.mgr, connector->mst.port); - ret = intel_connector_update_modes(connector, drm_edid); + ret = intel_connector_update_modes(&connector->base, drm_edid); drm_edid_free(drm_edid); @@ -1373,32 +1412,29 @@ static int mst_connector_get_ddc_modes(struct drm_connector *connector) } static int -mst_connector_late_register(struct drm_connector *connector) +mst_connector_late_register(struct drm_connector *_connector) { - struct intel_connector *intel_connector = to_intel_connector(connector); + struct intel_connector *connector = to_intel_connector(_connector); int ret; - ret = drm_dp_mst_connector_late_register(connector, - intel_connector->port); + ret = drm_dp_mst_connector_late_register(&connector->base, connector->mst.port); if (ret < 0) return ret; - ret = intel_connector_register(connector); + ret = intel_connector_register(&connector->base); if (ret < 0) - drm_dp_mst_connector_early_unregister(connector, - intel_connector->port); + drm_dp_mst_connector_early_unregister(&connector->base, connector->mst.port); return ret; } static void -mst_connector_early_unregister(struct drm_connector *connector) +mst_connector_early_unregister(struct drm_connector *_connector) { - struct intel_connector *intel_connector = to_intel_connector(connector); + struct intel_connector *connector = to_intel_connector(_connector); - intel_connector_unregister(connector); - drm_dp_mst_connector_early_unregister(connector, - intel_connector->port); + intel_connector_unregister(&connector->base); + drm_dp_mst_connector_early_unregister(&connector->base, connector->mst.port); } static const struct drm_connector_funcs mst_connector_funcs = { @@ -1412,23 +1448,24 @@ static const struct drm_connector_funcs mst_connector_funcs = { .atomic_duplicate_state = intel_digital_connector_duplicate_state, }; -static int mst_connector_get_modes(struct drm_connector *connector) +static int mst_connector_get_modes(struct drm_connector *_connector) { - return mst_connector_get_ddc_modes(connector); + struct intel_connector *connector = to_intel_connector(_connector); + + return mst_connector_get_ddc_modes(&connector->base); } static int -mst_connector_mode_valid_ctx(struct drm_connector *connector, - struct drm_display_mode *mode, +mst_connector_mode_valid_ctx(struct drm_connector *_connector, + const struct drm_display_mode *mode, struct drm_modeset_acquire_ctx *ctx, enum drm_mode_status *status) { - struct intel_display *display = to_intel_display(connector->dev); - struct drm_i915_private *dev_priv = to_i915(connector->dev); - struct intel_connector *intel_connector = to_intel_connector(connector); - struct intel_dp *intel_dp = intel_connector->mst_port; - struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr; - struct drm_dp_mst_port *port = intel_connector->port; + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); + struct intel_dp *intel_dp = connector->mst.dp; + struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst.mgr; + struct drm_dp_mst_port *port = connector->mst.port; const int min_bpp = 18; int max_dotclk = display->cdclk.max_dotclk_freq; int max_rate, mode_rate, max_lanes, max_link_clock; @@ -1439,12 +1476,12 @@ mst_connector_mode_valid_ctx(struct drm_connector *connector, int target_clock = mode->clock; int num_joined_pipes; - if (drm_connector_is_unregistered(connector)) { + if (drm_connector_is_unregistered(&connector->base)) { *status = MODE_ERROR; return 0; } - *status = intel_cpu_transcoder_mode_valid(dev_priv, mode); + *status = intel_cpu_transcoder_mode_valid(display, mode); if (*status != MODE_OK) return 0; @@ -1477,7 +1514,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *connector, * corresponding link capabilities of the sink) in case the * stream is uncompressed for it by the last branch device. */ - num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, intel_connector, + num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector, mode->hdisplay, target_clock); max_dotclk *= num_joined_pipes; @@ -1491,14 +1528,14 @@ mst_connector_mode_valid_ctx(struct drm_connector *connector, return 0; } - if (intel_dp_has_dsc(intel_connector)) { + if (intel_dp_has_dsc(connector)) { /* * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_connector, U8_MAX); + int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); - if (drm_dp_sink_supports_fec(intel_connector->dp.fec_capability)) { + if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(display, max_link_clock, @@ -1509,7 +1546,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *connector, INTEL_OUTPUT_FORMAT_RGB, pipe_bpp, 64); dsc_slice_count = - intel_dp_dsc_get_slice_count(intel_connector, + intel_dp_dsc_get_slice_count(connector, target_clock, mode->hdisplay, num_joined_pipes); @@ -1528,44 +1565,44 @@ mst_connector_mode_valid_ctx(struct drm_connector *connector, return 0; } - *status = intel_mode_valid_max_plane_size(dev_priv, mode, num_joined_pipes); + *status = intel_mode_valid_max_plane_size(display, mode, num_joined_pipes); return 0; } static struct drm_encoder * -mst_connector_atomic_best_encoder(struct drm_connector *connector, +mst_connector_atomic_best_encoder(struct drm_connector *_connector, struct drm_atomic_state *state) { - struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, - connector); - struct intel_connector *intel_connector = to_intel_connector(connector); - struct intel_dp *intel_dp = intel_connector->mst_port; + struct intel_connector *connector = to_intel_connector(_connector); + struct drm_connector_state *connector_state = + drm_atomic_get_new_connector_state(state, &connector->base); + struct intel_dp *intel_dp = connector->mst.dp; struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc); - return &intel_dp->mst_encoders[crtc->pipe]->base.base; + return &intel_dp->mst.stream_encoders[crtc->pipe]->base.base; } static int -mst_connector_detect_ctx(struct drm_connector *connector, +mst_connector_detect_ctx(struct drm_connector *_connector, struct drm_modeset_acquire_ctx *ctx, bool force) { - struct intel_display *display = to_intel_display(connector->dev); - struct intel_connector *intel_connector = to_intel_connector(connector); - struct intel_dp *intel_dp = intel_connector->mst_port; + struct intel_connector *connector = to_intel_connector(_connector); + struct intel_display *display = to_intel_display(connector); + struct intel_dp *intel_dp = connector->mst.dp; if (!intel_display_device_enabled(display)) return connector_status_disconnected; - if (drm_connector_is_unregistered(connector)) + if (drm_connector_is_unregistered(&connector->base)) return connector_status_disconnected; if (!intel_display_driver_check_access(display)) - return connector->status; + return connector->base.status; - intel_dp_flush_connector_commits(intel_connector); + intel_dp_flush_connector_commits(connector); - return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr, - intel_connector->port); + return drm_dp_mst_detect_port(&connector->base, ctx, &intel_dp->mst.mgr, + connector->mst.port); } static const struct drm_connector_helper_funcs mst_connector_helper_funcs = { @@ -1601,29 +1638,30 @@ static bool mst_connector_get_hw_state(struct intel_connector *connector) } static int mst_topology_add_connector_properties(struct intel_dp *intel_dp, - struct drm_connector *connector, + struct drm_connector *_connector, const char *pathprop) { struct intel_display *display = to_intel_display(intel_dp); + struct intel_connector *connector = to_intel_connector(_connector); - drm_object_attach_property(&connector->base, + drm_object_attach_property(&connector->base.base, display->drm->mode_config.path_property, 0); - drm_object_attach_property(&connector->base, + drm_object_attach_property(&connector->base.base, display->drm->mode_config.tile_property, 0); - intel_attach_force_audio_property(connector); - intel_attach_broadcast_rgb_property(connector); + intel_attach_force_audio_property(&connector->base); + intel_attach_broadcast_rgb_property(&connector->base); /* * Reuse the prop from the SST connector because we're * not allowed to create new props after device registration. */ - connector->max_bpc_property = + connector->base.max_bpc_property = intel_dp->attached_connector->base.max_bpc_property; - if (connector->max_bpc_property) - drm_connector_attach_max_bpc_property(connector, 6, 12); + if (connector->base.max_bpc_property) + drm_connector_attach_max_bpc_property(&connector->base, 6, 12); - return drm_connector_set_path_property(connector, pathprop); + return drm_connector_set_path_property(&connector->base, pathprop); } static void @@ -1655,10 +1693,10 @@ static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *conn * A logical port's OUI (at least for affected sinks) is all 0, so * instead of that the parent port's OUI is used for identification. */ - if (drm_dp_mst_port_is_logical(connector->port)) { - aux = drm_dp_mst_aux_for_parent(connector->port); + if (drm_dp_mst_port_is_logical(connector->mst.port)) { + aux = drm_dp_mst_aux_for_parent(connector->mst.port); if (!aux) - aux = &connector->mst_port->aux; + aux = &connector->mst.dp->aux; } if (drm_dp_read_dpcd_caps(aux, dpcd) < 0) @@ -1693,72 +1731,68 @@ mst_topology_add_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) { - struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); + struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst.mgr); struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - struct intel_connector *intel_connector; - struct drm_connector *connector; + struct intel_connector *connector; enum pipe pipe; int ret; - intel_connector = intel_connector_alloc(); - if (!intel_connector) + connector = intel_connector_alloc(); + if (!connector) return NULL; - connector = &intel_connector->base; - - intel_connector->get_hw_state = mst_connector_get_hw_state; - intel_connector->sync_state = intel_dp_connector_sync_state; - intel_connector->mst_port = intel_dp; - intel_connector->port = port; + connector->get_hw_state = mst_connector_get_hw_state; + connector->sync_state = intel_dp_connector_sync_state; + connector->mst.dp = intel_dp; + connector->mst.port = port; drm_dp_mst_get_port_malloc(port); - intel_dp_init_modeset_retry_work(intel_connector); - - ret = drm_connector_dynamic_init(display->drm, connector, &mst_connector_funcs, + ret = drm_connector_dynamic_init(display->drm, &connector->base, &mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort, NULL); - if (ret) { - drm_dp_mst_put_port_malloc(port); - intel_connector_free(intel_connector); - return NULL; - } + if (ret) + goto err_put_port; - intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port); - intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector); - intel_connector->dp.dsc_hblank_expansion_quirk = - detect_dsc_hblank_expansion_quirk(intel_connector); + connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port); + intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, connector); + connector->dp.dsc_hblank_expansion_quirk = + detect_dsc_hblank_expansion_quirk(connector); - drm_connector_helper_add(connector, &mst_connector_helper_funcs); + drm_connector_helper_add(&connector->base, &mst_connector_helper_funcs); for_each_pipe(display, pipe) { struct drm_encoder *enc = - &intel_dp->mst_encoders[pipe]->base.base; + &intel_dp->mst.stream_encoders[pipe]->base.base; - ret = drm_connector_attach_encoder(&intel_connector->base, enc); + ret = drm_connector_attach_encoder(&connector->base, enc); if (ret) - goto err; + goto err_cleanup_connector; } - ret = mst_topology_add_connector_properties(intel_dp, connector, pathprop); + ret = mst_topology_add_connector_properties(intel_dp, &connector->base, pathprop); if (ret) - goto err; + goto err_cleanup_connector; - ret = intel_dp_hdcp_init(dig_port, intel_connector); + ret = intel_dp_hdcp_init(dig_port, connector); if (ret) drm_dbg_kms(display->drm, "[%s:%d] HDCP MST init failed, skipping.\n", - connector->name, connector->base.id); + connector->base.name, connector->base.base.id); + + return &connector->base; - return connector; +err_cleanup_connector: + drm_connector_cleanup(&connector->base); +err_put_port: + drm_dp_mst_put_port_malloc(port); + intel_connector_free(connector); -err: - drm_connector_cleanup(connector); return NULL; } static void mst_topology_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr) { - struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); + struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst.mgr); intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); } @@ -1831,14 +1865,14 @@ mst_stream_encoders_create(struct intel_digital_port *dig_port) enum pipe pipe; for_each_pipe(display, pipe) - intel_dp->mst_encoders[pipe] = mst_stream_encoder_create(dig_port, pipe); + intel_dp->mst.stream_encoders[pipe] = mst_stream_encoder_create(dig_port, pipe); return true; } int intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port) { - return dig_port->dp.active_mst_links; + return dig_port->dp.mst.active_links; } int @@ -1858,14 +1892,15 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) if (DISPLAY_VER(display) < 11 && port == PORT_E) return 0; - intel_dp->mst_mgr.cbs = &mst_topology_cbs; + intel_dp->mst.mgr.cbs = &mst_topology_cbs; /* create encoders */ mst_stream_encoders_create(dig_port); - ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, display->drm, - &intel_dp->aux, 16, 3, conn_base_id); + ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst.mgr, display->drm, + &intel_dp->aux, 16, + INTEL_NUM_PIPES(display), conn_base_id); if (ret) { - intel_dp->mst_mgr.cbs = NULL; + intel_dp->mst.mgr.cbs = NULL; return ret; } @@ -1874,7 +1909,7 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) bool intel_dp_mst_source_support(struct intel_dp *intel_dp) { - return intel_dp->mst_mgr.cbs; + return intel_dp->mst.mgr.cbs; } void @@ -1885,10 +1920,10 @@ intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port) if (!intel_dp_mst_source_support(intel_dp)) return; - drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr); + drm_dp_mst_topology_mgr_destroy(&intel_dp->mst.mgr); /* encoders will get killed by normal cleanup */ - intel_dp->mst_mgr.cbs = NULL; + intel_dp->mst.mgr.cbs = NULL; } bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state) @@ -1919,11 +1954,11 @@ intel_dp_mst_add_topology_state_for_connector(struct intel_atomic_state *state, { struct drm_dp_mst_topology_state *mst_state; - if (!connector->mst_port) + if (!connector->mst.dp) return 0; mst_state = drm_atomic_get_mst_topology_state(&state->base, - &connector->mst_port->mst_mgr); + &connector->mst.dp->mst.mgr); if (IS_ERR(mst_state)) return PTR_ERR(mst_state); @@ -2021,7 +2056,7 @@ bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state; struct intel_crtc *crtc_iter; - if (connector->mst_port != crtc_connector->mst_port || + if (connector->mst.dp != crtc_connector->mst.dp || !conn_state->crtc) continue; @@ -2044,7 +2079,7 @@ bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state, * case. */ if (connector->dp.dsc_decompression_aux == - &connector->mst_port->aux) + &connector->mst.dp->aux) return true; } @@ -2056,7 +2091,7 @@ bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state, * @intel_dp: DP port object * * Prepare an MST link for topology probing, programming the target - * link parameters to DPCD. This step is a requirement of the enumaration + * link parameters to DPCD. This step is a requirement of the enumeration * of path resources during probing. */ void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp) @@ -2105,7 +2140,7 @@ bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp) if (!intel_dp->is_mst) return true; - ret = drm_dp_dpcd_readb(intel_dp->mst_mgr.aux, DP_MSTM_CTRL, &val); + ret = drm_dp_dpcd_readb(intel_dp->mst.mgr.aux, DP_MSTM_CTRL, &val); /* Adjust the expected register value for SST + SideBand. */ if (ret < 0 || val != (DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC)) { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h index c6bdc1d190a4..c1bbfeb02ca9 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.h +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h @@ -33,8 +33,7 @@ bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp); int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, - int max_bpp, int min_bpp, struct drm_connector_state *conn_state, - int step, bool dsc); + int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc); #endif /* __INTEL_DP_MST_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_test.c b/drivers/gpu/drm/i915/display/intel_dp_test.c index 380b359b0420..bd61f3c3ec91 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_test.c +++ b/drivers/gpu/drm/i915/display/intel_dp_test.c @@ -6,6 +6,8 @@ #include <drm/display/drm_dp.h> #include <drm/display/drm_dp_helper.h> #include <drm/drm_edid.h> +#include <drm/drm_file.h> +#include <drm/drm_print.h> #include <drm/drm_probe_helper.h> #include "i915_reg.h" @@ -257,7 +259,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, /* * FIXME: Ideally pattern should come from DPCD 0x250. As * current firmware of DPR-100 could not set it, so hardcoding - * now for complaince test. + * now for compliance test. */ drm_dbg_kms(display->drm, "Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); @@ -275,7 +277,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, /* * FIXME: Ideally pattern should come from DPCD 0x24A. As * current firmware of DPR-100 could not set it, so hardcoding - * now for complaince test. + * now for compliance test. */ drm_dbg_kms(display->drm, "Set HBR2 compliance Phy Test Pattern\n"); diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c index 589872babdd7..faa2b7a46699 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c @@ -4,6 +4,7 @@ */ #include <drm/display/drm_dp_tunnel.h> +#include <drm/drm_print.h> #include "intel_atomic.h" #include "intel_display_core.h" @@ -647,7 +648,7 @@ void intel_dp_tunnel_atomic_clear_stream_bw(struct intel_atomic_state *state, * @state must be recomputed with the updated @limits. * * Returns: - * - 0 if the confugration is valid + * - 0 if the configuration is valid * - %-EAGAIN, if the configuration is invalid and @limits got updated * with fallback values with which the configuration of all CRTCs in * @state must be recomputed diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h index e9314cf25a19..7f0f720e8dca 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h @@ -20,7 +20,8 @@ struct intel_dp; struct intel_encoder; struct intel_link_bw_limits; -#if IS_ENABLED(CONFIG_DRM_I915_DP_TUNNEL) && defined(I915) +#if (IS_ENABLED(CONFIG_DRM_I915_DP_TUNNEL) && defined(I915)) || \ + (IS_ENABLED(CONFIG_DRM_XE_DP_TUNNEL) && !defined(I915)) int intel_dp_tunnel_detect(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx); void intel_dp_tunnel_disconnect(struct intel_dp *intel_dp); @@ -127,6 +128,6 @@ intel_dp_tunnel_mgr_init(struct intel_display *display) static inline void intel_dp_tunnel_mgr_cleanup(struct intel_display *display) {} -#endif /* CONFIG_DRM_I915_DP_TUNNEL */ +#endif /* CONFIG_DRM_I915_DP_TUNNEL || CONFIG_DRM_XE_DP_TUNNEL */ #endif /* __INTEL_DP_TUNNEL_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 52a36a2281e6..429f89543789 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -40,7 +40,7 @@ * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI * ports. DPIO is the name given to such a display PHY. These PHYs * don't follow the standard programming model using direct MMIO - * registers, and instead their registers must be accessed trough IOSF + * registers, and instead their registers must be accessed through IOSF * sideband. VLV has one such PHY for driving ports B and C, and CHV * adds another PHY for driving port D. Each PHY responds to specific * IOSF-SB port. @@ -1156,3 +1156,37 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder, vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060); vlv_dpio_put(dev_priv); } + +void vlv_wait_port_ready(struct intel_encoder *encoder, + unsigned int expected_mask) +{ + struct intel_display *display = to_intel_display(encoder); + u32 port_mask; + i915_reg_t dpll_reg; + + switch (encoder->port) { + default: + MISSING_CASE(encoder->port); + fallthrough; + case PORT_B: + port_mask = DPLL_PORTB_READY_MASK; + dpll_reg = DPLL(display, 0); + break; + case PORT_C: + port_mask = DPLL_PORTC_READY_MASK; + dpll_reg = DPLL(display, 0); + expected_mask <<= 4; + break; + case PORT_D: + port_mask = DPLL_PORTD_READY_MASK; + dpll_reg = DPIO_PHY_STATUS; + break; + } + + if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000)) + drm_WARN(display->drm, 1, + "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", + encoder->base.base.id, encoder->base.name, + intel_de_read(display, dpll_reg) & port_mask, + expected_mask); +} diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h index a82939165546..35baede3d6ad 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h @@ -72,6 +72,8 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void vlv_phy_reset_lanes(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state); +void vlv_wait_port_ready(struct intel_encoder *encoder, + unsigned int expected_mask); #else static inline void bxt_port_to_phy_channel(struct intel_display *display, enum port port, enum dpio_phy *phy, enum dpio_channel *ch) @@ -170,6 +172,10 @@ static inline void vlv_phy_reset_lanes(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state) { } +static inline void vlv_wait_port_ready(struct intel_encoder *encoder, + unsigned int expected_mask) +{ +} #endif #endif /* __INTEL_DPIO_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 3256b1293f7f..08a30e5aafce 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1843,7 +1843,7 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; int i; - assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); + assert_transcoder_disabled(display, crtc_state->cpu_transcoder); /* PLL is protected by panel, make sure we can write it */ if (i9xx_has_pps(dev_priv)) @@ -2024,7 +2024,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state) const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; - assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); + assert_transcoder_disabled(display, crtc_state->cpu_transcoder); /* PLL is protected by panel, make sure we can write it */ assert_pps_unlocked(display, pipe); @@ -2171,7 +2171,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; - assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); + assert_transcoder_disabled(display, crtc_state->cpu_transcoder); /* PLL is protected by panel, make sure we can write it */ assert_pps_unlocked(display, pipe); @@ -2253,36 +2253,38 @@ int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) { + struct intel_display *display = &dev_priv->display; u32 val; /* Make sure the pipe isn't still relying on us */ - assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); + assert_transcoder_disabled(display, (enum transcoder)pipe); val = DPLL_INTEGRATED_REF_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; if (pipe != PIPE_A) val |= DPLL_INTEGRATED_CRI_CLK_VLV; - intel_de_write(dev_priv, DPLL(dev_priv, pipe), val); - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); + intel_de_write(display, DPLL(display, pipe), val); + intel_de_posting_read(display, DPLL(display, pipe)); } void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) { + struct intel_display *display = &dev_priv->display; enum dpio_channel ch = vlv_pipe_to_channel(pipe); enum dpio_phy phy = vlv_pipe_to_phy(pipe); u32 val; /* Make sure the pipe isn't still relying on us */ - assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); + assert_transcoder_disabled(display, (enum transcoder)pipe); val = DPLL_SSC_REF_CLK_CHV | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; if (pipe != PIPE_A) val |= DPLL_INTEGRATED_CRI_CLK_VLV; - intel_de_write(dev_priv, DPLL(dev_priv, pipe), val); - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); + intel_de_write(display, DPLL(display, pipe), val); + intel_de_posting_read(display, DPLL(display, pipe)); vlv_dpio_get(dev_priv); @@ -2296,19 +2298,19 @@ void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; /* Don't disable pipe or pipe PLLs if needed */ - if (IS_I830(dev_priv)) + if (display->platform.i830) return; /* Make sure the pipe isn't still relying on us */ - assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); + assert_transcoder_disabled(display, crtc_state->cpu_transcoder); - intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS); - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); + intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); + intel_de_posting_read(display, DPLL(display, pipe)); } @@ -2329,10 +2331,9 @@ void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) } /* Only for pre-ILK configs */ -static void assert_pll(struct drm_i915_private *dev_priv, +static void assert_pll(struct intel_display *display, enum pipe pipe, bool state) { - struct intel_display *display = &dev_priv->display; bool cur_state; cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE; @@ -2341,12 +2342,12 @@ static void assert_pll(struct drm_i915_private *dev_priv, str_on_off(state), str_on_off(cur_state)); } -void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe) +void assert_pll_enabled(struct intel_display *display, enum pipe pipe) { - assert_pll(i915, pipe, true); + assert_pll(display, pipe, true); } -void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe) +void assert_pll_disabled(struct intel_display *display, enum pipe pipe) { - assert_pll(i915, pipe, false); + assert_pll(display, pipe, false); } diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h index a86a79408af0..21d06cbd2ce7 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.h +++ b/drivers/gpu/drm/i915/display/intel_dpll.h @@ -13,6 +13,7 @@ struct drm_i915_private; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; +struct intel_display; struct intel_dpll_hw_state; enum pipe; @@ -46,7 +47,7 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state); void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state); void chv_crtc_clock_get(struct intel_crtc_state *crtc_state); -void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe); -void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe); +void assert_pll_enabled(struct intel_display *display, enum pipe pipe); +void assert_pll_disabled(struct intel_display *display, enum pipe pipe); #endif diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index d86cc9ffd4ac..c825a507b905 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -27,6 +27,7 @@ #include "bxt_dpio_phy_regs.h" #include "i915_drv.h" #include "i915_reg.h" +#include "intel_cx0_phy.h" #include "intel_de.h" #include "intel_display_types.h" #include "intel_dkl_phy.h" @@ -65,7 +66,7 @@ struct intel_shared_dpll_funcs { * Hook for enabling the pll, called from intel_enable_shared_dpll() if * the pll is not already enabled. */ - void (*enable)(struct drm_i915_private *i915, + void (*enable)(struct intel_display *display, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state); @@ -74,7 +75,7 @@ struct intel_shared_dpll_funcs { * only when it is safe to disable the pll, i.e., there are no more * tracked users for it. */ - void (*disable)(struct drm_i915_private *i915, + void (*disable)(struct intel_display *display, struct intel_shared_dpll *pll); /* @@ -82,7 +83,7 @@ struct intel_shared_dpll_funcs { * registers. This is used for initial hw state readout and state * verification after a mode set. */ - bool (*get_hw_state)(struct drm_i915_private *i915, + bool (*get_hw_state)(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state); @@ -90,7 +91,7 @@ struct intel_shared_dpll_funcs { * Hook for calculating the pll's output frequency based on its passed * in state. */ - int (*get_freq)(struct drm_i915_private *i915, + int (*get_freq)(struct intel_display *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state); }; @@ -109,7 +110,7 @@ struct intel_dpll_mgr { void (*update_active_dpll)(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder); - void (*update_ref_clks)(struct drm_i915_private *i915); + void (*update_ref_clks)(struct intel_display *display); void (*dump_hw_state)(struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state); bool (*compare_hw_state)(const struct intel_dpll_hw_state *a, @@ -117,14 +118,14 @@ struct intel_dpll_mgr { }; static void -intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915, +intel_atomic_duplicate_dpll_state(struct intel_display *display, struct intel_shared_dpll_state *shared_dpll) { struct intel_shared_dpll *pll; int i; /* Copy shared dpll state */ - for_each_shared_dpll(i915, pll, i) + for_each_shared_dpll(display, pll, i) shared_dpll[pll->index] = pll->state; } @@ -132,13 +133,14 @@ static struct intel_shared_dpll_state * intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) { struct intel_atomic_state *state = to_intel_atomic_state(s); + struct intel_display *display = to_intel_display(state); drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); if (!state->dpll_set) { state->dpll_set = true; - intel_atomic_duplicate_dpll_state(to_i915(s->dev), + intel_atomic_duplicate_dpll_state(display, state->shared_dpll); } @@ -147,20 +149,20 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s) /** * intel_get_shared_dpll_by_id - get a DPLL given its id - * @i915: i915 device instance + * @display: intel_display device instance * @id: pll id * * Returns: * A pointer to the DPLL with @id */ struct intel_shared_dpll * -intel_get_shared_dpll_by_id(struct drm_i915_private *i915, +intel_get_shared_dpll_by_id(struct intel_display *display, enum intel_dpll_id id) { struct intel_shared_dpll *pll; int i; - for_each_shared_dpll(i915, pll, i) { + for_each_shared_dpll(display, pll, i) { if (pll->info->id == id) return pll; } @@ -170,11 +172,10 @@ intel_get_shared_dpll_by_id(struct drm_i915_private *i915, } /* For ILK+ */ -void assert_shared_dpll(struct drm_i915_private *i915, +void assert_shared_dpll(struct intel_display *display, struct intel_shared_dpll *pll, bool state) { - struct intel_display *display = &i915->display; bool cur_state; struct intel_dpll_hw_state hw_state; @@ -182,7 +183,7 @@ void assert_shared_dpll(struct drm_i915_private *i915, "asserting DPLL %s with no DPLL\n", str_on_off(state))) return; - cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state); + cur_state = intel_dpll_get_hw_state(display, pll, &hw_state); INTEL_DISPLAY_STATE_WARN(display, cur_state != state, "%s assertion failure (expected %s, current %s)\n", pll->info->name, str_on_off(state), @@ -200,12 +201,12 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) } static i915_reg_t -intel_combo_pll_enable_reg(struct drm_i915_private *i915, +intel_combo_pll_enable_reg(struct intel_display *display, struct intel_shared_dpll *pll) { - if (IS_DG1(i915)) + if (display->platform.dg1) return DG1_DPLL_ENABLE(pll->info->id); - else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && + else if ((display->platform.jasperlake || display->platform.elkhartlake) && (pll->info->id == DPLL_ID_EHL_DPLL4)) return MG_PLL_ENABLE(0); @@ -213,36 +214,36 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915, } static i915_reg_t -intel_tc_pll_enable_reg(struct drm_i915_private *i915, +intel_tc_pll_enable_reg(struct intel_display *display, struct intel_shared_dpll *pll) { const enum intel_dpll_id id = pll->info->id; enum tc_port tc_port = icl_pll_id_to_tc_port(id); - if (IS_ALDERLAKE_P(i915)) + if (display->platform.alderlake_p) return ADLP_PORTTC_PLL_ENABLE(tc_port); return MG_PLL_ENABLE(tc_port); } -static void _intel_enable_shared_dpll(struct drm_i915_private *i915, +static void _intel_enable_shared_dpll(struct intel_display *display, struct intel_shared_dpll *pll) { if (pll->info->power_domain) - pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); + pll->wakeref = intel_display_power_get(display, pll->info->power_domain); - pll->info->funcs->enable(i915, pll, &pll->state.hw_state); + pll->info->funcs->enable(display, pll, &pll->state.hw_state); pll->on = true; } -static void _intel_disable_shared_dpll(struct drm_i915_private *i915, +static void _intel_disable_shared_dpll(struct intel_display *display, struct intel_shared_dpll *pll) { - pll->info->funcs->disable(i915, pll); + pll->info->funcs->disable(display, pll); pll->on = false; if (pll->info->power_domain) - intel_display_power_put(i915, pll->info->power_domain, pll->wakeref); + intel_display_power_put(display, pll->info->power_domain, pll->wakeref); } /** @@ -253,42 +254,42 @@ static void _intel_disable_shared_dpll(struct drm_i915_private *i915, */ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; unsigned int pipe_mask = BIT(crtc->pipe); unsigned int old_mask; - if (drm_WARN_ON(&i915->drm, pll == NULL)) + if (drm_WARN_ON(display->drm, !pll)) return; - mutex_lock(&i915->display.dpll.lock); + mutex_lock(&display->dpll.lock); old_mask = pll->active_mask; - if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) || - drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask)) + if (drm_WARN_ON(display->drm, !(pll->state.pipe_mask & pipe_mask)) || + drm_WARN_ON(display->drm, pll->active_mask & pipe_mask)) goto out; pll->active_mask |= pipe_mask; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "enable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n", pll->info->name, pll->active_mask, pll->on, crtc->base.base.id, crtc->base.name); if (old_mask) { - drm_WARN_ON(&i915->drm, !pll->on); - assert_shared_dpll_enabled(i915, pll); + drm_WARN_ON(display->drm, !pll->on); + assert_shared_dpll_enabled(display, pll); goto out; } - drm_WARN_ON(&i915->drm, pll->on); + drm_WARN_ON(display->drm, pll->on); - drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name); + drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name); - _intel_enable_shared_dpll(i915, pll); + _intel_enable_shared_dpll(display, pll); out: - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); } /** @@ -299,53 +300,53 @@ out: */ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; unsigned int pipe_mask = BIT(crtc->pipe); /* PCH only available on ILK+ */ - if (DISPLAY_VER(i915) < 5) + if (DISPLAY_VER(display) < 5) return; if (pll == NULL) return; - mutex_lock(&i915->display.dpll.lock); - if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask), + mutex_lock(&display->dpll.lock); + if (drm_WARN(display->drm, !(pll->active_mask & pipe_mask), "%s not used by [CRTC:%d:%s]\n", pll->info->name, crtc->base.base.id, crtc->base.name)) goto out; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "disable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n", pll->info->name, pll->active_mask, pll->on, crtc->base.base.id, crtc->base.name); - assert_shared_dpll_enabled(i915, pll); - drm_WARN_ON(&i915->drm, !pll->on); + assert_shared_dpll_enabled(display, pll); + drm_WARN_ON(display->drm, !pll->on); pll->active_mask &= ~pipe_mask; if (pll->active_mask) goto out; - drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name); + drm_dbg_kms(display->drm, "disabling %s\n", pll->info->name); - _intel_disable_shared_dpll(i915, pll); + _intel_disable_shared_dpll(display, pll); out: - mutex_unlock(&i915->display.dpll.lock); + mutex_unlock(&display->dpll.lock); } static unsigned long -intel_dpll_mask_all(struct drm_i915_private *i915) +intel_dpll_mask_all(struct intel_display *display) { struct intel_shared_dpll *pll; unsigned long dpll_mask = 0; int i; - for_each_shared_dpll(i915, pll, i) { - drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id)); + for_each_shared_dpll(display, pll, i) { + drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id)); dpll_mask |= BIT(pll->info->id); } @@ -359,20 +360,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state, const struct intel_dpll_hw_state *dpll_hw_state, unsigned long dpll_mask) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); - unsigned long dpll_mask_all = intel_dpll_mask_all(i915); + struct intel_display *display = to_intel_display(crtc); + unsigned long dpll_mask_all = intel_dpll_mask_all(display); struct intel_shared_dpll_state *shared_dpll; struct intel_shared_dpll *unused_pll = NULL; enum intel_dpll_id id; shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); - drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all); + drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all); for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) { struct intel_shared_dpll *pll; - pll = intel_get_shared_dpll_by_id(i915, id); + pll = intel_get_shared_dpll_by_id(display, id); if (!pll) continue; @@ -386,7 +387,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state, if (memcmp(dpll_hw_state, &shared_dpll[pll->index].hw_state, sizeof(*dpll_hw_state)) == 0) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n", crtc->base.base.id, crtc->base.name, pll->info->name, @@ -398,7 +399,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state, /* Ok no matching timings, maybe there's a free one? */ if (unused_pll) { - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n", + drm_dbg_kms(display->drm, "[CRTC:%d:%s] allocated %s\n", crtc->base.base.id, crtc->base.name, unused_pll->info->name); return unused_pll; @@ -420,13 +421,13 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); - drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0); + drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0); shared_dpll_state->pipe_mask |= BIT(crtc->pipe); - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n", + drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); } @@ -459,13 +460,13 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); - drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0); + drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0); shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe); - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n", + drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); } @@ -509,7 +510,7 @@ static void intel_put_dpll(struct intel_atomic_state *state, */ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_shared_dpll_state *shared_dpll = state->shared_dpll; struct intel_shared_dpll *pll; int i; @@ -517,11 +518,11 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) if (!state->dpll_set) return; - for_each_shared_dpll(i915, pll, i) + for_each_shared_dpll(display, pll, i) swap(pll->state, shared_dpll[pll->index]); } -static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915, +static bool ibx_pch_dpll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { @@ -530,24 +531,23 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915, intel_wakeref_t wakeref; u32 val; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(i915, PCH_DPLL(id)); + val = intel_de_read(display, PCH_DPLL(id)); hw_state->dpll = val; - hw_state->fp0 = intel_de_read(i915, PCH_FP0(id)); - hw_state->fp1 = intel_de_read(i915, PCH_FP1(id)); + hw_state->fp0 = intel_de_read(display, PCH_FP0(id)); + hw_state->fp1 = intel_de_read(display, PCH_FP1(id)); - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return val & DPLL_VCO_ENABLE; } -static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915) +static void ibx_assert_pch_refclk_enabled(struct intel_display *display) { - struct intel_display *display = &i915->display; u32 val; bool enabled; @@ -558,7 +558,7 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915) "PCH refclk assertion failure, should be active but is disabled\n"); } -static void ibx_pch_dpll_enable(struct drm_i915_private *i915, +static void ibx_pch_dpll_enable(struct intel_display *display, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { @@ -566,15 +566,15 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *i915, const enum intel_dpll_id id = pll->info->id; /* PCH refclock must be enabled first */ - ibx_assert_pch_refclk_enabled(i915); + ibx_assert_pch_refclk_enabled(display); - intel_de_write(i915, PCH_FP0(id), hw_state->fp0); - intel_de_write(i915, PCH_FP1(id), hw_state->fp1); + intel_de_write(display, PCH_FP0(id), hw_state->fp0); + intel_de_write(display, PCH_FP1(id), hw_state->fp1); - intel_de_write(i915, PCH_DPLL(id), hw_state->dpll); + intel_de_write(display, PCH_DPLL(id), hw_state->dpll); /* Wait for the clocks to stabilize. */ - intel_de_posting_read(i915, PCH_DPLL(id)); + intel_de_posting_read(display, PCH_DPLL(id)); udelay(150); /* The pixel multiplier can only be updated once the @@ -582,18 +582,18 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *i915, * * So write it again. */ - intel_de_write(i915, PCH_DPLL(id), hw_state->dpll); - intel_de_posting_read(i915, PCH_DPLL(id)); + intel_de_write(display, PCH_DPLL(id), hw_state->dpll); + intel_de_posting_read(display, PCH_DPLL(id)); udelay(200); } -static void ibx_pch_dpll_disable(struct drm_i915_private *i915, +static void ibx_pch_dpll_disable(struct intel_display *display, struct intel_shared_dpll *pll) { const enum intel_dpll_id id = pll->info->id; - intel_de_write(i915, PCH_DPLL(id), 0); - intel_de_posting_read(i915, PCH_DPLL(id)); + intel_de_write(display, PCH_DPLL(id), 0); + intel_de_posting_read(display, PCH_DPLL(id)); udelay(200); } @@ -608,18 +608,19 @@ static int ibx_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { + struct intel_display *display = to_intel_display(state); + struct drm_i915_private *i915 = to_i915(display->drm); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; enum intel_dpll_id id; if (HAS_PCH_IBX(i915)) { /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ id = (enum intel_dpll_id) crtc->pipe; - pll = intel_get_shared_dpll_by_id(i915, id); + pll = intel_get_shared_dpll_by_id(display, id); - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); @@ -688,62 +689,64 @@ static const struct intel_dpll_mgr pch_pll_mgr = { .compare_hw_state = ibx_compare_hw_state, }; -static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915, +static void hsw_ddi_wrpll_enable(struct intel_display *display, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; const enum intel_dpll_id id = pll->info->id; - intel_de_write(i915, WRPLL_CTL(id), hw_state->wrpll); - intel_de_posting_read(i915, WRPLL_CTL(id)); + intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll); + intel_de_posting_read(display, WRPLL_CTL(id)); udelay(20); } -static void hsw_ddi_spll_enable(struct drm_i915_private *i915, +static void hsw_ddi_spll_enable(struct intel_display *display, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; - intel_de_write(i915, SPLL_CTL, hw_state->spll); - intel_de_posting_read(i915, SPLL_CTL); + intel_de_write(display, SPLL_CTL, hw_state->spll); + intel_de_posting_read(display, SPLL_CTL); udelay(20); } -static void hsw_ddi_wrpll_disable(struct drm_i915_private *i915, +static void hsw_ddi_wrpll_disable(struct intel_display *display, struct intel_shared_dpll *pll) { + struct drm_i915_private *i915 = to_i915(display->drm); const enum intel_dpll_id id = pll->info->id; - intel_de_rmw(i915, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0); - intel_de_posting_read(i915, WRPLL_CTL(id)); + intel_de_rmw(display, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0); + intel_de_posting_read(display, WRPLL_CTL(id)); /* * Try to set up the PCH reference clock once all DPLLs * that depend on it have been shut down. */ - if (i915->display.dpll.pch_ssc_use & BIT(id)) + if (display->dpll.pch_ssc_use & BIT(id)) intel_init_pch_refclk(i915); } -static void hsw_ddi_spll_disable(struct drm_i915_private *i915, +static void hsw_ddi_spll_disable(struct intel_display *display, struct intel_shared_dpll *pll) { + struct drm_i915_private *i915 = to_i915(display->drm); enum intel_dpll_id id = pll->info->id; - intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0); - intel_de_posting_read(i915, SPLL_CTL); + intel_de_rmw(display, SPLL_CTL, SPLL_PLL_ENABLE, 0); + intel_de_posting_read(display, SPLL_CTL); /* * Try to set up the PCH reference clock once all DPLLs * that depend on it have been shut down. */ - if (i915->display.dpll.pch_ssc_use & BIT(id)) + if (display->dpll.pch_ssc_use & BIT(id)) intel_init_pch_refclk(i915); } -static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915, +static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { @@ -752,20 +755,20 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915, intel_wakeref_t wakeref; u32 val; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(i915, WRPLL_CTL(id)); + val = intel_de_read(display, WRPLL_CTL(id)); hw_state->wrpll = val; - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return val & WRPLL_PLL_ENABLE; } -static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915, +static bool hsw_ddi_spll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { @@ -773,15 +776,15 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915, intel_wakeref_t wakeref; u32 val; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(i915, SPLL_CTL); + val = intel_de_read(display, SPLL_CTL); hw_state->spll = val; - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return val & SPLL_PLL_ENABLE; } @@ -992,7 +995,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, *r2_out = best.r2; } -static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915, +static int hsw_ddi_wrpll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { @@ -1004,8 +1007,8 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915, switch (wrpll & WRPLL_REF_MASK) { case WRPLL_REF_SPECIAL_HSW: /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */ - if (IS_HASWELL(i915) && !IS_HASWELL_ULT(i915)) { - refclk = i915->display.dpll.ref_clks.nssc; + if (display->platform.haswell && !display->platform.haswell_ult) { + refclk = display->dpll.ref_clks.nssc; break; } fallthrough; @@ -1015,7 +1018,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915, * code only cares about 5% accuracy, and spread is a max of * 0.5% downspread. */ - refclk = i915->display.dpll.ref_clks.ssc; + refclk = display->dpll.ref_clks.ssc; break; case WRPLL_REF_LCPLL: refclk = 2700000; @@ -1037,7 +1040,7 @@ static int hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw; @@ -1050,7 +1053,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state, WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | WRPLL_DIVIDER_POST(p); - crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL, + crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL, &crtc_state->dpll_hw_state); return 0; @@ -1072,7 +1075,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state, static int hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); int clock = crtc_state->port_clock; switch (clock / 2) { @@ -1081,7 +1084,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state) case 270000: return 0; default: - drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n", + drm_dbg_kms(display->drm, "Invalid clock for DP: %d\n", clock); return -EINVAL; } @@ -1090,7 +1093,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state) static struct intel_shared_dpll * hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); struct intel_shared_dpll *pll; enum intel_dpll_id pll_id; int clock = crtc_state->port_clock; @@ -1110,7 +1113,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) return NULL; } - pll = intel_get_shared_dpll_by_id(i915, pll_id); + pll = intel_get_shared_dpll_by_id(display, pll_id); if (!pll) return NULL; @@ -1118,7 +1121,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) return pll; } -static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915, +static int hsw_ddi_lcpll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { @@ -1135,7 +1138,7 @@ static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915, link_clock = 270000; break; default: - drm_WARN(&i915->drm, 1, "bad port clock sel\n"); + drm_WARN(display->drm, 1, "bad port clock sel\n"); break; } @@ -1170,7 +1173,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state, BIT(DPLL_ID_SPLL)); } -static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915, +static int hsw_ddi_spll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { @@ -1188,7 +1191,7 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915, link_clock = 270000; break; default: - drm_WARN(&i915->drm, 1, "bad spll freq\n"); + drm_WARN(display->drm, 1, "bad spll freq\n"); break; } @@ -1238,14 +1241,14 @@ static int hsw_get_dpll(struct intel_atomic_state *state, return 0; } -static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915) +static void hsw_update_dpll_ref_clks(struct intel_display *display) { - i915->display.dpll.ref_clks.ssc = 135000; + display->dpll.ref_clks.ssc = 135000; /* Non-SSC is only used on non-ULT HSW. */ - if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT) - i915->display.dpll.ref_clks.nssc = 24000; + if (intel_de_read(display, FUSE_STRAP3) & HSW_REF_CLK_SELECT) + display->dpll.ref_clks.nssc = 24000; else - i915->display.dpll.ref_clks.nssc = 135000; + display->dpll.ref_clks.nssc = 135000; } static void hsw_dump_hw_state(struct drm_printer *p, @@ -1281,18 +1284,18 @@ static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = { .get_freq = hsw_ddi_spll_get_freq, }; -static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915, +static void hsw_ddi_lcpll_enable(struct intel_display *display, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *hw_state) { } -static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915, +static void hsw_ddi_lcpll_disable(struct intel_display *display, struct intel_shared_dpll *pll) { } -static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915, +static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { @@ -1360,21 +1363,21 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = { }, }; -static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915, +static void skl_ddi_pll_write_ctrl1(struct intel_display *display, struct intel_shared_dpll *pll, const struct skl_dpll_hw_state *hw_state) { const enum intel_dpll_id id = pll->info->id; - intel_de_rmw(i915, DPLL_CTRL1, + intel_de_rmw(display, DPLL_CTRL1, DPLL_CTRL1_HDMI_MODE(id) | DPLL_CTRL1_SSC(id) | DPLL_CTRL1_LINK_RATE_MASK(id), hw_state->ctrl1 << (id * 6)); - intel_de_posting_read(i915, DPLL_CTRL1); + intel_de_posting_read(display, DPLL_CTRL1); } -static void skl_ddi_pll_enable(struct drm_i915_private *i915, +static void skl_ddi_pll_enable(struct intel_display *display, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { @@ -1382,46 +1385,46 @@ static void skl_ddi_pll_enable(struct drm_i915_private *i915, const struct skl_dpll_regs *regs = skl_dpll_regs; const enum intel_dpll_id id = pll->info->id; - skl_ddi_pll_write_ctrl1(i915, pll, hw_state); + skl_ddi_pll_write_ctrl1(display, pll, hw_state); - intel_de_write(i915, regs[id].cfgcr1, hw_state->cfgcr1); - intel_de_write(i915, regs[id].cfgcr2, hw_state->cfgcr2); - intel_de_posting_read(i915, regs[id].cfgcr1); - intel_de_posting_read(i915, regs[id].cfgcr2); + intel_de_write(display, regs[id].cfgcr1, hw_state->cfgcr1); + intel_de_write(display, regs[id].cfgcr2, hw_state->cfgcr2); + intel_de_posting_read(display, regs[id].cfgcr1); + intel_de_posting_read(display, regs[id].cfgcr2); /* the enable bit is always bit 31 */ - intel_de_rmw(i915, regs[id].ctl, 0, LCPLL_PLL_ENABLE); + intel_de_rmw(display, regs[id].ctl, 0, LCPLL_PLL_ENABLE); - if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5)) - drm_err(&i915->drm, "DPLL %d not locked\n", id); + if (intel_de_wait_for_set(display, DPLL_STATUS, DPLL_LOCK(id), 5)) + drm_err(display->drm, "DPLL %d not locked\n", id); } -static void skl_ddi_dpll0_enable(struct drm_i915_private *i915, +static void skl_ddi_dpll0_enable(struct intel_display *display, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; - skl_ddi_pll_write_ctrl1(i915, pll, hw_state); + skl_ddi_pll_write_ctrl1(display, pll, hw_state); } -static void skl_ddi_pll_disable(struct drm_i915_private *i915, +static void skl_ddi_pll_disable(struct intel_display *display, struct intel_shared_dpll *pll) { const struct skl_dpll_regs *regs = skl_dpll_regs; const enum intel_dpll_id id = pll->info->id; /* the enable bit is always bit 31 */ - intel_de_rmw(i915, regs[id].ctl, LCPLL_PLL_ENABLE, 0); - intel_de_posting_read(i915, regs[id].ctl); + intel_de_rmw(display, regs[id].ctl, LCPLL_PLL_ENABLE, 0); + intel_de_posting_read(display, regs[id].ctl); } -static void skl_ddi_dpll0_disable(struct drm_i915_private *i915, +static void skl_ddi_dpll0_disable(struct intel_display *display, struct intel_shared_dpll *pll) { } -static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915, +static bool skl_ddi_pll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { @@ -1432,34 +1435,34 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915, bool ret; u32 val; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; ret = false; - val = intel_de_read(i915, regs[id].ctl); + val = intel_de_read(display, regs[id].ctl); if (!(val & LCPLL_PLL_ENABLE)) goto out; - val = intel_de_read(i915, DPLL_CTRL1); + val = intel_de_read(display, DPLL_CTRL1); hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; /* avoid reading back stale values if HDMI mode is not enabled */ if (val & DPLL_CTRL1_HDMI_MODE(id)) { - hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1); - hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2); + hw_state->cfgcr1 = intel_de_read(display, regs[id].cfgcr1); + hw_state->cfgcr2 = intel_de_read(display, regs[id].cfgcr2); } ret = true; out: - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } -static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915, +static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { @@ -1470,7 +1473,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915, u32 val; bool ret; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; @@ -1478,17 +1481,17 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915, ret = false; /* DPLL0 is always enabled since it drives CDCLK */ - val = intel_de_read(i915, regs[id].ctl); - if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE))) + val = intel_de_read(display, regs[id].ctl); + if (drm_WARN_ON(display->drm, !(val & LCPLL_PLL_ENABLE))) goto out; - val = intel_de_read(i915, DPLL_CTRL1); + val = intel_de_read(display, DPLL_CTRL1); hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; ret = true; out: - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } @@ -1732,12 +1735,12 @@ skip_remaining_dividers: return 0; } -static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, +static int skl_ddi_wrpll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; - int ref_clock = i915->display.dpll.ref_clks.nssc; + int ref_clock = display->dpll.ref_clks.nssc; u32 p0, p1, p2, dco_freq; p0 = hw_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; @@ -1764,7 +1767,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0, * handling it the same way as PDIV_7. */ - drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n"); + drm_dbg_kms(display->drm, "Invalid WRPLL PDIV divider value, fixing it.\n"); fallthrough; case DPLL_CFGCR2_PDIV_7: p0 = 7; @@ -1798,7 +1801,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, dco_freq += ((hw_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * ref_clock / 0x8000; - if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)) + if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0)) return 0; return dco_freq / (p0 * p1 * p2 * 5); @@ -1806,13 +1809,13 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl; struct skl_wrpll_params wrpll_params = {}; int ret; ret = skl_ddi_calculate_wrpll(crtc_state->port_clock, - i915->display.dpll.ref_clks.nssc, &wrpll_params); + display->dpll.ref_clks.nssc, &wrpll_params); if (ret) return ret; @@ -1836,7 +1839,7 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | wrpll_params.central_freq; - crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL, + crtc_state->port_clock = skl_ddi_wrpll_get_freq(display, NULL, &crtc_state->dpll_hw_state); return 0; @@ -1880,7 +1883,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) return 0; } -static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915, +static int skl_ddi_lcpll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { @@ -1908,7 +1911,7 @@ static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915, link_clock = 270000; break; default: - drm_WARN(&i915->drm, 1, "Unsupported link rate\n"); + drm_WARN(display->drm, 1, "Unsupported link rate\n"); break; } @@ -1959,7 +1962,7 @@ static int skl_get_dpll(struct intel_atomic_state *state, return 0; } -static int skl_ddi_pll_get_freq(struct drm_i915_private *i915, +static int skl_ddi_pll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { @@ -1970,15 +1973,15 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915, * the internal shift for each field */ if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) - return skl_ddi_wrpll_get_freq(i915, pll, dpll_hw_state); + return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state); else - return skl_ddi_lcpll_get_freq(i915, pll, dpll_hw_state); + return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state); } -static void skl_update_dpll_ref_clks(struct drm_i915_private *i915) +static void skl_update_dpll_ref_clks(struct intel_display *display) { /* No SSC ref */ - i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; + display->dpll.ref_clks.nssc = display->cdclk.hw.ref; } static void skl_dump_hw_state(struct drm_printer *p, @@ -2034,134 +2037,132 @@ static const struct intel_dpll_mgr skl_pll_mgr = { .compare_hw_state = skl_compare_hw_state, }; -static void bxt_ddi_pll_enable(struct drm_i915_private *i915, +static void bxt_ddi_pll_enable(struct intel_display *display, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { - struct intel_display *display = &i915->display; const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ - enum dpio_phy phy; - enum dpio_channel ch; + enum dpio_phy phy = DPIO_PHY0; + enum dpio_channel ch = DPIO_CH0; u32 temp; bxt_port_to_phy_channel(display, port, &phy, &ch); /* Non-SSC reference */ - intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL); + intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL); - if (IS_GEMINILAKE(i915)) { - intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), + if (display->platform.geminilake) { + intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_POWER_ENABLE); - if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & + if (wait_for_us((intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_POWER_STATE), 200)) - drm_err(&i915->drm, + drm_err(display->drm, "Power state not set for PLL:%d\n", port); } /* Disable 10 bit clock */ - intel_de_rmw(i915, BXT_PORT_PLL_EBB_4(phy, ch), + intel_de_rmw(display, BXT_PORT_PLL_EBB_4(phy, ch), PORT_PLL_10BIT_CLK_ENABLE, 0); /* Write P1 & P2 */ - intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch), + intel_de_rmw(display, BXT_PORT_PLL_EBB_0(phy, ch), PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, hw_state->ebb0); /* Write M2 integer */ - intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 0), + intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 0), PORT_PLL_M2_INT_MASK, hw_state->pll0); /* Write N */ - intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 1), + intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 1), PORT_PLL_N_MASK, hw_state->pll1); /* Write M2 fraction */ - intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 2), + intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 2), PORT_PLL_M2_FRAC_MASK, hw_state->pll2); /* Write M2 fraction enable */ - intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 3), + intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 3), PORT_PLL_M2_FRAC_ENABLE, hw_state->pll3); /* Write coeff */ - temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); + temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6)); temp &= ~PORT_PLL_PROP_COEFF_MASK; temp &= ~PORT_PLL_INT_COEFF_MASK; temp &= ~PORT_PLL_GAIN_CTL_MASK; temp |= hw_state->pll6; - intel_de_write(i915, BXT_PORT_PLL(phy, ch, 6), temp); + intel_de_write(display, BXT_PORT_PLL(phy, ch, 6), temp); /* Write calibration val */ - intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 8), + intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 8), PORT_PLL_TARGET_CNT_MASK, hw_state->pll8); - intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 9), + intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 9), PORT_PLL_LOCK_THRESHOLD_MASK, hw_state->pll9); - temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); + temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10)); temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; temp &= ~PORT_PLL_DCO_AMP_MASK; temp |= hw_state->pll10; - intel_de_write(i915, BXT_PORT_PLL(phy, ch, 10), temp); + intel_de_write(display, BXT_PORT_PLL(phy, ch, 10), temp); /* Recalibrate with new settings */ - temp = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); + temp = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch)); temp |= PORT_PLL_RECALIBRATE; - intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp); + intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp); temp &= ~PORT_PLL_10BIT_CLK_ENABLE; temp |= hw_state->ebb4; - intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp); + intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp); /* Enable PLL */ - intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE); - intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port)); + intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE); + intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port)); - if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), + if (wait_for_us((intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), 200)) - drm_err(&i915->drm, "PLL %d not locked\n", port); + drm_err(display->drm, "PLL %d not locked\n", port); - if (IS_GEMINILAKE(i915)) { - temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN(phy, ch, 0)); + if (display->platform.geminilake) { + temp = intel_de_read(display, BXT_PORT_TX_DW5_LN(phy, ch, 0)); temp |= DCC_DELAY_RANGE_2; - intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp); + intel_de_write(display, BXT_PORT_TX_DW5_GRP(phy, ch), temp); } /* * While we write to the group register to program all lanes at once we * can read only lane registers and we pick lanes 0/1 for that. */ - temp = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch)); + temp = intel_de_read(display, BXT_PORT_PCS_DW12_LN01(phy, ch)); temp &= ~LANE_STAGGER_MASK; temp &= ~LANESTAGGER_STRAP_OVRD; temp |= hw_state->pcsdw12; - intel_de_write(i915, BXT_PORT_PCS_DW12_GRP(phy, ch), temp); + intel_de_write(display, BXT_PORT_PCS_DW12_GRP(phy, ch), temp); } -static void bxt_ddi_pll_disable(struct drm_i915_private *i915, +static void bxt_ddi_pll_disable(struct intel_display *display, struct intel_shared_dpll *pll) { enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ - intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0); - intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port)); + intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0); + intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port)); - if (IS_GEMINILAKE(i915)) { - intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), + if (display->platform.geminilake) { + intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), PORT_PLL_POWER_ENABLE, 0); - if (wait_for_us(!(intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & + if (wait_for_us(!(intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_POWER_STATE), 200)) - drm_err(&i915->drm, + drm_err(display->drm, "Power state not reset for PLL:%d\n", port); } } -static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915, +static bool bxt_ddi_pll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { - struct intel_display *display = &i915->display; struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ intel_wakeref_t wakeref; @@ -2172,47 +2173,47 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915, bxt_port_to_phy_channel(display, port, &phy, &ch); - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; ret = false; - val = intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)); + val = intel_de_read(display, BXT_PORT_PLL_ENABLE(port)); if (!(val & PORT_PLL_ENABLE)) goto out; - hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch)); + hw_state->ebb0 = intel_de_read(display, BXT_PORT_PLL_EBB_0(phy, ch)); hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; - hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch)); + hw_state->ebb4 = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch)); hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; - hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0)); + hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0)); hw_state->pll0 &= PORT_PLL_M2_INT_MASK; - hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1)); + hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1)); hw_state->pll1 &= PORT_PLL_N_MASK; - hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2)); + hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2)); hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; - hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3)); + hw_state->pll3 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 3)); hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; - hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6)); + hw_state->pll6 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6)); hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | PORT_PLL_INT_COEFF_MASK | PORT_PLL_GAIN_CTL_MASK; - hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8)); + hw_state->pll8 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 8)); hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; - hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9)); + hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9)); hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; - hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10)); + hw_state->pll10 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10)); hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | PORT_PLL_DCO_AMP_MASK; @@ -2221,20 +2222,20 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915, * can read only lane registers. We configure all lanes the same way, so * here just read out lanes 0/1 and output a note if lanes 2/3 differ. */ - hw_state->pcsdw12 = intel_de_read(i915, + hw_state->pcsdw12 = intel_de_read(display, BXT_PORT_PCS_DW12_LN01(phy, ch)); - if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) - drm_dbg(&i915->drm, + if (intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) + drm_dbg(display->drm, "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", hw_state->pcsdw12, - intel_de_read(i915, + intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch))); hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; ret = true; out: - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } @@ -2255,7 +2256,7 @@ static int bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state, struct dpll *clk_div) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); /* Calculate HDMI div */ /* @@ -2265,7 +2266,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state, if (!bxt_find_best_dpll(crtc_state, clk_div)) return -EINVAL; - drm_WARN_ON(&i915->drm, clk_div->m1 != 2); + drm_WARN_ON(display->drm, clk_div->m1 != 2); return 0; } @@ -2273,7 +2274,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state, static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state, struct dpll *clk_div) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); int i; *clk_div = bxt_dp_clk_val[0]; @@ -2284,16 +2285,16 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state, } } - chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div); + chv_calc_dpll_params(display->dpll.ref_clks.nssc, clk_div); - drm_WARN_ON(&i915->drm, clk_div->vco == 0 || + drm_WARN_ON(display->drm, clk_div->vco == 0 || clk_div->dot != crtc_state->port_clock); } static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, const struct dpll *clk_div) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt; int clock = crtc_state->port_clock; int vco = clk_div->vco; @@ -2317,7 +2318,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, gain_ctl = 1; targ_cnt = 9; } else { - drm_err(&i915->drm, "Invalid VCO\n"); + drm_err(display->drm, "Invalid VCO\n"); return -EINVAL; } @@ -2358,7 +2359,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, return 0; } -static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915, +static int bxt_ddi_pll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { @@ -2374,7 +2375,7 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915, clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, hw_state->ebb0); clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, hw_state->ebb0); - return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock); + return chv_calc_dpll_params(display->dpll.ref_clks.nssc, &clock); } static int @@ -2390,7 +2391,7 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) static int bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); struct dpll clk_div = {}; int ret; @@ -2400,7 +2401,7 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state) if (ret) return ret; - crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL, + crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL, &crtc_state->dpll_hw_state); return 0; @@ -2425,17 +2426,17 @@ static int bxt_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; enum intel_dpll_id id; /* 1:1 mapping between ports and PLLs */ id = (enum intel_dpll_id) encoder->port; - pll = intel_get_shared_dpll_by_id(i915, id); + pll = intel_get_shared_dpll_by_id(display, id); - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n", + drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n", crtc->base.base.id, crtc->base.name, pll->info->name); intel_reference_shared_dpll(state, crtc, @@ -2446,10 +2447,10 @@ static int bxt_get_dpll(struct intel_atomic_state *state, return 0; } -static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915) +static void bxt_update_dpll_ref_clks(struct intel_display *display) { - i915->display.dpll.ref_clks.ssc = 100000; - i915->display.dpll.ref_clks.nssc = 100000; + display->dpll.ref_clks.ssc = 100000; + display->dpll.ref_clks.nssc = 100000; /* DSI non-SSC ref 19.2MHz */ } @@ -2601,12 +2602,14 @@ static void icl_wrpll_params_populate(struct skl_wrpll_params *params, * Program half of the nominal DCO divider fraction value. */ static bool -ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) +ehl_combo_pll_div_frac_wa_needed(struct intel_display *display) { - return ((IS_ELKHARTLAKE(i915) && - IS_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) || - IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) && - i915->display.dpll.ref_clks.nssc == 38400; + return ((display->platform.elkhartlake && + IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) || + display->platform.tigerlake || + display->platform.alderlake_s || + display->platform.alderlake_p) && + display->dpll.ref_clks.nssc == 38400; } struct icl_combo_pll_params { @@ -2698,9 +2701,9 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = { static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state, struct skl_wrpll_params *pll_params) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); const struct icl_combo_pll_params *params = - i915->display.dpll.ref_clks.nssc == 24000 ? + display->dpll.ref_clks.nssc == 24000 ? icl_dp_combo_pll_24MHz_values : icl_dp_combo_pll_19_2MHz_values; int clock = crtc_state->port_clock; @@ -2720,12 +2723,12 @@ static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state, static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, struct skl_wrpll_params *pll_params) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); - if (DISPLAY_VER(i915) >= 12) { - switch (i915->display.dpll.ref_clks.nssc) { + if (DISPLAY_VER(display) >= 12) { + switch (display->dpll.ref_clks.nssc) { default: - MISSING_CASE(i915->display.dpll.ref_clks.nssc); + MISSING_CASE(display->dpll.ref_clks.nssc); fallthrough; case 19200: case 38400: @@ -2736,9 +2739,9 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, break; } } else { - switch (i915->display.dpll.ref_clks.nssc) { + switch (display->dpll.ref_clks.nssc) { default: - MISSING_CASE(i915->display.dpll.ref_clks.nssc); + MISSING_CASE(display->dpll.ref_clks.nssc); fallthrough; case 19200: case 38400: @@ -2753,7 +2756,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, return 0; } -static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915, +static int icl_ddi_tbt_pll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { @@ -2761,14 +2764,14 @@ static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915, * The PLL outputs multiple frequencies at the same time, selection is * made at DDI clock mux level. */ - drm_WARN_ON(&i915->drm, 1); + drm_WARN_ON(display->drm, 1); return 0; } -static int icl_wrpll_ref_clock(struct drm_i915_private *i915) +static int icl_wrpll_ref_clock(struct intel_display *display) { - int ref_clock = i915->display.dpll.ref_clks.nssc; + int ref_clock = display->dpll.ref_clks.nssc; /* * For ICL+, the spec states: if reference frequency is 38.4, @@ -2784,8 +2787,8 @@ static int icl_calc_wrpll(struct intel_crtc_state *crtc_state, struct skl_wrpll_params *wrpll_params) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - int ref_clock = icl_wrpll_ref_clock(i915); + struct intel_display *display = to_intel_display(crtc_state); + int ref_clock = icl_wrpll_ref_clock(display); u32 afe_clock = crtc_state->port_clock * 5; u32 dco_min = 7998000; u32 dco_max = 10000000; @@ -2824,12 +2827,12 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state, return 0; } -static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915, +static int icl_ddi_combo_pll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; - int ref_clock = icl_wrpll_ref_clock(i915); + int ref_clock = icl_wrpll_ref_clock(display); u32 dco_fraction; u32 p0, p1, p2, dco_freq; @@ -2875,25 +2878,25 @@ static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915, dco_fraction = (hw_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> DPLL_CFGCR0_DCO_FRACTION_SHIFT; - if (ehl_combo_pll_div_frac_wa_needed(i915)) + if (ehl_combo_pll_div_frac_wa_needed(display)) dco_fraction *= 2; dco_freq += (dco_fraction * ref_clock) / 0x8000; - if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0)) + if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0)) return 0; return dco_freq / (p0 * p1 * p2 * 5); } -static void icl_calc_dpll_state(struct drm_i915_private *i915, +static void icl_calc_dpll_state(struct intel_display *display, const struct skl_wrpll_params *pll_params, struct intel_dpll_hw_state *dpll_hw_state) { struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; u32 dco_fraction = pll_params->dco_fraction; - if (ehl_combo_pll_div_frac_wa_needed(i915)) + if (ehl_combo_pll_div_frac_wa_needed(display)) dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2); hw_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) | @@ -2904,13 +2907,13 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915, DPLL_CFGCR1_KDIV(pll_params->kdiv) | DPLL_CFGCR1_PDIV(pll_params->pdiv); - if (DISPLAY_VER(i915) >= 12) + if (DISPLAY_VER(display) >= 12) hw_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL; else hw_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400; - if (i915->display.vbt.override_afc_startup) - hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val); + if (display->vbt.override_afc_startup) + hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(display->vbt.override_afc_startup_val); } static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, @@ -2996,9 +2999,9 @@ static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, struct intel_dpll_hw_state *dpll_hw_state) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; - int refclk_khz = i915->display.dpll.ref_clks.nssc; + int refclk_khz = display->dpll.ref_clks.nssc; int clock = crtc_state->port_clock; u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac; u32 iref_ndiv, iref_trim, iref_pulse_w; @@ -3008,7 +3011,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, u64 tmp; bool use_ssc = false; bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI); - bool is_dkl = DISPLAY_VER(i915) >= 12; + bool is_dkl = DISPLAY_VER(display) >= 12; int ret; ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz, @@ -3106,8 +3109,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, DKL_PLL_DIV0_PROP_COEFF(prop_coeff) | DKL_PLL_DIV0_FBPREDIV(m1div) | DKL_PLL_DIV0_FBDIV_INT(m2div_int); - if (i915->display.vbt.override_afc_startup) { - u8 val = i915->display.vbt.override_afc_startup_val; + if (display->vbt.override_afc_startup) { + u8 val = display->vbt.override_afc_startup_val; hw_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val); } @@ -3197,7 +3200,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, return 0; } -static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915, +static int icl_ddi_mg_pll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { @@ -3205,9 +3208,9 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915, u32 m1, m2_int, m2_frac, div1, div2, ref_clock; u64 tmp; - ref_clock = i915->display.dpll.ref_clks.nssc; + ref_clock = display->dpll.ref_clks.nssc; - if (DISPLAY_VER(i915) >= 12) { + if (DISPLAY_VER(display) >= 12) { m1 = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT; m2_int = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; @@ -3312,7 +3315,7 @@ static void icl_update_active_dpll(struct intel_atomic_state *state, static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct icl_port_dpll *port_dpll = @@ -3329,12 +3332,12 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state, if (ret) return ret; - icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); + icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state); /* this is mainly for the fastset check */ icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); - crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL, + crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL, &port_dpll->hw_state); return 0; @@ -3345,7 +3348,6 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct icl_port_dpll *port_dpll = @@ -3353,13 +3355,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, enum port port = encoder->port; unsigned long dpll_mask; - if (IS_ALDERLAKE_S(i915)) { + if (display->platform.alderlake_s) { dpll_mask = BIT(DPLL_ID_DG1_DPLL3) | BIT(DPLL_ID_DG1_DPLL2) | BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); - } else if (IS_DG1(i915)) { + } else if (display->platform.dg1) { if (port == PORT_D || port == PORT_E) { dpll_mask = BIT(DPLL_ID_DG1_DPLL2) | @@ -3369,12 +3371,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, BIT(DPLL_ID_DG1_DPLL0) | BIT(DPLL_ID_DG1_DPLL1); } - } else if (IS_ROCKETLAKE(i915)) { + } else if (display->platform.rocketlake) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0); - } else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && + } else if ((display->platform.jasperlake || + display->platform.elkhartlake) && port != PORT_A) { dpll_mask = BIT(DPLL_ID_EHL_DPLL4) | @@ -3404,7 +3407,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state, static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_crtc_state *old_crtc_state = @@ -3419,7 +3422,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, if (ret) return ret; - icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state); + icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state); port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state); @@ -3433,7 +3436,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state, else icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY); - crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL, + crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL, &port_dpll->hw_state); return 0; @@ -3537,7 +3540,7 @@ static void icl_put_dplls(struct intel_atomic_state *state, } } -static bool mg_pll_get_hw_state(struct drm_i915_private *i915, +static bool mg_pll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { @@ -3548,46 +3551,46 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915, bool ret = false; u32 val; - i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); + i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(i915, enable_reg); + val = intel_de_read(display, enable_reg); if (!(val & PLL_ENABLE)) goto out; - hw_state->mg_refclkin_ctl = intel_de_read(i915, + hw_state->mg_refclkin_ctl = intel_de_read(display, MG_REFCLKIN_CTL(tc_port)); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_coreclkctl1 = - intel_de_read(i915, MG_CLKTOP2_CORECLKCTL1(tc_port)); + intel_de_read(display, MG_CLKTOP2_CORECLKCTL1(tc_port)); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; hw_state->mg_clktop2_hsclkctl = - intel_de_read(i915, MG_CLKTOP2_HSCLKCTL(tc_port)); + intel_de_read(display, MG_CLKTOP2_HSCLKCTL(tc_port)); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; - hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port)); - hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port)); - hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port)); - hw_state->mg_pll_frac_lock = intel_de_read(i915, + hw_state->mg_pll_div0 = intel_de_read(display, MG_PLL_DIV0(tc_port)); + hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port)); + hw_state->mg_pll_lf = intel_de_read(display, MG_PLL_LF(tc_port)); + hw_state->mg_pll_frac_lock = intel_de_read(display, MG_PLL_FRAC_LOCK(tc_port)); - hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port)); + hw_state->mg_pll_ssc = intel_de_read(display, MG_PLL_SSC(tc_port)); - hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port)); + hw_state->mg_pll_bias = intel_de_read(display, MG_PLL_BIAS(tc_port)); hw_state->mg_pll_tdc_coldst_bias = - intel_de_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port)); - if (i915->display.dpll.ref_clks.nssc == 38400) { + if (display->dpll.ref_clks.nssc == 38400) { hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART; hw_state->mg_pll_bias_mask = 0; } else { @@ -3600,11 +3603,11 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915, ret = true; out: - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } -static bool dkl_pll_get_hw_state(struct drm_i915_private *i915, +static bool dkl_pll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { @@ -3615,12 +3618,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915, bool ret = false; u32 val; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(i915, intel_tc_pll_enable_reg(i915, pll)); + val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll)); if (!(val & PLL_ENABLE)) goto out; @@ -3628,12 +3631,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915, * All registers read here have the same HIP_INDEX_REG even though * they are on different building blocks */ - hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915, + hw_state->mg_refclkin_ctl = intel_dkl_phy_read(display, DKL_REFCLKIN_CTL(tc_port)); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_hsclkctl = - intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port)); + intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port)); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | @@ -3641,42 +3644,42 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915, MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; hw_state->mg_clktop2_coreclkctl1 = - intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port)); + intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port)); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; - hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port)); + hw_state->mg_pll_div0 = intel_dkl_phy_read(display, DKL_PLL_DIV0(tc_port)); val = DKL_PLL_DIV0_MASK; - if (i915->display.vbt.override_afc_startup) + if (display->vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; hw_state->mg_pll_div0 &= val; - hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); + hw_state->mg_pll_div1 = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port)); hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); - hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); + hw_state->mg_pll_ssc = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port)); hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); - hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); + hw_state->mg_pll_bias = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port)); hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); hw_state->mg_pll_tdc_coldst_bias = - intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port)); hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); ret = true; out: - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } -static bool icl_pll_get_hw_state(struct drm_i915_private *i915, +static bool icl_pll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state, i915_reg_t enable_reg) @@ -3687,94 +3690,94 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *i915, bool ret = false; u32 val; - wakeref = intel_display_power_get_if_enabled(i915, + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); if (!wakeref) return false; - val = intel_de_read(i915, enable_reg); + val = intel_de_read(display, enable_reg); if (!(val & PLL_ENABLE)) goto out; - if (IS_ALDERLAKE_S(i915)) { - hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id)); - } else if (IS_DG1(i915)) { - hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id)); - } else if (IS_ROCKETLAKE(i915)) { - hw_state->cfgcr0 = intel_de_read(i915, + if (display->platform.alderlake_s) { + hw_state->cfgcr0 = intel_de_read(display, ADLS_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(display, ADLS_DPLL_CFGCR1(id)); + } else if (display->platform.dg1) { + hw_state->cfgcr0 = intel_de_read(display, DG1_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(display, DG1_DPLL_CFGCR1(id)); + } else if (display->platform.rocketlake) { + hw_state->cfgcr0 = intel_de_read(display, RKL_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(i915, + hw_state->cfgcr1 = intel_de_read(display, RKL_DPLL_CFGCR1(id)); - } else if (DISPLAY_VER(i915) >= 12) { - hw_state->cfgcr0 = intel_de_read(i915, + } else if (DISPLAY_VER(display) >= 12) { + hw_state->cfgcr0 = intel_de_read(display, TGL_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(i915, + hw_state->cfgcr1 = intel_de_read(display, TGL_DPLL_CFGCR1(id)); - if (i915->display.vbt.override_afc_startup) { - hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id)); + if (display->vbt.override_afc_startup) { + hw_state->div0 = intel_de_read(display, TGL_DPLL0_DIV0(id)); hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK; } } else { - if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && + if ((display->platform.jasperlake || display->platform.elkhartlake) && id == DPLL_ID_EHL_DPLL4) { - hw_state->cfgcr0 = intel_de_read(i915, + hw_state->cfgcr0 = intel_de_read(display, ICL_DPLL_CFGCR0(4)); - hw_state->cfgcr1 = intel_de_read(i915, + hw_state->cfgcr1 = intel_de_read(display, ICL_DPLL_CFGCR1(4)); } else { - hw_state->cfgcr0 = intel_de_read(i915, + hw_state->cfgcr0 = intel_de_read(display, ICL_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = intel_de_read(i915, + hw_state->cfgcr1 = intel_de_read(display, ICL_DPLL_CFGCR1(id)); } } ret = true; out: - intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return ret; } -static bool combo_pll_get_hw_state(struct drm_i915_private *i915, +static bool combo_pll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { - i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); + i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); - return icl_pll_get_hw_state(i915, pll, dpll_hw_state, enable_reg); + return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg); } -static bool tbt_pll_get_hw_state(struct drm_i915_private *i915, +static bool tbt_pll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { - return icl_pll_get_hw_state(i915, pll, dpll_hw_state, TBT_PLL_ENABLE); + return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE); } -static void icl_dpll_write(struct drm_i915_private *i915, +static void icl_dpll_write(struct intel_display *display, struct intel_shared_dpll *pll, const struct icl_dpll_hw_state *hw_state) { const enum intel_dpll_id id = pll->info->id; i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG; - if (IS_ALDERLAKE_S(i915)) { + if (display->platform.alderlake_s) { cfgcr0_reg = ADLS_DPLL_CFGCR0(id); cfgcr1_reg = ADLS_DPLL_CFGCR1(id); - } else if (IS_DG1(i915)) { + } else if (display->platform.dg1) { cfgcr0_reg = DG1_DPLL_CFGCR0(id); cfgcr1_reg = DG1_DPLL_CFGCR1(id); - } else if (IS_ROCKETLAKE(i915)) { + } else if (display->platform.rocketlake) { cfgcr0_reg = RKL_DPLL_CFGCR0(id); cfgcr1_reg = RKL_DPLL_CFGCR1(id); - } else if (DISPLAY_VER(i915) >= 12) { + } else if (DISPLAY_VER(display) >= 12) { cfgcr0_reg = TGL_DPLL_CFGCR0(id); cfgcr1_reg = TGL_DPLL_CFGCR1(id); div0_reg = TGL_DPLL0_DIV0(id); } else { - if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) && + if ((display->platform.jasperlake || display->platform.elkhartlake) && id == DPLL_ID_EHL_DPLL4) { cfgcr0_reg = ICL_DPLL_CFGCR0(4); cfgcr1_reg = ICL_DPLL_CFGCR1(4); @@ -3784,18 +3787,18 @@ static void icl_dpll_write(struct drm_i915_private *i915, } } - intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0); - intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1); - drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup && + intel_de_write(display, cfgcr0_reg, hw_state->cfgcr0); + intel_de_write(display, cfgcr1_reg, hw_state->cfgcr1); + drm_WARN_ON_ONCE(display->drm, display->vbt.override_afc_startup && !i915_mmio_reg_valid(div0_reg)); - if (i915->display.vbt.override_afc_startup && + if (display->vbt.override_afc_startup && i915_mmio_reg_valid(div0_reg)) - intel_de_rmw(i915, div0_reg, + intel_de_rmw(display, div0_reg, TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0); - intel_de_posting_read(i915, cfgcr1_reg); + intel_de_posting_read(display, cfgcr1_reg); } -static void icl_mg_pll_write(struct drm_i915_private *i915, +static void icl_mg_pll_write(struct intel_display *display, struct intel_shared_dpll *pll, const struct icl_dpll_hw_state *hw_state) { @@ -3807,38 +3810,38 @@ static void icl_mg_pll_write(struct drm_i915_private *i915, * during the calc/readout phase if the mask depends on some other HW * state like refclk, see icl_calc_mg_pll_state(). */ - intel_de_rmw(i915, MG_REFCLKIN_CTL(tc_port), + intel_de_rmw(display, MG_REFCLKIN_CTL(tc_port), MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl); - intel_de_rmw(i915, MG_CLKTOP2_CORECLKCTL1(tc_port), + intel_de_rmw(display, MG_CLKTOP2_CORECLKCTL1(tc_port), MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK, hw_state->mg_clktop2_coreclkctl1); - intel_de_rmw(i915, MG_CLKTOP2_HSCLKCTL(tc_port), + intel_de_rmw(display, MG_CLKTOP2_HSCLKCTL(tc_port), MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK, hw_state->mg_clktop2_hsclkctl); - intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); - intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); - intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); - intel_de_write(i915, MG_PLL_FRAC_LOCK(tc_port), + intel_de_write(display, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); + intel_de_write(display, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); + intel_de_write(display, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); + intel_de_write(display, MG_PLL_FRAC_LOCK(tc_port), hw_state->mg_pll_frac_lock); - intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); + intel_de_write(display, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); - intel_de_rmw(i915, MG_PLL_BIAS(tc_port), + intel_de_rmw(display, MG_PLL_BIAS(tc_port), hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias); - intel_de_rmw(i915, MG_PLL_TDC_COLDST_BIAS(tc_port), + intel_de_rmw(display, MG_PLL_TDC_COLDST_BIAS(tc_port), hw_state->mg_pll_tdc_coldst_bias_mask, hw_state->mg_pll_tdc_coldst_bias); - intel_de_posting_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_posting_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port)); } -static void dkl_pll_write(struct drm_i915_private *i915, +static void dkl_pll_write(struct intel_display *display, struct intel_shared_dpll *pll, const struct icl_dpll_hw_state *hw_state) { @@ -3850,90 +3853,90 @@ static void dkl_pll_write(struct drm_i915_private *i915, * though on different building block */ /* All the registers are RMW */ - val = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port)); + val = intel_dkl_phy_read(display, DKL_REFCLKIN_CTL(tc_port)); val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; val |= hw_state->mg_refclkin_ctl; - intel_dkl_phy_write(i915, DKL_REFCLKIN_CTL(tc_port), val); + intel_dkl_phy_write(display, DKL_REFCLKIN_CTL(tc_port), val); - val = intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port)); + val = intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port)); val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; val |= hw_state->mg_clktop2_coreclkctl1; - intel_dkl_phy_write(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); + intel_dkl_phy_write(display, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); - val = intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port)); + val = intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port)); val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK); val |= hw_state->mg_clktop2_hsclkctl; - intel_dkl_phy_write(i915, DKL_CLKTOP2_HSCLKCTL(tc_port), val); + intel_dkl_phy_write(display, DKL_CLKTOP2_HSCLKCTL(tc_port), val); val = DKL_PLL_DIV0_MASK; - if (i915->display.vbt.override_afc_startup) + if (display->vbt.override_afc_startup) val |= DKL_PLL_DIV0_AFC_STARTUP_MASK; - intel_dkl_phy_rmw(i915, DKL_PLL_DIV0(tc_port), val, + intel_dkl_phy_rmw(display, DKL_PLL_DIV0(tc_port), val, hw_state->mg_pll_div0); - val = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port)); + val = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port)); val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); val |= hw_state->mg_pll_div1; - intel_dkl_phy_write(i915, DKL_PLL_DIV1(tc_port), val); + intel_dkl_phy_write(display, DKL_PLL_DIV1(tc_port), val); - val = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port)); + val = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port)); val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); val |= hw_state->mg_pll_ssc; - intel_dkl_phy_write(i915, DKL_PLL_SSC(tc_port), val); + intel_dkl_phy_write(display, DKL_PLL_SSC(tc_port), val); - val = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port)); + val = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port)); val &= ~(DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); val |= hw_state->mg_pll_bias; - intel_dkl_phy_write(i915, DKL_PLL_BIAS(tc_port), val); + intel_dkl_phy_write(display, DKL_PLL_BIAS(tc_port), val); - val = intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + val = intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port)); val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); val |= hw_state->mg_pll_tdc_coldst_bias; - intel_dkl_phy_write(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); + intel_dkl_phy_write(display, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); - intel_dkl_phy_posting_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_dkl_phy_posting_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port)); } -static void icl_pll_power_enable(struct drm_i915_private *i915, +static void icl_pll_power_enable(struct intel_display *display, struct intel_shared_dpll *pll, i915_reg_t enable_reg) { - intel_de_rmw(i915, enable_reg, 0, PLL_POWER_ENABLE); + intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE); /* * The spec says we need to "wait" but it also says it should be * immediate. */ - if (intel_de_wait_for_set(i915, enable_reg, PLL_POWER_STATE, 1)) - drm_err(&i915->drm, "PLL %d Power not enabled\n", + if (intel_de_wait_for_set(display, enable_reg, PLL_POWER_STATE, 1)) + drm_err(display->drm, "PLL %d Power not enabled\n", pll->info->id); } -static void icl_pll_enable(struct drm_i915_private *i915, +static void icl_pll_enable(struct intel_display *display, struct intel_shared_dpll *pll, i915_reg_t enable_reg) { - intel_de_rmw(i915, enable_reg, 0, PLL_ENABLE); + intel_de_rmw(display, enable_reg, 0, PLL_ENABLE); /* Timeout is actually 600us. */ - if (intel_de_wait_for_set(i915, enable_reg, PLL_LOCK, 1)) - drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id); + if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 1)) + drm_err(display->drm, "PLL %d not locked\n", pll->info->id); } -static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll) +static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_shared_dpll *pll) { u32 val; - if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) || + if (!(display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) || pll->info->id != DPLL_ID_ICL_DPLL0) return; /* @@ -3947,22 +3950,22 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte * Instead of the usual place for workarounds we apply this one here, * since TRANS_CMTG_CHICKEN is only accessible while DPLL0 is enabled. */ - val = intel_de_read(i915, TRANS_CMTG_CHICKEN); - val = intel_de_rmw(i915, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING); - if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING)) - drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val); + val = intel_de_read(display, TRANS_CMTG_CHICKEN); + val = intel_de_rmw(display, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING); + if (drm_WARN_ON(display->drm, val & ~DISABLE_DPT_CLK_GATING)) + drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val); } -static void combo_pll_enable(struct drm_i915_private *i915, +static void combo_pll_enable(struct intel_display *display, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; - i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); + i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); - icl_pll_power_enable(i915, pll, enable_reg); + icl_pll_power_enable(display, pll, enable_reg); - icl_dpll_write(i915, pll, hw_state); + icl_dpll_write(display, pll, hw_state); /* * DVFS pre sequence would be here, but in our driver the cdclk code @@ -3970,22 +3973,22 @@ static void combo_pll_enable(struct drm_i915_private *i915, * nothing here. */ - icl_pll_enable(i915, pll, enable_reg); + icl_pll_enable(display, pll, enable_reg); - adlp_cmtg_clock_gating_wa(i915, pll); + adlp_cmtg_clock_gating_wa(display, pll); /* DVFS post sequence would be here. See the comment above. */ } -static void tbt_pll_enable(struct drm_i915_private *i915, +static void tbt_pll_enable(struct intel_display *display, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; - icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE); + icl_pll_power_enable(display, pll, TBT_PLL_ENABLE); - icl_dpll_write(i915, pll, hw_state); + icl_dpll_write(display, pll, hw_state); /* * DVFS pre sequence would be here, but in our driver the cdclk code @@ -3993,24 +3996,24 @@ static void tbt_pll_enable(struct drm_i915_private *i915, * nothing here. */ - icl_pll_enable(i915, pll, TBT_PLL_ENABLE); + icl_pll_enable(display, pll, TBT_PLL_ENABLE); /* DVFS post sequence would be here. See the comment above. */ } -static void mg_pll_enable(struct drm_i915_private *i915, +static void mg_pll_enable(struct intel_display *display, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; - i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); + i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); - icl_pll_power_enable(i915, pll, enable_reg); + icl_pll_power_enable(display, pll, enable_reg); - if (DISPLAY_VER(i915) >= 12) - dkl_pll_write(i915, pll, hw_state); + if (DISPLAY_VER(display) >= 12) + dkl_pll_write(display, pll, hw_state); else - icl_mg_pll_write(i915, pll, hw_state); + icl_mg_pll_write(display, pll, hw_state); /* * DVFS pre sequence would be here, but in our driver the cdclk code @@ -4018,12 +4021,12 @@ static void mg_pll_enable(struct drm_i915_private *i915, * nothing here. */ - icl_pll_enable(i915, pll, enable_reg); + icl_pll_enable(display, pll, enable_reg); /* DVFS post sequence would be here. See the comment above. */ } -static void icl_pll_disable(struct drm_i915_private *i915, +static void icl_pll_disable(struct intel_display *display, struct intel_shared_dpll *pll, i915_reg_t enable_reg) { @@ -4035,51 +4038,51 @@ static void icl_pll_disable(struct drm_i915_private *i915, * nothing here. */ - intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0); + intel_de_rmw(display, enable_reg, PLL_ENABLE, 0); /* Timeout is actually 1us. */ - if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 1)) - drm_err(&i915->drm, "PLL %d locked\n", pll->info->id); + if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 1)) + drm_err(display->drm, "PLL %d locked\n", pll->info->id); /* DVFS post sequence would be here. See the comment above. */ - intel_de_rmw(i915, enable_reg, PLL_POWER_ENABLE, 0); + intel_de_rmw(display, enable_reg, PLL_POWER_ENABLE, 0); /* * The spec says we need to "wait" but it also says it should be * immediate. */ - if (intel_de_wait_for_clear(i915, enable_reg, PLL_POWER_STATE, 1)) - drm_err(&i915->drm, "PLL %d Power not disabled\n", + if (intel_de_wait_for_clear(display, enable_reg, PLL_POWER_STATE, 1)) + drm_err(display->drm, "PLL %d Power not disabled\n", pll->info->id); } -static void combo_pll_disable(struct drm_i915_private *i915, +static void combo_pll_disable(struct intel_display *display, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll); + i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); - icl_pll_disable(i915, pll, enable_reg); + icl_pll_disable(display, pll, enable_reg); } -static void tbt_pll_disable(struct drm_i915_private *i915, +static void tbt_pll_disable(struct intel_display *display, struct intel_shared_dpll *pll) { - icl_pll_disable(i915, pll, TBT_PLL_ENABLE); + icl_pll_disable(display, pll, TBT_PLL_ENABLE); } -static void mg_pll_disable(struct drm_i915_private *i915, +static void mg_pll_disable(struct intel_display *display, struct intel_shared_dpll *pll) { - i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll); + i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); - icl_pll_disable(i915, pll, enable_reg); + icl_pll_disable(display, pll, enable_reg); } -static void icl_update_dpll_ref_clks(struct drm_i915_private *i915) +static void icl_update_dpll_ref_clks(struct intel_display *display) { /* No SSC ref */ - i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; + display->dpll.ref_clks.nssc = display->cdclk.hw.ref; } static void icl_dump_hw_state(struct drm_printer *p, @@ -4300,40 +4303,41 @@ static const struct intel_dpll_mgr adlp_pll_mgr = { /** * intel_shared_dpll_init - Initialize shared DPLLs - * @i915: i915 device + * @display: intel_display device * - * Initialize shared DPLLs for @i915. + * Initialize shared DPLLs for @display. */ -void intel_shared_dpll_init(struct drm_i915_private *i915) +void intel_shared_dpll_init(struct intel_display *display) { + struct drm_i915_private *i915 = to_i915(display->drm); const struct intel_dpll_mgr *dpll_mgr = NULL; const struct dpll_info *dpll_info; int i; - mutex_init(&i915->display.dpll.lock); + mutex_init(&display->dpll.lock); - if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915)) + if (DISPLAY_VER(display) >= 14 || display->platform.dg2) /* No shared DPLLs on DG2; port PLLs are part of the PHY */ dpll_mgr = NULL; - else if (IS_ALDERLAKE_P(i915)) + else if (display->platform.alderlake_p) dpll_mgr = &adlp_pll_mgr; - else if (IS_ALDERLAKE_S(i915)) + else if (display->platform.alderlake_s) dpll_mgr = &adls_pll_mgr; - else if (IS_DG1(i915)) + else if (display->platform.dg1) dpll_mgr = &dg1_pll_mgr; - else if (IS_ROCKETLAKE(i915)) + else if (display->platform.rocketlake) dpll_mgr = &rkl_pll_mgr; - else if (DISPLAY_VER(i915) >= 12) + else if (DISPLAY_VER(display) >= 12) dpll_mgr = &tgl_pll_mgr; - else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) + else if (display->platform.jasperlake || display->platform.elkhartlake) dpll_mgr = &ehl_pll_mgr; - else if (DISPLAY_VER(i915) >= 11) + else if (DISPLAY_VER(display) >= 11) dpll_mgr = &icl_pll_mgr; - else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) + else if (display->platform.geminilake || display->platform.broxton) dpll_mgr = &bxt_pll_mgr; - else if (DISPLAY_VER(i915) == 9) + else if (DISPLAY_VER(display) == 9) dpll_mgr = &skl_pll_mgr; - else if (HAS_DDI(i915)) + else if (HAS_DDI(display)) dpll_mgr = &hsw_pll_mgr; else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915)) dpll_mgr = &pch_pll_mgr; @@ -4344,20 +4348,20 @@ void intel_shared_dpll_init(struct drm_i915_private *i915) dpll_info = dpll_mgr->dpll_info; for (i = 0; dpll_info[i].name; i++) { - if (drm_WARN_ON(&i915->drm, - i >= ARRAY_SIZE(i915->display.dpll.shared_dplls))) + if (drm_WARN_ON(display->drm, + i >= ARRAY_SIZE(display->dpll.shared_dplls))) break; /* must fit into unsigned long bitmask on 32bit */ - if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32)) + if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32)) break; - i915->display.dpll.shared_dplls[i].info = &dpll_info[i]; - i915->display.dpll.shared_dplls[i].index = i; + display->dpll.shared_dplls[i].info = &dpll_info[i]; + display->dpll.shared_dplls[i].index = i; } - i915->display.dpll.mgr = dpll_mgr; - i915->display.dpll.num_shared_dpll = i; + display->dpll.mgr = dpll_mgr; + display->dpll.num_shared_dpll = i; } /** @@ -4372,16 +4376,16 @@ void intel_shared_dpll_init(struct drm_i915_private *i915) * calling intel_shared_dpll_swap_state(). * * Returns: - * 0 on success, negative error code on falure. + * 0 on success, negative error code on failure. */ int intel_compute_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(state->base.dev); - const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; + struct intel_display *display = to_intel_display(state); + const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; - if (drm_WARN_ON(&i915->drm, !dpll_mgr)) + if (drm_WARN_ON(display->drm, !dpll_mgr)) return -EINVAL; return dpll_mgr->compute_dplls(state, crtc, encoder); @@ -4411,10 +4415,10 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(state->base.dev); - const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; + struct intel_display *display = to_intel_display(state); + const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; - if (drm_WARN_ON(&i915->drm, !dpll_mgr)) + if (drm_WARN_ON(display->drm, !dpll_mgr)) return -EINVAL; return dpll_mgr->get_dplls(state, crtc, encoder); @@ -4434,8 +4438,8 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state, void intel_release_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(state->base.dev); - const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; + struct intel_display *display = to_intel_display(state); + const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; /* * FIXME: this function is called for every platform having a @@ -4463,10 +4467,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); - const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr; + struct intel_display *display = to_intel_display(encoder); + const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr; - if (drm_WARN_ON(&i915->drm, !dpll_mgr)) + if (drm_WARN_ON(display->drm, !dpll_mgr)) return; dpll_mgr->update_active_dpll(state, crtc, encoder); @@ -4474,49 +4478,49 @@ void intel_update_active_dpll(struct intel_atomic_state *state, /** * intel_dpll_get_freq - calculate the DPLL's output frequency - * @i915: i915 device + * @display: intel_display device * @pll: DPLL for which to calculate the output frequency * @dpll_hw_state: DPLL state from which to calculate the output frequency * * Return the output frequency corresponding to @pll's passed in @dpll_hw_state. */ -int intel_dpll_get_freq(struct drm_i915_private *i915, +int intel_dpll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) { - if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq)) + if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq)) return 0; - return pll->info->funcs->get_freq(i915, pll, dpll_hw_state); + return pll->info->funcs->get_freq(display, pll, dpll_hw_state); } /** * intel_dpll_get_hw_state - readout the DPLL's hardware state - * @i915: i915 device + * @display: intel_display device instance * @pll: DPLL for which to calculate the output frequency * @dpll_hw_state: DPLL's hardware state * * Read out @pll's hardware state into @dpll_hw_state. */ -bool intel_dpll_get_hw_state(struct drm_i915_private *i915, +bool intel_dpll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { - return pll->info->funcs->get_hw_state(i915, pll, dpll_hw_state); + return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state); } -static void readout_dpll_hw_state(struct drm_i915_private *i915, +static void readout_dpll_hw_state(struct intel_display *display, struct intel_shared_dpll *pll) { struct intel_crtc *crtc; - pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state); + pll->on = intel_dpll_get_hw_state(display, pll, &pll->state.hw_state); if (pll->on && pll->info->power_domain) - pll->wakeref = intel_display_power_get(i915, pll->info->power_domain); + pll->wakeref = intel_display_power_get(display, pll->info->power_domain); pll->state.pipe_mask = 0; - for_each_intel_crtc(&i915->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); @@ -4525,67 +4529,69 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915, } pll->active_mask = pll->state.pipe_mask; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "%s hw state readout: pipe_mask 0x%x, on %i\n", pll->info->name, pll->state.pipe_mask, pll->on); } -void intel_dpll_update_ref_clks(struct drm_i915_private *i915) +void intel_dpll_update_ref_clks(struct intel_display *display) { - if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks) - i915->display.dpll.mgr->update_ref_clks(i915); + if (display->dpll.mgr && display->dpll.mgr->update_ref_clks) + display->dpll.mgr->update_ref_clks(display); } -void intel_dpll_readout_hw_state(struct drm_i915_private *i915) +void intel_dpll_readout_hw_state(struct intel_display *display) { struct intel_shared_dpll *pll; int i; - for_each_shared_dpll(i915, pll, i) - readout_dpll_hw_state(i915, pll); + for_each_shared_dpll(display, pll, i) + readout_dpll_hw_state(display, pll); } -static void sanitize_dpll_state(struct drm_i915_private *i915, +static void sanitize_dpll_state(struct intel_display *display, struct intel_shared_dpll *pll) { if (!pll->on) return; - adlp_cmtg_clock_gating_wa(i915, pll); + adlp_cmtg_clock_gating_wa(display, pll); if (pll->active_mask) return; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "%s enabled but not in use, disabling\n", pll->info->name); - _intel_disable_shared_dpll(i915, pll); + _intel_disable_shared_dpll(display, pll); } -void intel_dpll_sanitize_state(struct drm_i915_private *i915) +void intel_dpll_sanitize_state(struct intel_display *display) { struct intel_shared_dpll *pll; int i; - for_each_shared_dpll(i915, pll, i) - sanitize_dpll_state(i915, pll); + intel_cx0_pll_power_save_wa(display); + + for_each_shared_dpll(display, pll, i) + sanitize_dpll_state(display, pll); } /** * intel_dpll_dump_hw_state - dump hw_state - * @i915: i915 drm device + * @display: intel_display structure * @p: where to print the state to * @dpll_hw_state: hw state to be dumped * * Dumo out the relevant values in @dpll_hw_state. */ -void intel_dpll_dump_hw_state(struct drm_i915_private *i915, +void intel_dpll_dump_hw_state(struct intel_display *display, struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state) { - if (i915->display.dpll.mgr) { - i915->display.dpll.mgr->dump_hw_state(p, dpll_hw_state); + if (display->dpll.mgr) { + display->dpll.mgr->dump_hw_state(p, dpll_hw_state); } else { /* fallback for platforms that don't use the shared dpll * infrastructure @@ -4596,7 +4602,7 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *i915, /** * intel_dpll_compare_hw_state - compare the two states - * @i915: i915 drm device + * @display: intel_display structure * @a: first DPLL hw state * @b: second DPLL hw state * @@ -4604,12 +4610,12 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *i915, * * Returns: true if the states are equal, false if the differ */ -bool intel_dpll_compare_hw_state(struct drm_i915_private *i915, +bool intel_dpll_compare_hw_state(struct intel_display *display, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b) { - if (i915->display.dpll.mgr) { - return i915->display.dpll.mgr->compare_hw_state(a, b); + if (display->dpll.mgr) { + return display->dpll.mgr->compare_hw_state(a, b); } else { /* fallback for platforms that don't use the shared dpll * infrastructure @@ -4619,17 +4625,16 @@ bool intel_dpll_compare_hw_state(struct drm_i915_private *i915, } static void -verify_single_dpll_state(struct drm_i915_private *i915, +verify_single_dpll_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_crtc *crtc, const struct intel_crtc_state *new_crtc_state) { - struct intel_display *display = &i915->display; struct intel_dpll_hw_state dpll_hw_state = {}; u8 pipe_mask; bool active; - active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state); + active = intel_dpll_get_hw_state(display, pll, &dpll_hw_state); if (!pll->info->always_on) { INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask, @@ -4685,14 +4690,13 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); if (new_crtc_state->shared_dpll) - verify_single_dpll_state(i915, new_crtc_state->shared_dpll, + verify_single_dpll_state(display, new_crtc_state->shared_dpll, crtc, new_crtc_state); if (old_crtc_state->shared_dpll && @@ -4715,10 +4719,10 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state, void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_shared_dpll *pll; int i; - for_each_shared_dpll(i915, pll, i) - verify_single_dpll_state(i915, pll, NULL, NULL); + for_each_shared_dpll(display, pll, i) + verify_single_dpll_state(display, pll, NULL, NULL); } diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 6af325b8e27d..caffb084830c 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -30,12 +30,11 @@ #include "intel_display_power.h" #include "intel_wakeref.h" -#define for_each_shared_dpll(__i915, __pll, __i) \ - for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \ - ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++) +#define for_each_shared_dpll(__display, __pll, __i) \ + for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \ + ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++) enum tc_port; -struct drm_i915_private; struct drm_printer; struct intel_atomic_state; struct intel_crtc; @@ -318,7 +317,7 @@ struct dpll_info { const struct intel_shared_dpll_funcs *funcs; /** - * @id: unique indentifier for this DPLL + * @id: unique identifier for this DPLL */ enum intel_dpll_id id; @@ -390,9 +389,9 @@ struct intel_shared_dpll { /* shared dpll functions */ struct intel_shared_dpll * -intel_get_shared_dpll_by_id(struct drm_i915_private *i915, +intel_get_shared_dpll_by_id(struct intel_display *display, enum intel_dpll_id id); -void assert_shared_dpll(struct drm_i915_private *i915, +void assert_shared_dpll(struct intel_display *display, struct intel_shared_dpll *pll, bool state); #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) @@ -413,24 +412,24 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, void intel_update_active_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder); -int intel_dpll_get_freq(struct drm_i915_private *i915, +int intel_dpll_get_freq(struct intel_display *display, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state); -bool intel_dpll_get_hw_state(struct drm_i915_private *i915, +bool intel_dpll_get_hw_state(struct intel_display *display, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state); void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state); void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state); void intel_shared_dpll_swap_state(struct intel_atomic_state *state); -void intel_shared_dpll_init(struct drm_i915_private *i915); -void intel_dpll_update_ref_clks(struct drm_i915_private *i915); -void intel_dpll_readout_hw_state(struct drm_i915_private *i915); -void intel_dpll_sanitize_state(struct drm_i915_private *i915); +void intel_shared_dpll_init(struct intel_display *display); +void intel_dpll_update_ref_clks(struct intel_display *display); +void intel_dpll_readout_hw_state(struct intel_display *display); +void intel_dpll_sanitize_state(struct intel_display *display); -void intel_dpll_dump_hw_state(struct drm_i915_private *i915, +void intel_dpll_dump_hw_state(struct intel_display *display, struct drm_printer *p, const struct intel_dpll_hw_state *dpll_hw_state); -bool intel_dpll_compare_hw_state(struct drm_i915_private *i915, +bool intel_dpll_compare_hw_state(struct intel_display *display, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b); enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c index 8b1f0e92a11c..0d8ebe38226e 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt.c +++ b/drivers/gpu/drm/i915/display/intel_dpt.c @@ -125,6 +125,7 @@ struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm, unsigned int alignment) { struct drm_i915_private *i915 = vm->i915; + struct intel_display *display = &i915->display; struct i915_dpt *dpt = i915_vm_to_dpt(vm); intel_wakeref_t wakeref; struct i915_vma *vma; @@ -137,7 +138,7 @@ struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm, pin_flags |= PIN_MAPPABLE; wakeref = intel_runtime_pm_get(&i915->runtime_pm); - atomic_inc(&i915->gpu_error.pending_fb_pin); + atomic_inc(&display->restore.pending_fb_pin); for_i915_gem_ww(&ww, err, true) { err = i915_gem_object_lock(dpt->obj, &ww); @@ -167,7 +168,7 @@ struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm, dpt->obj->mm.dirty = true; - atomic_dec(&i915->gpu_error.pending_fb_pin); + atomic_dec(&display->restore.pending_fb_pin); intel_runtime_pm_put(&i915->runtime_pm, wakeref); return err ? ERR_PTR(err) : vma; @@ -183,7 +184,7 @@ void intel_dpt_unpin_from_ggtt(struct i915_address_space *vm) /** * intel_dpt_resume - restore the memory mapping for all DPT FBs during system resume - * @i915: device instance + * @display: display device instance * * Restore the memory mapping during system resume for all framebuffers which * are mapped to HW via a GGTT->DPT page table. The content of these page @@ -193,26 +194,26 @@ void intel_dpt_unpin_from_ggtt(struct i915_address_space *vm) * This function must be called after the mappings in GGTT have been restored calling * i915_ggtt_resume(). */ -void intel_dpt_resume(struct drm_i915_private *i915) +void intel_dpt_resume(struct intel_display *display) { struct drm_framebuffer *drm_fb; - if (!HAS_DISPLAY(i915)) + if (!HAS_DISPLAY(display)) return; - mutex_lock(&i915->drm.mode_config.fb_lock); - drm_for_each_fb(drm_fb, &i915->drm) { + mutex_lock(&display->drm->mode_config.fb_lock); + drm_for_each_fb(drm_fb, display->drm) { struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); if (fb->dpt_vm) i915_ggtt_resume_vm(fb->dpt_vm, true); } - mutex_unlock(&i915->drm.mode_config.fb_lock); + mutex_unlock(&display->drm->mode_config.fb_lock); } /** * intel_dpt_suspend - suspend the memory mapping for all DPT FBs during system suspend - * @i915: device instance + * @display: display device instance * * Suspend the memory mapping during system suspend for all framebuffers which * are mapped to HW via a GGTT->DPT page table. @@ -220,23 +221,23 @@ void intel_dpt_resume(struct drm_i915_private *i915) * This function must be called before the mappings in GGTT are suspended calling * i915_ggtt_suspend(). */ -void intel_dpt_suspend(struct drm_i915_private *i915) +void intel_dpt_suspend(struct intel_display *display) { struct drm_framebuffer *drm_fb; - if (!HAS_DISPLAY(i915)) + if (!HAS_DISPLAY(display)) return; - mutex_lock(&i915->drm.mode_config.fb_lock); + mutex_lock(&display->drm->mode_config.fb_lock); - drm_for_each_fb(drm_fb, &i915->drm) { + drm_for_each_fb(drm_fb, display->drm) { struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); if (fb->dpt_vm) i915_ggtt_suspend_vm(fb->dpt_vm, true); } - mutex_unlock(&i915->drm.mode_config.fb_lock); + mutex_unlock(&display->drm->mode_config.fb_lock); } struct i915_address_space * diff --git a/drivers/gpu/drm/i915/display/intel_dpt.h b/drivers/gpu/drm/i915/display/intel_dpt.h index 1f88b0ee17e7..db521401b828 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt.h +++ b/drivers/gpu/drm/i915/display/intel_dpt.h @@ -8,18 +8,17 @@ #include <linux/types.h> -struct drm_i915_private; - struct i915_address_space; struct i915_vma; +struct intel_display; struct intel_framebuffer; void intel_dpt_destroy(struct i915_address_space *vm); struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm, unsigned int alignment); void intel_dpt_unpin_from_ggtt(struct i915_address_space *vm); -void intel_dpt_suspend(struct drm_i915_private *i915); -void intel_dpt_resume(struct drm_i915_private *i915); +void intel_dpt_suspend(struct intel_display *display); +void intel_dpt_resume(struct intel_display *display); struct i915_address_space * intel_dpt_create(struct intel_framebuffer *fb); u64 intel_dpt_offset(struct i915_vma *dpt_vma); diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c index 0fec01b79b23..05cd0f6e6d71 100644 --- a/drivers/gpu/drm/i915/display/intel_drrs.c +++ b/drivers/gpu/drm/i915/display/intel_drrs.c @@ -65,31 +65,29 @@ const char *intel_drrs_type_str(enum drrs_type drrs_type) return str[drrs_type]; } -bool intel_cpu_transcoder_has_drrs(struct drm_i915_private *i915, +bool intel_cpu_transcoder_has_drrs(struct intel_display *display, enum transcoder cpu_transcoder) { - struct intel_display *display = &i915->display; - if (HAS_DOUBLE_BUFFERED_M_N(display)) return true; - return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder); + return intel_cpu_transcoder_has_m2_n2(display, cpu_transcoder); } static void intel_drrs_set_refresh_rate_pipeconf(struct intel_crtc *crtc, enum drrs_refresh_rate refresh_rate) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); enum transcoder cpu_transcoder = crtc->drrs.cpu_transcoder; u32 bit; - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + if (display->platform.valleyview || display->platform.cherryview) bit = TRANSCONF_REFRESH_RATE_ALT_VLV; else bit = TRANSCONF_REFRESH_RATE_ALT_ILK; - intel_de_rmw(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), + intel_de_rmw(display, TRANSCONF(display, cpu_transcoder), bit, refresh_rate == DRRS_REFRESH_RATE_LOW ? bit : 0); } @@ -110,12 +108,12 @@ bool intel_drrs_is_active(struct intel_crtc *crtc) static void intel_drrs_set_state(struct intel_crtc *crtc, enum drrs_refresh_rate refresh_rate) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); if (refresh_rate == crtc->drrs.refresh_rate) return; - if (intel_cpu_transcoder_has_m2_n2(dev_priv, crtc->drrs.cpu_transcoder)) + if (intel_cpu_transcoder_has_m2_n2(display, crtc->drrs.cpu_transcoder)) intel_drrs_set_refresh_rate_pipeconf(crtc, refresh_rate); else intel_drrs_set_refresh_rate_m_n(crtc, refresh_rate); @@ -132,13 +130,13 @@ static void intel_drrs_schedule_work(struct intel_crtc *crtc) static unsigned int intel_drrs_frontbuffer_bits(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); unsigned int frontbuffer_bits; frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, + for_each_intel_crtc_in_pipe_mask(display->drm, crtc, crtc_state->joiner_pipes) frontbuffer_bits |= INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); @@ -222,13 +220,13 @@ static void intel_drrs_downclock_work(struct work_struct *work) mutex_unlock(&crtc->drrs.mutex); } -static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv, +static void intel_drrs_frontbuffer_update(struct intel_display *display, unsigned int all_frontbuffer_bits, bool invalidate) { struct intel_crtc *crtc; - for_each_intel_crtc(&dev_priv->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { unsigned int frontbuffer_bits; mutex_lock(&crtc->drrs.mutex); @@ -262,7 +260,7 @@ static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv, /** * intel_drrs_invalidate - Disable Idleness DRRS - * @dev_priv: i915 device + * @display: display device * @frontbuffer_bits: frontbuffer plane tracking bits * * This function gets called everytime rendering on the given planes start. @@ -270,15 +268,15 @@ static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv, * * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. */ -void intel_drrs_invalidate(struct drm_i915_private *dev_priv, +void intel_drrs_invalidate(struct intel_display *display, unsigned int frontbuffer_bits) { - intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, true); + intel_drrs_frontbuffer_update(display, frontbuffer_bits, true); } /** * intel_drrs_flush - Restart Idleness DRRS - * @dev_priv: i915 device + * @display: display device * @frontbuffer_bits: frontbuffer plane tracking bits * * This function gets called every time rendering on the given planes has @@ -288,10 +286,10 @@ void intel_drrs_invalidate(struct drm_i915_private *dev_priv, * * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. */ -void intel_drrs_flush(struct drm_i915_private *dev_priv, +void intel_drrs_flush(struct intel_display *display, unsigned int frontbuffer_bits) { - intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); + intel_drrs_frontbuffer_update(display, frontbuffer_bits, false); } /** @@ -312,7 +310,7 @@ void intel_drrs_crtc_init(struct intel_crtc *crtc) static int intel_drrs_debugfs_status_show(struct seq_file *m, void *unused) { struct intel_crtc *crtc = m->private; - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); const struct intel_crtc_state *crtc_state; int ret; @@ -325,7 +323,7 @@ static int intel_drrs_debugfs_status_show(struct seq_file *m, void *unused) mutex_lock(&crtc->drrs.mutex); seq_printf(m, "DRRS capable: %s\n", - str_yes_no(intel_cpu_transcoder_has_drrs(i915, + str_yes_no(intel_cpu_transcoder_has_drrs(display, crtc_state->cpu_transcoder))); seq_printf(m, "DRRS enabled: %s\n", @@ -353,7 +351,7 @@ DEFINE_SHOW_ATTRIBUTE(intel_drrs_debugfs_status); static int intel_drrs_debugfs_ctl_set(void *data, u64 val) { struct intel_crtc *crtc = data; - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_crtc_state *crtc_state; struct drm_crtc_commit *commit; int ret; @@ -375,8 +373,7 @@ static int intel_drrs_debugfs_ctl_set(void *data, u64 val) goto out; } - drm_dbg(&i915->drm, - "Manually %sactivating DRRS\n", val ? "" : "de"); + drm_dbg_kms(display->drm, "Manually %sactivating DRRS\n", val ? "" : "de"); if (val) intel_drrs_activate(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_drrs.h b/drivers/gpu/drm/i915/display/intel_drrs.h index 0982f95eab72..32b45a93a68f 100644 --- a/drivers/gpu/drm/i915/display/intel_drrs.h +++ b/drivers/gpu/drm/i915/display/intel_drrs.h @@ -10,21 +10,21 @@ enum drrs_type; enum transcoder; -struct drm_i915_private; struct intel_atomic_state; +struct intel_connector; struct intel_crtc; struct intel_crtc_state; -struct intel_connector; +struct intel_display; -bool intel_cpu_transcoder_has_drrs(struct drm_i915_private *i915, +bool intel_cpu_transcoder_has_drrs(struct intel_display *display, enum transcoder cpu_transcoder); const char *intel_drrs_type_str(enum drrs_type drrs_type); bool intel_drrs_is_active(struct intel_crtc *crtc); void intel_drrs_activate(const struct intel_crtc_state *crtc_state); void intel_drrs_deactivate(const struct intel_crtc_state *crtc_state); -void intel_drrs_invalidate(struct drm_i915_private *dev_priv, +void intel_drrs_invalidate(struct intel_display *display, unsigned int frontbuffer_bits); -void intel_drrs_flush(struct drm_i915_private *dev_priv, +void intel_drrs_flush(struct intel_display *display, unsigned int frontbuffer_bits); void intel_drrs_crtc_init(struct intel_crtc *crtc); void intel_drrs_crtc_debugfs_add(struct intel_crtc *crtc); diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index e6f8fc743fb4..9fc4003d1579 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -109,38 +109,32 @@ static bool pre_commit_is_vrr_active(struct intel_atomic_state *state, return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc); } -static const struct intel_crtc_state * -pre_commit_crtc_state(struct intel_atomic_state *state, - struct intel_crtc *crtc) +static int dsb_vblank_delay(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - const struct intel_crtc_state *old_crtc_state = - intel_atomic_get_old_crtc_state(state, crtc); - const struct intel_crtc_state *new_crtc_state = - intel_atomic_get_new_crtc_state(state, crtc); + const struct intel_crtc_state *crtc_state = + intel_pre_commit_crtc_state(state, crtc); - /* - * During fastsets/etc. the transcoder is still - * running with the old timings at this point. - */ - if (intel_crtc_needs_modeset(new_crtc_state)) - return new_crtc_state; + if (pre_commit_is_vrr_active(state, crtc)) + /* + * When the push is sent during vblank it will trigger + * on the next scanline, hence we have up to one extra + * scanline until the delayed vblank occurs after + * TRANS_PUSH has been written. + */ + return intel_vrr_vblank_delay(crtc_state) + 1; else - return old_crtc_state; -} - -static int dsb_vblank_delay(const struct intel_crtc_state *crtc_state) -{ - return intel_mode_vblank_start(&crtc_state->hw.adjusted_mode) - - intel_mode_vdisplay(&crtc_state->hw.adjusted_mode); + return intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode); } static int dsb_vtotal(struct intel_atomic_state *state, struct intel_crtc *crtc) { - const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); + const struct intel_crtc_state *crtc_state = + intel_pre_commit_crtc_state(state, crtc); if (pre_commit_is_vrr_active(state, crtc)) - return crtc_state->vrr.vmax; + return intel_vrr_vmax_vtotal(crtc_state); else return intel_mode_vtotal(&crtc_state->hw.adjusted_mode); } @@ -148,7 +142,8 @@ static int dsb_vtotal(struct intel_atomic_state *state, static int dsb_dewake_scanline_start(struct intel_atomic_state *state, struct intel_crtc *crtc) { - const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); + const struct intel_crtc_state *crtc_state = + intel_pre_commit_crtc_state(state, crtc); struct drm_i915_private *i915 = to_i915(state->base.dev); unsigned int latency = skl_watermark_max_latency(i915, 0); @@ -159,7 +154,8 @@ static int dsb_dewake_scanline_start(struct intel_atomic_state *state, static int dsb_dewake_scanline_end(struct intel_atomic_state *state, struct intel_crtc *crtc) { - const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); + const struct intel_crtc_state *crtc_state = + intel_pre_commit_crtc_state(state, crtc); return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode); } @@ -167,23 +163,33 @@ static int dsb_dewake_scanline_end(struct intel_atomic_state *state, static int dsb_scanline_to_hw(struct intel_atomic_state *state, struct intel_crtc *crtc, int scanline) { - const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); + const struct intel_crtc_state *crtc_state = + intel_pre_commit_crtc_state(state, crtc); int vtotal = dsb_vtotal(state, crtc); return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal; } +/* + * Bspec suggests that we should always set DSB_SKIP_WAITS_EN. We have approach + * different from what is explained in Bspec on how flip is considered being + * complete. We are waiting for vblank in DSB and generate interrupt when it + * happens and this interrupt is considered as indication of completion -> we + * definitely do not want to skip vblank wait. We also have concern what comes + * to skipping vblank evasion. I.e. arming registers are latched before we have + * managed writing them. Due to these reasons we are not setting + * DSB_SKIP_WAITS_EN. + */ static u32 dsb_chicken(struct intel_atomic_state *state, struct intel_crtc *crtc) { if (pre_commit_is_vrr_active(state, crtc)) - return DSB_SKIP_WAITS_EN | - DSB_CTRL_WAIT_SAFE_WINDOW | + return DSB_CTRL_WAIT_SAFE_WINDOW | DSB_CTRL_NO_WAIT_VBLANK | DSB_INST_WAIT_SAFE_WINDOW | DSB_INST_NO_WAIT_VBLANK; else - return DSB_SKIP_WAITS_EN; + return 0; } static bool assert_dsb_has_room(struct intel_dsb *dsb) @@ -378,7 +384,8 @@ void intel_dsb_interrupt(struct intel_dsb *dsb) void intel_dsb_wait_usec(struct intel_dsb *dsb, int count) { - intel_dsb_emit(dsb, count, + /* +1 to make sure we never wait less time than asked for */ + intel_dsb_emit(dsb, count + 1, DSB_OPCODE_WAIT_USEC << DSB_OPCODE_SHIFT); } @@ -461,6 +468,25 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, start, end); } +void intel_dsb_poll(struct intel_dsb *dsb, + i915_reg_t reg, u32 mask, u32 val, + int wait_us, int count) +{ + struct intel_crtc *crtc = dsb->crtc; + enum pipe pipe = crtc->pipe; + + intel_dsb_reg_write(dsb, DSB_POLLMASK(pipe, dsb->id), mask); + intel_dsb_reg_write(dsb, DSB_POLLFUNC(pipe, dsb->id), + DSB_POLL_ENABLE | + DSB_POLL_WAIT(wait_us) | DSB_POLL_COUNT(count)); + + intel_dsb_noop(dsb, 5); + + intel_dsb_emit(dsb, val, + (DSB_OPCODE_POLL << DSB_OPCODE_SHIFT) | + i915_mmio_reg_offset(reg)); +} + static void intel_dsb_align_tail(struct intel_dsb *dsb) { u32 aligned_tail, tail; @@ -532,13 +558,27 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state, struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; - const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); + const struct intel_crtc_state *crtc_state = + intel_pre_commit_crtc_state(state, crtc); /* FIXME calibrate sensibly */ int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 20); - int vblank_delay = dsb_vblank_delay(crtc_state); int start, end; + /* + * PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). On + * wake-up scanline counting starts from vblank_start - 1. We don't know + * if wake-up is already ongoing when evasion starts. In worst case + * PIPEDSL could start reading valid value right after checking the + * scanline. In this scenario we wouldn't have enough time to write all + * registers. To tackle this evade scanline 0 as well. As a drawback we + * have 1 frame delay in flip when waking up. + */ + if (crtc_state->has_psr) + intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0); + if (pre_commit_is_vrr_active(state, crtc)) { + int vblank_delay = intel_vrr_vblank_delay(crtc_state); + end = intel_vrr_vmin_vblank_start(crtc_state); start = end - vblank_delay - latency; intel_dsb_wait_scanline_out(state, dsb, start, end); @@ -547,6 +587,8 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state, start = end - vblank_delay - latency; intel_dsb_wait_scanline_out(state, dsb, start, end); } else { + int vblank_delay = intel_mode_vblank_delay(&crtc_state->hw.adjusted_mode); + end = intel_mode_vblank_start(&crtc_state->hw.adjusted_mode); start = end - vblank_delay - latency; intel_dsb_wait_scanline_out(state, dsb, start, end); @@ -624,9 +666,10 @@ void intel_dsb_wait_vblank_delay(struct intel_atomic_state *state, struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; - const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); + const struct intel_crtc_state *crtc_state = + intel_pre_commit_crtc_state(state, crtc); int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode, - dsb_vblank_delay(crtc_state)) + 1; + dsb_vblank_delay(state, crtc)); intel_dsb_wait_usec(dsb, usecs); } @@ -825,7 +868,7 @@ void intel_dsb_irq_handler(struct intel_display *display, if (crtc->dsb_event) { /* - * Update vblank counter/timestmap in case it + * Update vblank counter/timestamp in case it * hasn't been done yet for this frame. */ drm_crtc_accurate_vblank_count(&crtc->base); @@ -838,7 +881,16 @@ void intel_dsb_irq_handler(struct intel_display *display, } errors = tmp & dsb_error_int_status(display); - if (errors) - drm_err(display->drm, "[CRTC:%d:%s] DSB %d error interrupt: 0x%x\n", - crtc->base.base.id, crtc->base.name, dsb_id, errors); + if (errors & DSB_ATS_FAULT_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d ATS fault\n", + crtc->base.base.id, crtc->base.name, dsb_id); + if (errors & DSB_GTT_FAULT_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d GTT fault\n", + crtc->base.base.id, crtc->base.name, dsb_id); + if (errors & DSB_RSPTIMEOUT_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d response timeout\n", + crtc->base.base.id, crtc->base.name, dsb_id); + if (errors & DSB_POLL_ERR_INT_STATUS) + drm_err(display->drm, "[CRTC:%d:%s] DSB %d poll error\n", + crtc->base.base.id, crtc->base.name, dsb_id); } diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index da6df07a3c83..e843c52bf97c 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -54,6 +54,9 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, int lower, int upper); void intel_dsb_vblank_evade(struct intel_atomic_state *state, struct intel_dsb *dsb); +void intel_dsb_poll(struct intel_dsb *dsb, + i915_reg_t reg, u32 mask, u32 val, + int wait_us, int count); void intel_dsb_chain(struct intel_atomic_state *state, struct intel_dsb *dsb, struct intel_dsb *chained_dsb, diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c index 0be46c6c9611..403151175a87 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi.c +++ b/drivers/gpu/drm/i915/display/intel_dsi.c @@ -58,16 +58,16 @@ int intel_dsi_get_modes(struct drm_connector *connector) } enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { - struct drm_i915_private *dev_priv = to_i915(connector->dev); + struct intel_display *display = to_intel_display(connector->dev); struct intel_connector *intel_connector = to_intel_connector(connector); const struct drm_display_mode *fixed_mode = intel_panel_fixed_mode(intel_connector, mode); - int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; + int max_dotclk = display->cdclk.max_dotclk_freq; enum drm_mode_status status; - drm_dbg_kms(&dev_priv->drm, "\n"); + drm_dbg_kms(display->drm, "\n"); status = intel_panel_mode_valid(intel_connector, mode); if (status != MODE_OK) @@ -76,7 +76,7 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector, if (fixed_mode->clock > max_dotclk) return MODE_CLOCK_HIGH; - return intel_mode_valid_max_plane_size(dev_priv, mode, 1); + return intel_mode_valid_max_plane_size(display, mode, 1); } struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h index e8ba4ccd99d3..89c7166a3860 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi.h +++ b/drivers/gpu/drm/i915/display/intel_dsi.h @@ -165,7 +165,7 @@ enum drm_panel_orientation intel_dsi_get_panel_orientation(struct intel_connector *connector); int intel_dsi_get_modes(struct drm_connector *connector); enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode); + const struct drm_display_mode *mode); struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, const struct mipi_dsi_host_ops *funcs, enum port port); diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c index b2b78f39cfd3..7b2ffd14ae6e 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c @@ -582,7 +582,7 @@ static const fn_mipi_elem_exec exec_elem[] = { /* * MIPI Sequence from VBT #53 parsing logic - * We have already separated each seqence during bios parsing + * We have already separated each sequence during bios parsing * Following is generic execution function for any sequence */ diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c index abf19dfd6d9d..c16fb34b737d 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.c +++ b/drivers/gpu/drm/i915/display/intel_dvo.c @@ -217,18 +217,18 @@ static void intel_enable_dvo(struct intel_atomic_state *state, static enum drm_mode_status intel_dvo_mode_valid(struct drm_connector *_connector, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { + struct intel_display *display = to_intel_display(_connector->dev); struct intel_connector *connector = to_intel_connector(_connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_dvo *intel_dvo = intel_attached_dvo(connector); const struct drm_display_mode *fixed_mode = intel_panel_fixed_mode(connector, mode); - int max_dotclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq; + int max_dotclk = display->cdclk.max_dotclk_freq; int target_clock = mode->clock; enum drm_mode_status status; - status = intel_cpu_transcoder_mode_valid(i915, mode); + status = intel_cpu_transcoder_mode_valid(display, mode); if (status != MODE_OK) return status; @@ -524,7 +524,7 @@ void intel_dvo_init(struct drm_i915_private *i915) return; } - assert_port_valid(i915, intel_dvo->dev.port); + assert_port_valid(display, intel_dvo->dev.port); encoder->type = INTEL_OUTPUT_DVO; encoder->power_domain = POWER_DOMAIN_PORT_OTHER; diff --git a/drivers/gpu/drm/i915/display/intel_dvo_dev.h b/drivers/gpu/drm/i915/display/intel_dvo_dev.h index 4bf476656b8c..f1e939aaf7fa 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo_dev.h +++ b/drivers/gpu/drm/i915/display/intel_dvo_dev.h @@ -57,7 +57,7 @@ struct intel_dvo_dev_ops { * Turn on/off output. * * Because none of our dvo drivers support an intermediate power levels, - * we don't expose this in the interfac. + * we don't expose this in the interface. */ void (*dpms)(struct intel_dvo_device *dvo, bool enable); @@ -71,7 +71,7 @@ struct intel_dvo_dev_ops { * \return MODE_OK if the mode is valid, or another MODE_* otherwise. */ enum drm_mode_status (*mode_valid)(struct intel_dvo_device *dvo, - struct drm_display_mode *mode); + const struct drm_display_mode *mode); /* * Callback for setting up a video mode after fixups have been made. diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 223c4218c019..2b0e0f220442 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -20,7 +20,7 @@ #include "intel_fb_bo.h" #include "intel_frontbuffer.h" -#define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a)) +#define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a)) /* * From the Sky Lake PRM: @@ -539,11 +539,13 @@ static bool check_modifier_display_ver_range(const struct intel_modifier_desc *m display_ver_from <= md->display_ver.until; } -static bool plane_has_modifier(struct drm_i915_private *i915, +static bool plane_has_modifier(struct intel_display *display, u8 plane_caps, const struct intel_modifier_desc *md) { - if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until)) + struct drm_i915_private *i915 = to_i915(display->drm); + + if (!IS_DISPLAY_VER(display, md->display_ver.from, md->display_ver.until)) return false; if (!plane_caps_contain_all(plane_caps, md->plane_caps)) @@ -570,14 +572,14 @@ static bool plane_has_modifier(struct drm_i915_private *i915, /** * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities - * @i915: i915 device instance + * @display: display instance * @plane_caps: capabilities for the plane the modifiers are queried for * * Returns: - * Returns the list of modifiers allowed by the @i915 platform and @plane_caps. + * Returns the list of modifiers allowed by the @display platform and @plane_caps. * The caller must free the returned buffer. */ -u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, +u64 *intel_fb_plane_get_modifiers(struct intel_display *display, u8 plane_caps) { u64 *list, *p; @@ -585,17 +587,17 @@ u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, int i; for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { - if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) + if (plane_has_modifier(display, plane_caps, &intel_modifiers[i])) count++; } list = kmalloc_array(count, sizeof(*list), GFP_KERNEL); - if (drm_WARN_ON(&i915->drm, !list)) + if (drm_WARN_ON(display->drm, !list)) return NULL; p = list; for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { - if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) + if (plane_has_modifier(display, plane_caps, &intel_modifiers[i])) *p++ = intel_modifiers[i].modifier; } *p++ = DRM_FORMAT_MOD_INVALID; @@ -751,33 +753,34 @@ static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_p int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) { const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); - struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes) return main_to_ccs_plane(fb, main_plane); - else if (DISPLAY_VER(i915) < 11 && + else if (DISPLAY_VER(display) < 11 && format_is_yuv_semiplanar(md, fb->format)) return 1; else return 0; } -unsigned int intel_tile_size(const struct drm_i915_private *i915) +unsigned int intel_tile_size(struct intel_display *display) { - return DISPLAY_VER(i915) == 2 ? 2048 : 4096; + return DISPLAY_VER(display) == 2 ? 2048 : 4096; } unsigned int intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *dev_priv = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); + struct drm_i915_private *i915 = to_i915(display->drm); unsigned int cpp = fb->format->cpp[color_plane]; switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: - return intel_tile_size(dev_priv); + return intel_tile_size(display); case I915_FORMAT_MOD_X_TILED: - if (DISPLAY_VER(dev_priv) == 2) + if (DISPLAY_VER(display) == 2) return 128; else return 512; @@ -807,7 +810,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) return 64; fallthrough; case I915_FORMAT_MOD_Y_TILED: - if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv)) + if (DISPLAY_VER(display) == 2 || HAS_128_BYTE_Y_TILING(i915)) return 128; else return 512; @@ -838,7 +841,9 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane) { - return intel_tile_size(to_i915(fb->dev)) / + struct intel_display *display = to_intel_display(fb->dev); + + return intel_tile_size(display) / intel_tile_width_bytes(fb, color_plane); } @@ -890,15 +895,17 @@ intel_fb_align_height(const struct drm_framebuffer *fb, return ALIGN(height, tile_height); } -bool intel_fb_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier) +bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier) { - return HAS_DPT(i915) && modifier != DRM_FORMAT_MOD_LINEAR; + return HAS_DPT(display) && modifier != DRM_FORMAT_MOD_LINEAR; } bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) { - return to_i915(fb->dev)->display.params.enable_dpt && - intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier); + struct intel_display *display = to_intel_display(fb->dev); + + return display->params.enable_dpt && + intel_fb_modifier_uses_dpt(display, fb->modifier); } void intel_fb_plane_get_subsampling(int *hsub, int *vsub, @@ -1007,16 +1014,16 @@ static u32 intel_adjust_aligned_offset(int *x, int *y, unsigned int pitch, u32 old_offset, u32 new_offset) { - struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); unsigned int cpp = fb->format->cpp[color_plane]; - drm_WARN_ON(&i915->drm, new_offset > old_offset); + drm_WARN_ON(display->drm, new_offset > old_offset); if (!is_surface_linear(fb, color_plane)) { unsigned int tile_size, tile_width, tile_height; unsigned int pitch_tiles; - tile_size = intel_tile_size(i915); + tile_size = intel_tile_size(display); intel_tile_dims(fb, color_plane, &tile_width, &tile_height); if (drm_rotation_90_or_270(rotation)) { @@ -1042,13 +1049,13 @@ static u32 intel_adjust_aligned_offset(int *x, int *y, * the x/y offsets. */ u32 intel_plane_adjust_aligned_offset(int *x, int *y, - const struct intel_plane_state *state, + const struct intel_plane_state *plane_state, int color_plane, u32 old_offset, u32 new_offset) { - return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane, - state->hw.rotation, - state->view.color_plane[color_plane].mapping_stride, + return intel_adjust_aligned_offset(x, y, plane_state->hw.fb, color_plane, + plane_state->hw.rotation, + plane_state->view.color_plane[color_plane].mapping_stride, old_offset, new_offset); } @@ -1066,7 +1073,7 @@ u32 intel_plane_adjust_aligned_offset(int *x, int *y, * used. This is why the user has to pass in the pitch since it * is specified in the rotated orientation. */ -static u32 intel_compute_aligned_offset(struct drm_i915_private *i915, +static u32 intel_compute_aligned_offset(struct intel_display *display, int *x, int *y, const struct drm_framebuffer *fb, int color_plane, @@ -1081,7 +1088,7 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *i915, unsigned int tile_size, tile_width, tile_height; unsigned int tile_rows, tiles, pitch_tiles; - tile_size = intel_tile_size(i915); + tile_size = intel_tile_size(display); intel_tile_dims(fb, color_plane, &tile_width, &tile_height); if (drm_rotation_90_or_270(rotation)) { @@ -1122,17 +1129,17 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *i915, } u32 intel_plane_compute_aligned_offset(int *x, int *y, - const struct intel_plane_state *state, + const struct intel_plane_state *plane_state, int color_plane) { - struct intel_plane *plane = to_intel_plane(state->uapi.plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); - const struct drm_framebuffer *fb = state->hw.fb; - unsigned int rotation = state->hw.rotation; - unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; + struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + const struct drm_framebuffer *fb = plane_state->hw.fb; + unsigned int rotation = plane_state->hw.rotation; + unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride; unsigned int alignment = plane->min_alignment(plane, fb, color_plane); - return intel_compute_aligned_offset(i915, x, y, fb, color_plane, + return intel_compute_aligned_offset(display, x, y, fb, color_plane, pitch, rotation, alignment); } @@ -1141,16 +1148,16 @@ static int intel_fb_offset_to_xy(int *x, int *y, const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); unsigned int height, alignment, unused; if (fb->modifier != DRM_FORMAT_MOD_LINEAR) - alignment = intel_tile_size(i915); + alignment = intel_tile_size(display); else alignment = 0; if (alignment != 0 && fb->offsets[color_plane] % alignment) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "Misaligned offset 0x%08x for color plane %d\n", fb->offsets[color_plane], color_plane); return -EINVAL; @@ -1162,7 +1169,7 @@ static int intel_fb_offset_to_xy(int *x, int *y, /* Catch potential overflows early */ if (check_add_overflow(mul_u32_u32(height, fb->pitches[color_plane]), fb->offsets[color_plane], &unused)) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "Bad offset 0x%08x or pitch %d for color plane %d\n", fb->offsets[color_plane], fb->pitches[color_plane], color_plane); @@ -1182,7 +1189,7 @@ static int intel_fb_offset_to_xy(int *x, int *y, static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y) { - struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); int main_plane; int hsub, vsub; @@ -1216,13 +1223,12 @@ static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane * x/y offsets must match between CCS and the main surface. */ if (main_x != ccs_x || main_y != ccs_y) { - drm_dbg_kms(&i915->drm, - "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", - main_x, main_y, - ccs_x, ccs_y, - intel_fb->normal_view.color_plane[main_plane].x, - intel_fb->normal_view.color_plane[main_plane].y, - x, y); + drm_dbg_kms(display->drm, + "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", + main_x, main_y, ccs_x, ccs_y, + intel_fb->normal_view.color_plane[main_plane].x, + intel_fb->normal_view.color_plane[main_plane].y, + x, y); return -EINVAL; } @@ -1231,8 +1237,8 @@ static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; int i; @@ -1246,7 +1252,7 @@ static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) * Would also need to deal with the fence POT alignment * and gen2 2KiB GTT tile size. */ - if (DISPLAY_VER(i915) < 4) + if (DISPLAY_VER(display) < 4) return false; /* @@ -1258,7 +1264,7 @@ static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) /* Linear needs a page aligned stride for remapping */ if (fb->modifier == DRM_FORMAT_MOD_LINEAR) { - unsigned int alignment = intel_tile_size(i915) - 1; + unsigned int alignment = intel_tile_size(display) - 1; for (i = 0; i < fb->format->num_planes; i++) { if (fb->pitches[i] & alignment) @@ -1271,12 +1277,22 @@ static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb) { - struct drm_i915_private *i915 = to_i915(fb->base.dev); + struct intel_display *display = to_intel_display(fb->base.dev); - return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) && + return (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) && intel_fb_uses_dpt(&fb->base); } +bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) +{ + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + + return DISPLAY_VER(dev_priv) < 4 || + (plane->fbc && !plane_state->no_fbc_reason && + plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); +} + static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation) { if (drm_rotation_90_or_270(rotation)) @@ -1318,12 +1334,13 @@ static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane, int plane_width, int *x, int *y) { + struct intel_display *display = to_intel_display(fb->base.dev); struct drm_gem_object *obj = intel_fb_bo(&fb->base); int ret; ret = intel_fb_offset_to_xy(x, y, &fb->base, color_plane); if (ret) { - drm_dbg_kms(fb->base.dev, + drm_dbg_kms(display->drm, "bad fb plane %d offset: 0x%x\n", color_plane, fb->base.offsets[color_plane]); return ret; @@ -1344,7 +1361,7 @@ static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int co */ if (color_plane == 0 && intel_bo_is_tiled(obj) && (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) { - drm_dbg_kms(fb->base.dev, + drm_dbg_kms(display->drm, "bad fb plane %d offset: 0x%x\n", color_plane, fb->base.offsets[color_plane]); return -EINVAL; @@ -1355,11 +1372,11 @@ static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int co static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y) { - struct drm_i915_private *i915 = to_i915(fb->base.dev); - unsigned int tile_size = intel_tile_size(i915); + struct intel_display *display = to_intel_display(fb->base.dev); + unsigned int tile_size = intel_tile_size(display); u32 offset; - offset = intel_compute_aligned_offset(i915, x, y, &fb->base, color_plane, + offset = intel_compute_aligned_offset(display, x, y, &fb->base, color_plane, fb->base.pitches[color_plane], DRM_MODE_ROTATE_0, tile_size); @@ -1410,10 +1427,10 @@ plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane, unsigned int tile_width, unsigned int src_stride_tiles, unsigned int dst_stride_tiles) { - struct drm_i915_private *i915 = to_i915(fb->base.dev); + struct intel_display *display = to_intel_display(fb->base.dev); unsigned int stride_tiles; - if ((IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) && + if ((display->platform.alderlake_p || DISPLAY_VER(display) >= 14) && src_stride_tiles < dst_stride_tiles) stride_tiles = src_stride_tiles; else @@ -1443,23 +1460,23 @@ plane_view_linear_tiles(const struct intel_framebuffer *fb, int color_plane, const struct fb_plane_view_dims *dims, int x, int y) { - struct drm_i915_private *i915 = to_i915(fb->base.dev); + struct intel_display *display = to_intel_display(fb->base.dev); unsigned int size; size = (y + dims->height) * fb->base.pitches[color_plane] + x * fb->base.format->cpp[color_plane]; - return DIV_ROUND_UP(size, intel_tile_size(i915)); + return DIV_ROUND_UP(size, intel_tile_size(display)); } -#define assign_chk_ovf(i915, var, val) ({ \ - drm_WARN_ON(&(i915)->drm, overflows_type(val, var)); \ +#define assign_chk_ovf(display, var, val) ({ \ + drm_WARN_ON((display)->drm, overflows_type(val, var)); \ (var) = (val); \ }) -#define assign_bfld_chk_ovf(i915, var, val) ({ \ +#define assign_bfld_chk_ovf(display, var, val) ({ \ (var) = (val); \ - drm_WARN_ON(&(i915)->drm, (var) != (val)); \ + drm_WARN_ON((display)->drm, (var) != (val)); \ (var); \ }) @@ -1468,38 +1485,38 @@ static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_p u32 obj_offset, u32 gtt_offset, int x, int y, struct intel_fb_view *view) { - struct drm_i915_private *i915 = to_i915(fb->base.dev); + struct intel_display *display = to_intel_display(fb->base.dev); struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane]; struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane]; unsigned int tile_width = dims->tile_width; unsigned int tile_height = dims->tile_height; - unsigned int tile_size = intel_tile_size(i915); + unsigned int tile_size = intel_tile_size(display); struct drm_rect r; u32 size = 0; - assign_bfld_chk_ovf(i915, remap_info->offset, obj_offset); + assign_bfld_chk_ovf(display, remap_info->offset, obj_offset); if (intel_fb_is_gen12_ccs_aux_plane(&fb->base, color_plane)) { remap_info->linear = 1; - assign_chk_ovf(i915, remap_info->size, + assign_chk_ovf(display, remap_info->size, plane_view_linear_tiles(fb, color_plane, dims, x, y)); } else { remap_info->linear = 0; - assign_chk_ovf(i915, remap_info->src_stride, + assign_chk_ovf(display, remap_info->src_stride, plane_view_src_stride_tiles(fb, color_plane, dims)); - assign_chk_ovf(i915, remap_info->width, + assign_chk_ovf(display, remap_info->width, plane_view_width_tiles(fb, color_plane, dims, x)); - assign_chk_ovf(i915, remap_info->height, + assign_chk_ovf(display, remap_info->height, plane_view_height_tiles(fb, color_plane, dims, y)); } if (view->gtt.type == I915_GTT_VIEW_ROTATED) { - drm_WARN_ON(&i915->drm, remap_info->linear); - check_array_bounds(i915, view->gtt.rotated.plane, color_plane); + drm_WARN_ON(display->drm, remap_info->linear); + check_array_bounds(display, view->gtt.rotated.plane, color_plane); - assign_chk_ovf(i915, remap_info->dst_stride, + assign_chk_ovf(display, remap_info->dst_stride, plane_view_dst_stride_tiles(fb, color_plane, remap_info->height)); /* rotate the x/y offsets to match the GTT view */ @@ -1520,9 +1537,9 @@ static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_p /* rotate the tile dimensions to match the GTT view */ swap(tile_width, tile_height); } else { - drm_WARN_ON(&i915->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED); + drm_WARN_ON(display->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED); - check_array_bounds(i915, view->gtt.remapped.plane, color_plane); + check_array_bounds(display, view->gtt.remapped.plane, color_plane); if (view->gtt.remapped.plane_alignment) { u32 aligned_offset = ALIGN(gtt_offset, @@ -1556,7 +1573,7 @@ static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_p dst_stride = plane_view_dst_stride_tiles(fb, color_plane, dst_stride); - assign_chk_ovf(i915, remap_info->dst_stride, dst_stride); + assign_chk_ovf(display, remap_info->dst_stride, dst_stride); color_plane_info->mapping_stride = dst_stride * tile_width * fb->base.format->cpp[color_plane]; @@ -1614,20 +1631,23 @@ calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane, return tiles; } -static void intel_fb_view_init(struct drm_i915_private *i915, struct intel_fb_view *view, +static void intel_fb_view_init(struct intel_display *display, + struct intel_fb_view *view, enum i915_gtt_view_type view_type) { memset(view, 0, sizeof(*view)); view->gtt.type = view_type; if (view_type == I915_GTT_VIEW_REMAPPED && - (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)) + (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE; } bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb) { - if (DISPLAY_VER(to_i915(fb->base.dev)) >= 13) + struct intel_display *display = to_intel_display(fb->base.dev); + + if (DISPLAY_VER(display) >= 13) return false; return fb->base.modifier == I915_FORMAT_MOD_Y_TILED || @@ -1636,11 +1656,11 @@ bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb) static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb) { - struct drm_i915_private *i915 = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); struct intel_plane *plane; unsigned int min_alignment = 0; - for_each_intel_plane(&i915->drm, plane) { + for_each_intel_plane(display->drm, plane) { unsigned int plane_min_alignment; if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier)) @@ -1648,7 +1668,7 @@ static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb) plane_min_alignment = plane->min_alignment(plane, fb, 0); - drm_WARN_ON(&i915->drm, plane_min_alignment && + drm_WARN_ON(display->drm, plane_min_alignment && !is_power_of_2(plane_min_alignment)); if (intel_plane_needs_physical(plane)) @@ -1660,25 +1680,41 @@ static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb) return min_alignment; } -int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb) +static unsigned int intel_fb_vtd_guard(const struct drm_framebuffer *fb) +{ + struct intel_display *display = to_intel_display(fb->dev); + struct intel_plane *plane; + unsigned int vtd_guard = 0; + + for_each_intel_plane(display->drm, plane) { + if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier)) + continue; + + vtd_guard = max_t(unsigned int, vtd_guard, plane->vtd_guard); + } + + return vtd_guard; +} + +int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb) { struct drm_gem_object *obj = intel_fb_bo(&fb->base); u32 gtt_offset_rotated = 0; u32 gtt_offset_remapped = 0; unsigned int max_size = 0; int i, num_planes = fb->base.format->num_planes; - unsigned int tile_size = intel_tile_size(i915); + unsigned int tile_size = intel_tile_size(display); - intel_fb_view_init(i915, &fb->normal_view, I915_GTT_VIEW_NORMAL); + intel_fb_view_init(display, &fb->normal_view, I915_GTT_VIEW_NORMAL); - drm_WARN_ON(&i915->drm, + drm_WARN_ON(display->drm, intel_fb_supports_90_270_rotation(fb) && intel_fb_needs_pot_stride_remap(fb)); if (intel_fb_supports_90_270_rotation(fb)) - intel_fb_view_init(i915, &fb->rotated_view, I915_GTT_VIEW_ROTATED); + intel_fb_view_init(display, &fb->rotated_view, I915_GTT_VIEW_ROTATED); if (intel_fb_needs_pot_stride_remap(fb)) - intel_fb_view_init(i915, &fb->remapped_view, I915_GTT_VIEW_REMAPPED); + intel_fb_view_init(display, &fb->remapped_view, I915_GTT_VIEW_REMAPPED); for (i = 0; i < num_planes; i++) { struct fb_plane_view_dims view_dims; @@ -1694,10 +1730,24 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer * * arithmetic related to alignment and offset calculation. */ if (is_gen12_ccs_cc_plane(&fb->base, i)) { - if (IS_ALIGNED(fb->base.offsets[i], 64)) - continue; - else + unsigned int end; + + if (!IS_ALIGNED(fb->base.offsets[i], 64)) { + drm_dbg_kms(display->drm, + "fb misaligned clear color plane %d offset (0x%x)\n", + i, fb->base.offsets[i]); + return -EINVAL; + } + + if (check_add_overflow(fb->base.offsets[i], 64, &end)) { + drm_dbg_kms(display->drm, + "fb bad clear color plane %d offset (0x%x)\n", + i, fb->base.offsets[i]); return -EINVAL; + } + + max_size = max(max_size, DIV_ROUND_UP(end, tile_size)); + continue; } intel_fb_plane_dims(fb, i, &width, &height); @@ -1736,21 +1786,52 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer * } if (mul_u32_u32(max_size, tile_size) > obj->size) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "fb too big for bo (need %llu bytes, have %zu bytes)\n", mul_u32_u32(max_size, tile_size), obj->size); return -EINVAL; } fb->min_alignment = intel_fb_min_alignment(&fb->base); + fb->vtd_guard = intel_fb_vtd_guard(&fb->base); return 0; } +unsigned int intel_fb_view_vtd_guard(const struct drm_framebuffer *fb, + const struct intel_fb_view *view, + unsigned int rotation) +{ + unsigned int vtd_guard; + int color_plane; + + vtd_guard = to_intel_framebuffer(fb)->vtd_guard; + if (!vtd_guard) + return 0; + + for (color_plane = 0; color_plane < fb->format->num_planes; color_plane++) { + unsigned int stride, tile; + + if (intel_fb_is_ccs_aux_plane(fb, color_plane) || + is_gen12_ccs_cc_plane(fb, color_plane)) + continue; + + stride = view->color_plane[color_plane].mapping_stride; + + if (drm_rotation_90_or_270(rotation)) + tile = intel_tile_height(fb, color_plane); + else + tile = intel_tile_width_bytes(fb, color_plane); + + vtd_guard = max(vtd_guard, DIV_ROUND_UP(stride, tile)); + } + + return vtd_guard; +} + static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) { - struct drm_i915_private *i915 = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); struct drm_framebuffer *fb = plane_state->hw.fb; struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); unsigned int rotation = plane_state->hw.rotation; @@ -1759,7 +1840,7 @@ static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) unsigned int src_w, src_h; u32 gtt_offset = 0; - intel_fb_view_init(i915, &plane_state->view, + intel_fb_view_init(display, &plane_state->view, drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED : I915_GTT_VIEW_REMAPPED); @@ -1768,7 +1849,7 @@ static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) src_w = drm_rect_width(&plane_state->uapi.src) >> 16; src_h = drm_rect_height(&plane_state->uapi.src) >> 16; - drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier)); + drm_WARN_ON(display->drm, intel_fb_is_ccs_modifier(fb->modifier)); /* Make src coordinates relative to the viewport */ drm_rect_translate(&plane_state->uapi.src, @@ -1810,6 +1891,42 @@ static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) } } +unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) +{ + unsigned int size = 0; + int i; + + for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) + size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; + + return size; +} + +unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) +{ + unsigned int size = 0; + int i; + + for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { + unsigned int plane_size; + + if (rem_info->plane[i].linear) + plane_size = rem_info->plane[i].size; + else + plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; + + if (plane_size == 0) + continue; + + if (rem_info->plane_alignment) + size = ALIGN(size, rem_info->plane_alignment); + + size += plane_size; + } + + return size; +} + void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation, struct intel_fb_view *view) { @@ -1821,8 +1938,39 @@ void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotatio *view = fb->normal_view; } +/* + * Convert the x/y offsets into a linear offset. + * Only valid with 0/180 degree rotation, which is fine since linear + * offset is only used with linear buffers on pre-hsw and tiled buffers + * with gen2/3, and 90/270 degree rotations isn't supported on any of them. + */ +u32 intel_fb_xy_to_linear(int x, int y, + const struct intel_plane_state *plane_state, + int color_plane) +{ + const struct drm_framebuffer *fb = plane_state->hw.fb; + unsigned int cpp = fb->format->cpp[color_plane]; + unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride; + + return y * pitch + x * cpp; +} + +/* + * Add the x/y offsets derived from fb->offsets[] to the user + * specified plane src x/y offsets. The resulting x/y offsets + * specify the start of scanout from the beginning of the gtt mapping. + */ +void intel_add_fb_offsets(int *x, int *y, + const struct intel_plane_state *plane_state, + int color_plane) + +{ + *x += plane_state->view.color_plane[color_plane].x; + *y += plane_state->view.color_plane[color_plane].y; +} + static -u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, +u32 intel_fb_max_stride(struct intel_display *display, u32 pixel_format, u64 modifier) { /* @@ -1831,10 +1979,10 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, * * The new CCS hash mode makes remapping impossible */ - if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) || - intel_fb_modifier_uses_dpt(dev_priv, modifier)) - return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier); - else if (DISPLAY_VER(dev_priv) >= 7) + if (DISPLAY_VER(display) < 4 || intel_fb_is_ccs_modifier(modifier) || + intel_fb_modifier_uses_dpt(display, modifier)) + return intel_plane_fb_max_stride(display->drm, pixel_format, modifier); + else if (DISPLAY_VER(display) >= 7) return 256 * 1024; else return 128 * 1024; @@ -1843,11 +1991,11 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, static unsigned int intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *dev_priv = to_i915(fb->dev); + struct intel_display *display = to_intel_display(fb->dev); unsigned int tile_width; if (is_surface_linear(fb, color_plane)) { - unsigned int max_stride = intel_plane_fb_max_stride(dev_priv, + unsigned int max_stride = intel_plane_fb_max_stride(display->drm, fb->format->format, fb->modifier); @@ -1857,7 +2005,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) */ if (fb->pitches[color_plane] > max_stride && !intel_fb_is_ccs_modifier(fb->modifier)) - return intel_tile_size(dev_priv); + return intel_tile_size(display); else return 64; } @@ -1868,7 +2016,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) * On TGL the surface stride must be 4 tile aligned, mapped by * one 64 byte cacheline on the CCS AUX surface. */ - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) tile_width *= 4; /* * Display WA #0531: skl,bxt,kbl,glk @@ -1879,7 +2027,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) * require the entire fb to accommodate that to avoid * potential runtime errors at plane configuration time. */ - else if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) && + else if ((DISPLAY_VER(display) == 9 || display->platform.geminilake) && color_plane == 0 && fb->width > 3840) tile_width *= 4; } @@ -1888,6 +2036,7 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) static int intel_plane_check_stride(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; @@ -1909,7 +2058,7 @@ static int intel_plane_check_stride(const struct intel_plane_state *plane_state) fb->modifier, rotation); if (stride > max_stride) { - drm_dbg_kms(plane->base.dev, + drm_dbg_kms(display->drm, "[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n", fb->base.id, stride, plane->base.base.id, plane->base.name, max_stride); @@ -2058,13 +2207,13 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, struct drm_gem_object *obj, struct drm_mode_fb_cmd2 *mode_cmd) { - struct drm_i915_private *dev_priv = to_i915(obj->dev); + struct intel_display *display = to_intel_display(obj->dev); struct drm_framebuffer *fb = &intel_fb->base; u32 max_stride; int ret = -EINVAL; int i; - ret = intel_fb_bo_framebuffer_init(intel_fb, obj, mode_cmd); + ret = intel_fb_bo_framebuffer_init(fb, obj, mode_cmd); if (ret) return ret; @@ -2075,19 +2224,19 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, } ret = -EINVAL; - if (!drm_any_plane_has_format(&dev_priv->drm, + if (!drm_any_plane_has_format(display->drm, mode_cmd->pixel_format, mode_cmd->modifier[0])) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "unsupported pixel format %p4cc / modifier 0x%llx\n", &mode_cmd->pixel_format, mode_cmd->modifier[0]); goto err_frontbuffer_put; } - max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format, + max_stride = intel_fb_max_stride(display, mode_cmd->pixel_format, mode_cmd->modifier[0]); if (mode_cmd->pitches[0] > max_stride) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "%s pitch (%u) must be at most %d\n", mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? "tiled" : "linear", @@ -2097,26 +2246,25 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ if (mode_cmd->offsets[0] != 0) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "plane 0 offset (0x%08x) must be 0\n", mode_cmd->offsets[0]); goto err_frontbuffer_put; } - drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); + drm_helper_mode_fill_fb_struct(display->drm, fb, mode_cmd); for (i = 0; i < fb->format->num_planes; i++) { unsigned int stride_alignment; if (mode_cmd->handles[i] != mode_cmd->handles[0]) { - drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n", - i); + drm_dbg_kms(display->drm, "bad plane %d handle\n", i); goto err_frontbuffer_put; } stride_alignment = intel_fb_stride_alignment(fb, i); if (fb->pitches[i] & (stride_alignment - 1)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "plane %d pitch (%d) must be at least %u byte aligned\n", i, fb->pitches[i], stride_alignment); goto err_frontbuffer_put; @@ -2126,10 +2274,9 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, unsigned int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i); if (fb->pitches[i] != ccs_aux_stride) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "ccs aux plane %d pitch (%d) must be %d\n", - i, - fb->pitches[i], ccs_aux_stride); + i, fb->pitches[i], ccs_aux_stride); goto err_frontbuffer_put; } } @@ -2137,7 +2284,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, fb->obj[i] = obj; } - ret = intel_fill_fb_info(dev_priv, intel_fb); + ret = intel_fill_fb_info(display, intel_fb); if (ret) goto err_frontbuffer_put; @@ -2146,7 +2293,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, vm = intel_dpt_create(intel_fb); if (IS_ERR(vm)) { - drm_dbg_kms(&dev_priv->drm, "failed to create DPT\n"); + drm_dbg_kms(display->drm, "failed to create DPT\n"); ret = PTR_ERR(vm); goto err_frontbuffer_put; } @@ -2154,9 +2301,9 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, intel_fb->dpt_vm = vm; } - ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); + ret = drm_framebuffer_init(display->drm, fb, &intel_fb_funcs); if (ret) { - drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret); + drm_err(display->drm, "framebuffer init failed %d\n", ret); goto err_free_dpt; } @@ -2180,9 +2327,8 @@ intel_user_framebuffer_create(struct drm_device *dev, struct drm_framebuffer *fb; struct drm_gem_object *obj; struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; - struct drm_i915_private *i915 = to_i915(dev); - obj = intel_fb_bo_lookup_valid_bo(i915, filp, &mode_cmd); + obj = intel_fb_bo_lookup_valid_bo(dev, filp, &mode_cmd); if (IS_ERR(obj)) return ERR_CAST(obj); diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index d78993e5eb62..bdd76b372957 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -13,13 +13,14 @@ struct drm_device; struct drm_file; struct drm_framebuffer; struct drm_gem_object; -struct drm_i915_gem_object; -struct drm_i915_private; struct drm_mode_fb_cmd2; +struct intel_display; struct intel_fb_view; struct intel_framebuffer; struct intel_plane; struct intel_plane_state; +struct intel_remapped_info; +struct intel_rotation_info; #define INTEL_PLANE_CAP_NONE 0 #define INTEL_PLANE_CAP_CCS_RC BIT(0) @@ -41,7 +42,7 @@ bool intel_fb_is_tile4_modifier(u64 modifier); bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane); int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb); -u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, +u64 *intel_fb_plane_get_modifiers(struct intel_display *display, u8 plane_caps); bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier); @@ -58,7 +59,7 @@ int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane); int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane); int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane); -unsigned int intel_tile_size(const struct drm_i915_private *i915); +unsigned int intel_tile_size(struct intel_display *display); unsigned int intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane); unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane); unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane); @@ -70,21 +71,35 @@ void intel_fb_plane_get_subsampling(int *hsub, int *vsub, int color_plane); u32 intel_plane_adjust_aligned_offset(int *x, int *y, - const struct intel_plane_state *state, + const struct intel_plane_state *plane_state, int color_plane, u32 old_offset, u32 new_offset); u32 intel_plane_compute_aligned_offset(int *x, int *y, - const struct intel_plane_state *state, + const struct intel_plane_state *plane_state, int color_plane); bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb); +bool intel_plane_uses_fence(const struct intel_plane_state *plane_state); bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb); -int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb); +unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info); +unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info); + +int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb); void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation, struct intel_fb_view *view); +unsigned int intel_fb_view_vtd_guard(const struct drm_framebuffer *fb, + const struct intel_fb_view *view, + unsigned int rotation); int intel_plane_compute_gtt(struct intel_plane_state *plane_state); +unsigned int intel_fb_xy_to_linear(int x, int y, + const struct intel_plane_state *plane_state, + int color_plane); +void intel_add_fb_offsets(int *x, int *y, + const struct intel_plane_state *plane_state, + int color_plane); + int intel_framebuffer_init(struct intel_framebuffer *ifb, struct drm_gem_object *obj, struct drm_mode_fb_cmd2 *mode_cmd); @@ -96,7 +111,7 @@ intel_user_framebuffer_create(struct drm_device *dev, struct drm_file *filp, const struct drm_mode_fb_cmd2 *user_mode_cmd); -bool intel_fb_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier); +bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier); bool intel_fb_uses_dpt(const struct drm_framebuffer *fb); unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier); diff --git a/drivers/gpu/drm/i915/display/intel_fb_bo.c b/drivers/gpu/drm/i915/display/intel_fb_bo.c index 810ca6ff8640..3d338a728354 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_bo.c +++ b/drivers/gpu/drm/i915/display/intel_fb_bo.c @@ -8,6 +8,7 @@ #include "gem/i915_gem_object.h" #include "i915_drv.h" +#include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_bo.h" @@ -16,12 +17,12 @@ void intel_fb_bo_framebuffer_fini(struct drm_gem_object *obj) /* Nothing to do for i915 */ } -int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, +int intel_fb_bo_framebuffer_init(struct drm_framebuffer *fb, struct drm_gem_object *_obj, struct drm_mode_fb_cmd2 *mode_cmd) { struct drm_i915_gem_object *obj = to_intel_bo(_obj); - struct drm_i915_private *i915 = to_i915(obj->base.dev); + struct intel_display *display = to_intel_display(obj->base.dev); unsigned int tiling, stride; i915_gem_object_lock(obj, NULL); @@ -36,7 +37,7 @@ int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, */ if (tiling != I915_TILING_NONE && tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "tiling_mode doesn't match fb modifier\n"); return -EINVAL; } @@ -44,7 +45,7 @@ int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, if (tiling == I915_TILING_X) { mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; } else if (tiling == I915_TILING_Y) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "No Y tiling for legacy addfb\n"); return -EINVAL; } @@ -54,9 +55,9 @@ int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, * gen2/3 display engine uses the fence if present, * so the tiling mode must match the fb modifier exactly. */ - if (DISPLAY_VER(i915) < 4 && + if (DISPLAY_VER(display) < 4 && tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "tiling_mode must match fb modifier exactly on gen2/3\n"); return -EINVAL; } @@ -66,7 +67,7 @@ int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, * the fb pitch and fence stride match. */ if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "pitch (%d) must match tiling stride (%d)\n", mode_cmd->pitches[0], stride); return -EINVAL; @@ -76,10 +77,11 @@ int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, } struct drm_gem_object * -intel_fb_bo_lookup_valid_bo(struct drm_i915_private *i915, +intel_fb_bo_lookup_valid_bo(struct drm_device *drm, struct drm_file *filp, const struct drm_mode_fb_cmd2 *mode_cmd) { + struct drm_i915_private *i915 = to_i915(drm); struct drm_i915_gem_object *obj; obj = i915_gem_object_lookup(filp, mode_cmd->handles[0]); diff --git a/drivers/gpu/drm/i915/display/intel_fb_bo.h b/drivers/gpu/drm/i915/display/intel_fb_bo.h index e71acd1bcb24..eefcb05a99f0 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_bo.h +++ b/drivers/gpu/drm/i915/display/intel_fb_bo.h @@ -6,20 +6,20 @@ #ifndef __INTEL_FB_BO_H__ #define __INTEL_FB_BO_H__ +struct drm_device; struct drm_file; +struct drm_framebuffer; struct drm_gem_object; -struct drm_i915_private; struct drm_mode_fb_cmd2; -struct intel_framebuffer; void intel_fb_bo_framebuffer_fini(struct drm_gem_object *obj); -int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, +int intel_fb_bo_framebuffer_init(struct drm_framebuffer *fb, struct drm_gem_object *obj, struct drm_mode_fb_cmd2 *mode_cmd); struct drm_gem_object * -intel_fb_bo_lookup_valid_bo(struct drm_i915_private *i915, +intel_fb_bo_lookup_valid_bo(struct drm_device *drm, struct drm_file *filp, const struct drm_mode_fb_cmd2 *user_mode_cmd); diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index d3a86f9c6bc8..30ac9b089ad6 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -25,6 +25,7 @@ intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, struct i915_address_space *vm) { struct drm_device *dev = fb->dev; + struct intel_display *display = to_intel_display(dev); struct drm_i915_private *dev_priv = to_i915(dev); struct drm_gem_object *_obj = intel_fb_bo(fb); struct drm_i915_gem_object *obj = to_intel_bo(_obj); @@ -42,7 +43,7 @@ intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, if (WARN_ON(!i915_gem_object_is_framebuffer(obj))) return ERR_PTR(-EINVAL); - atomic_inc(&dev_priv->gpu_error.pending_fb_pin); + atomic_inc(&display->restore.pending_fb_pin); for_i915_gem_ww(&ww, ret, true) { ret = i915_gem_object_lock(obj, &ww); @@ -97,7 +98,7 @@ intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, i915_vma_get(vma); err: - atomic_dec(&dev_priv->gpu_error.pending_fb_pin); + atomic_dec(&display->restore.pending_fb_pin); return vma; } @@ -107,10 +108,12 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, const struct i915_gtt_view *view, unsigned int alignment, unsigned int phys_alignment, + unsigned int vtd_guard, bool uses_fence, unsigned long *out_flags) { struct drm_device *dev = fb->dev; + struct intel_display *display = to_intel_display(dev); struct drm_i915_private *dev_priv = to_i915(dev); struct drm_gem_object *_obj = intel_fb_bo(fb); struct drm_i915_gem_object *obj = to_intel_bo(_obj); @@ -126,14 +129,6 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) return ERR_PTR(-EINVAL); - /* Note that the w/a also requires 64 PTE of padding following the - * bo. We currently fill all unused PTE with the shadow page and so - * we should always have valid PTE following the scanout preventing - * the VT-d warning. - */ - if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) - alignment = 256 * 1024; - /* * Global gtt pte registers are special registers which actually forward * writes to a chunk of system memory. Which means that there is no risk @@ -143,7 +138,7 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, */ wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); - atomic_inc(&dev_priv->gpu_error.pending_fb_pin); + atomic_inc(&display->restore.pending_fb_pin); /* * Valleyview is definitely limited to scanning out the first @@ -170,7 +165,7 @@ retry: goto err; vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment, - view, pinctl); + vtd_guard, view, pinctl); if (IS_ERR(vma)) { ret = PTR_ERR(vma); goto err_unpin; @@ -219,7 +214,7 @@ err: if (ret) vma = ERR_PTR(ret); - atomic_dec(&dev_priv->gpu_error.pending_fb_pin); + atomic_dec(&display->restore.pending_fb_pin); intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); return vma; } @@ -252,7 +247,16 @@ intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state) return plane->min_alignment(plane, fb, 0); } -int intel_plane_pin_fb(struct intel_plane_state *plane_state) +static unsigned int +intel_plane_fb_vtd_guard(const struct intel_plane_state *plane_state) +{ + return intel_fb_view_vtd_guard(plane_state->hw.fb, + &plane_state->view, + plane_state->hw.rotation); +} + +int intel_plane_pin_fb(struct intel_plane_state *plane_state, + const struct intel_plane_state *old_plane_state) { struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct intel_framebuffer *fb = @@ -263,6 +267,7 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state) vma = intel_fb_pin_to_ggtt(&fb->base, &plane_state->view.gtt, intel_plane_fb_min_alignment(plane_state), intel_plane_fb_min_phys_alignment(plane_state), + intel_plane_fb_vtd_guard(plane_state), intel_plane_uses_fence(plane_state), &plane_state->flags); if (IS_ERR(vma)) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/i915/display/intel_fb_pin.h index ac0319b53af0..01770dbba2e0 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h @@ -18,12 +18,14 @@ intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, const struct i915_gtt_view *view, unsigned int alignment, unsigned int phys_alignment, + unsigned int vtd_guard, bool uses_fence, unsigned long *out_flags); void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags); -int intel_plane_pin_fb(struct intel_plane_state *plane_state); +int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, + const struct intel_plane_state *old_plane_state); void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state); #endif diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index df05904bac8a..b6978135e8ad 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -88,6 +88,7 @@ struct intel_fbc_state { u16 override_cfb_stride; u16 interval; s8 fence_id; + struct drm_rect dirty_rect; }; struct intel_fbc { @@ -215,11 +216,9 @@ static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_s */ static unsigned int intel_fbc_max_cfb_height(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (DISPLAY_VER(display) >= 8) return 2560; - else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) + else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) return 2048; else return 1536; @@ -269,9 +268,8 @@ static bool intel_fbc_has_fences(struct intel_display *display) static u32 i8xx_fbc_ctl(struct intel_fbc *fbc) { - const struct intel_fbc_state *fbc_state = &fbc->state; struct intel_display *display = fbc->display; - struct drm_i915_private *i915 = to_i915(display->drm); + const struct intel_fbc_state *fbc_state = &fbc->state; unsigned int cfb_stride; u32 fbc_ctl; @@ -287,7 +285,7 @@ static u32 i8xx_fbc_ctl(struct intel_fbc *fbc) FBC_CTL_INTERVAL(fbc_state->interval) | FBC_CTL_STRIDE(cfb_stride); - if (IS_I945GM(i915)) + if (display->platform.i945gm) fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ if (fbc_state->fence_id >= 0) @@ -333,8 +331,8 @@ static void i8xx_fbc_deactivate(struct intel_fbc *fbc) static void i8xx_fbc_activate(struct intel_fbc *fbc) { - const struct intel_fbc_state *fbc_state = &fbc->state; struct intel_display *display = fbc->display; + const struct intel_fbc_state *fbc_state = &fbc->state; int i; /* Clear old tags */ @@ -365,12 +363,12 @@ static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc) static void i8xx_fbc_nuke(struct intel_fbc *fbc) { + struct intel_display *display = fbc->display; struct intel_fbc_state *fbc_state = &fbc->state; enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; - struct drm_i915_private *dev_priv = to_i915(fbc->display->drm); - intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), - intel_de_read_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane))); + intel_de_write_fw(display, DSPADDR(display, i9xx_plane), + intel_de_read_fw(display, DSPADDR(display, i9xx_plane))); } static void i8xx_fbc_program_cfb(struct intel_fbc *fbc) @@ -386,9 +384,9 @@ static void i8xx_fbc_program_cfb(struct intel_fbc *fbc) range_overflows_end_t(u64, i915_gem_stolen_area_address(i915), i915_gem_stolen_node_offset(&fbc->compressed_llb), U32_MAX)); - intel_de_write(i915, FBC_CFB_BASE, + intel_de_write(display, FBC_CFB_BASE, i915_gem_stolen_node_address(i915, &fbc->compressed_fb)); - intel_de_write(i915, FBC_LL_BASE, + intel_de_write(display, FBC_LL_BASE, i915_gem_stolen_node_address(i915, &fbc->compressed_llb)); } @@ -403,12 +401,12 @@ static const struct intel_fbc_funcs i8xx_fbc_funcs = { static void i965_fbc_nuke(struct intel_fbc *fbc) { + struct intel_display *display = fbc->display; struct intel_fbc_state *fbc_state = &fbc->state; enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; - struct drm_i915_private *dev_priv = to_i915(fbc->display->drm); - intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), - intel_de_read_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane))); + intel_de_write_fw(display, DSPSURF(display, i9xx_plane), + intel_de_read_fw(display, DSPSURF(display, i9xx_plane))); } static const struct intel_fbc_funcs i965_fbc_funcs = { @@ -437,15 +435,14 @@ static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc) static u32 g4x_dpfc_ctl(struct intel_fbc *fbc) { - const struct intel_fbc_state *fbc_state = &fbc->state; struct intel_display *display = fbc->display; - struct drm_i915_private *i915 = to_i915(display->drm); + const struct intel_fbc_state *fbc_state = &fbc->state; u32 dpfc_ctl; dpfc_ctl = g4x_dpfc_ctl_limit(fbc) | DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane); - if (IS_G4X(i915)) + if (display->platform.g4x) dpfc_ctl |= DPFC_CTL_SR_EN; if (fbc_state->fence_id >= 0) { @@ -460,8 +457,8 @@ static u32 g4x_dpfc_ctl(struct intel_fbc *fbc) static void g4x_fbc_activate(struct intel_fbc *fbc) { - const struct intel_fbc_state *fbc_state = &fbc->state; struct intel_display *display = fbc->display; + const struct intel_fbc_state *fbc_state = &fbc->state; intel_de_write(display, DPFC_FENCE_YOFF, fbc_state->fence_y_offset); @@ -512,8 +509,8 @@ static const struct intel_fbc_funcs g4x_fbc_funcs = { static void ilk_fbc_activate(struct intel_fbc *fbc) { - struct intel_fbc_state *fbc_state = &fbc->state; struct intel_display *display = fbc->display; + struct intel_fbc_state *fbc_state = &fbc->state; intel_de_write(display, ILK_DPFC_FENCE_YOFF(fbc->id), fbc_state->fence_y_offset); @@ -527,6 +524,9 @@ static void ilk_fbc_deactivate(struct intel_fbc *fbc) struct intel_display *display = fbc->display; u32 dpfc_ctl; + if (HAS_FBC_DIRTY_RECT(display)) + intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0); + /* Disable compression */ dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id)); if (dpfc_ctl & DPFC_CTL_EN) { @@ -564,8 +564,8 @@ static const struct intel_fbc_funcs ilk_fbc_funcs = { static void snb_fbc_program_fence(struct intel_fbc *fbc) { - const struct intel_fbc_state *fbc_state = &fbc->state; struct intel_display *display = fbc->display; + const struct intel_fbc_state *fbc_state = &fbc->state; u32 ctl = 0; if (fbc_state->fence_id >= 0) @@ -601,8 +601,8 @@ static const struct intel_fbc_funcs snb_fbc_funcs = { static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc) { - const struct intel_fbc_state *fbc_state = &fbc->state; struct intel_display *display = fbc->display; + const struct intel_fbc_state *fbc_state = &fbc->state; u32 val = 0; if (fbc_state->override_cfb_stride) @@ -614,8 +614,8 @@ static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc) static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc) { - const struct intel_fbc_state *fbc_state = &fbc->state; struct intel_display *display = fbc->display; + const struct intel_fbc_state *fbc_state = &fbc->state; u32 val = 0; /* Display WA #0529: skl, kbl, bxt. */ @@ -630,14 +630,13 @@ static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc) static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) { - const struct intel_fbc_state *fbc_state = &fbc->state; struct intel_display *display = fbc->display; - struct drm_i915_private *i915 = to_i915(display->drm); + const struct intel_fbc_state *fbc_state = &fbc->state; u32 dpfc_ctl; dpfc_ctl = g4x_dpfc_ctl_limit(fbc); - if (IS_IVYBRIDGE(i915)) + if (display->platform.ivybridge) dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane); if (DISPLAY_VER(display) >= 20) @@ -670,6 +669,10 @@ static void ivb_fbc_activate(struct intel_fbc *fbc) if (DISPLAY_VER(display) >= 20) intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); + if (HAS_FBC_DIRTY_RECT(display)) + intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), + FBC_DIRTY_RECT_EN); + intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), DPFC_CTL_EN | dpfc_ctl); } @@ -739,8 +742,19 @@ static void intel_fbc_nuke(struct intel_fbc *fbc) static void intel_fbc_activate(struct intel_fbc *fbc) { + struct intel_display *display = fbc->display; + lockdep_assert_held(&fbc->lock); + /* only the fence can change for a flip nuke */ + if (fbc->active && !intel_fbc_has_fences(display)) + return; + /* + * In case of FBC dirt rect, any updates to the FBC registers will + * trigger the nuke. + */ + drm_WARN_ON(display->drm, fbc->active && HAS_FBC_DIRTY_RECT(display)); + intel_fbc_hw_activate(fbc); intel_fbc_nuke(fbc); @@ -759,9 +773,7 @@ static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason) static u64 intel_fbc_cfb_base_max(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - - if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) return BIT_ULL(28); else return BIT_ULL(32); @@ -776,8 +788,8 @@ static u64 intel_fbc_stolen_end(struct intel_display *display) * reserved range size, so it always assumes the maximum (8mb) is used. * If we enable FBC using a CFB on that memory range we'll get FIFO * underruns, even if that range is not reserved by the BIOS. */ - if (IS_BROADWELL(i915) || - (DISPLAY_VER(display) == 9 && !IS_BROXTON(i915))) + if (display->platform.broadwell || + (DISPLAY_VER(display) == 9 && !display->platform.broxton)) end = i915_gem_stolen_area_size(i915) - 8 * 1024 * 1024; else end = U64_MAX; @@ -792,10 +804,8 @@ static int intel_fbc_min_limit(const struct intel_plane_state *plane_state) static int intel_fbc_max_limit(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - /* WaFbcOnly1to1Ratio:ctg */ - if (IS_G4X(i915)) + if (display->platform.g4x) return 1; /* @@ -843,7 +853,7 @@ static int intel_fbc_alloc_cfb(struct intel_fbc *fbc, drm_WARN_ON(display->drm, i915_gem_stolen_node_allocated(&fbc->compressed_llb)); - if (DISPLAY_VER(display) < 5 && !IS_G4X(i915)) { + if (DISPLAY_VER(display) < 5 && !display->platform.g4x) { ret = i915_gem_stolen_insert_node(i915, &fbc->compressed_llb, 4096, 4096); if (ret) @@ -882,9 +892,8 @@ static void intel_fbc_program_cfb(struct intel_fbc *fbc) static void intel_fbc_program_workarounds(struct intel_fbc *fbc) { struct intel_display *display = fbc->display; - struct drm_i915_private *i915 = to_i915(display->drm); - if (IS_SKYLAKE(i915) || IS_BROXTON(i915)) { + if (display->platform.skylake || display->platform.broxton) { /* * WaFbcHighMemBwCorruptionAvoidance:skl,bxt * Display WA #0883: skl,bxt @@ -893,8 +902,8 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc) 0, DPFC_DISABLE_DUMMY0); } - if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) || - IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) { + if (display->platform.skylake || display->platform.kabylake || + display->platform.coffeelake || display->platform.cometlake) { /* * WaFbcNukeOnHostModify:skl,kbl,cfl * Display WA #0873: skl,kbl,cfl @@ -909,7 +918,7 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc) 0, DPFC_CHICKEN_COMP_DUMMY_PIXEL); /* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp,mtl */ - if (DISPLAY_VER(display) >= 11 && !IS_DG2(i915)) + if (DISPLAY_VER(display) >= 11 && !display->platform.dg2) intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 0, DPFC_CHICKEN_FORCE_SLB_INVALIDATION); } @@ -986,13 +995,12 @@ static bool icl_fbc_stride_is_valid(const struct intel_plane_state *plane_state) static bool stride_is_valid(const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); - struct drm_i915_private *i915 = to_i915(display->drm); if (DISPLAY_VER(display) >= 11) return icl_fbc_stride_is_valid(plane_state); else if (DISPLAY_VER(display) >= 9) return skl_fbc_stride_is_valid(plane_state); - else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) + else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) return g4x_fbc_stride_is_valid(plane_state); else if (DISPLAY_VER(display) == 4) return i965_fbc_stride_is_valid(plane_state); @@ -1023,7 +1031,6 @@ static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); - struct drm_i915_private *i915 = to_i915(display->drm); const struct drm_framebuffer *fb = plane_state->hw.fb; switch (fb->format->format) { @@ -1032,7 +1039,7 @@ static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_ return true; case DRM_FORMAT_RGB565: /* WaFbcOnly1to1Ratio:ctg */ - if (IS_G4X(i915)) + if (display->platform.g4x) return false; return true; default: @@ -1059,11 +1066,10 @@ static bool lnl_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_ static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); - struct drm_i915_private *i915 = to_i915(display->drm); if (DISPLAY_VER(display) >= 20) return lnl_fbc_pixel_format_is_valid(plane_state); - else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) + else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) return g4x_fbc_pixel_format_is_valid(plane_state); else return i8xx_fbc_pixel_format_is_valid(plane_state); @@ -1094,11 +1100,10 @@ static bool skl_fbc_rotation_is_valid(const struct intel_plane_state *plane_stat static bool rotation_is_valid(const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); - struct drm_i915_private *i915 = to_i915(display->drm); if (DISPLAY_VER(display) >= 9) return skl_fbc_rotation_is_valid(plane_state); - else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) + else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) return g4x_fbc_rotation_is_valid(plane_state); else return i8xx_fbc_rotation_is_valid(plane_state); @@ -1107,8 +1112,6 @@ static bool rotation_is_valid(const struct intel_plane_state *plane_state) static void intel_fbc_max_surface_size(struct intel_display *display, unsigned int *w, unsigned int *h) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (DISPLAY_VER(display) >= 11) { *w = 8192; *h = 4096; @@ -1118,7 +1121,7 @@ static void intel_fbc_max_surface_size(struct intel_display *display, } else if (DISPLAY_VER(display) >= 7) { *w = 4096; *h = 4096; - } else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) { + } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) { *w = 4096; *h = 2048; } else { @@ -1151,15 +1154,13 @@ static bool intel_fbc_surface_size_ok(const struct intel_plane_state *plane_stat static void intel_fbc_max_plane_size(struct intel_display *display, unsigned int *w, unsigned int *h) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (DISPLAY_VER(display) >= 10) { *w = 5120; *h = 4096; - } else if (DISPLAY_VER(display) >= 8 || IS_HASWELL(i915)) { + } else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) { *w = 4096; *h = 4096; - } else if (DISPLAY_VER(display) >= 5 || IS_G4X(i915)) { + } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) { *w = 4096; *h = 2048; } else { @@ -1203,6 +1204,74 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state) return i8xx_fbc_tiling_valid(plane_state); } +static void +intel_fbc_invalidate_dirty_rect(struct intel_fbc *fbc) +{ + lockdep_assert_held(&fbc->lock); + + fbc->state.dirty_rect = DRM_RECT_INIT(0, 0, 0, 0); +} + +static void +intel_fbc_program_dirty_rect(struct intel_dsb *dsb, struct intel_fbc *fbc, + const struct drm_rect *fbc_dirty_rect) +{ + struct intel_display *display = fbc->display; + + drm_WARN_ON(display->drm, fbc_dirty_rect->y2 == 0); + + intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id), + FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) | + FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2 - 1)); +} + +static void +intel_fbc_dirty_rect_update(struct intel_dsb *dsb, struct intel_fbc *fbc) +{ + const struct drm_rect *fbc_dirty_rect = &fbc->state.dirty_rect; + + lockdep_assert_held(&fbc->lock); + + if (!drm_rect_visible(fbc_dirty_rect)) + return; + + intel_fbc_program_dirty_rect(dsb, fbc, fbc_dirty_rect); +} + +void +intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb, + struct intel_plane *plane) +{ + struct intel_display *display = to_intel_display(plane); + struct intel_fbc *fbc = plane->fbc; + + if (!HAS_FBC_DIRTY_RECT(display)) + return; + + mutex_lock(&fbc->lock); + + if (fbc->state.plane == plane) + intel_fbc_dirty_rect_update(dsb, fbc); + + mutex_unlock(&fbc->lock); +} + +static void +intel_fbc_hw_intialize_dirty_rect(struct intel_fbc *fbc, + const struct intel_plane_state *plane_state) +{ + struct drm_rect src; + + /* + * Initializing the FBC HW with the whole plane area as the dirty rect. + * This is to ensure that we have valid coords be written to the + * HW as dirty rect. + */ + drm_rect_fp_to_int(&src, &plane_state->uapi.src); + + intel_fbc_program_dirty_rect(NULL, fbc, &src); +} + static void intel_fbc_update_state(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_plane *plane) @@ -1276,6 +1345,62 @@ static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state) intel_fbc_is_cfb_ok(plane_state); } +static void +__intel_fbc_prepare_dirty_rect(const struct intel_plane_state *plane_state, + const struct intel_crtc_state *crtc_state) +{ + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + struct intel_fbc *fbc = plane->fbc; + struct drm_rect *fbc_dirty_rect = &fbc->state.dirty_rect; + int width = drm_rect_width(&plane_state->uapi.src) >> 16; + const struct drm_rect *damage = &plane_state->damage; + int y_offset = plane_state->view.color_plane[0].y; + + lockdep_assert_held(&fbc->lock); + + if (intel_crtc_needs_modeset(crtc_state) || + !intel_fbc_is_ok(plane_state)) { + intel_fbc_invalidate_dirty_rect(fbc); + return; + } + + if (drm_rect_visible(damage)) + *fbc_dirty_rect = *damage; + else + /* dirty rect must cover at least one line */ + *fbc_dirty_rect = DRM_RECT_INIT(0, y_offset, width, 1); +} + +void +intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(state); + const struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + struct intel_plane_state *plane_state; + struct intel_plane *plane; + int i; + + if (!HAS_FBC_DIRTY_RECT(display)) + return; + + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + struct intel_fbc *fbc = plane->fbc; + + if (!fbc || plane->pipe != crtc->pipe) + continue; + + mutex_lock(&fbc->lock); + + if (fbc->state.plane == plane) + __intel_fbc_prepare_dirty_rect(plane_state, + crtc_state); + + mutex_unlock(&fbc->lock); + } +} + static int intel_fbc_check_plane(struct intel_atomic_state *state, struct intel_plane *plane) { @@ -1317,7 +1442,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, } /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ - if (i915_vtd_active(i915) && (IS_SKYLAKE(i915) || IS_BROXTON(i915))) { + if (i915_vtd_active(i915) && (display->platform.skylake || display->platform.broxton)) { plane_state->no_fbc_reason = "VT-d enabled"; return 0; } @@ -1338,16 +1463,21 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, * Display 12+ is not supporting FBC with PSR2. * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 + * + * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot + * coexist. So if PSR2 selective fetch is supported then mark that + * FBC is not supported. + * TODO: Need a logic to decide between PSR2 and FBC Dirty rect */ - if (IS_DISPLAY_VER(display, 12, 14) && crtc_state->has_sel_update && - !crtc_state->has_panel_replay) { + if ((IS_DISPLAY_VER(display, 12, 14) || HAS_FBC_DIRTY_RECT(display)) && + crtc_state->has_sel_update && !crtc_state->has_panel_replay) { plane_state->no_fbc_reason = "PSR2 enabled"; return 0; } /* Wa_14016291713 */ if ((IS_DISPLAY_VER(display, 12, 13) || - IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_A0, STEP_C0)) && + IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0)) && crtc_state->has_psr && !crtc_state->has_panel_replay) { plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)"; return 0; @@ -1410,7 +1540,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, } /* WaFbcExceedCdClockThreshold:hsw,bdw */ - if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { + if (display->platform.haswell || display->platform.broadwell) { const struct intel_cdclk_state *cdclk_state; cdclk_state = intel_atomic_get_cdclk_state(state); @@ -1547,6 +1677,8 @@ static void __intel_fbc_disable(struct intel_fbc *fbc) drm_dbg_kms(display->drm, "Disabling FBC on [PLANE:%d:%s]\n", plane->base.base.id, plane->base.name); + intel_fbc_invalidate_dirty_rect(fbc); + __intel_fbc_cleanup_cfb(fbc); fbc->state.plane = NULL; @@ -1614,14 +1746,14 @@ out: mutex_unlock(&fbc->lock); } -void intel_fbc_invalidate(struct drm_i915_private *i915, +void intel_fbc_invalidate(struct intel_display *display, unsigned int frontbuffer_bits, enum fb_op_origin origin) { struct intel_fbc *fbc; enum intel_fbc_id fbc_id; - for_each_intel_fbc(&i915->display, fbc, fbc_id) + for_each_intel_fbc(display, fbc, fbc_id) __intel_fbc_invalidate(fbc, frontbuffer_bits, origin); } @@ -1653,14 +1785,14 @@ out: mutex_unlock(&fbc->lock); } -void intel_fbc_flush(struct drm_i915_private *i915, +void intel_fbc_flush(struct intel_display *display, unsigned int frontbuffer_bits, enum fb_op_origin origin) { struct intel_fbc *fbc; enum intel_fbc_id fbc_id; - for_each_intel_fbc(&i915->display, fbc, fbc_id) + for_each_intel_fbc(display, fbc, fbc_id) __intel_fbc_flush(fbc, frontbuffer_bits, origin); } @@ -1732,6 +1864,9 @@ static void __intel_fbc_enable(struct intel_atomic_state *state, intel_fbc_update_state(state, crtc, plane); + if (HAS_FBC_DIRTY_RECT(display)) + intel_fbc_hw_intialize_dirty_rect(fbc, plane_state); + intel_fbc_program_workarounds(fbc); intel_fbc_program_cfb(fbc); } @@ -1897,15 +2032,13 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display) */ static int intel_sanitize_fbc_option(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (display->params.enable_fbc >= 0) return !!display->params.enable_fbc; if (!HAS_FBC(display)) return 0; - if (IS_BROADWELL(i915) || DISPLAY_VER(display) >= 9) + if (display->platform.broadwell || DISPLAY_VER(display) >= 9) return 1; return 0; @@ -1919,7 +2052,6 @@ void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane) static struct intel_fbc *intel_fbc_create(struct intel_display *display, enum intel_fbc_id fbc_id) { - struct drm_i915_private *i915 = to_i915(display->drm); struct intel_fbc *fbc; fbc = kzalloc(sizeof(*fbc), GFP_KERNEL); @@ -1937,7 +2069,7 @@ static struct intel_fbc *intel_fbc_create(struct intel_display *display, fbc->funcs = &snb_fbc_funcs; else if (DISPLAY_VER(display) == 5) fbc->funcs = &ilk_fbc_funcs; - else if (IS_G4X(i915)) + else if (display->platform.g4x) fbc->funcs = &g4x_fbc_funcs; else if (DISPLAY_VER(display) == 4) fbc->funcs = &i965_fbc_funcs; diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h index ceae55458e14..0e715cb6b4e6 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.h +++ b/drivers/gpu/drm/i915/display/intel_fbc.h @@ -9,11 +9,11 @@ #include <linux/types.h> enum fb_op_origin; -struct drm_i915_private; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; struct intel_display; +struct intel_dsb; struct intel_fbc; struct intel_plane; struct intel_plane_state; @@ -38,15 +38,19 @@ void intel_fbc_sanitize(struct intel_display *display); void intel_fbc_update(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_fbc_disable(struct intel_crtc *crtc); -void intel_fbc_invalidate(struct drm_i915_private *dev_priv, +void intel_fbc_invalidate(struct intel_display *display, unsigned int frontbuffer_bits, enum fb_op_origin origin); -void intel_fbc_flush(struct drm_i915_private *dev_priv, +void intel_fbc_flush(struct intel_display *display, unsigned int frontbuffer_bits, enum fb_op_origin origin); void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane); void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display); void intel_fbc_reset_underrun(struct intel_display *display); void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc); void intel_fbc_debugfs_register(struct intel_display *display); +void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state, + struct intel_crtc *crtc); +void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb, + struct intel_plane *plane); #endif /* __INTEL_FBC_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h index ae0699c3c2fe..b1d0161a3196 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h @@ -100,6 +100,15 @@ #define FBC_STRIDE_MASK REG_GENMASK(14, 0) #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) +#define XE3_FBC_DIRTY_RECT(fbc_id) _MMIO_PIPE((fbc_id), 0x43230, 0x43270) +#define FBC_DIRTY_RECT_END_LINE_MASK REG_GENMASK(31, 16) +#define FBC_DIRTY_RECT_END_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_END_LINE_MASK, (val)) +#define FBC_DIRTY_RECT_START_LINE_MASK REG_GENMASK(15, 0) +#define FBC_DIRTY_RECT_START_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_START_LINE_MASK, (val)) + +#define XE3_FBC_DIRTY_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x43234, 0x43274) +#define FBC_DIRTY_RECT_EN REG_BIT(31) + #define ILK_FBC_RT_BASE _MMIO(0x2128) #define ILK_FBC_RT_VALID REG_BIT(0) #define SNB_FBC_FRONT_BUFFER REG_BIT(1) diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 00852ff5b247..adc19d5607de 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -37,14 +37,18 @@ #include <linux/tty.h> #include <linux/vga_switcheroo.h> +#include <drm/clients/drm_client_setup.h> #include <drm/drm_crtc.h> #include <drm/drm_crtc_helper.h> #include <drm/drm_fb_helper.h> #include <drm/drm_fourcc.h> #include <drm/drm_gem.h> #include <drm/drm_gem_framebuffer_helper.h> +#include <drm/drm_managed.h> +#include <drm/drm_print.h> #include "i915_drv.h" +#include "i915_vma.h" #include "intel_bo.h" #include "intel_display_types.h" #include "intel_fb.h" @@ -54,24 +58,16 @@ #include "intel_frontbuffer.h" struct intel_fbdev { - struct drm_fb_helper helper; struct intel_framebuffer *fb; struct i915_vma *vma; unsigned long vma_flags; - int preferred_bpp; - - /* Whether or not fbdev hpd processing is temporarily suspended */ - bool hpd_suspended: 1; - /* Set when a hotplug was received while HPD processing was suspended */ - bool hpd_waiting: 1; - - /* Protects hpd_suspended */ - struct mutex hpd_lock; }; static struct intel_fbdev *to_intel_fbdev(struct drm_fb_helper *fb_helper) { - return container_of(fb_helper, struct intel_fbdev, helper); + struct drm_i915_private *i915 = to_i915(fb_helper->client.dev); + + return i915->display.fbdev.fbdev; } static struct intel_frontbuffer *to_frontbuffer(struct intel_fbdev *ifbdev) @@ -127,8 +123,8 @@ static int intel_fbdev_pan_display(struct fb_var_screeninfo *var, static int intel_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma) { - struct intel_fbdev *fbdev = to_intel_fbdev(info->par); - struct drm_gem_object *obj = drm_gem_fb_get_obj(&fbdev->fb->base, 0); + struct drm_fb_helper *fb_helper = info->par; + struct drm_gem_object *obj = drm_gem_fb_get_obj(fb_helper->fb, 0); return intel_bo_fb_mmap(obj, vma); } @@ -136,9 +132,9 @@ static int intel_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma) static void intel_fbdev_fb_destroy(struct fb_info *info) { struct drm_fb_helper *fb_helper = info->par; - struct intel_fbdev *ifbdev = container_of(fb_helper, struct intel_fbdev, helper); + struct intel_fbdev *ifbdev = to_intel_fbdev(fb_helper); - drm_fb_helper_fini(&ifbdev->helper); + drm_fb_helper_fini(fb_helper); /* * We rely on the object-free to release the VMA pinning for @@ -146,11 +142,11 @@ static void intel_fbdev_fb_destroy(struct fb_info *info) * trying to rectify all the possible error paths leading here. */ intel_fb_unpin_vma(ifbdev->vma, ifbdev->vma_flags); - drm_framebuffer_remove(&ifbdev->fb->base); + drm_framebuffer_remove(fb_helper->fb); drm_client_release(&fb_helper->client); - drm_fb_helper_unprepare(&ifbdev->helper); - kfree(ifbdev); + drm_fb_helper_unprepare(fb_helper); + kfree(fb_helper); } __diag_push(); @@ -170,16 +166,53 @@ static const struct fb_ops intelfb_ops = { __diag_pop(); -static int intelfb_create(struct drm_fb_helper *helper, - struct drm_fb_helper_surface_size *sizes) +static int intelfb_dirty(struct drm_fb_helper *helper, struct drm_clip_rect *clip) +{ + if (!(clip->x1 < clip->x2 && clip->y1 < clip->y2)) + return 0; + + if (helper->fb->funcs->dirty) + return helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, clip, 1); + + return 0; +} + +static void intelfb_restore(struct drm_fb_helper *fb_helper) +{ + struct intel_fbdev *ifbdev = to_intel_fbdev(fb_helper); + + intel_fbdev_invalidate(ifbdev); +} + +static void intelfb_set_suspend(struct drm_fb_helper *fb_helper, bool suspend) +{ + struct fb_info *info = fb_helper->info; + + /* + * When resuming from hibernation, Linux restores the object's + * content from swap if the buffer is backed by shmemfs. If the + * object is stolen however, it will be full of whatever garbage + * was left in there. Clear it to zero in this case. + */ + if (!suspend && !intel_bo_is_shmem(intel_fb_bo(fb_helper->fb))) + memset_io(info->screen_base, 0, info->screen_size); + + fb_set_suspend(info, suspend); +} + +static const struct drm_fb_helper_funcs intel_fb_helper_funcs = { + .fb_dirty = intelfb_dirty, + .fb_restore = intelfb_restore, + .fb_set_suspend = intelfb_set_suspend, +}; + +int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, + struct drm_fb_helper_surface_size *sizes) { struct intel_fbdev *ifbdev = to_intel_fbdev(helper); struct intel_framebuffer *fb = ifbdev->fb; struct drm_device *dev = helper->dev; struct drm_i915_private *dev_priv = to_i915(dev); - const struct i915_gtt_view view = { - .type = I915_GTT_VIEW_NORMAL, - }; intel_wakeref_t wakeref; struct fb_info *info; struct i915_vma *vma; @@ -188,12 +221,6 @@ static int intelfb_create(struct drm_fb_helper *helper, struct drm_gem_object *obj; int ret; - mutex_lock(&ifbdev->hpd_lock); - ret = ifbdev->hpd_suspended ? -EAGAIN : 0; - mutex_unlock(&ifbdev->hpd_lock); - if (ret) - return ret; - ifbdev->fb = NULL; if (fb && @@ -226,8 +253,10 @@ static int intelfb_create(struct drm_fb_helper *helper, * This also validates that any existing fb inherited from the * BIOS is suitable for own access. */ - vma = intel_fb_pin_to_ggtt(&fb->base, &view, + vma = intel_fb_pin_to_ggtt(&fb->base, &fb->normal_view.gtt, fb->min_alignment, 0, + intel_fb_view_vtd_guard(&fb->base, &fb->normal_view, + DRM_MODE_ROTATE_0), false, &flags); if (IS_ERR(vma)) { ret = PTR_ERR(vma); @@ -241,7 +270,8 @@ static int intelfb_create(struct drm_fb_helper *helper, goto out_unpin; } - ifbdev->helper.fb = &fb->base; + helper->funcs = &intel_fb_helper_funcs; + helper->fb = &fb->base; info->fbops = &intelfb_ops; @@ -251,7 +281,7 @@ static int intelfb_create(struct drm_fb_helper *helper, if (ret) goto out_unpin; - drm_fb_helper_fill_info(info, &ifbdev->helper, sizes); + drm_fb_helper_fill_info(info, dev->fb_helper, sizes); /* If the object is shmemfs backed, it will have given us zeroed pages. * If the object is stolen however, it will be full of whatever @@ -280,22 +310,6 @@ out_unlock: return ret; } -static int intelfb_dirty(struct drm_fb_helper *helper, struct drm_clip_rect *clip) -{ - if (!(clip->x1 < clip->x2 && clip->y1 < clip->y2)) - return 0; - - if (helper->fb->funcs->dirty) - return helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, clip, 1); - - return 0; -} - -static const struct drm_fb_helper_funcs intel_fb_helper_funcs = { - .fb_probe = intelfb_create, - .fb_dirty = intelfb_dirty, -}; - /* * Build an intel_fbdev struct using a BIOS allocated framebuffer, if possible. * The core display code will have read out the current plane configuration, @@ -418,7 +432,6 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, goto out; } - ifbdev->preferred_bpp = fb->base.format->cpp[0] * 8; ifbdev->fb = fb; drm_framebuffer_get(&ifbdev->fb->base); @@ -449,249 +462,54 @@ out: return false; } -static void intel_fbdev_suspend_worker(struct work_struct *work) +static unsigned int intel_fbdev_color_mode(const struct drm_format_info *info) { - intel_fbdev_set_suspend(&container_of(work, - struct drm_i915_private, - display.fbdev.suspend_work)->drm, - FBINFO_STATE_RUNNING, - true); -} + unsigned int bpp; -/* Suspends/resumes fbdev processing of incoming HPD events. When resuming HPD - * processing, fbdev will perform a full connector reprobe if a hotplug event - * was received while HPD was suspended. - */ -static void intel_fbdev_hpd_set_suspend(struct drm_i915_private *i915, int state) -{ - struct intel_fbdev *ifbdev = i915->display.fbdev.fbdev; - bool send_hpd = false; - - mutex_lock(&ifbdev->hpd_lock); - ifbdev->hpd_suspended = state == FBINFO_STATE_SUSPENDED; - send_hpd = !ifbdev->hpd_suspended && ifbdev->hpd_waiting; - ifbdev->hpd_waiting = false; - mutex_unlock(&ifbdev->hpd_lock); - - if (send_hpd) { - drm_dbg_kms(&i915->drm, "Handling delayed fbcon HPD event\n"); - drm_fb_helper_hotplug_event(&ifbdev->helper); - } -} - -void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) -{ - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev; - struct fb_info *info; - - if (!ifbdev) - return; - - if (drm_WARN_ON(&dev_priv->drm, !HAS_DISPLAY(dev_priv))) - return; - - if (!ifbdev->vma) - goto set_suspend; - - info = ifbdev->helper.info; - - if (synchronous) { - /* Flush any pending work to turn the console on, and then - * wait to turn it off. It must be synchronous as we are - * about to suspend or unload the driver. - * - * Note that from within the work-handler, we cannot flush - * ourselves, so only flush outstanding work upon suspend! - */ - if (state != FBINFO_STATE_RUNNING) - flush_work(&dev_priv->display.fbdev.suspend_work); - - console_lock(); - } else { - /* - * The console lock can be pretty contented on resume due - * to all the printk activity. Try to keep it out of the hot - * path of resume if possible. - */ - drm_WARN_ON(dev, state != FBINFO_STATE_RUNNING); - if (!console_trylock()) { - /* Don't block our own workqueue as this can - * be run in parallel with other i915.ko tasks. - */ - queue_work(dev_priv->unordered_wq, - &dev_priv->display.fbdev.suspend_work); - return; - } - } - - /* On resume from hibernation: If the object is shmemfs backed, it has - * been restored from swap. If the object is stolen however, it will be - * full of whatever garbage was left in there. - */ - if (state == FBINFO_STATE_RUNNING && - !intel_bo_is_shmem(intel_fb_bo(&ifbdev->fb->base))) - memset_io(info->screen_base, 0, info->screen_size); - - drm_fb_helper_set_suspend(&ifbdev->helper, state); - console_unlock(); - -set_suspend: - intel_fbdev_hpd_set_suspend(dev_priv, state); -} - -static int intel_fbdev_output_poll_changed(struct drm_device *dev) -{ - struct intel_fbdev *ifbdev = to_i915(dev)->display.fbdev.fbdev; - bool send_hpd; - - if (!ifbdev) - return -EINVAL; - - mutex_lock(&ifbdev->hpd_lock); - send_hpd = !ifbdev->hpd_suspended; - ifbdev->hpd_waiting = true; - mutex_unlock(&ifbdev->hpd_lock); - - if (send_hpd && (ifbdev->vma || ifbdev->helper.deferred_setup)) - drm_fb_helper_hotplug_event(&ifbdev->helper); - - return 0; -} - -static int intel_fbdev_restore_mode(struct drm_i915_private *dev_priv) -{ - struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev; - int ret; - - if (!ifbdev) - return -EINVAL; - - if (!ifbdev->vma) - return -ENOMEM; - - ret = drm_fb_helper_restore_fbdev_mode_unlocked(&ifbdev->helper); - if (ret) - return ret; - - intel_fbdev_invalidate(ifbdev); - - return 0; -} - -/* - * Fbdev client and struct drm_client_funcs - */ + if (!info->depth || info->num_planes != 1 || info->has_alpha || info->is_yuv) + return 0; -static void intel_fbdev_client_unregister(struct drm_client_dev *client) -{ - struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client); - struct drm_device *dev = fb_helper->dev; - struct pci_dev *pdev = to_pci_dev(dev->dev); + bpp = drm_format_info_bpp(info, 0); - if (fb_helper->info) { - vga_switcheroo_client_fb_set(pdev, NULL); - drm_fb_helper_unregister_info(fb_helper); - } else { - drm_fb_helper_unprepare(fb_helper); - drm_client_release(&fb_helper->client); - kfree(fb_helper); + switch (bpp) { + case 16: + return info->depth; // 15 or 16 + default: + return bpp; } } -static int intel_fbdev_client_restore(struct drm_client_dev *client) -{ - struct drm_i915_private *dev_priv = to_i915(client->dev); - int ret; - - ret = intel_fbdev_restore_mode(dev_priv); - if (ret) - return ret; - - vga_switcheroo_process_delayed_switch(); - - return 0; -} - -static int intel_fbdev_client_hotplug(struct drm_client_dev *client) -{ - struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client); - struct drm_device *dev = client->dev; - struct pci_dev *pdev = to_pci_dev(dev->dev); - int ret; - - if (dev->fb_helper) - return intel_fbdev_output_poll_changed(dev); - - ret = drm_fb_helper_init(dev, fb_helper); - if (ret) - goto err_drm_err; - - ret = drm_fb_helper_initial_config(fb_helper); - if (ret) - goto err_drm_fb_helper_fini; - - vga_switcheroo_client_fb_set(pdev, fb_helper->info); - - return 0; - -err_drm_fb_helper_fini: - drm_fb_helper_fini(fb_helper); -err_drm_err: - drm_err(dev, "Failed to setup i915 fbdev emulation (ret=%d)\n", ret); - return ret; -} - -static const struct drm_client_funcs intel_fbdev_client_funcs = { - .owner = THIS_MODULE, - .unregister = intel_fbdev_client_unregister, - .restore = intel_fbdev_client_restore, - .hotplug = intel_fbdev_client_hotplug, -}; - void intel_fbdev_setup(struct drm_i915_private *i915) { struct drm_device *dev = &i915->drm; struct intel_fbdev *ifbdev; - int ret; + unsigned int preferred_bpp = 0; if (!HAS_DISPLAY(i915)) return; - ifbdev = kzalloc(sizeof(*ifbdev), GFP_KERNEL); + ifbdev = drmm_kzalloc(dev, sizeof(*ifbdev), GFP_KERNEL); if (!ifbdev) return; - drm_fb_helper_prepare(dev, &ifbdev->helper, 32, &intel_fb_helper_funcs); i915->display.fbdev.fbdev = ifbdev; - INIT_WORK(&i915->display.fbdev.suspend_work, intel_fbdev_suspend_worker); - mutex_init(&ifbdev->hpd_lock); if (intel_fbdev_init_bios(dev, ifbdev)) - ifbdev->helper.preferred_bpp = ifbdev->preferred_bpp; - else - ifbdev->preferred_bpp = ifbdev->helper.preferred_bpp; - - ret = drm_client_init(dev, &ifbdev->helper.client, "intel-fbdev", - &intel_fbdev_client_funcs); - if (ret) { - drm_err(dev, "Failed to register client: %d\n", ret); - goto err_drm_fb_helper_unprepare; - } - - drm_client_register(&ifbdev->helper.client); + preferred_bpp = intel_fbdev_color_mode(ifbdev->fb->base.format); + if (!preferred_bpp) + preferred_bpp = 32; - return; - -err_drm_fb_helper_unprepare: - drm_fb_helper_unprepare(&ifbdev->helper); - mutex_destroy(&ifbdev->hpd_lock); - kfree(ifbdev); + drm_client_setup_with_color_mode(dev, preferred_bpp); } struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev) { - if (!fbdev || !fbdev->helper.fb) + if (!fbdev) return NULL; - return to_intel_framebuffer(fbdev->helper.fb); + return fbdev->fb; +} + +struct i915_vma *intel_fbdev_vma_pointer(struct intel_fbdev *fbdev) +{ + return fbdev ? fbdev->vma : NULL; } diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.h b/drivers/gpu/drm/i915/display/intel_fbdev.h index 08de2d5b3433..89bad3a2b01a 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.h +++ b/drivers/gpu/drm/i915/display/intel_fbdev.h @@ -8,28 +8,37 @@ #include <linux/types.h> -struct drm_device; +struct drm_fb_helper; +struct drm_fb_helper_surface_size; struct drm_i915_private; struct intel_fbdev; struct intel_framebuffer; #ifdef CONFIG_DRM_FBDEV_EMULATION +int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, + struct drm_fb_helper_surface_size *sizes); +#define INTEL_FBDEV_DRIVER_OPS \ + .fbdev_probe = intel_fbdev_driver_fbdev_probe void intel_fbdev_setup(struct drm_i915_private *dev_priv); -void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev); +struct i915_vma *intel_fbdev_vma_pointer(struct intel_fbdev *fbdev); + #else +#define INTEL_FBDEV_DRIVER_OPS \ + .fbdev_probe = NULL static inline void intel_fbdev_setup(struct drm_i915_private *dev_priv) { } - -static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) +static inline struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev) { + return NULL; } -static inline struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev) +static inline struct i915_vma *intel_fbdev_vma_pointer(struct intel_fbdev *fbdev) { return NULL; } + #endif #endif /* __INTEL_FBDEV_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 37cdfa9c692a..40deee0769ae 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -24,10 +24,9 @@ struct intel_fdi_funcs { const struct intel_crtc_state *crtc_state); }; -static void assert_fdi_tx(struct drm_i915_private *dev_priv, +static void assert_fdi_tx(struct intel_display *display, enum pipe pipe, bool state) { - struct intel_display *display = &dev_priv->display; bool cur_state; if (HAS_DDI(display)) { @@ -48,20 +47,19 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv, str_on_off(state), str_on_off(cur_state)); } -void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe) +void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe) { - assert_fdi_tx(i915, pipe, true); + assert_fdi_tx(display, pipe, true); } -void assert_fdi_tx_disabled(struct drm_i915_private *i915, enum pipe pipe) +void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe) { - assert_fdi_tx(i915, pipe, false); + assert_fdi_tx(display, pipe, false); } -static void assert_fdi_rx(struct drm_i915_private *dev_priv, +static void assert_fdi_rx(struct intel_display *display, enum pipe pipe, bool state) { - struct intel_display *display = &dev_priv->display; bool cur_state; cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE; @@ -70,24 +68,22 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv, str_on_off(state), str_on_off(cur_state)); } -void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe) +void assert_fdi_rx_enabled(struct intel_display *display, enum pipe pipe) { - assert_fdi_rx(i915, pipe, true); + assert_fdi_rx(display, pipe, true); } -void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe) +void assert_fdi_rx_disabled(struct intel_display *display, enum pipe pipe) { - assert_fdi_rx(i915, pipe, false); + assert_fdi_rx(display, pipe, false); } -void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915, - enum pipe pipe) +void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe) { - struct intel_display *display = &i915->display; bool cur_state; /* ILK FDI PLL is always enabled */ - if (IS_IRONLAKE(i915)) + if (display->platform.ironlake) return; /* On Haswell, DDI ports are responsible for the FDI PLL setup */ @@ -99,10 +95,9 @@ void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915, "FDI TX PLL assertion failure, should be active but is disabled\n"); } -static void assert_fdi_rx_pll(struct drm_i915_private *i915, +static void assert_fdi_rx_pll(struct intel_display *display, enum pipe pipe, bool state) { - struct intel_display *display = &i915->display; bool cur_state; cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE; @@ -111,22 +106,22 @@ static void assert_fdi_rx_pll(struct drm_i915_private *i915, str_on_off(state), str_on_off(cur_state)); } -void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe) +void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe) { - assert_fdi_rx_pll(i915, pipe, true); + assert_fdi_rx_pll(display, pipe, true); } -void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe) +void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe) { - assert_fdi_rx_pll(i915, pipe, false); + assert_fdi_rx_pll(display, pipe, false); } void intel_fdi_link_train(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); - dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state); + display->funcs.fdi->fdi_link_train(crtc, crtc_state); } /** @@ -143,12 +138,11 @@ void intel_fdi_link_train(struct intel_crtc *crtc, int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_crtc_state *old_crtc_state; const struct intel_crtc_state *new_crtc_state; struct intel_crtc *crtc; - if (!IS_IVYBRIDGE(i915) || INTEL_NUM_PIPES(i915) != 3) + if (!display->platform.ivybridge || INTEL_NUM_PIPES(display) != 3) return 0; crtc = intel_crtc_for_pipe(display, PIPE_C); @@ -186,31 +180,29 @@ static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) return 0; } -static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, +static int ilk_check_fdi_lanes(struct intel_display *display, enum pipe pipe, struct intel_crtc_state *pipe_config, enum pipe *pipe_to_reduce) { - struct intel_display *display = to_intel_display(dev); - struct drm_i915_private *dev_priv = to_i915(dev); struct drm_atomic_state *state = pipe_config->uapi.state; struct intel_crtc *other_crtc; struct intel_crtc_state *other_crtc_state; *pipe_to_reduce = pipe; - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "checking fdi config on pipe %c, lanes %i\n", pipe_name(pipe), pipe_config->fdi_lanes); if (pipe_config->fdi_lanes > 4) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "invalid fdi lane config on pipe %c: %i lanes\n", pipe_name(pipe), pipe_config->fdi_lanes); return -EINVAL; } - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { + if (display->platform.haswell || display->platform.broadwell) { if (pipe_config->fdi_lanes > 2) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "only 2 lanes on haswell, required: %i lanes\n", pipe_config->fdi_lanes); return -EINVAL; @@ -219,7 +211,7 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, } } - if (INTEL_NUM_PIPES(dev_priv) == 2) + if (INTEL_NUM_PIPES(display) == 2) return 0; /* Ivybridge 3 pipe is really complicated */ @@ -237,7 +229,7 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, return PTR_ERR(other_crtc_state); if (pipe_required_fdi_lanes(other_crtc_state) > 0) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "invalid shared fdi lane config on pipe %c: %i lanes\n", pipe_name(pipe), pipe_config->fdi_lanes); return -EINVAL; @@ -245,7 +237,7 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, return 0; case PIPE_C: if (pipe_config->fdi_lanes > 2) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "only 2 lanes on pipe %c: required %i lanes\n", pipe_name(pipe), pipe_config->fdi_lanes); return -EINVAL; @@ -258,7 +250,7 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, return PTR_ERR(other_crtc_state); if (pipe_required_fdi_lanes(other_crtc_state) > 2) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "fdi link B uses too many lanes to enable link C\n"); *pipe_to_reduce = PIPE_B; @@ -272,29 +264,30 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, } } -void intel_fdi_pll_freq_update(struct drm_i915_private *i915) +void intel_fdi_pll_freq_update(struct intel_display *display) { - if (IS_IRONLAKE(i915)) { - u32 fdi_pll_clk = - intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; + if (display->platform.ironlake) { + u32 fdi_pll_clk; + + fdi_pll_clk = intel_de_read(display, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; - i915->display.fdi.pll_freq = (fdi_pll_clk + 2) * 10000; - } else if (IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) { - i915->display.fdi.pll_freq = 270000; + display->fdi.pll_freq = (fdi_pll_clk + 2) * 10000; + } else if (display->platform.sandybridge || display->platform.ivybridge) { + display->fdi.pll_freq = 270000; } else { return; } - drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->display.fdi.pll_freq); + drm_dbg(display->drm, "FDI PLL freq=%d\n", display->fdi.pll_freq); } -int intel_fdi_link_freq(struct drm_i915_private *i915, +int intel_fdi_link_freq(struct intel_display *display, const struct intel_crtc_state *pipe_config) { - if (HAS_DDI(i915)) + if (HAS_DDI(display)) return pipe_config->port_clock; /* SPLL */ else - return i915->display.fdi.pll_freq; + return display->fdi.pll_freq; } /** @@ -328,8 +321,7 @@ bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state) int ilk_fdi_compute_config(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *i915 = to_i915(dev); + struct intel_display *display = to_intel_display(crtc); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; int lane, link_bw, fdi_dotclock; @@ -340,7 +332,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc, * Hence the bw of each lane in terms of the mode signal * is: */ - link_bw = intel_fdi_link_freq(i915, pipe_config); + link_bw = intel_fdi_link_freq(display, pipe_config); fdi_dotclock = adjusted_mode->crtc_clock; @@ -363,11 +355,11 @@ static int intel_fdi_atomic_check_bw(struct intel_atomic_state *state, struct intel_crtc_state *pipe_config, struct intel_link_bw_limits *limits) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); enum pipe pipe_to_reduce; int ret; - ret = ilk_check_fdi_lanes(&i915->drm, crtc->pipe, pipe_config, + ret = ilk_check_fdi_lanes(display, crtc->pipe, pipe_config, &pipe_to_reduce); if (ret != -EINVAL) return ret; @@ -390,7 +382,7 @@ static int intel_fdi_atomic_check_bw(struct intel_atomic_state *state, * @state must be recomputed with the updated @limits. * * Returns: - * - 0 if the confugration is valid + * - 0 if the configuration is valid * - %-EAGAIN, if the configuration is invalid and @limits got updated * with fallback values with which the configuration of all CRTCs * in @state must be recomputed @@ -420,48 +412,48 @@ int intel_fdi_atomic_check_link(struct intel_atomic_state *state, return 0; } -static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable) +static void cpt_set_fdi_bc_bifurcation(struct intel_display *display, bool enable) { u32 temp; - temp = intel_de_read(dev_priv, SOUTH_CHICKEN1); + temp = intel_de_read(display, SOUTH_CHICKEN1); if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) return; - drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & + drm_WARN_ON(display->drm, + intel_de_read(display, FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); - drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & + drm_WARN_ON(display->drm, + intel_de_read(display, FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); temp &= ~FDI_BC_BIFURCATION_SELECT; if (enable) temp |= FDI_BC_BIFURCATION_SELECT; - drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n", + drm_dbg_kms(display->drm, "%sabling fdi C rx\n", enable ? "en" : "dis"); - intel_de_write(dev_priv, SOUTH_CHICKEN1, temp); - intel_de_posting_read(dev_priv, SOUTH_CHICKEN1); + intel_de_write(display, SOUTH_CHICKEN1, temp); + intel_de_posting_read(display, SOUTH_CHICKEN1); } static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); switch (crtc->pipe) { case PIPE_A: break; case PIPE_B: if (crtc_state->fdi_lanes > 2) - cpt_set_fdi_bc_bifurcation(dev_priv, false); + cpt_set_fdi_bc_bifurcation(display, false); else - cpt_set_fdi_bc_bifurcation(dev_priv, true); + cpt_set_fdi_bc_bifurcation(display, true); break; case PIPE_C: - cpt_set_fdi_bc_bifurcation(dev_priv, true); + cpt_set_fdi_bc_bifurcation(display, true); break; default: @@ -471,26 +463,26 @@ static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_st void intel_fdi_normal_train(struct intel_crtc *crtc) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(crtc); + struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe = crtc->pipe; i915_reg_t reg; u32 temp; /* enable normal train */ reg = FDI_TX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); - if (IS_IVYBRIDGE(dev_priv)) { + temp = intel_de_read(display, reg); + if (display->platform.ivybridge) { temp &= ~FDI_LINK_TRAIN_NONE_IVB; temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; } else { temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; } - intel_de_write(dev_priv, reg, temp); + intel_de_write(display, reg, temp); reg = FDI_RX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); if (HAS_PCH_CPT(dev_priv)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_NORMAL_CPT; @@ -498,23 +490,22 @@ void intel_fdi_normal_train(struct intel_crtc *crtc) temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_NONE; } - intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); + intel_de_write(display, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); /* wait one idle pattern time */ - intel_de_posting_read(dev_priv, reg); + intel_de_posting_read(display, reg); udelay(1000); /* IVB wants error correction enabled */ - if (IS_IVYBRIDGE(dev_priv)) - intel_de_rmw(dev_priv, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE); + if (display->platform.ivybridge) + intel_de_rmw(display, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE); } /* The FDI link training functions for ILK/Ibexpeak. */ static void ilk_fdi_link_train(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; i915_reg_t reg; u32 temp, tries; @@ -523,84 +514,84 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc, * Write the TU size bits before fdi link training, so that error * detection works. */ - intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), - intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); + intel_de_write(display, FDI_RX_TUSIZE1(pipe), + intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK); /* FDI needs bits from pipe first */ - assert_transcoder_enabled(dev_priv, crtc_state->cpu_transcoder); + assert_transcoder_enabled(display, crtc_state->cpu_transcoder); /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit for train result */ reg = FDI_RX_IMR(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp &= ~FDI_RX_SYMBOL_LOCK; temp &= ~FDI_RX_BIT_LOCK; - intel_de_write(dev_priv, reg, temp); - intel_de_read(dev_priv, reg); + intel_de_write(display, reg, temp); + intel_de_read(display, reg); udelay(150); /* enable CPU FDI TX and PCH FDI RX */ reg = FDI_TX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp &= ~FDI_DP_PORT_WIDTH_MASK; temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_1; - intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); + intel_de_write(display, reg, temp | FDI_TX_ENABLE); reg = FDI_RX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_1; - intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); + intel_de_write(display, reg, temp | FDI_RX_ENABLE); - intel_de_posting_read(dev_priv, reg); + intel_de_posting_read(display, reg); udelay(150); /* Ironlake workaround, enable clock pointer after FDI enable*/ - intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), + intel_de_write(display, FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); - intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), + intel_de_write(display, FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN); reg = FDI_RX_IIR(pipe); for (tries = 0; tries < 5; tries++) { - temp = intel_de_read(dev_priv, reg); - drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); + temp = intel_de_read(display, reg); + drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp); if ((temp & FDI_RX_BIT_LOCK)) { - drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n"); - intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK); + drm_dbg_kms(display->drm, "FDI train 1 done.\n"); + intel_de_write(display, reg, temp | FDI_RX_BIT_LOCK); break; } } if (tries == 5) - drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); + drm_err(display->drm, "FDI train 1 fail!\n"); /* Train 2 */ - intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), + intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2); - intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), + intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2); - intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe)); + intel_de_posting_read(display, FDI_RX_CTL(pipe)); udelay(150); reg = FDI_RX_IIR(pipe); for (tries = 0; tries < 5; tries++) { - temp = intel_de_read(dev_priv, reg); - drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); + temp = intel_de_read(display, reg); + drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_SYMBOL_LOCK) { - intel_de_write(dev_priv, reg, + intel_de_write(display, reg, temp | FDI_RX_SYMBOL_LOCK); - drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n"); + drm_dbg_kms(display->drm, "FDI train 2 done.\n"); break; } } if (tries == 5) - drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); + drm_err(display->drm, "FDI train 2 fail!\n"); - drm_dbg_kms(&dev_priv->drm, "FDI train done\n"); + drm_dbg_kms(display->drm, "FDI train done\n"); } @@ -615,8 +606,8 @@ static const int snb_b_fdi_train_param[] = { static void gen6_fdi_link_train(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(crtc); + struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe = crtc->pipe; i915_reg_t reg; u32 temp, i, retry; @@ -625,23 +616,23 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, * Write the TU size bits before fdi link training, so that error * detection works. */ - intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), - intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); + intel_de_write(display, FDI_RX_TUSIZE1(pipe), + intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK); /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit for train result */ reg = FDI_RX_IMR(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp &= ~FDI_RX_SYMBOL_LOCK; temp &= ~FDI_RX_BIT_LOCK; - intel_de_write(dev_priv, reg, temp); + intel_de_write(display, reg, temp); - intel_de_posting_read(dev_priv, reg); + intel_de_posting_read(display, reg); udelay(150); /* enable CPU FDI TX and PCH FDI RX */ reg = FDI_TX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp &= ~FDI_DP_PORT_WIDTH_MASK; temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); temp &= ~FDI_LINK_TRAIN_NONE; @@ -649,13 +640,13 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; /* SNB-B */ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; - intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); + intel_de_write(display, reg, temp | FDI_TX_ENABLE); - intel_de_write(dev_priv, FDI_RX_MISC(pipe), + intel_de_write(display, FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); reg = FDI_RX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); if (HAS_PCH_CPT(dev_priv)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; @@ -663,25 +654,25 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_1; } - intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); + intel_de_write(display, reg, temp | FDI_RX_ENABLE); - intel_de_posting_read(dev_priv, reg); + intel_de_posting_read(display, reg); udelay(150); for (i = 0; i < 4; i++) { - intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), + intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]); - intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); + intel_de_posting_read(display, FDI_TX_CTL(pipe)); udelay(500); for (retry = 0; retry < 5; retry++) { reg = FDI_RX_IIR(pipe); - temp = intel_de_read(dev_priv, reg); - drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); + temp = intel_de_read(display, reg); + drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_BIT_LOCK) { - intel_de_write(dev_priv, reg, + intel_de_write(display, reg, temp | FDI_RX_BIT_LOCK); - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "FDI train 1 done.\n"); break; } @@ -691,22 +682,22 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, break; } if (i == 4) - drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); + drm_err(display->drm, "FDI train 1 fail!\n"); /* Train 2 */ reg = FDI_TX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_2; - if (IS_SANDYBRIDGE(dev_priv)) { + if (display->platform.sandybridge) { temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; /* SNB-B */ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; } - intel_de_write(dev_priv, reg, temp); + intel_de_write(display, reg, temp); reg = FDI_RX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); if (HAS_PCH_CPT(dev_priv)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; @@ -714,25 +705,25 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_2; } - intel_de_write(dev_priv, reg, temp); + intel_de_write(display, reg, temp); - intel_de_posting_read(dev_priv, reg); + intel_de_posting_read(display, reg); udelay(150); for (i = 0; i < 4; i++) { - intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), + intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]); - intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); + intel_de_posting_read(display, FDI_TX_CTL(pipe)); udelay(500); for (retry = 0; retry < 5; retry++) { reg = FDI_RX_IIR(pipe); - temp = intel_de_read(dev_priv, reg); - drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); + temp = intel_de_read(display, reg); + drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_SYMBOL_LOCK) { - intel_de_write(dev_priv, reg, + intel_de_write(display, reg, temp | FDI_RX_SYMBOL_LOCK); - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "FDI train 2 done.\n"); break; } @@ -742,17 +733,16 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, break; } if (i == 4) - drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); + drm_err(display->drm, "FDI train 2 fail!\n"); - drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); + drm_dbg_kms(display->drm, "FDI train done.\n"); } /* Manual link training for Ivy Bridge A0 parts */ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; i915_reg_t reg; u32 temp, i, j; @@ -763,72 +753,72 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, * Write the TU size bits before fdi link training, so that error * detection works. */ - intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), - intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); + intel_de_write(display, FDI_RX_TUSIZE1(pipe), + intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK); /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit for train result */ reg = FDI_RX_IMR(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp &= ~FDI_RX_SYMBOL_LOCK; temp &= ~FDI_RX_BIT_LOCK; - intel_de_write(dev_priv, reg, temp); + intel_de_write(display, reg, temp); - intel_de_posting_read(dev_priv, reg); + intel_de_posting_read(display, reg); udelay(150); - drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n", - intel_de_read(dev_priv, FDI_RX_IIR(pipe))); + drm_dbg_kms(display->drm, "FDI_RX_IIR before link train 0x%x\n", + intel_de_read(display, FDI_RX_IIR(pipe))); /* Try each vswing and preemphasis setting twice before moving on */ for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { /* disable first in case we need to retry */ reg = FDI_TX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); temp &= ~FDI_TX_ENABLE; - intel_de_write(dev_priv, reg, temp); + intel_de_write(display, reg, temp); reg = FDI_RX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp &= ~FDI_LINK_TRAIN_AUTO; temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp &= ~FDI_RX_ENABLE; - intel_de_write(dev_priv, reg, temp); + intel_de_write(display, reg, temp); /* enable CPU FDI TX and PCH FDI RX */ reg = FDI_TX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp &= ~FDI_DP_PORT_WIDTH_MASK; temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; temp |= snb_b_fdi_train_param[j/2]; temp |= FDI_COMPOSITE_SYNC; - intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); + intel_de_write(display, reg, temp | FDI_TX_ENABLE); - intel_de_write(dev_priv, FDI_RX_MISC(pipe), + intel_de_write(display, FDI_RX_MISC(pipe), FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); reg = FDI_RX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; temp |= FDI_COMPOSITE_SYNC; - intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); + intel_de_write(display, reg, temp | FDI_RX_ENABLE); - intel_de_posting_read(dev_priv, reg); + intel_de_posting_read(display, reg); udelay(1); /* should be 0.5us */ for (i = 0; i < 4; i++) { reg = FDI_RX_IIR(pipe); - temp = intel_de_read(dev_priv, reg); - drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); + temp = intel_de_read(display, reg); + drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_BIT_LOCK || - (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) { - intel_de_write(dev_priv, reg, + (intel_de_read(display, reg) & FDI_RX_BIT_LOCK)) { + intel_de_write(display, reg, temp | FDI_RX_BIT_LOCK); - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "FDI train 1 done, level %i.\n", i); break; @@ -836,31 +826,31 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, udelay(1); /* should be 0.5us */ } if (i == 4) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "FDI train 1 fail on vswing %d\n", j / 2); continue; } /* Train 2 */ - intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), + intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_LINK_TRAIN_NONE_IVB, FDI_LINK_TRAIN_PATTERN_2_IVB); - intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), + intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_LINK_TRAIN_PATTERN_MASK_CPT, FDI_LINK_TRAIN_PATTERN_2_CPT); - intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe)); + intel_de_posting_read(display, FDI_RX_CTL(pipe)); udelay(2); /* should be 1.5us */ for (i = 0; i < 4; i++) { reg = FDI_RX_IIR(pipe); - temp = intel_de_read(dev_priv, reg); - drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); + temp = intel_de_read(display, reg); + drm_dbg_kms(display->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_SYMBOL_LOCK || - (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) { - intel_de_write(dev_priv, reg, + (intel_de_read(display, reg) & FDI_RX_SYMBOL_LOCK)) { + intel_de_write(display, reg, temp | FDI_RX_SYMBOL_LOCK); - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "FDI train 2 done, level %i.\n", i); goto train_done; @@ -868,12 +858,12 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, udelay(2); /* should be 1.5us */ } if (i == 4) - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "FDI train 2 fail on vswing %d\n", j / 2); } train_done: - drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); + drm_dbg_kms(display->drm, "FDI train done.\n"); } /* Starting with Haswell, different DDI ports can work in FDI mode for @@ -887,8 +877,7 @@ train_done: void hsw_fdi_link_train(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); u32 temp, i, rx_ctl_val; int n_entries; @@ -903,33 +892,33 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, * * WaFDIAutoLinkSetTimingOverrride:hsw */ - intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), + intel_de_write(display, FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); /* Enable the PCH Receiver FDI PLL */ - rx_ctl_val = dev_priv->display.fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | + rx_ctl_val = display->fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | FDI_RX_PLL_ENABLE | FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); - intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); + intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val); + intel_de_posting_read(display, FDI_RX_CTL(PIPE_A)); udelay(220); /* Switch from Rawclk to PCDclk */ rx_ctl_val |= FDI_PCDCLK; - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); + intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val); /* Configure Port Clock Select */ - drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); + drm_WARN_ON(display->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); intel_ddi_enable_clock(encoder, crtc_state); /* Start the training iterating through available voltages and emphasis, * testing each value twice. */ for (i = 0; i < n_entries * 2; i++) { /* Configure DP_TP_CTL with auto-training */ - intel_de_write(dev_priv, DP_TP_CTL(PORT_E), + intel_de_write(display, DP_TP_CTL(PORT_E), DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1 | @@ -939,36 +928,36 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, * DDI E does not support port reversal, the functionality is * achieved on the PCH side in FDI_RX_CTL, so no need to set the * port reversal bit */ - intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), + intel_de_write(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); - intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); + intel_de_posting_read(display, DDI_BUF_CTL(PORT_E)); udelay(600); /* Program PCH FDI Receiver TU */ - intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); + intel_de_write(display, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); /* Enable PCH FDI Receiver with auto-training */ rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); - intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); + intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val); + intel_de_posting_read(display, FDI_RX_CTL(PIPE_A)); /* Wait for FDI receiver lane calibration */ udelay(30); /* Unset FDI_RX_MISC pwrdn lanes */ - intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A), + intel_de_rmw(display, FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 0); - intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); + intel_de_posting_read(display, FDI_RX_MISC(PIPE_A)); /* Wait for FDI auto training time */ udelay(5); - temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); + temp = intel_de_read(display, DP_TP_STATUS(PORT_E)); if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "FDI link training done on step %d\n", i); break; } @@ -978,32 +967,32 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, * Results in less fireworks from the state checker. */ if (i == n_entries * 2 - 1) { - drm_err(&dev_priv->drm, "FDI link training failed!\n"); + drm_err(display->drm, "FDI link training failed!\n"); break; } rx_ctl_val &= ~FDI_RX_ENABLE; - intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); - intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); + intel_de_write(display, FDI_RX_CTL(PIPE_A), rx_ctl_val); + intel_de_posting_read(display, FDI_RX_CTL(PIPE_A)); - intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); - intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); + intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); + intel_de_posting_read(display, DDI_BUF_CTL(PORT_E)); /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ - intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0); - intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); + intel_de_rmw(display, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0); + intel_de_posting_read(display, DP_TP_CTL(PORT_E)); - intel_wait_ddi_buf_idle(dev_priv, PORT_E); + intel_wait_ddi_buf_idle(display, PORT_E); /* Reset FDI_RX_MISC pwrdn lanes */ - intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A), + intel_de_rmw(display, FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2)); - intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); + intel_de_posting_read(display, FDI_RX_MISC(PIPE_A)); } /* Enable normal pixel sending for FDI */ - intel_de_write(dev_priv, DP_TP_CTL(PORT_E), + intel_de_write(display, DP_TP_CTL(PORT_E), DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_LINK_TRAIN_NORMAL | DP_TP_CTL_ENHANCED_FRAME_ENABLE | @@ -1012,7 +1001,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, void hsw_fdi_disable(struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); /* * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) @@ -1020,103 +1009,103 @@ void hsw_fdi_disable(struct intel_encoder *encoder) * step 13 is the correct place for it. Step 18 is where it was * originally before the BUN. */ - intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0); - intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); - intel_wait_ddi_buf_idle(dev_priv, PORT_E); + intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0); + intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); + intel_wait_ddi_buf_idle(display, PORT_E); intel_ddi_disable_clock(encoder); - intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A), + intel_de_rmw(display, FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2)); - intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0); - intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0); + intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0); + intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0); } void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; i915_reg_t reg; u32 temp; /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ reg = FDI_RX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); - temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; - intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE); + temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11; + intel_de_write(display, reg, temp | FDI_RX_PLL_ENABLE); - intel_de_posting_read(dev_priv, reg); + intel_de_posting_read(display, reg); udelay(200); /* Switch from Rawclk to PCDclk */ - intel_de_rmw(dev_priv, reg, 0, FDI_PCDCLK); - intel_de_posting_read(dev_priv, reg); + intel_de_rmw(display, reg, 0, FDI_PCDCLK); + intel_de_posting_read(display, reg); udelay(200); /* Enable CPU FDI TX PLL, always on for Ironlake */ reg = FDI_TX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); if ((temp & FDI_TX_PLL_ENABLE) == 0) { - intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE); + intel_de_write(display, reg, temp | FDI_TX_PLL_ENABLE); - intel_de_posting_read(dev_priv, reg); + intel_de_posting_read(display, reg); udelay(100); } } void ilk_fdi_pll_disable(struct intel_crtc *crtc) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; /* Switch from PCDclk to Rawclk */ - intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_PCDCLK, 0); + intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_PCDCLK, 0); /* Disable CPU FDI TX PLL */ - intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0); - intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); + intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0); + intel_de_posting_read(display, FDI_TX_CTL(pipe)); udelay(100); /* Wait for the clocks to turn off. */ - intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0); - intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe)); + intel_de_rmw(display, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0); + intel_de_posting_read(display, FDI_RX_CTL(pipe)); udelay(100); } void ilk_fdi_disable(struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; i915_reg_t reg; u32 temp; /* disable CPU FDI tx and PCH FDI rx */ - intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0); - intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); + intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0); + intel_de_posting_read(display, FDI_TX_CTL(pipe)); reg = FDI_RX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp &= ~(0x7 << 16); - temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; - intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE); + temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11; + intel_de_write(display, reg, temp & ~FDI_RX_ENABLE); - intel_de_posting_read(dev_priv, reg); + intel_de_posting_read(display, reg); udelay(100); /* Ironlake workaround, disable clock pointer after downing FDI */ if (HAS_PCH_IBX(dev_priv)) - intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), + intel_de_write(display, FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); /* still set train pattern 1 */ - intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), + intel_de_rmw(display, FDI_TX_CTL(pipe), FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_1); reg = FDI_RX_CTL(pipe); - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); if (HAS_PCH_CPT(dev_priv)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; @@ -1126,10 +1115,10 @@ void ilk_fdi_disable(struct intel_crtc *crtc) } /* BPC in FDI rx is consistent with that in TRANSCONF */ temp &= ~(0x07 << 16); - temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; - intel_de_write(dev_priv, reg, temp); + temp |= (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) << 11; + intel_de_write(display, reg, temp); - intel_de_posting_read(dev_priv, reg); + intel_de_posting_read(display, reg); udelay(100); } @@ -1146,14 +1135,14 @@ static const struct intel_fdi_funcs ivb_funcs = { }; void -intel_fdi_init_hook(struct drm_i915_private *dev_priv) +intel_fdi_init_hook(struct intel_display *display) { - if (IS_IRONLAKE(dev_priv)) { - dev_priv->display.funcs.fdi = &ilk_funcs; - } else if (IS_SANDYBRIDGE(dev_priv)) { - dev_priv->display.funcs.fdi = &gen6_funcs; - } else if (IS_IVYBRIDGE(dev_priv)) { + if (display->platform.ironlake) { + display->funcs.fdi = &ilk_funcs; + } else if (display->platform.sandybridge) { + display->funcs.fdi = &gen6_funcs; + } else if (display->platform.ivybridge) { /* FIXME: detect B0+ stepping and use auto training */ - dev_priv->display.funcs.fdi = &ivb_funcs; + display->funcs.fdi = &ivb_funcs; } } diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h index 477ff0136934..ad5e103c38a8 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.h +++ b/drivers/gpu/drm/i915/display/intel_fdi.h @@ -9,15 +9,16 @@ #include <linux/types.h> enum pipe; -struct drm_i915_private; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; +struct intel_display; +struct intel_display; struct intel_encoder; struct intel_link_bw_limits; int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state); -int intel_fdi_link_freq(struct drm_i915_private *i915, +int intel_fdi_link_freq(struct intel_display *display, const struct intel_crtc_state *pipe_config); bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state); int ilk_fdi_compute_config(struct intel_crtc *intel_crtc, @@ -28,21 +29,21 @@ void intel_fdi_normal_train(struct intel_crtc *crtc); void ilk_fdi_disable(struct intel_crtc *crtc); void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc); void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state); -void intel_fdi_init_hook(struct drm_i915_private *dev_priv); +void intel_fdi_init_hook(struct intel_display *display); void hsw_fdi_link_train(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void hsw_fdi_disable(struct intel_encoder *encoder); -void intel_fdi_pll_freq_update(struct drm_i915_private *i915); +void intel_fdi_pll_freq_update(struct intel_display *display); void intel_fdi_link_train(struct intel_crtc *crtc, const struct intel_crtc_state *crtc_state); -void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe); -void assert_fdi_tx_disabled(struct drm_i915_private *i915, enum pipe pipe); -void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe); -void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe); -void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe); -void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe); -void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe); +void assert_fdi_tx_enabled(struct intel_display *display, enum pipe pipe); +void assert_fdi_tx_disabled(struct intel_display *display, enum pipe pipe); +void assert_fdi_rx_enabled(struct intel_display *display, enum pipe pipe); +void assert_fdi_rx_disabled(struct intel_display *display, enum pipe pipe); +void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe); +void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe); +void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe); #endif diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c index cda1daf4cdea..7a8fbff39be0 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c @@ -55,16 +55,15 @@ * The code also supports underrun detection on the PCH transcoder. */ -static bool ivb_can_enable_err_int(struct drm_device *dev) +static bool ivb_can_enable_err_int(struct intel_display *display) { - struct intel_display *display = to_intel_display(dev); - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc *crtc; enum pipe pipe; lockdep_assert_held(&dev_priv->irq_lock); - for_each_pipe(dev_priv, pipe) { + for_each_pipe(display, pipe) { crtc = intel_crtc_for_pipe(display, pipe); if (crtc->cpu_fifo_underrun_disabled) @@ -74,16 +73,15 @@ static bool ivb_can_enable_err_int(struct drm_device *dev) return true; } -static bool cpt_can_enable_serr_int(struct drm_device *dev) +static bool cpt_can_enable_serr_int(struct intel_display *display) { - struct intel_display *display = to_intel_display(dev); - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe; struct intel_crtc *crtc; lockdep_assert_held(&dev_priv->irq_lock); - for_each_pipe(dev_priv, pipe) { + for_each_pipe(display, pipe) { crtc = intel_crtc_for_pipe(display, pipe); if (crtc->pch_fifo_underrun_disabled) @@ -97,48 +95,48 @@ static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe); + i915_reg_t reg = PIPESTAT(display, crtc->pipe); u32 enable_mask; lockdep_assert_held(&dev_priv->irq_lock); - if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) + if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) return; - enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); - intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); - intel_de_posting_read(dev_priv, reg); + enable_mask = i915_pipestat_enable_mask(display, crtc->pipe); + intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); + intel_de_posting_read(display, reg); trace_intel_cpu_fifo_underrun(display, crtc->pipe); - drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe)); + drm_err(display->drm, "pipe %c underrun\n", pipe_name(crtc->pipe)); } -static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, +static void i9xx_set_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable, bool old) { - struct drm_i915_private *dev_priv = to_i915(dev); - i915_reg_t reg = PIPESTAT(dev_priv, pipe); + struct drm_i915_private *dev_priv = to_i915(display->drm); + i915_reg_t reg = PIPESTAT(display, pipe); lockdep_assert_held(&dev_priv->irq_lock); if (enable) { - u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); + u32 enable_mask = i915_pipestat_enable_mask(display, pipe); - intel_de_write(dev_priv, reg, + intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); - intel_de_posting_read(dev_priv, reg); + intel_de_posting_read(display, reg); } else { - if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) - drm_err(&dev_priv->drm, "pipe %c underrun\n", + if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) + drm_err(display->drm, "pipe %c underrun\n", pipe_name(pipe)); } } -static void ilk_set_fifo_underrun_reporting(struct drm_device *dev, +static void ilk_set_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable) { - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(display->drm); u32 bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : DE_PIPEB_FIFO_UNDERRUN; @@ -153,30 +151,30 @@ static void ivb_check_fifo_underruns(struct intel_crtc *crtc) struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT); + u32 err_int = intel_de_read(display, GEN7_ERR_INT); lockdep_assert_held(&dev_priv->irq_lock); if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) return; - intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); - intel_de_posting_read(dev_priv, GEN7_ERR_INT); + intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); + intel_de_posting_read(display, GEN7_ERR_INT); trace_intel_cpu_fifo_underrun(display, pipe); - drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe)); + drm_err(display->drm, "fifo underrun on pipe %c\n", pipe_name(pipe)); } -static void ivb_set_fifo_underrun_reporting(struct drm_device *dev, +static void ivb_set_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable, bool old) { - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(display->drm); if (enable) { - intel_de_write(dev_priv, GEN7_ERR_INT, + intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); - if (!ivb_can_enable_err_int(dev)) + if (!ivb_can_enable_err_int(display)) return; ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB); @@ -184,18 +182,18 @@ static void ivb_set_fifo_underrun_reporting(struct drm_device *dev, ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB); if (old && - intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { - drm_err(&dev_priv->drm, + intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { + drm_err(display->drm, "uncleared fifo underrun on pipe %c\n", pipe_name(pipe)); } } } -static void bdw_set_fifo_underrun_reporting(struct drm_device *dev, +static void bdw_set_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable) { - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(display->drm); if (enable) bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); @@ -203,11 +201,11 @@ static void bdw_set_fifo_underrun_reporting(struct drm_device *dev, bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); } -static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, +static void ibx_set_fifo_underrun_reporting(struct intel_display *display, enum pipe pch_transcoder, bool enable) { - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(display->drm); u32 bit = (pch_transcoder == PIPE_A) ? SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; @@ -222,53 +220,52 @@ static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pch_transcoder = crtc->pipe; - u32 serr_int = intel_de_read(dev_priv, SERR_INT); + u32 serr_int = intel_de_read(display, SERR_INT); lockdep_assert_held(&dev_priv->irq_lock); if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0) return; - intel_de_write(dev_priv, SERR_INT, + intel_de_write(display, SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); - intel_de_posting_read(dev_priv, SERR_INT); + intel_de_posting_read(display, SERR_INT); trace_intel_pch_fifo_underrun(display, pch_transcoder); - drm_err(&dev_priv->drm, "pch fifo underrun on pch transcoder %c\n", + drm_err(display->drm, "pch fifo underrun on pch transcoder %c\n", pipe_name(pch_transcoder)); } -static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, +static void cpt_set_fifo_underrun_reporting(struct intel_display *display, enum pipe pch_transcoder, bool enable, bool old) { - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(display->drm); if (enable) { - intel_de_write(dev_priv, SERR_INT, + intel_de_write(display, SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); - if (!cpt_can_enable_serr_int(dev)) + if (!cpt_can_enable_serr_int(display)) return; ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); } else { ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); - if (old && intel_de_read(dev_priv, SERR_INT) & + if (old && intel_de_read(display, SERR_INT) & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { - drm_err(&dev_priv->drm, + drm_err(display->drm, "uncleared pch fifo underrun on pch transcoder %c\n", pipe_name(pch_transcoder)); } } } -static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, +static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable) { - struct intel_display *display = to_intel_display(dev); - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); bool old; @@ -277,21 +274,21 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, old = !crtc->cpu_fifo_underrun_disabled; crtc->cpu_fifo_underrun_disabled = !enable; - if (HAS_GMCH(dev_priv)) - i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); - else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) - ilk_set_fifo_underrun_reporting(dev, pipe, enable); - else if (DISPLAY_VER(dev_priv) == 7) - ivb_set_fifo_underrun_reporting(dev, pipe, enable, old); - else if (DISPLAY_VER(dev_priv) >= 8) - bdw_set_fifo_underrun_reporting(dev, pipe, enable); + if (HAS_GMCH(display)) + i9xx_set_fifo_underrun_reporting(display, pipe, enable, old); + else if (display->platform.ironlake || display->platform.sandybridge) + ilk_set_fifo_underrun_reporting(display, pipe, enable); + else if (DISPLAY_VER(display) == 7) + ivb_set_fifo_underrun_reporting(display, pipe, enable, old); + else if (DISPLAY_VER(display) >= 8) + bdw_set_fifo_underrun_reporting(display, pipe, enable); return old; } /** - * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrrun reporting state - * @dev_priv: i915 device instance + * intel_set_cpu_fifo_underrun_reporting - set cpu fifo underrun reporting state + * @display: display device instance * @pipe: (CPU) pipe to set state for * @enable: whether underruns should be reported or not * @@ -305,15 +302,15 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, * * Returns the previous state of underrun reporting. */ -bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, +bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable) { + struct drm_i915_private *dev_priv = to_i915(display->drm); unsigned long flags; bool ret; spin_lock_irqsave(&dev_priv->irq_lock, flags); - ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe, - enable); + ret = __intel_set_cpu_fifo_underrun_reporting(display, pipe, enable); spin_unlock_irqrestore(&dev_priv->irq_lock, flags); return ret; @@ -321,7 +318,7 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, /** * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state - * @dev_priv: i915 device instance + * @display: display device instance * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) * @enable: whether underruns should be reported or not * @@ -333,13 +330,12 @@ bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, * * Returns the previous state of underrun reporting. */ -bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, +bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display, enum pipe pch_transcoder, bool enable) { - struct intel_display *display = &dev_priv->display; - struct intel_crtc *crtc = - intel_crtc_for_pipe(display, pch_transcoder); + struct drm_i915_private *dev_priv = to_i915(display->drm); + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pch_transcoder); unsigned long flags; bool old; @@ -358,11 +354,11 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, crtc->pch_fifo_underrun_disabled = !enable; if (HAS_PCH_IBX(dev_priv)) - ibx_set_fifo_underrun_reporting(&dev_priv->drm, + ibx_set_fifo_underrun_reporting(display, pch_transcoder, enable); else - cpt_set_fifo_underrun_reporting(&dev_priv->drm, + cpt_set_fifo_underrun_reporting(display, pch_transcoder, enable, old); @@ -372,17 +368,16 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, /** * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt - * @dev_priv: i915 device instance + * @display: display device instance * @pipe: (CPU) pipe to set state for * * This handles a CPU fifo underrun interrupt, generating an underrun warning * into dmesg if underrun reporting is enabled and then disables the underrun * interrupt to avoid an irq storm. */ -void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, +void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display, enum pipe pipe) { - struct intel_display *display = &dev_priv->display; struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); /* We may be called too early in init, thanks BIOS! */ @@ -390,63 +385,62 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, return; /* GMCH can't disable fifo underruns, filter them. */ - if (HAS_GMCH(dev_priv) && + if (HAS_GMCH(display) && crtc->cpu_fifo_underrun_disabled) return; - if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) { + if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) { trace_intel_cpu_fifo_underrun(display, pipe); - drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe)); + drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe)); } - intel_fbc_handle_fifo_underrun_irq(&dev_priv->display); + intel_fbc_handle_fifo_underrun_irq(display); } /** * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt - * @dev_priv: i915 device instance + * @display: display device instance * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) * * This handles a PCH fifo underrun interrupt, generating an underrun warning * into dmesg if underrun reporting is enabled and then disables the underrun * interrupt to avoid an irq storm. */ -void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, +void intel_pch_fifo_underrun_irq_handler(struct intel_display *display, enum pipe pch_transcoder) { - struct intel_display *display = &dev_priv->display; - - if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, + if (intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, false)) { trace_intel_pch_fifo_underrun(display, pch_transcoder); - drm_err(&dev_priv->drm, "PCH transcoder %c FIFO underrun\n", + drm_err(display->drm, "PCH transcoder %c FIFO underrun\n", pipe_name(pch_transcoder)); } } /** * intel_check_cpu_fifo_underruns - check for CPU fifo underruns immediately - * @dev_priv: i915 device instance + * @display: display device instance * * Check for CPU fifo underruns immediately. Useful on IVB/HSW where the shared * error interrupt may have been disabled, and so CPU fifo underruns won't * necessarily raise an interrupt, and on GMCH platforms where underruns never * raise an interrupt. */ -void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) +void intel_check_cpu_fifo_underruns(struct intel_display *display) { + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc *crtc; spin_lock_irq(&dev_priv->irq_lock); - for_each_intel_crtc(&dev_priv->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { if (crtc->cpu_fifo_underrun_disabled) continue; - if (HAS_GMCH(dev_priv)) + if (HAS_GMCH(display)) i9xx_check_fifo_underruns(crtc); - else if (DISPLAY_VER(dev_priv) == 7) + else if (DISPLAY_VER(display) == 7) ivb_check_fifo_underruns(crtc); } @@ -455,19 +449,20 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) /** * intel_check_pch_fifo_underruns - check for PCH fifo underruns immediately - * @dev_priv: i915 device instance + * @display: display device instance * * Check for PCH fifo underruns immediately. Useful on CPT/PPT where the shared * error interrupt may have been disabled, and so PCH fifo underruns won't * necessarily raise an interrupt. */ -void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv) +void intel_check_pch_fifo_underruns(struct intel_display *display) { + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc *crtc; spin_lock_irq(&dev_priv->irq_lock); - for_each_intel_crtc(&dev_priv->drm, crtc) { + for_each_intel_crtc(display->drm, crtc) { if (crtc->pch_fifo_underrun_disabled) continue; @@ -478,10 +473,12 @@ void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv) spin_unlock_irq(&dev_priv->irq_lock); } -void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915, +void intel_init_fifo_underrun_reporting(struct intel_display *display, struct intel_crtc *crtc, bool enable) { + struct drm_i915_private *i915 = to_i915(display->drm); + crtc->cpu_fifo_underrun_disabled = !enable; /* diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h index b00d8abebcf9..ebecc4347cfb 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.h +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.h @@ -8,22 +8,22 @@ #include <linux/types.h> -struct drm_i915_private; -struct intel_crtc; enum pipe; +struct intel_crtc; +struct intel_display; -void intel_init_fifo_underrun_reporting(struct drm_i915_private *i915, +void intel_init_fifo_underrun_reporting(struct intel_display *display, struct intel_crtc *crtc, bool enable); -bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv, +bool intel_set_cpu_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable); -bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv, +bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display, enum pipe pch_transcoder, bool enable); -void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, +void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display, enum pipe pipe); -void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, +void intel_pch_fifo_underrun_irq_handler(struct intel_display *display, enum pipe pch_transcoder); -void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv); -void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv); +void intel_check_cpu_fifo_underruns(struct intel_display *display); +void intel_check_pch_fifo_underruns(struct intel_display *display); #endif /* __INTEL_FIFO_UNDERRUN_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c index 6ed5f726ee60..ba2f88ca6117 100644 --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c @@ -59,6 +59,7 @@ #include "i915_active.h" #include "i915_drv.h" +#include "i915_vma.h" #include "intel_bo.h" #include "intel_display_trace.h" #include "intel_display_types.h" @@ -98,10 +99,10 @@ static void frontbuffer_flush(struct drm_i915_private *i915, trace_intel_frontbuffer_flush(display, frontbuffer_bits, origin); might_sleep(); - intel_td_flush(i915); - intel_drrs_flush(i915, frontbuffer_bits); + intel_td_flush(display); + intel_drrs_flush(display, frontbuffer_bits); intel_psr_flush(display, frontbuffer_bits, origin); - intel_fbc_flush(i915, frontbuffer_bits, origin); + intel_fbc_flush(display, frontbuffer_bits, origin); } /** @@ -176,7 +177,6 @@ void __intel_fb_invalidate(struct intel_frontbuffer *front, unsigned int frontbuffer_bits) { struct intel_display *display = to_intel_display(front->obj->dev); - struct drm_i915_private *i915 = to_i915(display->drm); if (origin == ORIGIN_CS) { spin_lock(&display->fb_tracking.lock); @@ -189,8 +189,8 @@ void __intel_fb_invalidate(struct intel_frontbuffer *front, might_sleep(); intel_psr_invalidate(display, frontbuffer_bits, origin); - intel_drrs_invalidate(i915, frontbuffer_bits); - intel_fbc_invalidate(i915, frontbuffer_bits, origin); + intel_drrs_invalidate(display, frontbuffer_bits); + intel_fbc_invalidate(display, frontbuffer_bits, origin); } void __intel_fb_flush(struct intel_frontbuffer *front, @@ -227,7 +227,7 @@ static void intel_frontbuffer_flush_work(struct work_struct *work) * @front: GEM object to flush * * This function is targeted for our dirty callback for queueing flush when - * dma fence is signales + * dma fence is signals */ void intel_frontbuffer_queue_flush(struct intel_frontbuffer *front) { diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index 807cf606e7a8..abf457e68ee9 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -761,11 +761,10 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) { struct intel_gmbus *bus = to_intel_gmbus(adapter); struct intel_display *display = bus->display; - struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref; int ret; - wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); + wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); if (bus->force_bit) { ret = i2c_bit_algo.master_xfer(adapter, msgs, num); @@ -777,7 +776,7 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) bus->force_bit |= GMBUS_FORCE_BIT_RETRY; } - intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); + intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); return ret; } @@ -786,7 +785,6 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter) { struct intel_gmbus *bus = to_intel_gmbus(adapter); struct intel_display *display = bus->display; - struct drm_i915_private *i915 = to_i915(display->drm); u8 cmd = DRM_HDCP_DDC_AKSV; u8 buf[DRM_HDCP_KSV_LEN] = {}; struct i2c_msg msgs[] = { @@ -806,7 +804,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter) intel_wakeref_t wakeref; int ret; - wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); + wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); mutex_lock(&display->gmbus.mutex); /* @@ -817,7 +815,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter) ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); mutex_unlock(&display->gmbus.mutex); - intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); + intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 7464b44c8bb3..1bf424a822f3 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -9,6 +9,7 @@ */ #include <linux/component.h> +#include <linux/debugfs.h> #include <linux/i2c.h> #include <linux/random.h> @@ -41,7 +42,7 @@ intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder, u32 rekey_bit = 0; /* Here we assume HDMI is in TMDS mode of operation */ - if (encoder->type != INTEL_OUTPUT_HDMI) + if (!intel_encoder_is_hdmi(encoder)) return; if (DISPLAY_VER(display) >= 30) { @@ -69,13 +70,13 @@ static int intel_conn_to_vcpi(struct intel_atomic_state *state, int vcpi = 0; /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ - if (!connector->port) + if (!connector->mst.port) return 0; - mgr = connector->port->mgr; + mgr = connector->mst.port->mgr; drm_modeset_lock(&mgr->base.lock, state->base.acquire_ctx); mst_state = to_drm_dp_mst_topology_state(mgr->base.state); - payload = drm_atomic_get_mst_payload_state(mst_state, connector->port); + payload = drm_atomic_get_mst_payload_state(mst_state, connector->mst.port); if (drm_WARN_ON(mgr->dev, !payload)) goto out; @@ -106,16 +107,16 @@ intel_hdcp_required_content_stream(struct intel_atomic_state *state, struct drm_connector_list_iter conn_iter; struct intel_digital_port *conn_dig_port; struct intel_connector *connector; - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; bool enforce_type0 = false; int k; - if (dig_port->hdcp_auth_status) + if (dig_port->hdcp.auth_status) return 0; data->k = 0; - if (!dig_port->hdcp_mst_type1_capable) + if (!dig_port->hdcp.mst_type1_capable) enforce_type0 = true; drm_connector_list_iter_begin(display->drm, &conn_iter); @@ -135,7 +136,7 @@ intel_hdcp_required_content_stream(struct intel_atomic_state *state, data->k++; /* if there is only one active stream */ - if (dig_port->dp.active_mst_links <= 1) + if (dig_port->dp.mst.active_links <= 1) break; } drm_connector_list_iter_end(&conn_iter); @@ -158,7 +159,7 @@ static int intel_hdcp_prepare_streams(struct intel_atomic_state *state, struct intel_connector *connector) { struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct intel_hdcp *hdcp = &connector->hdcp; if (intel_encoder_is_mst(intel_attached_encoder(connector))) @@ -208,7 +209,7 @@ int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, } /* Is HDCP1.4 capable on Platform and Sink */ -bool intel_hdcp_get_capability(struct intel_connector *connector) +static bool intel_hdcp_get_capability(struct intel_connector *connector) { struct intel_digital_port *dig_port; const struct intel_hdcp_shim *shim = connector->hdcp.shim; @@ -264,7 +265,7 @@ static bool intel_hdcp2_prerequisite(struct intel_connector *connector) } /* Is HDCP2.2 capable on Platform and Sink */ -bool intel_hdcp2_get_capability(struct intel_connector *connector) +static bool intel_hdcp2_get_capability(struct intel_connector *connector) { struct intel_hdcp *hdcp = &connector->hdcp; bool capable = false; @@ -278,9 +279,9 @@ bool intel_hdcp2_get_capability(struct intel_connector *connector) return capable; } -void intel_hdcp_get_remote_capability(struct intel_connector *connector, - bool *hdcp_capable, - bool *hdcp2_capable) +static void intel_hdcp_get_remote_capability(struct intel_connector *connector, + bool *hdcp_capable, + bool *hdcp2_capable) { struct intel_hdcp *hdcp = &connector->hdcp; @@ -342,7 +343,7 @@ static bool hdcp_key_loadable(struct intel_display *display) * On HSW and BDW, Display HW loads the Key as soon as Display resumes. * On all BXT+, SW can load the keys only when the PW#1 is turned on. */ - if (IS_HASWELL(i915) || IS_BROADWELL(i915)) + if (display->platform.haswell || display->platform.broadwell) id = HSW_DISP_PW_GLOBAL; else id = SKL_DISP_PW_1; @@ -353,7 +354,7 @@ static bool hdcp_key_loadable(struct intel_display *display) /* * Another req for hdcp key loadability is enabled state of pll for - * cdclk. Without active crtc we wont land here. So we are assuming that + * cdclk. Without active crtc we won't land here. So we are assuming that * cdclk is already on. */ @@ -381,7 +382,7 @@ static int intel_hdcp_load_keys(struct intel_display *display) * On HSW and BDW HW loads the HDCP1.4 Key when Display comes * out of reset. So if Key is not already loaded, its an error state. */ - if (IS_HASWELL(i915) || IS_BROADWELL(i915)) + if (display->platform.haswell || display->platform.broadwell) if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) return -ENXIO; @@ -393,7 +394,7 @@ static int intel_hdcp_load_keys(struct intel_display *display) * process from other platforms. These platforms use the GT Driver * Mailbox interface. */ - if (DISPLAY_VER(display) == 9 && !IS_BROXTON(i915)) { + if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { ret = snb_pcode_write(&i915->uncore, SKL_PCODE_LOAD_HDCP_KEYS, 1); if (ret) { drm_err(display->drm, @@ -1000,7 +1001,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector) * don't disable it until it disabled HDCP encryption for * all connectors in MST topology. */ - if (dig_port->num_hdcp_streams > 0) + if (dig_port->hdcp.num_streams > 0) return 0; } @@ -1093,13 +1094,13 @@ static void intel_hdcp_update_value(struct intel_connector *connector, if (hdcp->value == value) return; - drm_WARN_ON(display->drm, !mutex_is_locked(&dig_port->hdcp_mutex)); + drm_WARN_ON(display->drm, !mutex_is_locked(&dig_port->hdcp.mutex)); if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { - if (!drm_WARN_ON(display->drm, dig_port->num_hdcp_streams == 0)) - dig_port->num_hdcp_streams--; + if (!drm_WARN_ON(display->drm, dig_port->hdcp.num_streams == 0)) + dig_port->hdcp.num_streams--; } else if (value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { - dig_port->num_hdcp_streams++; + dig_port->hdcp.num_streams++; } hdcp->value = value; @@ -1121,7 +1122,7 @@ static int intel_hdcp_check_link(struct intel_connector *connector) int ret = 0; mutex_lock(&hdcp->mutex); - mutex_lock(&dig_port->hdcp_mutex); + mutex_lock(&dig_port->hdcp.mutex); cpu_transcoder = hdcp->cpu_transcoder; @@ -1176,7 +1177,7 @@ static int intel_hdcp_check_link(struct intel_connector *connector) } out: - mutex_unlock(&dig_port->hdcp_mutex); + mutex_unlock(&dig_port->hdcp.mutex); mutex_unlock(&hdcp->mutex); return ret; } @@ -1218,7 +1219,7 @@ hdcp2_prepare_ake_init(struct intel_connector *connector, { struct intel_display *display = to_intel_display(connector); struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct i915_hdcp_arbiter *arbiter; int ret; @@ -1248,7 +1249,7 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, { struct intel_display *display = to_intel_display(connector); struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct i915_hdcp_arbiter *arbiter; int ret; @@ -1276,7 +1277,7 @@ static int hdcp2_verify_hprime(struct intel_connector *connector, { struct intel_display *display = to_intel_display(connector); struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct i915_hdcp_arbiter *arbiter; int ret; @@ -1302,7 +1303,7 @@ hdcp2_store_pairing_info(struct intel_connector *connector, { struct intel_display *display = to_intel_display(connector); struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct i915_hdcp_arbiter *arbiter; int ret; @@ -1329,7 +1330,7 @@ hdcp2_prepare_lc_init(struct intel_connector *connector, { struct intel_display *display = to_intel_display(connector); struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct i915_hdcp_arbiter *arbiter; int ret; @@ -1356,7 +1357,7 @@ hdcp2_verify_lprime(struct intel_connector *connector, { struct intel_display *display = to_intel_display(connector); struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct i915_hdcp_arbiter *arbiter; int ret; @@ -1382,7 +1383,7 @@ static int hdcp2_prepare_skey(struct intel_connector *connector, { struct intel_display *display = to_intel_display(connector); struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct i915_hdcp_arbiter *arbiter; int ret; @@ -1411,7 +1412,7 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, { struct intel_display *display = to_intel_display(connector); struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct i915_hdcp_arbiter *arbiter; int ret; @@ -1441,7 +1442,7 @@ hdcp2_verify_mprime(struct intel_connector *connector, { struct intel_display *display = to_intel_display(connector); struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct i915_hdcp_arbiter *arbiter; int ret; @@ -1465,7 +1466,7 @@ static int hdcp2_authenticate_port(struct intel_connector *connector) { struct intel_display *display = to_intel_display(connector); struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct i915_hdcp_arbiter *arbiter; int ret; @@ -1502,7 +1503,7 @@ static int hdcp2_close_session(struct intel_connector *connector) } ret = arbiter->ops->close_hdcp_session(arbiter->hdcp_dev, - &dig_port->hdcp_port_data); + &dig_port->hdcp.port_data); mutex_unlock(&display->hdcp.hdcp_mutex); return ret; @@ -1550,9 +1551,9 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) * with a 50ms delay if not hdcp2 capable for DP/DPMST encoders * (dock decides to stop advertising hdcp2 capability for some reason). * The reason being that during suspend resume dock usually keeps the - * HDCP2 registers inaccesible causing AUX error. This wouldn't be a + * HDCP2 registers inaccessible causing AUX error. This wouldn't be a * big problem if the userspace just kept retrying with some delay while - * it continues to play low value content but most userpace applications + * it continues to play low value content but most userspace applications * end up throwing an error when it receives one from KMD. This makes * sure we give the dock and the sink devices to complete its power cycle * and then try HDCP authentication. The values of 10 and delay of 50ms @@ -1690,7 +1691,7 @@ static int _hdcp2_propagate_stream_management_info(struct intel_connector *connector) { struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct intel_hdcp *hdcp = &connector->hdcp; union { struct hdcp2_rep_stream_manage stream_manage; @@ -1768,11 +1769,11 @@ int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) * MST topology is not Type 1 capable if it contains a downstream * device that is only HDCP 1.x or Legacy HDCP 2.0/2.1 compliant. */ - dig_port->hdcp_mst_type1_capable = + dig_port->hdcp.mst_type1_capable = !HDCP_2_2_HDCP1_DEVICE_CONNECTED(rx_info[1]) && !HDCP_2_2_HDCP_2_0_REP_CONNECTED(rx_info[1]); - if (!dig_port->hdcp_mst_type1_capable && hdcp->content_type) { + if (!dig_port->hdcp.mst_type1_capable && hdcp->content_type) { drm_dbg_kms(display->drm, "HDCP1.x or 2.0 Legacy Device Downstream\n"); return -EINVAL; @@ -1868,7 +1869,7 @@ static int hdcp2_enable_stream_encryption(struct intel_connector *connector) { struct intel_display *display = to_intel_display(connector); struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct intel_hdcp *hdcp = &connector->hdcp; enum transcoder cpu_transcoder = hdcp->cpu_transcoder; enum port port = dig_port->base.port; @@ -1899,7 +1900,7 @@ link_recover: if (hdcp2_deauthenticate_port(connector) < 0) drm_dbg_kms(display->drm, "Port deauth failed.\n"); - dig_port->hdcp_auth_status = false; + dig_port->hdcp.auth_status = false; data->k = 0; return ret; @@ -1939,7 +1940,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector) port), LINK_ENCRYPTION_STATUS, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); - dig_port->hdcp_auth_status = true; + dig_port->hdcp.auth_status = true; return ret; } @@ -2018,7 +2019,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_atomic_state *state, struct intel_digital_port *dig_port = intel_attached_dig_port(connector); int ret = 0, i, tries = 3; - for (i = 0; i < tries && !dig_port->hdcp_auth_status; i++) { + for (i = 0; i < tries && !dig_port->hdcp.auth_status; i++) { ret = hdcp2_authenticate_sink(connector); if (!ret) { ret = intel_hdcp_prepare_streams(state, connector); @@ -2051,7 +2052,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_atomic_state *state, drm_dbg_kms(display->drm, "Port deauth failed.\n"); } - if (!ret && !dig_port->hdcp_auth_status) { + if (!ret && !dig_port->hdcp.auth_status) { /* * Ensuring the required 200mSec min time interval between * Session Key Exchange and encryption. @@ -2105,7 +2106,7 @@ _intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery { struct intel_display *display = to_intel_display(connector); struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; struct intel_hdcp *hdcp = &connector->hdcp; int ret; @@ -2122,7 +2123,7 @@ _intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n", transcoder_name(hdcp->stream_transcoder)); - if (dig_port->num_hdcp_streams > 0 && !hdcp2_link_recovery) + if (dig_port->hdcp.num_streams > 0 && !hdcp2_link_recovery) return 0; } @@ -2132,7 +2133,7 @@ _intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery drm_dbg_kms(display->drm, "Port deauth failed.\n"); connector->hdcp.hdcp2_encrypted = false; - dig_port->hdcp_auth_status = false; + dig_port->hdcp.auth_status = false; data->k = 0; return ret; @@ -2149,7 +2150,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) int ret = 0; mutex_lock(&hdcp->mutex); - mutex_lock(&dig_port->hdcp_mutex); + mutex_lock(&dig_port->hdcp.mutex); cpu_transcoder = hdcp->cpu_transcoder; /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */ @@ -2188,6 +2189,19 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) drm_dbg_kms(display->drm, "HDCP2.2 Downstream topology change\n"); + + ret = hdcp2_authenticate_repeater_topology(connector); + if (!ret) { + intel_hdcp_update_value(connector, + DRM_MODE_CONTENT_PROTECTION_ENABLED, + true); + goto out; + } + + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] Repeater topology auth failed.(%d)\n", + connector->base.base.id, connector->base.name, + ret); } else { drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n", @@ -2207,7 +2221,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) intel_hdcp_update_value(connector, DRM_MODE_CONTENT_PROTECTION_DESIRED, true); out: - mutex_unlock(&dig_port->hdcp_mutex); + mutex_unlock(&dig_port->hdcp.mutex); mutex_unlock(&hdcp->mutex); return ret; } @@ -2289,7 +2303,7 @@ static int initialize_hdcp_port_data(struct intel_connector *connector, const struct intel_hdcp_shim *shim) { struct intel_display *display = to_intel_display(connector); - struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct hdcp_port_data *data = &dig_port->hdcp.port_data; enum port port = dig_port->base.port; if (DISPLAY_VER(display) < 12) @@ -2325,18 +2339,16 @@ static int initialize_hdcp_port_data(struct intel_connector *connector, static bool is_hdcp2_supported(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (intel_hdcp_gsc_cs_required(display)) return true; if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) return false; - return (DISPLAY_VER(display) >= 10 || - IS_KABYLAKE(i915) || - IS_COFFEELAKE(i915) || - IS_COMETLAKE(i915)); + return DISPLAY_VER(display) >= 10 || + display->platform.kabylake || + display->platform.coffeelake || + display->platform.cometlake; } void intel_hdcp_component_init(struct intel_display *display) @@ -2402,7 +2414,7 @@ int intel_hdcp_init(struct intel_connector *connector, hdcp->hdcp2_supported); if (ret) { hdcp->hdcp2_supported = false; - kfree(dig_port->hdcp_port_data.streams); + kfree(dig_port->hdcp.port_data.streams); return ret; } @@ -2439,7 +2451,7 @@ static int _intel_hdcp_enable(struct intel_atomic_state *state, } mutex_lock(&hdcp->mutex); - mutex_lock(&dig_port->hdcp_mutex); + mutex_lock(&dig_port->hdcp.mutex); drm_WARN_ON(display->drm, hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); hdcp->content_type = (u8)conn_state->hdcp_content_type; @@ -2453,20 +2465,23 @@ static int _intel_hdcp_enable(struct intel_atomic_state *state, } if (DISPLAY_VER(display) >= 12) - dig_port->hdcp_port_data.hdcp_transcoder = + dig_port->hdcp.port_data.hdcp_transcoder = intel_get_hdcp_transcoder(hdcp->cpu_transcoder); /* * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup * is capable of HDCP2.2, it is preferred to use HDCP2.2. */ - if (intel_hdcp2_get_capability(connector)) { + if (!hdcp->force_hdcp14 && intel_hdcp2_get_capability(connector)) { ret = _intel_hdcp2_enable(state, connector); if (!ret) check_link_interval = DRM_HDCP2_CHECK_PERIOD_MS; } + if (hdcp->force_hdcp14) + drm_dbg_kms(display->drm, "Forcing HDCP 1.4\n"); + /* * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will * be attempted. @@ -2484,7 +2499,7 @@ static int _intel_hdcp_enable(struct intel_atomic_state *state, true); } - mutex_unlock(&dig_port->hdcp_mutex); + mutex_unlock(&dig_port->hdcp.mutex); mutex_unlock(&hdcp->mutex); return ret; } @@ -2520,7 +2535,7 @@ int intel_hdcp_disable(struct intel_connector *connector) return -ENOENT; mutex_lock(&hdcp->mutex); - mutex_lock(&dig_port->hdcp_mutex); + mutex_lock(&dig_port->hdcp.mutex); if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) goto out; @@ -2533,7 +2548,7 @@ int intel_hdcp_disable(struct intel_connector *connector) ret = _intel_hdcp_disable(connector); out: - mutex_unlock(&dig_port->hdcp_mutex); + mutex_unlock(&dig_port->hdcp.mutex); mutex_unlock(&hdcp->mutex); cancel_delayed_work_sync(&hdcp->check_work); return ret; @@ -2560,7 +2575,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state, /* * During the HDCP encryption session if Type change is requested, - * disable the HDCP and reenable it with new TYPE value. + * disable the HDCP and re-enable it with new TYPE value. */ if (conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED || @@ -2603,6 +2618,15 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state, _intel_hdcp_enable(state, encoder, crtc_state, conn_state); } +void intel_hdcp_cancel_works(struct intel_connector *connector) +{ + if (!connector->hdcp.shim) + return; + + cancel_delayed_work_sync(&connector->hdcp.check_work); + cancel_work_sync(&connector->hdcp.prop_work); +} + void intel_hdcp_component_fini(struct intel_display *display) { mutex_lock(&display->hdcp.hdcp_mutex); @@ -2718,3 +2742,153 @@ void intel_hdcp_handle_cp_irq(struct intel_connector *connector) queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 0); } + +static void __intel_hdcp_info(struct seq_file *m, struct intel_connector *connector, + bool remote_req) +{ + bool hdcp_cap = false, hdcp2_cap = false; + + if (!connector->hdcp.shim) { + seq_puts(m, "No Connector Support"); + goto out; + } + + if (remote_req) { + intel_hdcp_get_remote_capability(connector, &hdcp_cap, &hdcp2_cap); + } else { + hdcp_cap = intel_hdcp_get_capability(connector); + hdcp2_cap = intel_hdcp2_get_capability(connector); + } + + if (hdcp_cap) + seq_puts(m, "HDCP1.4 "); + if (hdcp2_cap) + seq_puts(m, "HDCP2.2 "); + + if (!hdcp_cap && !hdcp2_cap) + seq_puts(m, "None"); + +out: + seq_puts(m, "\n"); +} + +void intel_hdcp_info(struct seq_file *m, struct intel_connector *connector) +{ + seq_puts(m, "\tHDCP version: "); + if (connector->mst.dp) { + __intel_hdcp_info(m, connector, true); + seq_puts(m, "\tMST Hub HDCP version: "); + } + __intel_hdcp_info(m, connector, false); +} + +static int intel_hdcp_sink_capability_show(struct seq_file *m, void *data) +{ + struct intel_connector *connector = m->private; + struct intel_display *display = to_intel_display(connector); + int ret; + + ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); + if (ret) + return ret; + + if (!connector->base.encoder || + connector->base.status != connector_status_connected) { + ret = -ENODEV; + goto out; + } + + seq_printf(m, "%s:%d HDCP version: ", connector->base.name, + connector->base.base.id); + __intel_hdcp_info(m, connector, false); + +out: + drm_modeset_unlock(&display->drm->mode_config.connection_mutex); + + return ret; +} +DEFINE_SHOW_ATTRIBUTE(intel_hdcp_sink_capability); + +static ssize_t intel_hdcp_force_14_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct intel_connector *connector = m->private; + struct intel_hdcp *hdcp = &connector->hdcp; + bool force_hdcp14 = false; + int ret; + + if (len == 0) + return 0; + + ret = kstrtobool_from_user(ubuf, len, &force_hdcp14); + if (ret < 0) + return ret; + + hdcp->force_hdcp14 = force_hdcp14; + *offp += len; + + return len; +} + +static int intel_hdcp_force_14_show(struct seq_file *m, void *data) +{ + struct intel_connector *connector = m->private; + struct intel_display *display = to_intel_display(connector); + struct intel_encoder *encoder = intel_attached_encoder(connector); + struct intel_hdcp *hdcp = &connector->hdcp; + struct drm_crtc *crtc; + int ret; + + if (!encoder) + return -ENODEV; + + ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); + if (ret) + return ret; + + crtc = connector->base.state->crtc; + if (connector->base.status != connector_status_connected || !crtc) { + ret = -ENODEV; + goto out; + } + + seq_printf(m, "%s\n", + str_yes_no(hdcp->force_hdcp14)); +out: + drm_modeset_unlock(&display->drm->mode_config.connection_mutex); + + return ret; +} + +static int intel_hdcp_force_14_open(struct inode *inode, + struct file *file) +{ + return single_open(file, intel_hdcp_force_14_show, + inode->i_private); +} + +static const struct file_operations intel_hdcp_force_14_fops = { + .owner = THIS_MODULE, + .open = intel_hdcp_force_14_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = intel_hdcp_force_14_write +}; + +void intel_hdcp_connector_debugfs_add(struct intel_connector *connector) +{ + struct dentry *root = connector->base.debugfs_entry; + int connector_type = connector->base.connector_type; + + if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || + connector_type == DRM_MODE_CONNECTOR_HDMIA || + connector_type == DRM_MODE_CONNECTOR_HDMIB) { + debugfs_create_file("i915_hdcp_sink_capability", 0444, root, + connector, &intel_hdcp_sink_capability_fops); + debugfs_create_file("i915_force_hdcp14", 0644, root, + connector, &intel_hdcp_force_14_fops); + } +} diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h index d99830cfb798..efe86808e17e 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.h +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h @@ -19,8 +19,8 @@ struct intel_digital_port; struct intel_display; struct intel_encoder; struct intel_hdcp_shim; +struct seq_file; enum port; -enum transcoder; void intel_hdcp_atomic_check(struct drm_connector *connector, struct drm_connector_state *old_state, @@ -33,19 +33,18 @@ void intel_hdcp_enable(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state); int intel_hdcp_disable(struct intel_connector *connector); +void intel_hdcp_cancel_works(struct intel_connector *connector); void intel_hdcp_update_pipe(struct intel_atomic_state *state, struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); bool is_hdcp_supported(struct intel_display *display, enum port port); -bool intel_hdcp_get_capability(struct intel_connector *connector); -bool intel_hdcp2_get_capability(struct intel_connector *connector); -void intel_hdcp_get_remote_capability(struct intel_connector *connector, - bool *hdcp_capable, - bool *hdcp2_capable); void intel_hdcp_component_init(struct intel_display *display); void intel_hdcp_component_fini(struct intel_display *display); void intel_hdcp_cleanup(struct intel_connector *connector); void intel_hdcp_handle_cp_irq(struct intel_connector *connector); +void intel_hdcp_info(struct seq_file *m, struct intel_connector *connector); +void intel_hdcp_connector_debugfs_add(struct intel_connector *connector); + #endif /* __INTEL_HDCP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index ed29dd0ccef0..33b8d5229db0 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1909,18 +1909,6 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800) return MODE_CLOCK_RANGE; - /* - * SNPS PHYs' MPLLB table-based programming can only handle a fixed - * set of link rates. - * - * FIXME: We will hopefully get an algorithmic way of programming - * the MPLLB for HDMI in the future. - */ - if (DISPLAY_VER(display) >= 14) - return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock); - else if (IS_DG2(dev_priv)) - return intel_snps_phy_check_hdmi_link_rate(clock); - return MODE_OK; } @@ -2023,11 +2011,10 @@ intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, static enum drm_mode_status intel_hdmi_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { struct intel_display *display = to_intel_display(connector->dev); struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); - struct drm_i915_private *dev_priv = to_i915(display->drm); enum drm_mode_status status; int clock = mode->clock; int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; @@ -2035,7 +2022,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector, bool ycbcr_420_only; enum intel_output_format sink_format; - status = intel_cpu_transcoder_mode_valid(dev_priv, mode); + status = intel_cpu_transcoder_mode_valid(display, mode); if (status != MODE_OK) return status; @@ -2080,7 +2067,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector, return status; } - return intel_mode_valid_max_plane_size(dev_priv, mode, 1); + return intel_mode_valid_max_plane_size(display, mode, 1); } bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, @@ -2373,7 +2360,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, } if (intel_hdmi_is_ycbcr420(pipe_config)) { - ret = intel_panel_fitting(pipe_config, conn_state); + ret = intel_pfit_compute_config(pipe_config, conn_state); if (ret) return ret; } @@ -2503,14 +2490,13 @@ static bool intel_hdmi_set_edid(struct drm_connector *connector) { struct intel_display *display = to_intel_display(connector->dev); - struct drm_i915_private *dev_priv = to_i915(connector->dev); struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); struct i2c_adapter *ddc = connector->ddc; intel_wakeref_t wakeref; const struct drm_edid *drm_edid; bool connected = false; - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); + wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); drm_edid = drm_edid_read_ddc(connector, ddc); @@ -2533,7 +2519,7 @@ intel_hdmi_set_edid(struct drm_connector *connector) connected = true; } - intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); + intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, connector->display_info.source_physical_address); @@ -2546,7 +2532,6 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) { struct intel_display *display = to_intel_display(connector->dev); enum drm_connector_status status = connector_status_disconnected; - struct drm_i915_private *dev_priv = to_i915(connector->dev); struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; intel_wakeref_t wakeref; @@ -2560,7 +2545,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) if (!intel_display_driver_check_access(display)) return connector->status; - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); + wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); if (DISPLAY_VER(display) >= 11 && !intel_digital_port_connected(encoder)) @@ -2572,7 +2557,7 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) status = connector_status_connected; out: - intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); + intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); if (status != connector_status_connected) cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h index 38deaeb302a2..dec2ad7dd8a2 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.h +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h @@ -14,7 +14,6 @@ enum port; struct drm_connector; struct drm_connector_state; struct drm_encoder; -struct drm_i915_private; struct intel_connector; struct intel_crtc_state; struct intel_digital_port; @@ -62,4 +61,13 @@ int intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, int hdmi_max_slices, int hdmi_throughput); int intel_hdmi_dsc_get_slice_height(int vactive); +void hsw_write_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + const void *frame, ssize_t len); +void hsw_read_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + void *frame, ssize_t len); + #endif /* __INTEL_HDMI_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index 3adc791d3776..00d7b1ccf190 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -28,8 +28,10 @@ #include "i915_drv.h" #include "i915_irq.h" +#include "intel_connector.h" #include "intel_display_power.h" #include "intel_display_types.h" +#include "intel_hdcp.h" #include "intel_hotplug.h" #include "intel_hotplug_irq.h" @@ -82,15 +84,13 @@ /** * intel_hpd_pin_default - return default pin associated with certain port. - * @dev_priv: private driver data pointer * @port: the hpd port to get associated pin * * It is only valid and used by digital port encoder. * * Return pin that is associatade with @port. */ -enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, - enum port port) +enum hpd_pin intel_hpd_pin_default(enum port port) { return HPD_PORT_A + port - PORT_A; } @@ -732,6 +732,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work) struct drm_i915_private *dev_priv = container_of(work, struct drm_i915_private, display.hotplug.poll_init_work); + struct intel_display *display = &dev_priv->display; struct drm_connector_list_iter conn_iter; struct intel_connector *connector; intel_wakeref_t wakeref; @@ -747,7 +748,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work) * and so risk an endless loop of this same sequence. */ if (!enabled) { - wakeref = intel_display_power_get(dev_priv, + wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); drm_WARN_ON(&dev_priv->drm, READ_ONCE(dev_priv->display.hotplug.poll_enabled)); @@ -789,7 +790,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work) if (!enabled) { i915_hpd_poll_detect_connectors(dev_priv); - intel_display_power_put(dev_priv, + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); } @@ -806,7 +807,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work) * of the powerwells. * * Since this function can get called in contexts where we're already holding - * dev->mode_config.mutex, we do the actual hotplug enabling in a seperate + * dev->mode_config.mutex, we do the actual hotplug enabling in a separate * worker. * * Also see: intel_hpd_init() and intel_hpd_poll_disable(). @@ -823,7 +824,7 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv) /* * We might already be holding dev->mode_config.mutex, so do this in a - * seperate worker + * separate worker * As well, there's no issue if we race here since we always reschedule * this worker anyway */ @@ -844,7 +845,7 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv) * of the powerwells. * * Since this function can get called in contexts where we're already holding - * dev->mode_config.mutex, we do the actual hotplug enabling in a seperate + * dev->mode_config.mutex, we do the actual hotplug enabling in a separate * worker. * * Also used during driver init to initialize connector->polled @@ -865,6 +866,20 @@ void intel_hpd_poll_disable(struct drm_i915_private *dev_priv) spin_unlock_irq(&dev_priv->irq_lock); } +void intel_hpd_poll_fini(struct drm_i915_private *i915) +{ + struct intel_connector *connector; + struct drm_connector_list_iter conn_iter; + + /* Kill all the work that may have been queued by hpd. */ + drm_connector_list_iter_begin(&i915->drm, &conn_iter); + for_each_intel_connector_iter(connector, &conn_iter) { + intel_connector_cancel_modeset_retry_work(connector); + intel_hdcp_cancel_works(connector); + } + drm_connector_list_iter_end(&conn_iter); +} + void intel_hpd_init_early(struct drm_i915_private *i915) { INIT_DELAYED_WORK(&i915->display.hotplug.hotplug_work, diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h b/drivers/gpu/drm/i915/display/intel_hotplug.h index a17253ddec83..d6986902b054 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.h +++ b/drivers/gpu/drm/i915/display/intel_hotplug.h @@ -16,6 +16,7 @@ enum port; void intel_hpd_poll_enable(struct drm_i915_private *dev_priv); void intel_hpd_poll_disable(struct drm_i915_private *dev_priv); +void intel_hpd_poll_fini(struct drm_i915_private *i915); enum intel_hotplug_state intel_encoder_hotplug(struct intel_encoder *encoder, struct intel_connector *connector); void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, @@ -24,8 +25,7 @@ void intel_hpd_trigger_irq(struct intel_digital_port *dig_port); void intel_hpd_init(struct drm_i915_private *dev_priv); void intel_hpd_init_early(struct drm_i915_private *i915); void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); -enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, - enum port port); +enum hpd_pin intel_hpd_pin_default(enum port port); bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); void intel_hpd_debugfs_register(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c index 476ac88087e0..2137ac7b882a 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c @@ -197,7 +197,7 @@ void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, * @bits: bits to enable * NOTE: the HPD enable bits are modified both inside and outside * of an interrupt context. To avoid that read-modify-write cycles - * interfer, these bits are protected by a spinlock. Since this + * interfere, these bits are protected by a spinlock. Since this * function is usually not called from a context where the lock is * held already, this function acquires the lock itself. A non-locking * version is also available. diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.c b/drivers/gpu/drm/i915/display/intel_link_bw.c index 29705c159119..a10cd3992607 100644 --- a/drivers/gpu/drm/i915/display/intel_link_bw.c +++ b/drivers/gpu/drm/i915/display/intel_link_bw.c @@ -4,6 +4,7 @@ */ #include <drm/drm_fixed.h> +#include <drm/drm_print.h> #include "intel_atomic.h" #include "intel_crtc.h" @@ -221,7 +222,7 @@ assert_link_limit_change_valid(struct intel_display *display, * limits in @new_limits if there is a BW limitation. * * Returns: - * - 0 if the confugration is valid + * - 0 if the configuration is valid * - %-EAGAIN, if the configuration is invalid and @new_limits got updated * with fallback values with which the configuration of all CRTCs * in @state must be recomputed diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c index f11626176fe2..59551c8414c2 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c @@ -77,12 +77,12 @@ #include "intel_lpe_audio.h" #include "intel_pci_config.h" -#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display.audio.lpe.platdev != NULL) +#define HAS_LPE_AUDIO(display) ((display)->audio.lpe.platdev) static struct platform_device * -lpe_audio_platdev_create(struct drm_i915_private *dev_priv) +lpe_audio_platdev_create(struct intel_display *display) { - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); struct platform_device_info pinfo = {}; struct resource *rsc; struct platform_device *platdev; @@ -98,7 +98,8 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv) return ERR_PTR(-ENOMEM); } - rsc[0].start = rsc[0].end = dev_priv->display.audio.lpe.irq; + rsc[0].start = display->audio.lpe.irq; + rsc[0].end = display->audio.lpe.irq; rsc[0].flags = IORESOURCE_IRQ; rsc[0].name = "hdmi-lpe-audio-irq"; @@ -109,7 +110,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv) rsc[1].flags = IORESOURCE_MEM; rsc[1].name = "hdmi-lpe-audio-mmio"; - pinfo.parent = dev_priv->drm.dev; + pinfo.parent = display->drm->dev; pinfo.name = "hdmi-lpe-audio"; pinfo.id = -1; pinfo.res = rsc; @@ -118,8 +119,8 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv) pinfo.size_data = sizeof(*pdata); pinfo.dma_mask = DMA_BIT_MASK(32); - pdata->num_pipes = INTEL_NUM_PIPES(dev_priv); - pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */ + pdata->num_pipes = INTEL_NUM_PIPES(display); + pdata->num_ports = display->platform.cherryview ? 3 : 2; /* B,C,D or B,C */ pdata->port[0].pipe = -1; pdata->port[1].pipe = -1; pdata->port[2].pipe = -1; @@ -130,7 +131,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv) kfree(pdata); if (IS_ERR(platdev)) { - drm_err(&dev_priv->drm, + drm_err(display->drm, "Failed to allocate LPE audio platform device\n"); return platdev; } @@ -140,7 +141,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv) return platdev; } -static void lpe_audio_platdev_destroy(struct drm_i915_private *dev_priv) +static void lpe_audio_platdev_destroy(struct intel_display *display) { /* XXX Note that platform_device_register_full() allocates a dma_mask * and never frees it. We can't free it here as we cannot guarantee @@ -150,7 +151,7 @@ static void lpe_audio_platdev_destroy(struct drm_i915_private *dev_priv) * than us fiddle with its internals. */ - platform_device_unregister(dev_priv->display.audio.lpe.platdev); + platform_device_unregister(display->audio.lpe.platdev); } static void lpe_audio_irq_unmask(struct irq_data *d) @@ -167,11 +168,12 @@ static struct irq_chip lpe_audio_irqchip = { .irq_unmask = lpe_audio_irq_unmask, }; -static int lpe_audio_irq_init(struct drm_i915_private *dev_priv) +static int lpe_audio_irq_init(struct intel_display *display) { - int irq = dev_priv->display.audio.lpe.irq; + struct drm_i915_private *dev_priv = to_i915(display->drm); + int irq = display->audio.lpe.irq; - drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); + drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)); irq_set_chip_and_handler_name(irq, &lpe_audio_irqchip, handle_simple_irq, @@ -180,11 +182,11 @@ static int lpe_audio_irq_init(struct drm_i915_private *dev_priv) return irq_set_chip_data(irq, dev_priv); } -static bool lpe_audio_detect(struct drm_i915_private *dev_priv) +static bool lpe_audio_detect(struct intel_display *display) { int lpe_present = false; - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + if (display->platform.valleyview || display->platform.cherryview) { static const struct pci_device_id atom_hdaudio_ids[] = { /* Baytrail */ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f04)}, @@ -194,7 +196,7 @@ static bool lpe_audio_detect(struct drm_i915_private *dev_priv) }; if (!pci_dev_present(atom_hdaudio_ids)) { - drm_info(&dev_priv->drm, + drm_info(display->drm, "HDaudio controller not detected, using LPE audio instead\n"); lpe_present = true; } @@ -202,34 +204,34 @@ static bool lpe_audio_detect(struct drm_i915_private *dev_priv) return lpe_present; } -static int lpe_audio_setup(struct drm_i915_private *dev_priv) +static int lpe_audio_setup(struct intel_display *display) { int ret; - dev_priv->display.audio.lpe.irq = irq_alloc_desc(0); - if (dev_priv->display.audio.lpe.irq < 0) { - drm_err(&dev_priv->drm, "Failed to allocate IRQ desc: %d\n", - dev_priv->display.audio.lpe.irq); - ret = dev_priv->display.audio.lpe.irq; + display->audio.lpe.irq = irq_alloc_desc(0); + if (display->audio.lpe.irq < 0) { + drm_err(display->drm, "Failed to allocate IRQ desc: %d\n", + display->audio.lpe.irq); + ret = display->audio.lpe.irq; goto err; } - drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->display.audio.lpe.irq); + drm_dbg(display->drm, "irq = %d\n", display->audio.lpe.irq); - ret = lpe_audio_irq_init(dev_priv); + ret = lpe_audio_irq_init(display); if (ret) { - drm_err(&dev_priv->drm, + drm_err(display->drm, "Failed to initialize irqchip for lpe audio: %d\n", ret); goto err_free_irq; } - dev_priv->display.audio.lpe.platdev = lpe_audio_platdev_create(dev_priv); + display->audio.lpe.platdev = lpe_audio_platdev_create(display); - if (IS_ERR(dev_priv->display.audio.lpe.platdev)) { - ret = PTR_ERR(dev_priv->display.audio.lpe.platdev); - drm_err(&dev_priv->drm, + if (IS_ERR(display->audio.lpe.platdev)) { + ret = PTR_ERR(display->audio.lpe.platdev); + drm_err(display->drm, "Failed to create lpe audio platform device: %d\n", ret); goto err_free_irq; @@ -238,54 +240,54 @@ static int lpe_audio_setup(struct drm_i915_private *dev_priv) /* enable chicken bit; at least this is required for Dell Wyse 3040 * with DP outputs (but only sometimes by some reason!) */ - intel_de_write(dev_priv, VLV_AUD_CHICKEN_BIT_REG, + intel_de_write(display, VLV_AUD_CHICKEN_BIT_REG, VLV_CHICKEN_BIT_DBG_ENABLE); return 0; err_free_irq: - irq_free_desc(dev_priv->display.audio.lpe.irq); + irq_free_desc(display->audio.lpe.irq); err: - dev_priv->display.audio.lpe.irq = -1; - dev_priv->display.audio.lpe.platdev = NULL; + display->audio.lpe.irq = -1; + display->audio.lpe.platdev = NULL; return ret; } /** * intel_lpe_audio_irq_handler() - forwards the LPE audio irq - * @dev_priv: the i915 drm device private data + * @display: display device * * the LPE Audio irq is forwarded to the irq handler registered by LPE audio * driver. */ -void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv) +void intel_lpe_audio_irq_handler(struct intel_display *display) { int ret; - if (!HAS_LPE_AUDIO(dev_priv)) + if (!HAS_LPE_AUDIO(display)) return; - ret = generic_handle_irq(dev_priv->display.audio.lpe.irq); + ret = generic_handle_irq(display->audio.lpe.irq); if (ret) - drm_err_ratelimited(&dev_priv->drm, + drm_err_ratelimited(display->drm, "error handling LPE audio irq: %d\n", ret); } /** * intel_lpe_audio_init() - detect and setup the bridge between HDMI LPE Audio * driver and i915 - * @dev_priv: the i915 drm device private data + * @display: display device * * Return: 0 if successful. non-zero if detection or * llocation/initialization fails */ -int intel_lpe_audio_init(struct drm_i915_private *dev_priv) +int intel_lpe_audio_init(struct intel_display *display) { int ret = -ENODEV; - if (lpe_audio_detect(dev_priv)) { - ret = lpe_audio_setup(dev_priv); + if (lpe_audio_detect(display)) { + ret = lpe_audio_setup(display); if (ret < 0) - drm_err(&dev_priv->drm, + drm_err(display->drm, "failed to setup LPE Audio bridge\n"); } return ret; @@ -294,27 +296,27 @@ int intel_lpe_audio_init(struct drm_i915_private *dev_priv) /** * intel_lpe_audio_teardown() - destroy the bridge between HDMI LPE * audio driver and i915 - * @dev_priv: the i915 drm device private data + * @display: display device * * release all the resources for LPE audio <-> i915 bridge. */ -void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv) +void intel_lpe_audio_teardown(struct intel_display *display) { - if (!HAS_LPE_AUDIO(dev_priv)) + if (!HAS_LPE_AUDIO(display)) return; - lpe_audio_platdev_destroy(dev_priv); + lpe_audio_platdev_destroy(display); - irq_free_desc(dev_priv->display.audio.lpe.irq); + irq_free_desc(display->audio.lpe.irq); - dev_priv->display.audio.lpe.irq = -1; - dev_priv->display.audio.lpe.platdev = NULL; + display->audio.lpe.irq = -1; + display->audio.lpe.platdev = NULL; } /** * intel_lpe_audio_notify() - notify lpe audio event * audio driver and i915 - * @dev_priv: the i915 drm device private data + * @display: display device * @cpu_transcoder: CPU transcoder * @port: port * @eld : ELD data @@ -323,7 +325,7 @@ void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv) * * Notify lpe audio driver of eld change. */ -void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, +void intel_lpe_audio_notify(struct intel_display *display, enum transcoder cpu_transcoder, enum port port, const void *eld, int ls_clock, bool dp_output) { @@ -332,15 +334,15 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, struct intel_hdmi_lpe_audio_port_pdata *ppdata; u32 audio_enable; - if (!HAS_LPE_AUDIO(dev_priv)) + if (!HAS_LPE_AUDIO(display)) return; - pdata = dev_get_platdata(&dev_priv->display.audio.lpe.platdev->dev); + pdata = dev_get_platdata(&display->audio.lpe.platdev->dev); ppdata = &pdata->port[port - PORT_B]; spin_lock_irqsave(&pdata->lpe_audio_slock, irqflags); - audio_enable = intel_de_read(dev_priv, VLV_AUD_PORT_EN_DBG(port)); + audio_enable = intel_de_read(display, VLV_AUD_PORT_EN_DBG(port)); if (eld != NULL) { memcpy(ppdata->eld, eld, HDMI_MAX_ELD_BYTES); @@ -349,7 +351,7 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, ppdata->dp_output = dp_output; /* Unmute the amp for both DP and HDMI */ - intel_de_write(dev_priv, VLV_AUD_PORT_EN_DBG(port), + intel_de_write(display, VLV_AUD_PORT_EN_DBG(port), audio_enable & ~VLV_AMP_MUTE); } else { memset(ppdata->eld, 0, HDMI_MAX_ELD_BYTES); @@ -358,12 +360,12 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, ppdata->dp_output = false; /* Mute the amp for both DP and HDMI */ - intel_de_write(dev_priv, VLV_AUD_PORT_EN_DBG(port), + intel_de_write(display, VLV_AUD_PORT_EN_DBG(port), audio_enable | VLV_AMP_MUTE); } if (pdata->notify_audio_lpe) - pdata->notify_audio_lpe(dev_priv->display.audio.lpe.platdev, port - PORT_B); + pdata->notify_audio_lpe(display->audio.lpe.platdev, port - PORT_B); spin_unlock_irqrestore(&pdata->lpe_audio_slock, irqflags); } diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.h b/drivers/gpu/drm/i915/display/intel_lpe_audio.h index 2c5fcb6e1fd0..5234e11fd662 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.h +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.h @@ -10,27 +10,27 @@ enum port; enum transcoder; -struct drm_i915_private; +struct intel_display; #ifdef I915 -int intel_lpe_audio_init(struct drm_i915_private *dev_priv); -void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv); -void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv); -void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, +int intel_lpe_audio_init(struct intel_display *display); +void intel_lpe_audio_teardown(struct intel_display *display); +void intel_lpe_audio_irq_handler(struct intel_display *display); +void intel_lpe_audio_notify(struct intel_display *display, enum transcoder cpu_transcoder, enum port port, const void *eld, int ls_clock, bool dp_output); #else -static inline int intel_lpe_audio_init(struct drm_i915_private *dev_priv) +static inline int intel_lpe_audio_init(struct intel_display *display) { return -ENODEV; } -static inline void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv) +static inline void intel_lpe_audio_teardown(struct intel_display *display) { } -static inline void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv) +static inline void intel_lpe_audio_irq_handler(struct intel_display *display) { } -static inline void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, +static inline void intel_lpe_audio_notify(struct intel_display *display, enum transcoder cpu_transcoder, enum port port, const void *eld, int ls_clock, bool dp_output) { diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index d75dd17fad32..63c1afa30b05 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -55,6 +55,11 @@ #define LSPCON_PARADE_AVI_IF_KICKOFF (1 << 7) #define LSPCON_PARADE_AVI_IF_DATA_SIZE 32 +static struct intel_lspcon *enc_to_intel_lspcon(struct intel_encoder *encoder) +{ + return &enc_to_dig_port(encoder)->lspcon; +} + static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon) { struct intel_digital_port *dig_port = @@ -121,8 +126,9 @@ static u32 get_hdr_status_reg(struct intel_lspcon *lspcon) return DPCD_PARADE_LSPCON_HDR_STATUS; } -void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) +bool intel_lspcon_detect_hdr_capability(struct intel_digital_port *dig_port) { + struct intel_lspcon *lspcon = &dig_port->lspcon; struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); struct intel_display *display = to_intel_display(intel_dp); u8 hdr_caps; @@ -138,6 +144,8 @@ void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) drm_dbg_kms(display->drm, "LSPCON capable of HDR\n"); lspcon->hdr_supported = true; } + + return lspcon->hdr_supported; } static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) @@ -212,7 +220,8 @@ static int lspcon_change_mode(struct intel_lspcon *lspcon, return 0; } - err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, ddc, mode); + err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, ddc, mode, + lspcon_get_mode_settle_timeout(lspcon)); if (err < 0) { drm_err(display->drm, "LSPCON mode change failed\n"); return err; @@ -652,12 +661,14 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, return val; } -void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon) +void intel_lspcon_wait_pcon_mode(struct intel_digital_port *dig_port) { + struct intel_lspcon *lspcon = &dig_port->lspcon; + lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON); } -bool lspcon_init(struct intel_digital_port *dig_port) +bool intel_lspcon_init(struct intel_digital_port *dig_port) { struct intel_display *display = to_intel_display(dig_port); struct intel_dp *intel_dp = &dig_port->dp; @@ -688,6 +699,13 @@ bool lspcon_init(struct intel_digital_port *dig_port) return true; } +bool intel_lspcon_active(struct intel_digital_port *dig_port) +{ + struct intel_lspcon *lspcon = &dig_port->lspcon; + + return lspcon->active; +} + u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { @@ -696,7 +714,7 @@ u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder, return dig_port->infoframes_enabled(encoder, pipe_config); } -void lspcon_resume(struct intel_digital_port *dig_port) +void intel_lspcon_resume(struct intel_digital_port *dig_port) { struct intel_display *display = to_intel_display(dig_port); struct intel_lspcon *lspcon = &dig_port->lspcon; @@ -706,7 +724,7 @@ void lspcon_resume(struct intel_digital_port *dig_port) return; if (!lspcon->active) { - if (!lspcon_init(dig_port)) { + if (!intel_lspcon_init(dig_port)) { drm_err(display->drm, "LSPCON init failed on port %c\n", port_name(dig_port->base.port)); return; diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h index e19e10492b05..41d142a5c440 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h @@ -8,17 +8,20 @@ #include <linux/types.h> -struct drm_connector; struct drm_connector_state; struct intel_crtc_state; struct intel_digital_port; struct intel_encoder; -struct intel_lspcon; -bool lspcon_init(struct intel_digital_port *dig_port); -void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon); -void lspcon_resume(struct intel_digital_port *dig_port); -void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon); +bool intel_lspcon_init(struct intel_digital_port *dig_port); +bool intel_lspcon_active(struct intel_digital_port *dig_port); +bool intel_lspcon_detect_hdr_capability(struct intel_digital_port *dig_port); +void intel_lspcon_resume(struct intel_digital_port *dig_port); +void intel_lspcon_wait_pcon_mode(struct intel_digital_port *dig_port); +u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder, + const struct intel_crtc_state *pipe_config); + +/* digital port infoframes hooks */ void lspcon_write_infoframe(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, unsigned int type, @@ -33,15 +36,5 @@ void lspcon_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state); u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config); -u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder, - const struct intel_crtc_state *pipe_config); -void hsw_write_infoframe(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - unsigned int type, - const void *frame, ssize_t len); -void hsw_read_infoframe(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - unsigned int type, - void *frame, ssize_t len); #endif /* __INTEL_LSPCON_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 6ffd55c17445..19f52d1659fa 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -53,6 +53,7 @@ #include "intel_lvds_regs.h" #include "intel_panel.h" #include "intel_pfit.h" +#include "intel_pfit_regs.h" #include "intel_pps_regs.h" /* Private structure for the integrated LVDS support */ @@ -102,18 +103,19 @@ bool intel_lvds_port_enabled(struct drm_i915_private *i915, static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); intel_wakeref_t wakeref; bool ret; - wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain); + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe); - intel_display_power_put(i915, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return ret; } @@ -239,6 +241,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(state); struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -247,10 +250,10 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state, u32 temp; if (HAS_PCH_SPLIT(i915)) { - assert_fdi_rx_pll_disabled(i915, pipe); - assert_shared_dpll_disabled(i915, crtc_state->shared_dpll); + assert_fdi_rx_pll_disabled(display, pipe); + assert_shared_dpll_disabled(display, crtc_state->shared_dpll); } else { - assert_pll_disabled(i915, pipe); + assert_pll_disabled(display, pipe); } intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps); @@ -390,16 +393,16 @@ static void intel_lvds_shutdown(struct intel_encoder *encoder) static enum drm_mode_status intel_lvds_mode_valid(struct drm_connector *_connector, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { + struct intel_display *display = to_intel_display(_connector->dev); struct intel_connector *connector = to_intel_connector(_connector); - struct drm_i915_private *i915 = to_i915(connector->base.dev); const struct drm_display_mode *fixed_mode = intel_panel_fixed_mode(connector, mode); - int max_pixclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq; + int max_pixclk = display->cdclk.max_dotclk_freq; enum drm_mode_status status; - status = intel_cpu_transcoder_mode_valid(i915, mode); + status = intel_cpu_transcoder_mode_valid(display, mode); if (status != MODE_OK) return status; @@ -466,7 +469,7 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder, if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) return -EINVAL; - ret = intel_panel_fitting(crtc_state, conn_state); + ret = intel_pfit_compute_config(crtc_state, conn_state); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 9a2bea19f17b..312b21b1ab59 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -15,6 +15,7 @@ #include "i9xx_wm.h" #include "intel_atomic.h" #include "intel_bw.h" +#include "intel_cmtg.h" #include "intel_color.h" #include "intel_crtc.h" #include "intel_crtc_state_dump.h" @@ -155,12 +156,6 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - struct intel_bw_state *bw_state = - to_intel_bw_state(i915->display.bw.obj.state); - struct intel_cdclk_state *cdclk_state = - to_intel_cdclk_state(i915->display.cdclk.obj.state); - struct intel_dbuf_state *dbuf_state = - to_intel_dbuf_state(i915->display.dbuf.obj.state); struct intel_pmdemand_state *pmdemand_state = to_intel_pmdemand_state(i915->display.pmdemand.obj.state); struct intel_crtc_state *crtc_state = @@ -176,16 +171,11 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc) intel_fbc_disable(crtc); intel_update_watermarks(i915); - intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains); + intel_display_power_put_all_in_set(display, &crtc->enabled_power_domains); - cdclk_state->min_cdclk[pipe] = 0; - cdclk_state->min_voltage_level[pipe] = 0; - cdclk_state->active_pipes &= ~BIT(pipe); - - dbuf_state->active_pipes &= ~BIT(pipe); - - bw_state->data_rate[pipe] = 0; - bw_state->num_active_planes[pipe] = 0; + intel_cdclk_crtc_disable_noatomic(crtc); + skl_wm_crtc_disable_noatomic(crtc); + intel_bw_crtc_disable_noatomic(crtc); intel_pmdemand_update_port_clock(display, pmdemand_state, pipe, 0); } @@ -453,8 +443,8 @@ static struct intel_connector *intel_encoder_find_connector(struct intel_encoder static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); /* * We start out with underrun reporting disabled on active @@ -469,9 +459,9 @@ static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state * No protection against concurrent access is required - at * worst a fifo underrun happens which also sets this to false. */ - intel_init_fifo_underrun_reporting(i915, crtc, + intel_init_fifo_underrun_reporting(display, crtc, !crtc_state->hw.active && - !HAS_GMCH(i915)); + !HAS_GMCH(display)); } static bool intel_sanitize_crtc(struct intel_crtc *crtc, @@ -703,10 +693,6 @@ static void readout_plane_state(struct drm_i915_private *i915) static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) { struct intel_display *display = &i915->display; - struct intel_cdclk_state *cdclk_state = - to_intel_cdclk_state(i915->display.cdclk.obj.state); - struct intel_dbuf_state *dbuf_state = - to_intel_dbuf_state(i915->display.dbuf.obj.state); struct intel_pmdemand_state *pmdemand_state = to_intel_pmdemand_state(i915->display.pmdemand.obj.state); enum pipe pipe; @@ -714,7 +700,6 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) struct intel_encoder *encoder; struct intel_connector *connector; struct drm_connector_list_iter conn_iter; - u8 active_pipes = 0; for_each_intel_crtc(&i915->drm, crtc) { struct intel_crtc_state *crtc_state = @@ -731,18 +716,12 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) crtc->base.enabled = crtc_state->hw.enable; crtc->active = crtc_state->hw.active; - if (crtc_state->hw.active) - active_pipes |= BIT(crtc->pipe); - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] hw state readout: %s\n", crtc->base.base.id, crtc->base.name, str_enabled_disabled(crtc_state->hw.active)); } - cdclk_state->active_pipes = active_pipes; - dbuf_state->active_pipes = active_pipes; - readout_plane_state(i915); for_each_intel_encoder(&i915->drm, encoder) { @@ -794,7 +773,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) pipe_name(pipe)); } - intel_dpll_readout_hw_state(i915); + intel_dpll_readout_hw_state(display); drm_connector_list_iter_begin(&i915->drm, &conn_iter); for_each_intel_connector_iter(connector, &conn_iter) { @@ -838,12 +817,9 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) drm_connector_list_iter_end(&conn_iter); for_each_intel_crtc(&i915->drm, crtc) { - struct intel_bw_state *bw_state = - to_intel_bw_state(i915->display.bw.obj.state); struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_plane *plane; - int min_cdclk = 0; if (crtc_state->hw.active) { /* @@ -892,22 +868,17 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) crtc_state->min_cdclk[plane->id]); } - if (crtc_state->hw.active) { - min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); - if (drm_WARN_ON(&i915->drm, min_cdclk < 0)) - min_cdclk = 0; - } - - cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; - cdclk_state->min_voltage_level[crtc->pipe] = - crtc_state->min_voltage_level; - intel_pmdemand_update_port_clock(display, pmdemand_state, pipe, crtc_state->port_clock); - - intel_bw_crtc_update(bw_state, crtc_state); } + /* TODO move here (or even earlier?) on all platforms */ + if (DISPLAY_VER(display) >= 9) + intel_wm_get_hw_state(i915); + + intel_bw_update_hw_state(display); + intel_cdclk_update_hw_state(display); + intel_pmdemand_init_pmdemand_params(display, pmdemand_state); } @@ -968,7 +939,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915, struct intel_crtc *crtc; intel_wakeref_t wakeref; - wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); + wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); intel_early_display_was(i915); intel_modeset_readout_hw_state(i915); @@ -978,6 +949,8 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915, intel_pch_sanitize(i915); + intel_cmtg_sanitize(display); + /* * intel_sanitize_plane_mapping() may need to do vblank * waits, so we need vblank interrupts restored beforehand. @@ -1011,9 +984,12 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915, intel_sanitize_all_crtcs(i915, ctx); - intel_dpll_sanitize_state(i915); + intel_dpll_sanitize_state(display); - intel_wm_get_hw_state(i915); + /* TODO move earlier on all platforms */ + if (DISPLAY_VER(display) < 9) + intel_wm_get_hw_state(i915); + intel_wm_sanitize(i915); for_each_intel_crtc(&i915->drm, crtc) { struct intel_crtc_state *crtc_state = @@ -1025,7 +1001,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915, intel_modeset_put_crtc_power_domains(crtc, &put_domains); } - intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); + intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); intel_power_domains_sanitize_state(display); } diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index bc70e72ccc2e..a008412fdd04 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -90,10 +90,11 @@ verify_connector_state(struct intel_atomic_state *state, static void intel_pipe_config_sanity_check(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); if (crtc_state->has_pch_encoder) { - int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(i915, crtc_state), + int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state), &crtc_state->fdi_m_n); int dotclock = crtc_state->hw.adjusted_mode.crtc_clock; diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index ca30fff61876..aff9a3455c1b 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -42,11 +42,13 @@ #include "intel_frontbuffer.h" #include "intel_overlay.h" #include "intel_pci_config.h" +#include "intel_pfit_regs.h" /* Limits for overlay size. According to intel doc, the real limits are: * Y width: 4095, UV width (planar): 2047, Y height: 2047, * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use - * the mininum of both. */ + * the minimum of both. + */ #define IMAGE_MAX_WIDTH 2048 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ /* on 830 and 845 these large limits result in the card hanging */ @@ -408,10 +410,12 @@ static int intel_overlay_off(struct intel_overlay *overlay) drm_WARN_ON(display->drm, !overlay->active); - /* According to intel docs the overlay hw may hang (when switching + /* + * According to intel docs the overlay hw may hang (when switching * off) without loading the filter coeffs. It is however unclear whether * this applies to the disabling of the overlay or to the switching off - * of the hw. Do it in both cases */ + * of the hw. Do it in both cases. + */ flip_addr |= OFC_UPDATE; rq = alloc_request(overlay, intel_overlay_off_tail); @@ -442,16 +446,19 @@ static int intel_overlay_off(struct intel_overlay *overlay) return i915_active_wait(&overlay->last_flip); } -/* recover from an interruption due to a signal - * We have to be careful not to repeat work forever an make forward progess. */ +/* + * Recover from an interruption due to a signal. + * We have to be careful not to repeat work forever an make forward progress. + */ static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) { return i915_active_wait(&overlay->last_flip); } -/* Wait for pending overlay flip and release old frame. +/* + * Wait for pending overlay flip and release old frame. * Needs to be called before the overlay register are changed - * via intel_overlay_(un)map_regs + * via intel_overlay_(un)map_regs. */ static int intel_overlay_release_old_vid(struct intel_overlay *overlay) { @@ -772,7 +779,7 @@ static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo) retry: ret = i915_gem_object_lock(new_bo, &ww); if (!ret) { - vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0, + vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0, 0, NULL, PIN_MAPPABLE); ret = PTR_ERR_OR_ZERO(vma); } @@ -793,7 +800,6 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, struct drm_intel_overlay_put_image *params) { struct intel_display *display = overlay->display; - struct drm_i915_private *dev_priv = to_i915(display->drm); struct overlay_registers __iomem *regs = overlay->regs; u32 swidth, swidthsw, sheight, ostride; enum pipe pipe = overlay->crtc->pipe; @@ -808,7 +814,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, if (ret != 0) return ret; - atomic_inc(&dev_priv->gpu_error.pending_fb_pin); + atomic_inc(&display->restore.pending_fb_pin); vma = intel_overlay_pin_fb(new_bo); if (IS_ERR(vma)) { @@ -896,7 +902,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, out_unpin: i915_vma_unpin(vma); out_pin_section: - atomic_dec(&dev_priv->gpu_error.pending_fb_pin); + atomic_dec(&display->restore.pending_fb_pin); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_overlay.h b/drivers/gpu/drm/i915/display/intel_overlay.h index 45a42fce754e..d259e4c74b03 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.h +++ b/drivers/gpu/drm/i915/display/intel_overlay.h @@ -10,7 +10,6 @@ struct drm_device; struct drm_file; -struct drm_i915_private; struct drm_printer; struct intel_display; struct intel_overlay; diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 4e6c5592c7ae..f5c972880391 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -32,6 +32,7 @@ #include <linux/pwm.h> #include <drm/drm_edid.h> +#include <drm/drm_print.h> #include "intel_backlight.h" #include "intel_connector.h" diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 8fa5a6334d10..99f6d6f53fa7 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -45,7 +45,7 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, enum pipe port_pipe; bool state; - state = g4x_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe); + state = g4x_dp_port_enabled(display, dp_reg, port, &port_pipe); INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe, "PCH DP %c enabled on transcoder %c, should be disabled\n", @@ -65,7 +65,7 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, enum pipe port_pipe; bool state; - state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe); + state = intel_sdvo_port_enabled(display, hdmi_reg, &port_pipe); INTEL_DISPLAY_STATE_WARN(display, state && port_pipe == pipe, "PCH HDMI %c enabled on transcoder %c, should be disabled\n", @@ -181,10 +181,10 @@ static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv) static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc, const struct intel_link_m_n *m_n) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - intel_set_m_n(dev_priv, m_n, + intel_set_m_n(display, m_n, PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); } @@ -192,10 +192,10 @@ static void intel_pch_transcoder_set_m1_n1(struct intel_crtc *crtc, static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc, const struct intel_link_m_n *m_n) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - intel_set_m_n(dev_priv, m_n, + intel_set_m_n(display, m_n, PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); } @@ -203,10 +203,10 @@ static void intel_pch_transcoder_set_m2_n2(struct intel_crtc *crtc, void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc, struct intel_link_m_n *m_n) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - intel_get_m_n(dev_priv, m_n, + intel_get_m_n(display, m_n, PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe), PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe)); } @@ -214,10 +214,10 @@ void intel_pch_transcoder_get_m1_n1(struct intel_crtc *crtc, void intel_pch_transcoder_get_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - intel_get_m_n(dev_priv, m_n, + intel_get_m_n(display, m_n, PCH_TRANS_DATA_M2(pipe), PCH_TRANS_DATA_N2(pipe), PCH_TRANS_LINK_M2(pipe), PCH_TRANS_LINK_N2(pipe)); } @@ -249,21 +249,22 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; i915_reg_t reg; u32 val, pipeconf_val; /* Make sure PCH DPLL is enabled */ - assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll); + assert_shared_dpll_enabled(display, crtc_state->shared_dpll); /* FDI must be feeding us bits for PCH ports */ - assert_fdi_tx_enabled(dev_priv, pipe); - assert_fdi_rx_enabled(dev_priv, pipe); + assert_fdi_tx_enabled(display, pipe); + assert_fdi_rx_enabled(display, pipe); if (HAS_PCH_CPT(dev_priv)) { reg = TRANS_CHICKEN2(pipe); - val = intel_de_read(dev_priv, reg); + val = intel_de_read(display, reg); /* * Workaround: Set the timing override bit * before enabling the pch transcoder. @@ -272,12 +273,12 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) /* Configure frame start delay to match the CPU */ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1); - intel_de_write(dev_priv, reg, val); + intel_de_write(display, reg, val); } reg = PCH_TRANSCONF(pipe); - val = intel_de_read(dev_priv, reg); - pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)); + val = intel_de_read(display, reg); + pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe)); if (HAS_PCH_IBX(dev_priv)) { /* Configure frame start delay to match the CPU */ @@ -307,21 +308,22 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) val |= TRANS_INTERLACE_PROGRESSIVE; } - intel_de_write(dev_priv, reg, val | TRANS_ENABLE); - if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100)) - drm_err(&dev_priv->drm, "failed to enable transcoder %c\n", + intel_de_write(display, reg, val | TRANS_ENABLE); + if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100)) + drm_err(display->drm, "failed to enable transcoder %c\n", pipe_name(pipe)); } static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; i915_reg_t reg; /* FDI relies on the transcoder */ - assert_fdi_tx_disabled(dev_priv, pipe); - assert_fdi_rx_disabled(dev_priv, pipe); + assert_fdi_tx_disabled(display, pipe); + assert_fdi_rx_disabled(display, pipe); /* Ports must be off as well */ assert_pch_ports_disabled(dev_priv, pipe); @@ -383,15 +385,15 @@ void ilk_pch_enable(struct intel_atomic_state *state, if (HAS_PCH_CPT(dev_priv)) { u32 sel; - temp = intel_de_read(dev_priv, PCH_DPLL_SEL); + temp = intel_de_read(display, PCH_DPLL_SEL); temp |= TRANS_DPLL_ENABLE(pipe); sel = TRANS_DPLLB_SEL(pipe); if (crtc_state->shared_dpll == - intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) + intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B)) temp |= sel; else temp &= ~sel; - intel_de_write(dev_priv, PCH_DPLL_SEL, temp); + intel_de_write(display, PCH_DPLL_SEL, temp); } /* @@ -420,11 +422,12 @@ void ilk_pch_enable(struct intel_atomic_state *state, intel_crtc_has_dp_encoder(crtc_state)) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5; + u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe)) + & TRANSCONF_BPC_MASK) >> 5; i915_reg_t reg = TRANS_DP_CTL(pipe); enum port port; - temp = intel_de_read(dev_priv, reg); + temp = intel_de_read(display, reg); temp &= ~(TRANS_DP_PORT_SEL_MASK | TRANS_DP_VSYNC_ACTIVE_HIGH | TRANS_DP_HSYNC_ACTIVE_HIGH | @@ -438,10 +441,10 @@ void ilk_pch_enable(struct intel_atomic_state *state, temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; port = intel_get_crtc_new_encoder(state, crtc_state)->port; - drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D); + drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D); temp |= TRANS_DP_PORT_SEL(port); - intel_de_write(dev_priv, reg, temp); + intel_de_write(display, reg, temp); } ilk_enable_pch_transcoder(crtc_state); @@ -477,8 +480,7 @@ void ilk_pch_post_disable(struct intel_atomic_state *state, static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); /* read out port_clock from the DPLL */ i9xx_crtc_clock_get(crtc_state); @@ -489,13 +491,14 @@ static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state) * Calculate one based on the FDI configuration. */ crtc_state->hw.adjusted_mode.crtc_clock = - intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, crtc_state), + intel_dotclock_calculate(intel_fdi_link_freq(display, crtc_state), &crtc_state->fdi_m_n); } void ilk_pch_get_config(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; enum pipe pipe = crtc->pipe; @@ -503,12 +506,12 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) bool pll_active; u32 tmp; - if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0) + if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0) return; crtc_state->has_pch_encoder = true; - tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); + tmp = intel_de_read(display, FDI_RX_CTL(pipe)); crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> FDI_DP_PORT_WIDTH_SHIFT) + 1; @@ -522,19 +525,19 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) */ pll_id = (enum intel_dpll_id) pipe; } else { - tmp = intel_de_read(dev_priv, PCH_DPLL_SEL); + tmp = intel_de_read(display, PCH_DPLL_SEL); if (tmp & TRANS_DPLLB_SEL(pipe)) pll_id = DPLL_ID_PCH_PLL_B; else pll_id = DPLL_ID_PCH_PLL_A; } - crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id); + crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id); pll = crtc_state->shared_dpll; - pll_active = intel_dpll_get_hw_state(dev_priv, pll, + pll_active = intel_dpll_get_hw_state(display, pll, &crtc_state->dpll_hw_state); - drm_WARN_ON(&dev_priv->drm, !pll_active); + drm_WARN_ON(display->drm, !pll_active); tmp = crtc_state->dpll_hw_state.i9xx.dpll; crtc_state->pixel_multiplier = @@ -546,14 +549,15 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state) static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 val, pipeconf_val; /* FDI must be feeding us bits for PCH ports */ - assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); - assert_fdi_rx_enabled(dev_priv, PIPE_A); + assert_fdi_tx_enabled(display, (enum pipe)cpu_transcoder); + assert_fdi_rx_enabled(display, PIPE_A); val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); /* Workaround: set timing override bit. */ diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c index 71471c1d7dc9..33467de3d115 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c @@ -505,7 +505,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) bool using_ssc_source = false; /* We need to take the global config into account */ - for_each_intel_encoder(&dev_priv->drm, encoder) { + for_each_intel_encoder(display->drm, encoder) { switch (encoder->type) { case INTEL_OUTPUT_LVDS: has_panel = true; @@ -522,7 +522,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) } if (HAS_PCH_IBX(dev_priv)) { - has_ck505 = dev_priv->display.vbt.display_clock_mode; + has_ck505 = display->vbt.display_clock_mode; can_ssc = has_ck505; } else { has_ck505 = false; @@ -530,10 +530,10 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) } /* Check if any DPLLs are using the SSC source */ - for_each_shared_dpll(dev_priv, pll, i) { + for_each_shared_dpll(display, pll, i) { u32 temp; - temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id)); + temp = intel_de_read(display, PCH_DPLL(pll->info->id)); if (!(temp & DPLL_VCO_ENABLE)) continue; @@ -545,7 +545,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) } } - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", has_panel, has_lvds, has_ck505, using_ssc_source); @@ -554,7 +554,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) * PCH B stepping, previous chipset stepping should be * ignoring this setting. */ - val = intel_de_read(dev_priv, PCH_DREF_CONTROL); + val = intel_de_read(display, PCH_DREF_CONTROL); /* As we must carefully and slowly disable/enable each source in turn, * compute the final state we want first and check if we need to @@ -614,8 +614,8 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) } /* Get SSC going before enabling the outputs */ - intel_de_write(dev_priv, PCH_DREF_CONTROL, val); - intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); + intel_de_write(display, PCH_DREF_CONTROL, val); + intel_de_posting_read(display, PCH_DREF_CONTROL); udelay(200); val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; @@ -633,23 +633,23 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; } - intel_de_write(dev_priv, PCH_DREF_CONTROL, val); - intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); + intel_de_write(display, PCH_DREF_CONTROL, val); + intel_de_posting_read(display, PCH_DREF_CONTROL); udelay(200); } else { - drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n"); + drm_dbg_kms(display->drm, "Disabling CPU source output\n"); val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; /* Turn off CPU output */ val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; - intel_de_write(dev_priv, PCH_DREF_CONTROL, val); - intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); + intel_de_write(display, PCH_DREF_CONTROL, val); + intel_de_posting_read(display, PCH_DREF_CONTROL); udelay(200); if (!using_ssc_source) { - drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n"); + drm_dbg_kms(display->drm, "Disabling SSC source\n"); /* Turn off the SSC source */ val &= ~DREF_SSC_SOURCE_MASK; @@ -658,13 +658,13 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) /* Turn off SSC1 */ val &= ~DREF_SSC1_ENABLE; - intel_de_write(dev_priv, PCH_DREF_CONTROL, val); - intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); + intel_de_write(display, PCH_DREF_CONTROL, val); + intel_de_posting_read(display, PCH_DREF_CONTROL); udelay(200); } } - drm_WARN_ON(&dev_priv->drm, val != final); + drm_WARN_ON(display->drm, val != final); } /* diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c index 4ee03d9d14ad..3c3ecf288570 100644 --- a/drivers/gpu/drm/i915/display/intel_pfit.c +++ b/drivers/gpu/drm/i915/display/intel_pfit.c @@ -3,13 +3,17 @@ * Copyright © 2024 Intel Corporation */ +#include <drm/drm_print.h> + #include "i915_reg.h" #include "i915_utils.h" +#include "intel_de.h" #include "intel_display_core.h" #include "intel_display_driver.h" #include "intel_display_types.h" #include "intel_lvds_regs.h" #include "intel_pfit.h" +#include "intel_pfit_regs.h" static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state) { @@ -542,8 +546,8 @@ out: return intel_gmch_pfit_check_timings(crtc_state); } -int intel_panel_fitting(struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state) +int intel_pfit_compute_config(struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -552,3 +556,165 @@ int intel_panel_fitting(struct intel_crtc_state *crtc_state, else return pch_panel_fitting(crtc_state, conn_state); } + +void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + const struct drm_rect *dst = &crtc_state->pch_pfit.dst; + enum pipe pipe = crtc->pipe; + int width = drm_rect_width(dst); + int height = drm_rect_height(dst); + int x = dst->x1; + int y = dst->y1; + + if (!crtc_state->pch_pfit.enabled) + return; + + /* + * Force use of hard-coded filter coefficients as some pre-programmed + * values are broken, e.g. x201. + */ + if (display->platform.ivybridge || display->platform.haswell) + intel_de_write_fw(display, PF_CTL(pipe), PF_ENABLE | + PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); + else + intel_de_write_fw(display, PF_CTL(pipe), PF_ENABLE | + PF_FILTER_MED_3x3); + intel_de_write_fw(display, PF_WIN_POS(pipe), + PF_WIN_XPOS(x) | PF_WIN_YPOS(y)); + intel_de_write_fw(display, PF_WIN_SZ(pipe), + PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height)); +} + +void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) +{ + struct intel_display *display = to_intel_display(old_crtc_state); + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); + enum pipe pipe = crtc->pipe; + + /* + * To avoid upsetting the power well on haswell only disable the pfit if + * it's in use. The hw state code will make sure we get this right. + */ + if (!old_crtc_state->pch_pfit.enabled) + return; + + intel_de_write_fw(display, PF_CTL(pipe), 0); + intel_de_write_fw(display, PF_WIN_POS(pipe), 0); + intel_de_write_fw(display, PF_WIN_SZ(pipe), 0); +} + +void ilk_pfit_get_config(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + u32 ctl, pos, size; + enum pipe pipe; + + ctl = intel_de_read(display, PF_CTL(crtc->pipe)); + if ((ctl & PF_ENABLE) == 0) + return; + + if (display->platform.ivybridge || display->platform.haswell) + pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl); + else + pipe = crtc->pipe; + + crtc_state->pch_pfit.enabled = true; + + pos = intel_de_read(display, PF_WIN_POS(crtc->pipe)); + size = intel_de_read(display, PF_WIN_SZ(crtc->pipe)); + + drm_rect_init(&crtc_state->pch_pfit.dst, + REG_FIELD_GET(PF_WIN_XPOS_MASK, pos), + REG_FIELD_GET(PF_WIN_YPOS_MASK, pos), + REG_FIELD_GET(PF_WIN_XSIZE_MASK, size), + REG_FIELD_GET(PF_WIN_YSIZE_MASK, size)); + + /* + * We currently do not free assignments of panel fitters on + * ivb/hsw (since we don't use the higher upscaling modes which + * differentiates them) so just WARN about this case for now. + */ + drm_WARN_ON(display->drm, pipe != crtc->pipe); +} + +void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + if (!crtc_state->gmch_pfit.control) + return; + + /* + * The panel fitter should only be adjusted whilst the pipe is disabled, + * according to register description and PRM. + */ + drm_WARN_ON(display->drm, + intel_de_read(display, PFIT_CONTROL(display)) & PFIT_ENABLE); + assert_transcoder_disabled(display, crtc_state->cpu_transcoder); + + intel_de_write(display, PFIT_PGM_RATIOS(display), + crtc_state->gmch_pfit.pgm_ratios); + intel_de_write(display, PFIT_CONTROL(display), + crtc_state->gmch_pfit.control); + + /* + * Border color in case we don't scale up to the full screen. Black by + * default, change to something else for debugging. + */ + intel_de_write(display, BCLRPAT(display, crtc->pipe), 0); +} + +void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) +{ + struct intel_display *display = to_intel_display(old_crtc_state); + + if (!old_crtc_state->gmch_pfit.control) + return; + + assert_transcoder_disabled(display, old_crtc_state->cpu_transcoder); + + drm_dbg_kms(display->drm, "disabling pfit, current: 0x%08x\n", + intel_de_read(display, PFIT_CONTROL(display))); + intel_de_write(display, PFIT_CONTROL(display), 0); +} + +static bool i9xx_has_pfit(struct intel_display *display) +{ + if (display->platform.i830) + return false; + + return DISPLAY_VER(display) >= 4 || + display->platform.pineview || display->platform.mobile; +} + +void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum pipe pipe; + u32 tmp; + + if (!i9xx_has_pfit(display)) + return; + + tmp = intel_de_read(display, PFIT_CONTROL(display)); + if (!(tmp & PFIT_ENABLE)) + return; + + /* Check whether the pfit is attached to our pipe. */ + if (DISPLAY_VER(display) >= 4) + pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp); + else + pipe = PIPE_B; + + if (pipe != crtc->pipe) + return; + + crtc_state->gmch_pfit.control = tmp; + crtc_state->gmch_pfit.pgm_ratios = + intel_de_read(display, PFIT_PGM_RATIOS(display)); +} diff --git a/drivers/gpu/drm/i915/display/intel_pfit.h b/drivers/gpu/drm/i915/display/intel_pfit.h index add8d78de2c9..ef34f9b49d09 100644 --- a/drivers/gpu/drm/i915/display/intel_pfit.h +++ b/drivers/gpu/drm/i915/display/intel_pfit.h @@ -9,7 +9,13 @@ struct drm_connector_state; struct intel_crtc_state; -int intel_panel_fitting(struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state); +int intel_pfit_compute_config(struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state); +void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); +void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state); +void ilk_pfit_get_config(struct intel_crtc_state *crtc_state); +void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state); +void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state); +void i9xx_pfit_get_config(struct intel_crtc_state *crtc_state); #endif /* __INTEL_PFIT_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_pfit_regs.h b/drivers/gpu/drm/i915/display/intel_pfit_regs.h new file mode 100644 index 000000000000..add8ce28004e --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_pfit_regs.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2025 Intel Corporation */ + +#ifndef __INTEL_PFIT_REGS_H__ +#define __INTEL_PFIT_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* Panel fitting */ +#define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) +#define PFIT_ENABLE REG_BIT(31) +#define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */ +#define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe)) +#define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */ +#define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0) +#define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1) +#define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2) +#define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3) +#define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */ +#define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0) +#define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1) +#define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2) +#define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */ +#define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1) +#define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */ +#define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */ +#define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1) +#define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */ +#define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */ + +#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) +#define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */ +#define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x)) +#define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */ +#define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x)) +#define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */ +#define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */ + +#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) + +/* CPU panel fitter */ +/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ +#define _PFA_CTL_1 0x68080 +#define _PFB_CTL_1 0x68880 +#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) +#define PF_ENABLE REG_BIT(31) +#define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */ +#define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe)) +#define PF_FILTER_MASK REG_GENMASK(24, 23) +#define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0) +#define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1) +#define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2) +#define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3) + +#define _PFA_WIN_SZ 0x68074 +#define _PFB_WIN_SZ 0x68874 +#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) +#define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16) +#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w)) +#define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0) +#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h)) + +#define _PFA_WIN_POS 0x68070 +#define _PFB_WIN_POS 0x68870 +#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) +#define PF_WIN_XPOS_MASK REG_GENMASK(31, 16) +#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x)) +#define PF_WIN_YPOS_MASK REG_GENMASK(15, 0) +#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y)) + +#define _PFA_VSCALE 0x68084 +#define _PFB_VSCALE 0x68884 +#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) + +#define _PFA_HSCALE 0x68090 +#define _PFB_HSCALE 0x68890 +#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) + +#endif /* __INTEL_PFIT_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index 90efc6f64e52..10e26c3db946 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -582,6 +582,7 @@ int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name) { struct intel_crtc *crtc = to_intel_crtc(_crtc); + struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; enum intel_display_power_domain power_domain; @@ -598,7 +599,7 @@ int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name) } power_domain = POWER_DOMAIN_PIPE(pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) { drm_dbg_kms(&dev_priv->drm, "Trying to capture CRC while pipe is off\n"); @@ -628,7 +629,7 @@ out: if (!enable) intel_crtc_crc_setup_workarounds(crtc, false); - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.h b/drivers/gpu/drm/i915/display/intel_pipe_crc.h index 43012b189415..6ddcea38488b 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.h @@ -9,7 +9,6 @@ #include <linux/types.h> struct drm_crtc; -struct drm_i915_private; struct intel_crtc; #ifdef CONFIG_DEBUG_FS diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c index 6789b7f14095..b1675b46e06c 100644 --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c @@ -14,6 +14,11 @@ #include "intel_frontbuffer.h" #include "intel_plane_initial.h" +void intel_plane_initial_vblank_wait(struct intel_crtc *crtc) +{ + intel_crtc_wait_for_next_vblank(crtc); +} + static bool intel_reuse_initial_plane_obj(struct intel_crtc *this, const struct intel_initial_plane_config plane_configs[], @@ -442,7 +447,7 @@ void intel_initial_plane_config(struct intel_display *display) intel_find_initial_plane_obj(crtc, plane_configs); if (display->funcs.display->fixup_initial_plane_config(crtc, plane_config)) - intel_crtc_wait_for_next_vblank(crtc); + intel_plane_initial_vblank_wait(crtc); plane_config_fini(plane_config); } diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.h b/drivers/gpu/drm/i915/display/intel_plane_initial.h index 6c6aa717ed21..5c315acda210 100644 --- a/drivers/gpu/drm/i915/display/intel_plane_initial.h +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.h @@ -6,8 +6,10 @@ #ifndef __INTEL_PLANE_INITIAL_H__ #define __INTEL_PLANE_INITIAL_H__ +struct intel_crtc; struct intel_display; void intel_initial_plane_config(struct intel_display *display); +void intel_plane_initial_vblank_wait(struct intel_crtc *crtc); #endif diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c index 975520322136..63301a01906c 100644 --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c @@ -609,7 +609,7 @@ intel_pmdemand_program_params(struct intel_display *display, goto unlock; drm_dbg_kms(display->drm, - "initate pmdemand request values: (0x%x 0x%x)\n", + "initiate pmdemand request values: (0x%x 0x%x)\n", mod_reg1, mod_reg2); intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0, diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index eb35f0249f2b..617ce4993172 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -65,13 +65,12 @@ static const char *pps_name(struct intel_dp *intel_dp) intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); intel_wakeref_t wakeref; /* * See vlv_pps_reset_all() why we need a power domain reference here. */ - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); + wakeref = intel_display_power_get(display, POWER_DOMAIN_DISPLAY_CORE); mutex_lock(&display->pps.mutex); return wakeref; @@ -81,10 +80,9 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); mutex_unlock(&display->pps.mutex); - intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); + intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref); return NULL; } @@ -136,7 +134,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) release_cl_override = display->platform.cherryview && !chv_phy_powergate_ch(display, phy, ch, true); - if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) { + if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(display))) { drm_err(display->drm, "Failed to force on PLL for pipe %c!\n", pipe_name(pipe)); @@ -741,7 +739,6 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp) bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; i915_reg_t pp_stat_reg, pp_ctrl_reg; @@ -759,7 +756,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp) return need_to_disable; drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); - intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv, + intel_dp->pps.vdd_wakeref = intel_display_power_get(display, intel_aux_power_domain(dig_port)); pp_stat_reg = _pp_stat_reg(intel_dp); @@ -825,7 +822,6 @@ void intel_pps_vdd_on(struct intel_dp *intel_dp) static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; i915_reg_t pp_stat_reg, pp_ctrl_reg; @@ -863,7 +859,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp) intel_dp_invalidate_source_oui(intel_dp); } - intel_display_power_put(dev_priv, + intel_display_power_put(display, intel_aux_power_domain(dig_port), fetch_and_zero(&intel_dp->pps.vdd_wakeref)); } @@ -1036,7 +1032,6 @@ void intel_pps_on(struct intel_dp *intel_dp) void intel_pps_off_unlocked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; i915_reg_t pp_ctrl_reg; @@ -1074,7 +1069,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp) intel_dp_invalidate_source_oui(intel_dp); /* We got a reference when we enabled the VDD. */ - intel_display_power_put(dev_priv, + intel_display_power_put(display, intel_aux_power_domain(dig_port), fetch_and_zero(&intel_dp->pps.vdd_wakeref)); } @@ -1230,11 +1225,10 @@ static void vlv_steal_power_sequencer(struct intel_display *display, static enum pipe vlv_active_pipe(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; enum pipe pipe; - if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg, + if (g4x_dp_port_enabled(display, intel_dp->output_reg, encoder->port, &pipe)) return pipe; @@ -1338,7 +1332,6 @@ void vlv_pps_port_disable(struct intel_encoder *encoder, static void pps_vdd_init(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); lockdep_assert_held(&display->pps.mutex); @@ -1357,7 +1350,7 @@ static void pps_vdd_init(struct intel_dp *intel_dp) dig_port->base.base.base.id, dig_port->base.base.name, pps_name(intel_dp)); drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref); - intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv, + intel_dp->pps.vdd_wakeref = intel_display_power_get(display, intel_aux_power_domain(dig_port)); } @@ -1501,8 +1494,9 @@ static void pps_init_delays_vbt(struct intel_dp *intel_dp, if (!pps_delays_valid(vbt)) return; - /* On Toshiba Satellite P50-C-18C system the VBT T12 delay - * of 500ms appears to be too short. Ocassionally the panel + /* + * On Toshiba Satellite P50-C-18C system the VBT T12 delay + * of 500ms appears to be too short. Occasionally the panel * just fails to power back on. Increasing the delay to 800ms * seems sufficient to avoid this problem. */ @@ -1864,13 +1858,13 @@ void assert_pps_unlocked(struct intel_display *display, enum pipe pipe) intel_lvds_port_enabled(dev_priv, PCH_LVDS, &panel_pipe); break; case PANEL_PORT_SELECT_DPA: - g4x_dp_port_enabled(dev_priv, DP_A, PORT_A, &panel_pipe); + g4x_dp_port_enabled(display, DP_A, PORT_A, &panel_pipe); break; case PANEL_PORT_SELECT_DPC: - g4x_dp_port_enabled(dev_priv, PCH_DP_C, PORT_C, &panel_pipe); + g4x_dp_port_enabled(display, PCH_DP_C, PORT_C, &panel_pipe); break; case PANEL_PORT_SELECT_DPD: - g4x_dp_port_enabled(dev_priv, PCH_DP_D, PORT_D, &panel_pipe); + g4x_dp_port_enabled(display, PCH_DP_D, PORT_D, &panel_pipe); break; default: MISSING_CASE(port_sel); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 0b021acb330f..4e938bad808c 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -44,6 +44,7 @@ #include "intel_psr.h" #include "intel_psr_regs.h" #include "intel_snps_phy.h" +#include "intel_vblank.h" #include "skl_universal_plane.h" /** @@ -154,7 +155,7 @@ * * Unfortunately CHICKEN_TRANS itself seems to be double buffered * and thus won't latch until the first vblank. So with DC states - * enabled the register effctively uses the reset value during DC5 + * enabled the register effectively uses the reset value during DC5 * exit+PSR exit sequence, and thus the bit does nothing until * latched by the vblank that it was trying to prevent from being * generated in the first place. So we should probably call this @@ -171,7 +172,7 @@ * CHICKEN_PIPESL_1[15]/HSW_UNMASK_VBL_TO_REGS_IN_SRD (hsw): * * On BDW without this bit is no vblanks whatsoever are - * generated after PSR exit. On HSW this has no apparant effect. + * generated after PSR exit. On HSW this has no apparent effect. * WaPsrDPRSUnmaskVBlankInSRD says to set this. * * The rest of the bits are more self-explanatory and/or @@ -185,7 +186,7 @@ * has_psr + has_panel_replay: Panel Replay * has_psr + has_panel_replay + has_sel_update: Panel Replay Selective Update * - * Description of some intel_psr varibles. enabled, panel_replay_enabled, + * Description of some intel_psr variables. enabled, panel_replay_enabled, * sel_update_enabled * * enabled (alone): PSR1 @@ -814,8 +815,8 @@ static void intel_psr_enable_sink_alpm(struct intel_dp *intel_dp, drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val); } -void intel_psr_enable_sink(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +static void intel_psr_enable_sink(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { intel_psr_enable_sink_alpm(intel_dp, crtc_state); @@ -827,6 +828,13 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp, drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); } +void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp) +{ + if (CAN_PANEL_REPLAY(intel_dp)) + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, + DP_PANEL_REPLAY_ENABLE); +} + static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); @@ -1043,7 +1051,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) }; /* * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see - * comments bellow for more information + * comments below for more information */ int tmp; @@ -1991,18 +1999,25 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, if (!psr_interrupt_error_check(intel_dp)) return; - if (intel_dp->psr.panel_replay_enabled) { + if (intel_dp->psr.panel_replay_enabled) drm_dbg_kms(display->drm, "Enabling Panel Replay\n"); - } else { + else drm_dbg_kms(display->drm, "Enabling PSR%s\n", intel_dp->psr.sel_update_enabled ? "2" : "1"); - /* - * Panel replay has to be enabled before link training: doing it - * only for PSR here. - */ - intel_psr_enable_sink(intel_dp, crtc_state); - } + /* + * Enabling here only for PSR. Panel Replay enable bit is already + * written at this point. See + * intel_psr_panel_replay_enable_sink. Modifiers/options: + * - Selective Update + * - Region Early Transport + * - Selective Update Region Scanline Capture + * - VSC_SDP_CRC + * - HPD on different Errors + * - CRC verification + * are written for PSR and Panel Replay here. + */ + intel_psr_enable_sink(intel_dp, crtc_state); if (intel_dp_is_edp(intel_dp)) intel_snps_phy_update_psr_power_state(&dig_port->base, true); @@ -2172,7 +2187,8 @@ void intel_psr_disable(struct intel_dp *intel_dp, if (!old_crtc_state->has_psr) return; - if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp))) + if (drm_WARN_ON(display->drm, !CAN_PSR(intel_dp) && + !CAN_PANEL_REPLAY(intel_dp))) return; mutex_lock(&intel_dp->psr.lock); @@ -2275,6 +2291,27 @@ bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state) return false; } +/** + * intel_psr_trigger_frame_change_event - Trigger "Frame Change" event + * @dsb: DSB context + * @state: the atomic state + * @crtc: the CRTC + * + * Generate PSR "Frame Change" event. + */ +void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, + struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + const struct intel_crtc_state *crtc_state = + intel_pre_commit_crtc_state(state, crtc); + struct intel_display *display = to_intel_display(crtc); + + if (crtc_state->has_psr) + intel_de_write_dsb(display, dsb, + CURSURFLIVE(display, crtc->pipe), 0); +} + static u32 man_trk_ctl_enable_bit_get(struct intel_display *display) { struct drm_i915_private *dev_priv = to_i915(display->drm); @@ -2310,18 +2347,9 @@ static u32 man_trk_ctl_continuos_full_frame(struct intel_display *display) PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; } -static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) +static void intel_psr_force_update(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - enum transcoder cpu_transcoder = intel_dp->psr.transcoder; - - if (intel_dp->psr.psr2_sel_fetch_enabled) - intel_de_write(display, - PSR2_MAN_TRK_CTL(display, cpu_transcoder), - man_trk_ctl_enable_bit_get(display) | - man_trk_ctl_partial_frame_bit_get(display) | - man_trk_ctl_single_full_frame_bit_get(display) | - man_trk_ctl_continuos_full_frame(display)); /* * Display WA #0884: skl+ @@ -2339,7 +2367,8 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0); } -void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) +void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -2353,20 +2382,23 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st crtc_state->uapi.encoder_mask) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - lockdep_assert_held(&intel_dp->psr.lock); - if (intel_dp->psr.psr2_sel_fetch_cff_enabled) + if (!dsb) + lockdep_assert_held(&intel_dp->psr.lock); + + if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled) return; break; } - intel_de_write(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), - crtc_state->psr2_man_track_ctl); + intel_de_write_dsb(display, dsb, + PSR2_MAN_TRK_CTL(display, cpu_transcoder), + crtc_state->psr2_man_track_ctl); if (!crtc_state->enable_psr2_su_region_et) return; - intel_de_write(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), - crtc_state->pipe_srcsz_early_tpt); + intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), + crtc_state->pipe_srcsz_early_tpt); } static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, @@ -2381,7 +2413,6 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, val |= man_trk_ctl_partial_frame_bit_get(display); if (full_update) { - val |= man_trk_ctl_single_full_frame_bit_get(display); val |= man_trk_ctl_continuos_full_frame(display); goto exit; } @@ -2790,32 +2821,30 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, old_crtc_state->uapi.encoder_mask) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_psr *psr = &intel_dp->psr; - bool needs_to_disable = false; mutex_lock(&psr->lock); - /* - * Reasons to disable: - * - PSR disabled in new state - * - All planes will go inactive - * - Changing between PSR versions - * - Region Early Transport changing - * - Display WA #1136: skl, bxt - */ - needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); - needs_to_disable |= !new_crtc_state->has_psr; - needs_to_disable |= !new_crtc_state->active_planes; - needs_to_disable |= new_crtc_state->has_sel_update != psr->sel_update_enabled; - needs_to_disable |= new_crtc_state->enable_psr2_su_region_et != - psr->su_region_et_enabled; - needs_to_disable |= DISPLAY_VER(i915) < 11 && - new_crtc_state->wm_level_disabled; - - if (psr->enabled && needs_to_disable) - intel_psr_disable_locked(intel_dp); - else if (psr->enabled && new_crtc_state->wm_level_disabled) - /* Wa_14015648006 */ - wm_optimization_wa(intel_dp, new_crtc_state); + if (psr->enabled) { + /* + * Reasons to disable: + * - PSR disabled in new state + * - All planes will go inactive + * - Changing between PSR versions + * - Region Early Transport changing + * - Display WA #1136: skl, bxt + */ + if (intel_crtc_needs_modeset(new_crtc_state) || + !new_crtc_state->has_psr || + !new_crtc_state->active_planes || + new_crtc_state->has_sel_update != psr->sel_update_enabled || + new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled || + new_crtc_state->has_panel_replay != psr->panel_replay_enabled || + (DISPLAY_VER(i915) < 11 && new_crtc_state->wm_level_disabled)) + intel_psr_disable_locked(intel_dp); + else if (new_crtc_state->wm_level_disabled) + /* Wa_14015648006 */ + wm_optimization_wa(intel_dp, new_crtc_state); + } mutex_unlock(&psr->lock); } @@ -2858,7 +2887,7 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state, /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ if (crtc_state->crc_enabled && psr->enabled) - psr_force_hw_tracking_exit(intel_dp); + intel_psr_force_update(intel_dp); /* * Clear possible busy bits in case we have @@ -3120,31 +3149,35 @@ unlock: mutex_unlock(&intel_dp->psr.lock); } -static void _psr_invalidate_handle(struct intel_dp *intel_dp) +static void intel_psr_configure_full_frame_update(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; - if (intel_dp->psr.psr2_sel_fetch_enabled) { - u32 val; - - if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { - /* Send one update otherwise lag is observed in screen */ - intel_de_write(display, - CURSURFLIVE(display, intel_dp->psr.pipe), - 0); - return; - } + if (!intel_dp->psr.psr2_sel_fetch_enabled) + return; - val = man_trk_ctl_enable_bit_get(display) | - man_trk_ctl_partial_frame_bit_get(display) | - man_trk_ctl_continuos_full_frame(display); + if (DISPLAY_VER(display) >= 20) + intel_de_write(display, LNL_SFF_CTL(cpu_transcoder), + LNL_SFF_CTL_SF_SINGLE_FULL_FRAME); + else intel_de_write(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), - val); - intel_de_write(display, - CURSURFLIVE(display, intel_dp->psr.pipe), 0); - intel_dp->psr.psr2_sel_fetch_cff_enabled = true; + man_trk_ctl_enable_bit_get(display) | + man_trk_ctl_partial_frame_bit_get(display) | + man_trk_ctl_single_full_frame_bit_get(display) | + man_trk_ctl_continuos_full_frame(display)); +} + +static void _psr_invalidate_handle(struct intel_dp *intel_dp) +{ + if (intel_dp->psr.psr2_sel_fetch_enabled) { + if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) { + intel_dp->psr.psr2_sel_fetch_cff_enabled = true; + intel_psr_configure_full_frame_update(intel_dp); + } + + intel_psr_force_update(intel_dp); } else { intel_psr_exit(intel_dp); } @@ -3225,44 +3258,31 @@ static void _psr_flush_handle(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); struct drm_i915_private *dev_priv = to_i915(display->drm); - enum transcoder cpu_transcoder = intel_dp->psr.transcoder; if (intel_dp->psr.psr2_sel_fetch_enabled) { if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { /* can we turn CFF off? */ - if (intel_dp->psr.busy_frontbuffer_bits == 0) { - u32 val = man_trk_ctl_enable_bit_get(display) | - man_trk_ctl_partial_frame_bit_get(display) | - man_trk_ctl_single_full_frame_bit_get(display) | - man_trk_ctl_continuos_full_frame(display); - - /* - * Set psr2_sel_fetch_cff_enabled as false to allow selective - * updates. Still keep cff bit enabled as we don't have proper - * SU configuration in case update is sent for any reason after - * sff bit gets cleared by the HW on next vblank. - */ - intel_de_write(display, - PSR2_MAN_TRK_CTL(display, cpu_transcoder), - val); - intel_de_write(display, - CURSURFLIVE(display, intel_dp->psr.pipe), - 0); + if (intel_dp->psr.busy_frontbuffer_bits == 0) intel_dp->psr.psr2_sel_fetch_cff_enabled = false; - } - } else { - /* - * continuous full frame is disabled, only a single full - * frame is required - */ - psr_force_hw_tracking_exit(intel_dp); } - } else { - psr_force_hw_tracking_exit(intel_dp); - if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) - queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); + /* + * Still keep cff bit enabled as we don't have proper SU + * configuration in case update is sent for any reason after + * sff bit gets cleared by the HW on next vblank. + * + * NOTE: Setting cff bit is not needed for LunarLake onwards as + * we have own register for SFF bit and we are not overwriting + * existing SU configuration + */ + intel_psr_configure_full_frame_update(intel_dp); } + + intel_psr_force_update(intel_dp); + + if (!intel_dp->psr.psr2_sel_fetch_enabled && !intel_dp->psr.active && + !intel_dp->psr.busy_frontbuffer_bits) + queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); } /** diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 956be263c09e..a43a374cff55 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -17,6 +17,7 @@ struct intel_crtc; struct intel_crtc_state; struct intel_display; struct intel_dp; +struct intel_dsb; struct intel_encoder; struct intel_plane; struct intel_plane_state; @@ -28,8 +29,7 @@ bool intel_encoder_can_psr(struct intel_encoder *encoder); bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_psr_init_dpcd(struct intel_dp *intel_dp); -void intel_psr_enable_sink(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state); +void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp); void intel_psr_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_psr_post_plane_update(struct intel_atomic_state *state, @@ -55,7 +55,8 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat bool intel_psr_enabled(struct intel_dp *intel_dp); int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, struct intel_crtc *crtc); -void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state); +void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state); void intel_psr_pause(struct intel_dp *intel_dp); void intel_psr_resume(struct intel_dp *intel_dp); bool intel_psr_needs_block_dc_vblank(const struct intel_crtc_state *crtc_state); @@ -63,6 +64,9 @@ bool intel_psr_link_ok(struct intel_dp *intel_dp); void intel_psr_lock(const struct intel_crtc_state *crtc_state); void intel_psr_unlock(const struct intel_crtc_state *crtc_state); +void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb, + struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_psr_connector_debugfs_add(struct intel_connector *connector); void intel_psr_debugfs_register(struct intel_display *display); diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 9ad7611506e8..795e6b9cc575 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -251,6 +251,16 @@ #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14) #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13) +#define _LNL_SFF_CTL_A 0x60918 +#define _LNL_SFF_CTL_B 0x61918 +#define LNL_SFF_CTL(tran) _MMIO_TRANS(tran, _LNL_SFF_CTL_A, _LNL_SFF_CTL_B) +#define LNL_SFF_CTL_SF_SINGLE_FULL_FRAME REG_BIT(1) + +#define _LNL_CFF_CTL_A 0x6091c +#define _LNL_CFF_CTL_B 0x6191c +#define LNL_CFF_CTL(tran) _MMIO_TRANS(tran, _LNL_CFF_CTL_A, _LNL_CFF_CTL_B) +#define LNL_CFF_CTL_SF_CONTINUOUS_FULL_FRAME REG_BIT(1) + /* PSR2 Early transport */ #define _PIPE_SRCSZ_ERLY_TPT_A 0x70074 #define _PIPE_SRCSZ_ERLY_TPT_B 0x71074 diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c index 8b30e9fd936e..a32fae510ed2 100644 --- a/drivers/gpu/drm/i915/display/intel_quirks.c +++ b/drivers/gpu/drm/i915/display/intel_quirks.c @@ -5,6 +5,8 @@ #include <linux/dmi.h> +#include <drm/drm_print.h> + #include "intel_display_core.h" #include "intel_display_types.h" #include "intel_quirks.h" diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index 498b35ec4e0f..6e2d9929b4d7 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -213,29 +213,29 @@ intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, */ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) { - struct drm_device *dev = intel_sdvo->base.base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); + struct drm_i915_private *dev_priv = to_i915(display->drm); u32 bval = val, cval = val; int i; if (HAS_PCH_SPLIT(dev_priv)) { - intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); - intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); + intel_de_write(display, intel_sdvo->sdvo_reg, val); + intel_de_posting_read(display, intel_sdvo->sdvo_reg); /* * HW workaround, need to write this twice for issue * that may result in first write getting masked. */ if (HAS_PCH_IBX(dev_priv)) { - intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); - intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); + intel_de_write(display, intel_sdvo->sdvo_reg, val); + intel_de_posting_read(display, intel_sdvo->sdvo_reg); } return; } if (intel_sdvo->base.port == PORT_B) - cval = intel_de_read(dev_priv, GEN3_SDVOC); + cval = intel_de_read(display, GEN3_SDVOC); else - bval = intel_de_read(dev_priv, GEN3_SDVOB); + bval = intel_de_read(display, GEN3_SDVOB); /* * Write the registers twice for luck. Sometimes, @@ -243,17 +243,17 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) * The BIOS does this too. Yay, magic */ for (i = 0; i < 2; i++) { - intel_de_write(dev_priv, GEN3_SDVOB, bval); - intel_de_posting_read(dev_priv, GEN3_SDVOB); + intel_de_write(display, GEN3_SDVOB, bval); + intel_de_posting_read(display, GEN3_SDVOB); - intel_de_write(dev_priv, GEN3_SDVOC, cval); - intel_de_posting_read(dev_priv, GEN3_SDVOC); + intel_de_write(display, GEN3_SDVOC, cval); + intel_de_posting_read(display, GEN3_SDVOC); } } static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) { - struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); struct i2c_msg msgs[] = { { .addr = intel_sdvo->target_addr, @@ -273,7 +273,7 @@ static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) return true; - drm_dbg_kms(&i915->drm, "i2c transfer returned %d\n", ret); + drm_dbg_kms(display->drm, "i2c transfer returned %d\n", ret); return false; } @@ -415,7 +415,7 @@ static const char *sdvo_cmd_name(u8 cmd) static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, const void *args, int args_len) { - struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); const char *cmd_name; int i, pos = 0; char buffer[64]; @@ -436,10 +436,10 @@ static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, else BUF_PRINT("(%02X)", cmd); - drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1); + drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1); #undef BUF_PRINT - drm_dbg_kms(&dev_priv->drm, "%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), + drm_dbg_kms(display->drm, "%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); } @@ -465,7 +465,7 @@ static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, const void *args, int args_len, bool unlocked) { - struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); u8 *buf, status; struct i2c_msg *msgs; int i, ret = true; @@ -515,13 +515,13 @@ static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, else ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3); if (ret < 0) { - drm_dbg_kms(&i915->drm, "I2c transfer returned %d\n", ret); + drm_dbg_kms(display->drm, "I2c transfer returned %d\n", ret); ret = false; goto out; } if (ret != i+3) { /* failure in I2C transfer */ - drm_dbg_kms(&i915->drm, "I2c transfer returned %d/%d\n", ret, i+3); + drm_dbg_kms(display->drm, "I2c transfer returned %d/%d\n", ret, i + 3); ret = false; } @@ -540,7 +540,7 @@ static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, void *response, int response_len) { - struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); const char *cmd_status; u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ u8 status; @@ -605,15 +605,15 @@ static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, BUF_PRINT(" %02X", ((u8 *)response)[i]); } - drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1); + drm_WARN_ON(display->drm, pos >= sizeof(buffer) - 1); #undef BUF_PRINT - drm_dbg_kms(&dev_priv->drm, "%s: R: %s\n", + drm_dbg_kms(display->drm, "%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); return true; log_fail: - drm_dbg_kms(&dev_priv->drm, "%s: R: ... failed %s\n", + drm_dbg_kms(display->drm, "%s: R: ... failed %s\n", SDVO_NAME(intel_sdvo), buffer); return false; } @@ -1009,7 +1009,7 @@ static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, unsigned int if_index, u8 tx_rate, const u8 *data, unsigned int length) { - struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); u8 set_buf_index[2] = { if_index, 0 }; u8 hbuf_size, tmp[8]; int i; @@ -1022,7 +1022,7 @@ static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) return false; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "writing sdvo hbuf: %i, length %u, hbuf_size: %i\n", if_index, length, hbuf_size); @@ -1049,7 +1049,7 @@ static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, unsigned int if_index, u8 *data, unsigned int length) { - struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); u8 set_buf_index[2] = { if_index, 0 }; u8 hbuf_size, tx_rate, av_split; int i; @@ -1079,7 +1079,7 @@ static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo, if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size)) return false; - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "reading sdvo hbuf: %i, length %u, hbuf_size: %i\n", if_index, length, hbuf_size); @@ -1100,7 +1100,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) { - struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; @@ -1126,7 +1126,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, HDMI_QUANTIZATION_RANGE_FULL); ret = hdmi_avi_infoframe_check(frame); - if (drm_WARN_ON(&dev_priv->drm, ret)) + if (drm_WARN_ON(display->drm, ret)) return false; return true; @@ -1135,7 +1135,7 @@ static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo, static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; const union hdmi_infoframe *frame = &crtc_state->infoframes.avi; ssize_t len; @@ -1144,12 +1144,12 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0) return true; - if (drm_WARN_ON(&dev_priv->drm, + if (drm_WARN_ON(display->drm, frame->any.type != HDMI_INFOFRAME_TYPE_AVI)) return false; len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data)); - if (drm_WARN_ON(&dev_priv->drm, len < 0)) + if (drm_WARN_ON(display->drm, len < 0)) return false; return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, @@ -1160,7 +1160,7 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; union hdmi_infoframe *frame = &crtc_state->infoframes.avi; ssize_t len; @@ -1172,7 +1172,7 @@ static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, sdvo_data, sizeof(sdvo_data)); if (len < 0) { - drm_dbg_kms(&i915->drm, "failed to read AVI infoframe\n"); + drm_dbg_kms(display->drm, "failed to read AVI infoframe\n"); return; } else if (len == 0) { return; @@ -1183,12 +1183,12 @@ static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, ret = hdmi_infoframe_unpack(frame, sdvo_data, len); if (ret) { - drm_dbg_kms(&i915->drm, "Failed to unpack AVI infoframe\n"); + drm_dbg_kms(display->drm, "Failed to unpack AVI infoframe\n"); return; } if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI) - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", frame->any.type, HDMI_INFOFRAME_TYPE_AVI); } @@ -1196,7 +1196,7 @@ static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo, static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo, struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); ssize_t len; u8 val; @@ -1212,7 +1212,7 @@ static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo, len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD, crtc_state->eld, sizeof(crtc_state->eld)); if (len < 0) - drm_dbg_kms(&i915->drm, "failed to read ELD\n"); + drm_dbg_kms(display->drm, "failed to read ELD\n"); } static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo, @@ -1282,7 +1282,7 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) { - struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev); + struct intel_display *display = to_intel_display(pipe_config); unsigned int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; struct dpll *clock = &pipe_config->dpll; @@ -1303,7 +1303,7 @@ static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) clock->m1 = 12; clock->m2 = 8; } else { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "SDVO TV clock out of range: %i\n", dotclock); return -EINVAL; } @@ -1359,6 +1359,7 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_sdvo *intel_sdvo = to_sdvo(encoder); struct intel_sdvo_connector *intel_sdvo_connector = @@ -1366,13 +1367,13 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder, struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; struct drm_display_mode *mode = &pipe_config->hw.mode; - if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) { + if (HAS_PCH_SPLIT(i915)) { pipe_config->has_pch_encoder = true; if (!intel_fdi_compute_pipe_bpp(pipe_config)) return -EINVAL; } - drm_dbg_kms(&i915->drm, "forcing bpc to 8 for SDVO\n"); + drm_dbg_kms(display->drm, "forcing bpc to 8 for SDVO\n"); /* FIXME: Don't increase pipe_bpp */ pipe_config->pipe_bpp = 8*3; pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; @@ -1451,7 +1452,7 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder, if (!intel_sdvo_compute_avi_infoframe(intel_sdvo, pipe_config, conn_state)) { - drm_dbg_kms(&i915->drm, "bad AVI infoframe\n"); + drm_dbg_kms(display->drm, "bad AVI infoframe\n"); return -EINVAL; } @@ -1525,6 +1526,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(intel_encoder); struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; @@ -1570,7 +1572,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state, intel_sdvo_get_dtd_from_mode(&output_dtd, mode); } if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) - drm_info(&dev_priv->drm, + drm_info(display->drm, "Setting output timings on %s failed\n", SDVO_NAME(intel_sdvo)); @@ -1600,13 +1602,13 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state, if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) - drm_info(&dev_priv->drm, + drm_info(display->drm, "Setting input timings on %s failed\n", SDVO_NAME(intel_sdvo)); switch (crtc_state->pixel_multiplier) { default: - drm_WARN(&dev_priv->drm, 1, + drm_WARN(display->drm, 1, "unknown pixel multiplier specified\n"); fallthrough; case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; @@ -1617,14 +1619,14 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state, return; /* Set the SDVO control regs. */ - if (DISPLAY_VER(dev_priv) >= 4) { + if (DISPLAY_VER(display) >= 4) { /* The real mode polarity is set by the SDVO commands, using * struct intel_sdvo_dtd. */ sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; - if (DISPLAY_VER(dev_priv) < 5) + if (DISPLAY_VER(display) < 5) sdvox |= SDVO_BORDER_ENABLE; } else { - sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); + sdvox = intel_de_read(display, intel_sdvo->sdvo_reg); if (intel_sdvo->base.port == PORT_B) sdvox &= SDVOB_PRESERVE_MASK; else @@ -1637,10 +1639,10 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state, else sdvox |= SDVO_PIPE_SEL(crtc->pipe); - if (DISPLAY_VER(dev_priv) >= 4) { + if (DISPLAY_VER(display) >= 4) { /* done in crtc_mode_set as the dpll_md reg must be written early */ - } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || - IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { + } else if (display->platform.i945g || display->platform.i945gm || + display->platform.g33 || display->platform.pineview) { /* done in crtc_mode_set as it lives inside the dpll register */ } else { sdvox |= (crtc_state->pixel_multiplier - 1) @@ -1648,7 +1650,7 @@ static void intel_sdvo_pre_enable(struct intel_atomic_state *state, } if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && - DISPLAY_VER(dev_priv) < 5) + DISPLAY_VER(display) < 5) sdvox |= SDVO_STALL_SELECT; intel_sdvo_write_sdvox(intel_sdvo, sdvox); } @@ -1665,17 +1667,18 @@ static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) return active_outputs & intel_sdvo_connector->output_flag; } -bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, +bool intel_sdvo_port_enabled(struct intel_display *display, i915_reg_t sdvo_reg, enum pipe *pipe) { + struct drm_i915_private *dev_priv = to_i915(display->drm); u32 val; - val = intel_de_read(dev_priv, sdvo_reg); + val = intel_de_read(display, sdvo_reg); /* asserts want to know the pipe even if the port is disabled */ if (HAS_PCH_CPT(dev_priv)) *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT; - else if (IS_CHERRYVIEW(dev_priv)) + else if (display->platform.cherryview) *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV; else *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT; @@ -1686,14 +1689,14 @@ bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); struct intel_sdvo *intel_sdvo = to_sdvo(encoder); u16 active_outputs = 0; bool ret; intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); - ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe); + ret = intel_sdvo_port_enabled(display, intel_sdvo->sdvo_reg, pipe); return ret || active_outputs; } @@ -1701,8 +1704,7 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, static void intel_sdvo_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(encoder); struct intel_sdvo *intel_sdvo = to_sdvo(encoder); struct intel_sdvo_dtd dtd; int encoder_pixel_multiplier = 0; @@ -1713,7 +1715,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); - sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); + sdvox = intel_de_read(display, intel_sdvo->sdvo_reg); ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); if (!ret) { @@ -1721,7 +1723,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, * Some sdvo encoders are not spec compliant and don't * implement the mandatory get_timings function. */ - drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n"); + drm_dbg_kms(display->drm, "failed to retrieve SDVO DTD\n"); pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; } else { if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) @@ -1741,10 +1743,10 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, * pixel multiplier readout is tricky: Only on i915g/gm it is stored in * the sdvo port register, on all other platforms it is part of the dpll * state. Since the general pipe state readout happens before the - * encoder->get_config we so already have a valid pixel multplier on all - * other platfroms. + * encoder->get_config we so already have a valid pixel multiplier on all + * other platforms. */ - if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { + if (display->platform.i915g || display->platform.i915gm) { pipe_config->pixel_multiplier = ((sdvox & SDVO_PORT_MULTIPLY_MASK) >> SDVO_PORT_MULTIPLY_SHIFT) + 1; @@ -1773,7 +1775,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, } } - drm_WARN(dev, + drm_WARN(display->drm, encoder_pixel_multiplier != pipe_config->pixel_multiplier, "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", pipe_config->pixel_multiplier, encoder_pixel_multiplier); @@ -1838,6 +1840,7 @@ static void intel_disable_sdvo(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state, const struct drm_connector_state *conn_state) { + struct intel_display *display = to_intel_display(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_sdvo *intel_sdvo = to_sdvo(encoder); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); @@ -1848,7 +1851,7 @@ static void intel_disable_sdvo(struct intel_atomic_state *state, intel_sdvo_set_encoder_power_state(intel_sdvo, DRM_MODE_DPMS_OFF); - temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); + temp = intel_de_read(display, intel_sdvo->sdvo_reg); temp &= ~SDVO_ENABLE; intel_sdvo_write_sdvox(intel_sdvo, temp); @@ -1863,8 +1866,8 @@ static void intel_disable_sdvo(struct intel_atomic_state *state, * We get CPU/PCH FIFO underruns on the other pipe when * doing the workaround. Sweep them under the rug. */ - intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); + intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); + intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); temp &= ~SDVO_PIPE_SEL_MASK; temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); @@ -1873,9 +1876,9 @@ static void intel_disable_sdvo(struct intel_atomic_state *state, temp &= ~SDVO_ENABLE; intel_sdvo_write_sdvox(intel_sdvo, temp); - intel_wait_for_vblank_if_active(dev_priv, PIPE_A); - intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); + intel_wait_for_vblank_if_active(display, PIPE_A); + intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); + intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); } } @@ -1899,8 +1902,7 @@ static void intel_enable_sdvo(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { - struct drm_device *dev = encoder->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_display *display = to_intel_display(encoder); struct intel_sdvo *intel_sdvo = to_sdvo(encoder); struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(conn_state->connector); @@ -1910,7 +1912,7 @@ static void intel_enable_sdvo(struct intel_atomic_state *state, int i; bool success; - temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); + temp = intel_de_read(display, intel_sdvo->sdvo_reg); temp |= SDVO_ENABLE; intel_sdvo_write_sdvox(intel_sdvo, temp); @@ -1925,7 +1927,7 @@ static void intel_enable_sdvo(struct intel_atomic_state *state, * a given it the status is a success, we succeeded. */ if (success && !input1) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "First %s output reported failure to sync\n", SDVO_NAME(intel_sdvo)); } @@ -1938,18 +1940,18 @@ static void intel_enable_sdvo(struct intel_atomic_state *state, static enum drm_mode_status intel_sdvo_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { - struct drm_i915_private *i915 = to_i915(connector->dev); + struct intel_display *display = to_intel_display(connector->dev); struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state); - int max_dotclk = i915->display.cdclk.max_dotclk_freq; + int max_dotclk = display->cdclk.max_dotclk_freq; enum drm_mode_status status; int clock = mode->clock; - status = intel_cpu_transcoder_mode_valid(i915, mode); + status = intel_cpu_transcoder_mode_valid(display, mode); if (status != MODE_OK) return status; @@ -1981,14 +1983,15 @@ intel_sdvo_mode_valid(struct drm_connector *connector, static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) { - struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); + BUILD_BUG_ON(sizeof(*caps) != 8); if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps))) return false; - drm_dbg_kms(&i915->drm, "SDVO capabilities:\n" + drm_dbg_kms(display->drm, "SDVO capabilities:\n" " vendor_id: %d\n" " device_id: %d\n" " device_rev_id: %d\n" @@ -2030,17 +2033,17 @@ static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo) static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) { - struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); u16 hotplug; - if (!I915_HAS_HOTPLUG(dev_priv)) + if (!I915_HAS_HOTPLUG(display)) return 0; /* * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise * on the line. */ - if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) + if (display->platform.i945g || display->platform.i945gm) return 0; if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, @@ -2137,13 +2140,12 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector, bool force) { struct intel_display *display = to_intel_display(connector->dev); - struct drm_i915_private *i915 = to_i915(connector->dev); struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); enum drm_connector_status ret; u16 response; - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.id, connector->name); if (!intel_display_device_enabled(display)) @@ -2161,7 +2163,7 @@ intel_sdvo_detect(struct drm_connector *connector, bool force) &response, 2)) return connector_status_unknown; - drm_dbg_kms(&i915->drm, "SDVO response %d %d [%x]\n", + drm_dbg_kms(display->drm, "SDVO response %d %d [%x]\n", response & 0xff, response >> 8, intel_sdvo_connector->output_flag); @@ -2300,7 +2302,6 @@ static int intel_sdvo_get_tv_modes(struct drm_connector *connector) { struct intel_display *display = to_intel_display(connector->dev); struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); - struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); const struct drm_connector_state *conn_state = connector->state; @@ -2309,7 +2310,7 @@ static int intel_sdvo_get_tv_modes(struct drm_connector *connector) int num_modes = 0; int i; - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.id, connector->name); if (!intel_display_driver_check_access(display)) @@ -2351,9 +2352,9 @@ static int intel_sdvo_get_tv_modes(struct drm_connector *connector) static int intel_sdvo_get_lvds_modes(struct drm_connector *connector) { - struct drm_i915_private *dev_priv = to_i915(connector->dev); + struct intel_display *display = to_intel_display(connector->dev); - drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.id, connector->name); return intel_panel_get_modes(to_intel_connector(connector)); @@ -2617,14 +2618,14 @@ static struct intel_sdvo_ddc * intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo, struct intel_sdvo_connector *connector) { - struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&sdvo->base); const struct sdvo_device_mapping *mapping; int ddc_bus; if (sdvo->base.port == PORT_B) - mapping = &dev_priv->display.vbt.sdvo_mappings[0]; + mapping = &display->vbt.sdvo_mappings[0]; else - mapping = &dev_priv->display.vbt.sdvo_mappings[1]; + mapping = &display->vbt.sdvo_mappings[1]; if (mapping->initialized) ddc_bus = (mapping->ddc_pin & 0xf0) >> 4; @@ -2641,14 +2642,13 @@ static void intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo) { struct intel_display *display = to_intel_display(&sdvo->base); - struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev); const struct sdvo_device_mapping *mapping; u8 pin; if (sdvo->base.port == PORT_B) - mapping = &dev_priv->display.vbt.sdvo_mappings[0]; + mapping = &display->vbt.sdvo_mappings[0]; else - mapping = &dev_priv->display.vbt.sdvo_mappings[1]; + mapping = &display->vbt.sdvo_mappings[1]; if (mapping->initialized && intel_gmbus_is_valid_pin(display, mapping->i2c_pin)) @@ -2656,7 +2656,7 @@ intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo) else pin = GMBUS_PIN_DPB; - drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] I2C pin %d, target addr 0x%x\n", + drm_dbg_kms(display->drm, "[ENCODER:%d:%s] I2C pin %d, target addr 0x%x\n", sdvo->base.base.base.id, sdvo->base.base.name, pin, sdvo->target_addr); @@ -2686,15 +2686,15 @@ intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo) static u8 intel_sdvo_get_target_addr(struct intel_sdvo *sdvo) { - struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&sdvo->base); const struct sdvo_device_mapping *my_mapping, *other_mapping; if (sdvo->base.port == PORT_B) { - my_mapping = &dev_priv->display.vbt.sdvo_mappings[0]; - other_mapping = &dev_priv->display.vbt.sdvo_mappings[1]; + my_mapping = &display->vbt.sdvo_mappings[0]; + other_mapping = &display->vbt.sdvo_mappings[1]; } else { - my_mapping = &dev_priv->display.vbt.sdvo_mappings[1]; - other_mapping = &dev_priv->display.vbt.sdvo_mappings[0]; + my_mapping = &display->vbt.sdvo_mappings[1]; + other_mapping = &display->vbt.sdvo_mappings[0]; } /* If the BIOS described our SDVO device, take advantage of it. */ @@ -2730,7 +2730,7 @@ static int intel_sdvo_connector_init(struct intel_sdvo_connector *connector, struct intel_sdvo *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.base.dev); + struct intel_display *display = to_intel_display(&encoder->base); struct intel_sdvo_ddc *ddc = NULL; int ret; @@ -2755,7 +2755,7 @@ intel_sdvo_connector_init(struct intel_sdvo_connector *connector, intel_connector_attach_encoder(&connector->base, &encoder->base); if (ddc) - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] using %s\n", + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] using %s\n", connector->base.base.base.id, connector->base.base.name, ddc->ddc.name); @@ -2798,14 +2798,14 @@ static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) static bool intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type) { + struct intel_display *display = to_intel_display(&intel_sdvo->base); struct drm_encoder *encoder = &intel_sdvo->base.base; struct drm_connector *connector; struct intel_encoder *intel_encoder = to_intel_encoder(encoder); - struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); struct intel_connector *intel_connector; struct intel_sdvo_connector *intel_sdvo_connector; - drm_dbg_kms(&i915->drm, "initialising DVI type 0x%x\n", type); + drm_dbg_kms(display->drm, "initialising DVI type 0x%x\n", type); intel_sdvo_connector = intel_sdvo_connector_alloc(); if (!intel_sdvo_connector) @@ -2851,13 +2851,13 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type) static bool intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type) { - struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); struct drm_encoder *encoder = &intel_sdvo->base.base; struct drm_connector *connector; struct intel_connector *intel_connector; struct intel_sdvo_connector *intel_sdvo_connector; - drm_dbg_kms(&i915->drm, "initialising TV type 0x%x\n", type); + drm_dbg_kms(display->drm, "initialising TV type 0x%x\n", type); intel_sdvo_connector = intel_sdvo_connector_alloc(); if (!intel_sdvo_connector) @@ -2891,13 +2891,13 @@ err: static bool intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type) { - struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); struct drm_encoder *encoder = &intel_sdvo->base.base; struct drm_connector *connector; struct intel_connector *intel_connector; struct intel_sdvo_connector *intel_sdvo_connector; - drm_dbg_kms(&i915->drm, "initialising analog type 0x%x\n", type); + drm_dbg_kms(display->drm, "initialising analog type 0x%x\n", type); intel_sdvo_connector = intel_sdvo_connector_alloc(); if (!intel_sdvo_connector) @@ -2925,12 +2925,11 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type) { struct intel_display *display = to_intel_display(&intel_sdvo->base); struct drm_encoder *encoder = &intel_sdvo->base.base; - struct drm_i915_private *i915 = to_i915(encoder->dev); struct drm_connector *connector; struct intel_connector *intel_connector; struct intel_sdvo_connector *intel_sdvo_connector; - drm_dbg_kms(&i915->drm, "initialising LVDS type 0x%x\n", type); + drm_dbg_kms(display->drm, "initialising LVDS type 0x%x\n", type); intel_sdvo_connector = intel_sdvo_connector_alloc(); if (!intel_sdvo_connector) @@ -2960,12 +2959,12 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type) intel_panel_add_vbt_sdvo_fixed_mode(intel_connector); if (!intel_panel_preferred_fixed_mode(intel_connector)) { - mutex_lock(&i915->drm.mode_config.mutex); + mutex_lock(&display->drm->mode_config.mutex); intel_ddc_get_modes(connector, connector->ddc); intel_panel_add_edid_fixed_modes(intel_connector, false); - mutex_unlock(&i915->drm.mode_config.mutex); + mutex_unlock(&display->drm->mode_config.mutex); } intel_panel_init(intel_connector, NULL); @@ -3014,7 +3013,7 @@ static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type) static bool intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo) { - struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); static const u16 probe_order[] = { SDVO_OUTPUT_TMDS0, SDVO_OUTPUT_TMDS1, @@ -3033,7 +3032,7 @@ intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo) flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags); if (flags == 0) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "%s: Unknown SDVO output type (0x%04x)\n", SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags); return false; @@ -3056,11 +3055,11 @@ intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo) static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) { - struct drm_device *dev = intel_sdvo->base.base.dev; + struct intel_display *display = to_intel_display(&intel_sdvo->base); struct drm_connector *connector, *tmp; list_for_each_entry_safe(connector, tmp, - &dev->mode_config.connector_list, head) { + &display->drm->mode_config.connector_list, head) { if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) { drm_connector_unregister(connector); intel_connector_destroy(connector); @@ -3072,7 +3071,7 @@ static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, struct intel_sdvo_connector *intel_sdvo_connector, int type) { - struct drm_device *dev = intel_sdvo->base.base.dev; + struct intel_display *display = to_intel_display(&intel_sdvo->base); struct intel_sdvo_tv_format format; u32 format_map, i; @@ -3097,7 +3096,7 @@ static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, intel_sdvo_connector->tv_format = - drm_property_create(dev, DRM_MODE_PROP_ENUM, + drm_property_create(display->drm, DRM_MODE_PROP_ENUM, "mode", intel_sdvo_connector->format_supported_num); if (!intel_sdvo_connector->tv_format) return false; @@ -3119,12 +3118,12 @@ static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ return false; \ intel_sdvo_connector->name = \ - drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ + drm_property_create_range(display->drm, 0, #name, 0, data_value[0]); \ if (!intel_sdvo_connector->name) return false; \ state_assignment = response; \ drm_object_attach_property(&connector->base, \ intel_sdvo_connector->name, 0); \ - drm_dbg_kms(dev, #name ": max %d, default %d, current %d\n", \ + drm_dbg_kms(display->drm, #name ": max %d, default %d, current %d\n", \ data_value[0], data_value[1], response); \ } \ } while (0) @@ -3136,8 +3135,7 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, struct intel_sdvo_connector *intel_sdvo_connector, struct intel_sdvo_enhancements_reply enhancements) { - struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); - struct drm_device *dev = intel_sdvo->base.base.dev; + struct intel_display *display = to_intel_display(&intel_sdvo->base); struct drm_connector *connector = &intel_sdvo_connector->base.base; struct drm_connector_state *conn_state = connector->state; struct intel_sdvo_connector_state *sdvo_state = @@ -3160,7 +3158,7 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, intel_sdvo_connector->max_hscan = data_value[0]; intel_sdvo_connector->left = - drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); + drm_property_create_range(display->drm, 0, "left_margin", 0, data_value[0]); if (!intel_sdvo_connector->left) return false; @@ -3168,13 +3166,13 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, intel_sdvo_connector->left, 0); intel_sdvo_connector->right = - drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); + drm_property_create_range(display->drm, 0, "right_margin", 0, data_value[0]); if (!intel_sdvo_connector->right) return false; drm_object_attach_property(&connector->base, intel_sdvo_connector->right, 0); - drm_dbg_kms(&i915->drm, "h_overscan: max %d, default %d, current %d\n", + drm_dbg_kms(display->drm, "h_overscan: max %d, default %d, current %d\n", data_value[0], data_value[1], response); } @@ -3193,7 +3191,7 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, intel_sdvo_connector->max_vscan = data_value[0]; intel_sdvo_connector->top = - drm_property_create_range(dev, 0, + drm_property_create_range(display->drm, 0, "top_margin", 0, data_value[0]); if (!intel_sdvo_connector->top) return false; @@ -3202,14 +3200,14 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, intel_sdvo_connector->top, 0); intel_sdvo_connector->bottom = - drm_property_create_range(dev, 0, + drm_property_create_range(display->drm, 0, "bottom_margin", 0, data_value[0]); if (!intel_sdvo_connector->bottom) return false; drm_object_attach_property(&connector->base, intel_sdvo_connector->bottom, 0); - drm_dbg_kms(&i915->drm, "v_overscan: max %d, default %d, current %d\n", + drm_dbg_kms(display->drm, "v_overscan: max %d, default %d, current %d\n", data_value[0], data_value[1], response); } @@ -3232,13 +3230,13 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, sdvo_state->tv.dot_crawl = response & 0x1; intel_sdvo_connector->dot_crawl = - drm_property_create_range(dev, 0, "dot_crawl", 0, 1); + drm_property_create_range(display->drm, 0, "dot_crawl", 0, 1); if (!intel_sdvo_connector->dot_crawl) return false; drm_object_attach_property(&connector->base, intel_sdvo_connector->dot_crawl, 0); - drm_dbg_kms(&i915->drm, "dot crawl: current %d\n", response); + drm_dbg_kms(display->drm, "dot crawl: current %d\n", response); } return true; @@ -3249,7 +3247,7 @@ intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, struct intel_sdvo_connector *intel_sdvo_connector, struct intel_sdvo_enhancements_reply enhancements) { - struct drm_device *dev = intel_sdvo->base.base.dev; + struct intel_display *display = to_intel_display(&intel_sdvo->base); struct drm_connector *connector = &intel_sdvo_connector->base.base; u16 response, data_value[2]; @@ -3263,7 +3261,7 @@ intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, struct intel_sdvo_connector *intel_sdvo_connector) { - struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); + struct intel_display *display = to_intel_display(&intel_sdvo->base); union { struct intel_sdvo_enhancements_reply reply; u16 response; @@ -3275,7 +3273,7 @@ static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, &enhancements, sizeof(enhancements)) || enhancements.response == 0) { - drm_dbg_kms(&i915->drm, "No enhancement is supported\n"); + drm_dbg_kms(display->drm, "No enhancement is supported\n"); return true; } @@ -3350,8 +3348,8 @@ static int intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc, struct intel_sdvo *sdvo, int ddc_bus) { - struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev); - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + struct intel_display *display = to_intel_display(&sdvo->base); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); ddc->sdvo = sdvo; ddc->ddc_bus = ddc_bus; @@ -3367,32 +3365,34 @@ intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc, return i2c_add_adapter(&ddc->ddc); } -static bool is_sdvo_port_valid(struct drm_i915_private *dev_priv, enum port port) +static bool is_sdvo_port_valid(struct intel_display *display, enum port port) { + struct drm_i915_private *dev_priv = to_i915(display->drm); + if (HAS_PCH_SPLIT(dev_priv)) return port == PORT_B; else return port == PORT_B || port == PORT_C; } -static bool assert_sdvo_port_valid(struct drm_i915_private *dev_priv, - enum port port) +static bool assert_sdvo_port_valid(struct intel_display *display, enum port port) { - return !drm_WARN(&dev_priv->drm, !is_sdvo_port_valid(dev_priv, port), + return !drm_WARN(display->drm, !is_sdvo_port_valid(display, port), "Platform does not support SDVO %c\n", port_name(port)); } -bool intel_sdvo_init(struct drm_i915_private *dev_priv, +bool intel_sdvo_init(struct intel_display *display, i915_reg_t sdvo_reg, enum port port) { + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *intel_encoder; struct intel_sdvo *intel_sdvo; int i; - if (!assert_port_valid(dev_priv, port)) + if (!assert_port_valid(display, port)) return false; - if (!assert_sdvo_port_valid(dev_priv, port)) + if (!assert_sdvo_port_valid(display, port)) return false; intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); @@ -3405,7 +3405,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; intel_encoder->port = port; - drm_encoder_init(&dev_priv->drm, &intel_encoder->base, + drm_encoder_init(display->drm, &intel_encoder->base, &intel_sdvo_enc_funcs, 0, "SDVO %c", port_name(port)); @@ -3419,7 +3419,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, u8 byte; if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "No SDVO device found on %s\n", SDVO_NAME(intel_sdvo)); goto err; @@ -3457,7 +3457,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, } if (!intel_sdvo_output_setup(intel_sdvo)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "SDVO output failed to setup on %s\n", SDVO_NAME(intel_sdvo)); /* Output_setup can leave behind connectors! */ @@ -3494,7 +3494,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, &intel_sdvo->pixel_clock_max)) goto err_output; - drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, " + drm_dbg_kms(display->drm, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "num inputs: %d, " "output 1: %c, output 2: %c\n", diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h b/drivers/gpu/drm/i915/display/intel_sdvo.h index d1815b4103d4..1a9e40fdd8a8 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.h +++ b/drivers/gpu/drm/i915/display/intel_sdvo.h @@ -10,22 +10,22 @@ #include "i915_reg_defs.h" -struct drm_i915_private; enum pipe; enum port; +struct intel_display; #ifdef I915 -bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, +bool intel_sdvo_port_enabled(struct intel_display *display, i915_reg_t sdvo_reg, enum pipe *pipe); -bool intel_sdvo_init(struct drm_i915_private *dev_priv, +bool intel_sdvo_init(struct intel_display *display, i915_reg_t reg, enum port port); #else -static inline bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, +static inline bool intel_sdvo_port_enabled(struct intel_display *display, i915_reg_t sdvo_reg, enum pipe *pipe) { return false; } -static inline bool intel_sdvo_init(struct drm_i915_private *dev_priv, +static inline bool intel_sdvo_init(struct intel_display *display, i915_reg_t reg, enum port port) { return false; diff --git a/drivers/gpu/drm/i915/display/intel_sdvo_regs.h b/drivers/gpu/drm/i915/display/intel_sdvo_regs.h index 54f099abefeb..56c4551abefd 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo_regs.h +++ b/drivers/gpu/drm/i915/display/intel_sdvo_regs.h @@ -244,7 +244,7 @@ struct intel_sdvo_set_target_input_args { * Takes a struct intel_sdvo_output_flags of which outputs are targeted by * future output commands. * - * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12], + * Affected commands include SET_OUTPUT_TIMINGS_PART[12], * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE. */ #define SDVO_CMD_SET_TARGET_OUTPUT 0x11 diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c new file mode 100644 index 000000000000..c6321dafef4f --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2025 Synopsys, Inc., Intel Corporation + */ + +#include <linux/math.h> + +#include "intel_cx0_phy_regs.h" +#include "intel_display_types.h" +#include "intel_snps_phy.h" +#include "intel_snps_phy_regs.h" +#include "intel_snps_hdmi_pll.h" + +#define INTEL_SNPS_PHY_HDMI_4999MHZ 4999999900ULL +#define INTEL_SNPS_PHY_HDMI_16GHZ 16000000000ULL +#define INTEL_SNPS_PHY_HDMI_9999MHZ (2 * INTEL_SNPS_PHY_HDMI_4999MHZ) + +#define CURVE0_MULTIPLIER 1000000000 +#define CURVE1_MULTIPLIER 100 +#define CURVE2_MULTIPLIER 1000000000000ULL + +struct pll_output_params { + u32 ssc_up_spread; + u32 mpll_div5_en; + u32 hdmi_div; + u32 ana_cp_int; + u32 ana_cp_prop; + u32 refclk_postscalar; + u32 tx_clk_div; + u32 fracn_quot; + u32 fracn_rem; + u32 fracn_den; + u32 fracn_en; + u32 pmix_en; + u32 multiplier; + int mpll_ana_v2i; + int ana_freq_vco; +}; + +static s64 interp(s64 x, s64 x1, s64 x2, s64 y1, s64 y2) +{ + s64 dydx; + + dydx = DIV_ROUND_UP_ULL((y2 - y1) * 100000, (x2 - x1)); + + return (y1 + DIV_ROUND_UP_ULL(dydx * (x - x1), 100000)); +} + +static void get_ana_cp_int_prop(u32 vco_clk, + u32 refclk_postscalar, + int mpll_ana_v2i, + int c, int a, + const u64 curve_freq_hz[2][8], + const u64 curve_0[2][8], + const u64 curve_1[2][8], + const u64 curve_2[2][8], + u32 *ana_cp_int, + u32 *ana_cp_prop) +{ + u64 vco_div_refclk_float; + u64 curve_0_interpolated; + u64 curve_2_interpolated; + u64 curve_1_interpolated; + u64 curve_2_scaled1; + u64 curve_2_scaled2; + u64 adjusted_vco_clk1; + u64 adjusted_vco_clk2; + u64 curve_2_scaled_int; + u64 interpolated_product; + u64 scaled_interpolated_sqrt; + u64 scaled_vco_div_refclk1; + u64 scaled_vco_div_refclk2; + u64 ana_cp_int_temp; + u64 temp; + + vco_div_refclk_float = vco_clk * DIV_ROUND_DOWN_ULL(1000000000000ULL, refclk_postscalar); + + /* Interpolate curve values at the target vco_clk frequency */ + curve_0_interpolated = interp(vco_clk, curve_freq_hz[c][a], curve_freq_hz[c][a + 1], + curve_0[c][a], curve_0[c][a + 1]); + + curve_2_interpolated = interp(vco_clk, curve_freq_hz[c][a], curve_freq_hz[c][a + 1], + curve_2[c][a], curve_2[c][a + 1]); + + curve_1_interpolated = interp(vco_clk, curve_freq_hz[c][a], curve_freq_hz[c][a + 1], + curve_1[c][a], curve_1[c][a + 1]); + + curve_1_interpolated = DIV_ROUND_DOWN_ULL(curve_1_interpolated, CURVE1_MULTIPLIER); + + /* + * Scale curve_2_interpolated based on mpll_ana_v2i, for integer part + * ana_cp_int and for the proportional part ana_cp_prop + */ + temp = curve_2_interpolated * (4 - mpll_ana_v2i); + curve_2_scaled1 = DIV_ROUND_DOWN_ULL(temp, 16000); + curve_2_scaled2 = DIV_ROUND_DOWN_ULL(temp, 160); + + /* Scale vco_div_refclk for ana_cp_int */ + scaled_vco_div_refclk1 = 112008301 * DIV_ROUND_DOWN_ULL(vco_div_refclk_float, 100000); + + adjusted_vco_clk1 = CURVE2_MULTIPLIER * + DIV_ROUND_DOWN_ULL(scaled_vco_div_refclk1, (curve_0_interpolated * + DIV_ROUND_DOWN_ULL(curve_1_interpolated, CURVE0_MULTIPLIER))); + + ana_cp_int_temp = + DIV_ROUND_CLOSEST_ULL(DIV_ROUND_DOWN_ULL(adjusted_vco_clk1, curve_2_scaled1), + CURVE2_MULTIPLIER); + + *ana_cp_int = max(1, min(ana_cp_int_temp, 127)); + + curve_2_scaled_int = curve_2_scaled1 * (*ana_cp_int); + + interpolated_product = curve_1_interpolated * + (curve_2_scaled_int * DIV_ROUND_DOWN_ULL(curve_0_interpolated, + CURVE0_MULTIPLIER)); + + scaled_interpolated_sqrt = + int_sqrt(DIV_ROUND_UP_ULL(interpolated_product, vco_div_refclk_float) * + DIV_ROUND_DOWN_ULL(1000000000000ULL, 55)); + + /* Scale vco_div_refclk for ana_cp_int */ + scaled_vco_div_refclk2 = DIV_ROUND_UP_ULL(vco_div_refclk_float, 1000000); + adjusted_vco_clk2 = 1460281 * DIV_ROUND_UP_ULL(scaled_interpolated_sqrt * + scaled_vco_div_refclk2, + curve_1_interpolated); + + *ana_cp_prop = DIV_ROUND_UP_ULL(adjusted_vco_clk2, curve_2_scaled2); + *ana_cp_prop = max(1, min(*ana_cp_prop, 127)); +} + +static void compute_hdmi_tmds_pll(u64 pixel_clock, u32 refclk, + u32 ref_range, + u32 ana_cp_int_gs, + u32 ana_cp_prop_gs, + const u64 curve_freq_hz[2][8], + const u64 curve_0[2][8], + const u64 curve_1[2][8], + const u64 curve_2[2][8], + u32 prescaler_divider, + struct pll_output_params *pll_params) +{ + u64 datarate = pixel_clock * 10000; + u32 ssc_up_spread = 1; + u32 mpll_div5_en = 1; + u32 hdmi_div = 1; + u32 ana_cp_int; + u32 ana_cp_prop; + u32 refclk_postscalar = refclk >> prescaler_divider; + u32 tx_clk_div; + u64 vco_clk; + u64 vco_clk_do_div; + u32 vco_div_refclk_integer; + u32 vco_div_refclk_fracn; + u32 fracn_quot; + u32 fracn_rem; + u32 fracn_den; + u32 fracn_en; + u32 pmix_en; + u32 multiplier; + int mpll_ana_v2i; + int ana_freq_vco = 0; + int c, a = 0; + int i; + + /* Select appropriate v2i point */ + if (datarate <= INTEL_SNPS_PHY_HDMI_9999MHZ) { + mpll_ana_v2i = 2; + tx_clk_div = ilog2(DIV_ROUND_DOWN_ULL(INTEL_SNPS_PHY_HDMI_9999MHZ, datarate)); + } else { + mpll_ana_v2i = 3; + tx_clk_div = ilog2(DIV_ROUND_DOWN_ULL(INTEL_SNPS_PHY_HDMI_16GHZ, datarate)); + } + vco_clk = (datarate << tx_clk_div) >> 1; + + vco_div_refclk_integer = DIV_ROUND_DOWN_ULL(vco_clk, refclk_postscalar); + vco_clk_do_div = do_div(vco_clk, refclk_postscalar); + vco_div_refclk_fracn = DIV_ROUND_DOWN_ULL(vco_clk_do_div << 32, refclk_postscalar); + + fracn_quot = vco_div_refclk_fracn >> 16; + fracn_rem = vco_div_refclk_fracn & 0xffff; + fracn_rem = fracn_rem - (fracn_rem >> 15); + fracn_den = 0xffff; + fracn_en = (fracn_quot != 0 || fracn_rem != 0) ? 1 : 0; + pmix_en = fracn_en; + multiplier = (vco_div_refclk_integer - 16) * 2; + /* Curve selection for ana_cp_* calculations. One curve hardcoded per v2i range */ + c = mpll_ana_v2i - 2; + + /* Find the right segment of the table */ + for (i = 0; i < 8; i += 2) { + if (vco_clk <= curve_freq_hz[c][i + 1]) { + a = i; + ana_freq_vco = 3 - (a >> 1); + break; + } + } + + get_ana_cp_int_prop(vco_clk, refclk_postscalar, mpll_ana_v2i, c, a, + curve_freq_hz, curve_0, curve_1, curve_2, + &ana_cp_int, &ana_cp_prop); + + pll_params->ssc_up_spread = ssc_up_spread; + pll_params->mpll_div5_en = mpll_div5_en; + pll_params->hdmi_div = hdmi_div; + pll_params->ana_cp_int = ana_cp_int; + pll_params->refclk_postscalar = refclk_postscalar; + pll_params->tx_clk_div = tx_clk_div; + pll_params->fracn_quot = fracn_quot; + pll_params->fracn_rem = fracn_rem; + pll_params->fracn_den = fracn_den; + pll_params->fracn_en = fracn_en; + pll_params->pmix_en = pmix_en; + pll_params->multiplier = multiplier; + pll_params->ana_cp_prop = ana_cp_prop; + pll_params->mpll_ana_v2i = mpll_ana_v2i; + pll_params->ana_freq_vco = ana_freq_vco; +} + +void intel_snps_hdmi_pll_compute_mpllb(struct intel_mpllb_state *pll_state, u64 pixel_clock) +{ + /* x axis frequencies. One curve in each array per v2i point */ + static const u64 dg2_curve_freq_hz[2][8] = { + { 2500000000ULL, 3000000000ULL, 3000000000ULL, 3500000000ULL, 3500000000ULL, + 4000000000ULL, 4000000000ULL, 5000000000ULL }, + { 4000000000ULL, 4600000000ULL, 4601000000ULL, 5400000000ULL, 5401000000ULL, + 6600000000ULL, 6601000000ULL, 8001000000ULL } + }; + + /* y axis heights multiplied with 1000000000 */ + static const u64 dg2_curve_0[2][8] = { + { 34149871, 39803269, 36034544, 40601014, 35646940, 40016109, 35127987, 41889522 }, + { 70000000, 78770454, 70451838, 80427119, 70991400, 84230173, 72945921, 87064218 } + }; + + /* Multiplied with 100 */ + static const u64 dg2_curve_1[2][8] = { + { 85177000000000ULL, 79385227160000ULL, 95672603580000ULL, 88857207160000ULL, + 109379790900000ULL, 103528193900000ULL, 131941242400000ULL, 117279000000000ULL }, + { 60255000000000ULL, 55569000000000ULL, 72036000000000ULL, 69509000000000ULL, + 81785000000000ULL, 731030000000000ULL, 96591000000000ULL, 69077000000000ULL } + }; + + /* Multiplied with 1000000000000 */ + static const u64 dg2_curve_2[2][8] = { + { 2186930000ULL, 2835287134ULL, 2395395343ULL, 2932270687ULL, 2351887545ULL, + 2861031697ULL, 2294149152ULL, 3091730000ULL }, + { 4560000000ULL, 5570000000ULL, 4610000000ULL, 5770000000ULL, 4670000000ULL, + 6240000000ULL, 4890000000ULL, 6600000000ULL } + }; + + struct pll_output_params pll_params; + u32 refclk = 100000000; + u32 prescaler_divider = 1; + u32 ref_range = 3; + u32 ana_cp_int_gs = 64; + u32 ana_cp_prop_gs = 124; + + compute_hdmi_tmds_pll(pixel_clock, refclk, ref_range, ana_cp_int_gs, ana_cp_prop_gs, + dg2_curve_freq_hz, dg2_curve_0, dg2_curve_1, dg2_curve_2, + prescaler_divider, &pll_params); + + pll_state->clock = pixel_clock; + pll_state->ref_control = + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, ref_range); + pll_state->mpllb_cp = + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, pll_params.ana_cp_int) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, pll_params.ana_cp_prop) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, ana_cp_int_gs) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, ana_cp_prop_gs); + pll_state->mpllb_div = + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, pll_params.mpll_div5_en) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_params.tx_clk_div) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, pll_params.pmix_en) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, pll_params.mpll_ana_v2i) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, pll_params.ana_freq_vco); + pll_state->mpllb_div2 = + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, prescaler_divider) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, pll_params.multiplier) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, pll_params.hdmi_div); + pll_state->mpllb_fracn1 = + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, pll_params.fracn_en) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, pll_params.fracn_den); + pll_state->mpllb_fracn2 = + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, pll_params.fracn_quot) | + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, pll_params.fracn_rem); + pll_state->mpllb_sscen = + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, pll_params.ssc_up_spread); +} + +void intel_snps_hdmi_pll_compute_c10pll(struct intel_c10pll_state *pll_state, u64 pixel_clock) +{ + /* x axis frequencies. One curve in each array per v2i point */ + static const u64 c10_curve_freq_hz[2][8] = { + { 2500000000ULL, 3000000000ULL, 3000000000ULL, 3500000000ULL, 3500000000ULL, + 4000000000ULL, 4000000000ULL, 5000000000ULL }, + { 4000000000ULL, 4600000000ULL, 4601000000ULL, 5400000000ULL, 5401000000ULL, + 6600000000ULL, 6601000000ULL, 8001000000ULL } + }; + + /* y axis heights multiplied with 1000000000 */ + static const u64 c10_curve_0[2][8] = { + { 41174500, 48605500, 42973700, 49433100, 42408600, 47681900, 40297400, 49131400 }, + { 82056800, 94420700, 82323400, 96370600, 81273300, 98630100, 81728700, 99105700} + }; + + static const u64 c10_curve_1[2][8] = { + { 73300000000000ULL, 66000000000000ULL, 83100000000000ULL, 75300000000000ULL, + 99700000000000ULL, 92300000000000ULL, 125000000000000ULL, 110000000000000ULL }, + { 53700000000000ULL, 47700000000000ULL, 62200000000000ULL, 54400000000000ULL, + 75100000000000ULL, 63400000000000ULL, 90600000000000ULL, 76300000000000ULL } + }; + + /* Multiplied with 1000000000000 */ + static const u64 c10_curve_2[2][8] = { + { 2415790000ULL, 3136460000ULL, 2581990000ULL, 3222670000ULL, 2529330000ULL, + 3042020000ULL, 2336970000ULL, 3191460000ULL}, + { 4808390000ULL, 5994250000ULL, 4832730000ULL, 6193730000ULL, 4737700000ULL, + 6428750000ULL, 4779200000ULL, 6479340000ULL } + }; + + struct pll_output_params pll_params; + u32 refclk = 38400000; + u32 prescaler_divider = 0; + u32 ref_range = 1; + u32 ana_cp_int_gs = 30; + u32 ana_cp_prop_gs = 28; + + compute_hdmi_tmds_pll(pixel_clock, refclk, ref_range, + ana_cp_int_gs, ana_cp_prop_gs, + c10_curve_freq_hz, c10_curve_0, + c10_curve_1, c10_curve_2, prescaler_divider, + &pll_params); + + pll_state->tx = 0x10; + pll_state->cmn = 0x1; + pll_state->pll[0] = REG_FIELD_PREP(C10_PLL0_DIV5CLK_EN, pll_params.mpll_div5_en) | + REG_FIELD_PREP(C10_PLL0_FRACEN, pll_params.fracn_en) | + REG_FIELD_PREP(C10_PLL0_PMIX_EN, pll_params.pmix_en) | + REG_FIELD_PREP(C10_PLL0_ANA_FREQ_VCO_MASK, pll_params.ana_freq_vco); + pll_state->pll[2] = REG_FIELD_PREP(C10_PLL2_MULTIPLIERL_MASK, pll_params.multiplier); + pll_state->pll[3] = REG_FIELD_PREP(C10_PLL3_MULTIPLIERH_MASK, pll_params.multiplier >> 8); + pll_state->pll[8] = REG_FIELD_PREP(C10_PLL8_SSC_UP_SPREAD, pll_params.ssc_up_spread); + pll_state->pll[9] = REG_FIELD_PREP(C10_PLL9_FRACN_DENL_MASK, pll_params.fracn_den); + pll_state->pll[10] = REG_FIELD_PREP(C10_PLL10_FRACN_DENH_MASK, pll_params.fracn_den >> 8); + pll_state->pll[11] = REG_FIELD_PREP(C10_PLL11_FRACN_QUOT_L_MASK, pll_params.fracn_quot); + pll_state->pll[12] = REG_FIELD_PREP(C10_PLL12_FRACN_QUOT_H_MASK, + pll_params.fracn_quot >> 8); + + pll_state->pll[13] = REG_FIELD_PREP(C10_PLL13_FRACN_REM_L_MASK, pll_params.fracn_rem); + pll_state->pll[14] = REG_FIELD_PREP(C10_PLL14_FRACN_REM_H_MASK, pll_params.fracn_rem >> 8); + pll_state->pll[15] = REG_FIELD_PREP(C10_PLL15_TXCLKDIV_MASK, pll_params.tx_clk_div) | + REG_FIELD_PREP(C10_PLL15_HDMIDIV_MASK, pll_params.hdmi_div); + pll_state->pll[16] = REG_FIELD_PREP(C10_PLL16_ANA_CPINT, pll_params.ana_cp_int) | + REG_FIELD_PREP(C10_PLL16_ANA_CPINTGS_L, ana_cp_int_gs); + pll_state->pll[17] = REG_FIELD_PREP(C10_PLL17_ANA_CPINTGS_H_MASK, ana_cp_int_gs >> 1) | + REG_FIELD_PREP(C10_PLL17_ANA_CPPROP_L_MASK, pll_params.ana_cp_prop); + pll_state->pll[18] = + REG_FIELD_PREP(C10_PLL18_ANA_CPPROP_H_MASK, pll_params.ana_cp_prop >> 2) | + REG_FIELD_PREP(C10_PLL18_ANA_CPPROPGS_L_MASK, ana_cp_prop_gs); + + pll_state->pll[19] = REG_FIELD_PREP(C10_PLL19_ANA_CPPROPGS_H_MASK, ana_cp_prop_gs >> 3) | + REG_FIELD_PREP(C10_PLL19_ANA_V2I_MASK, pll_params.mpll_ana_v2i); +} diff --git a/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h new file mode 100644 index 000000000000..aac70c4bb0f8 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2025 Synopsys, Inc., Intel Corporation + */ + +#ifndef __INTEL_SNPS_HDMI_PLL_H__ +#define __INTEL_SNPS_HDMI_PLL_H__ + +#include <linux/types.h> + +struct intel_c10pll_state; +struct intel_mpllb_state; + +void intel_snps_hdmi_pll_compute_mpllb(struct intel_mpllb_state *pll_state, u64 pixel_clock); +void intel_snps_hdmi_pll_compute_c10pll(struct intel_c10pll_state *pll_state, u64 pixel_clock); + +#endif /* __INTEL_SNPS_HDMI_PLL_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index 41fe26dc200b..b9acd9fe160c 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -5,12 +5,13 @@ #include <linux/math.h> -#include "i915_drv.h" #include "i915_reg.h" +#include "i915_utils.h" #include "intel_ddi.h" #include "intel_ddi_buf_trans.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_snps_hdmi_pll.h" #include "intel_snps_phy.h" #include "intel_snps_phy_regs.h" @@ -26,12 +27,12 @@ * since it is not handled by the shared DPLL framework as on other platforms. */ -void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915) +void intel_snps_phy_wait_for_calibration(struct intel_display *display) { enum phy phy; for_each_phy_masked(phy, ~0) { - if (!intel_phy_is_snps(i915, phy)) + if (!intel_phy_is_snps(display, phy)) continue; /* @@ -39,16 +40,16 @@ void intel_snps_phy_wait_for_calibration(struct drm_i915_private *i915) * which phy was affected and skip setup of the corresponding * output later. */ - if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy), + if (intel_de_wait_for_clear(display, DG2_PHY_MISC(phy), DG2_PHY_DP_TX_ACK_MASK, 25)) - i915->display.snps.phy_failed_calibration |= BIT(phy); + display->snps.phy_failed_calibration |= BIT(phy); } } void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder, bool enable) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); u32 val; @@ -57,20 +58,20 @@ void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder, val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, enable ? 2 : 3); - intel_de_rmw(i915, SNPS_PHY_TX_REQ(phy), + intel_de_rmw(display, SNPS_PHY_TX_REQ(phy), SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val); } void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_ddi_buf_trans *trans; enum phy phy = intel_encoder_to_phy(encoder); int n_entries, ln; trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) + if (drm_WARN_ON_ONCE(display->drm, !trans)) return; for (ln = 0; ln < 4; ln++) { @@ -81,7 +82,7 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor); val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor); - intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val); + intel_de_write(display, SNPS_PHY_TX_EQ(ln, phy), val); } } @@ -521,7 +522,7 @@ static const struct intel_mpllb_state dg2_hdmi_148_5 = { REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), }; -/* values in the below table are calculted using the algo */ +/* values in the below table are calculated using the algo */ static const struct intel_mpllb_state dg2_hdmi_25200 = { .clock = 25200, .ref_control = @@ -1788,24 +1789,9 @@ intel_mpllb_tables_get(struct intel_crtc_state *crtc_state, int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); const struct intel_mpllb_state * const *tables; int i; - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { - if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock) - != MODE_OK) { - /* - * FIXME: Can only support fixed HDMI frequencies - * until we have a proper algorithm under a valid - * license. - */ - drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d\n", - crtc_state->port_clock); - return -EINVAL; - } - } - tables = intel_mpllb_tables_get(crtc_state, encoder); if (!tables) return -EINVAL; @@ -1817,13 +1803,21 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, } } + /* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed tables */ + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { + intel_snps_hdmi_pll_compute_mpllb(&crtc_state->dpll_hw_state.mpllb, + crtc_state->port_clock); + + return 0; + } + return -EINVAL; } void intel_mpllb_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb; enum phy phy = intel_encoder_to_phy(encoder); i915_reg_t enable_reg = (phy <= PHY_D ? @@ -1833,13 +1827,13 @@ void intel_mpllb_enable(struct intel_encoder *encoder, * 3. Software programs the following PLL registers for the desired * frequency. */ - intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp); - intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div); - intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2); - intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen); - intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep); - intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1); - intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2); + intel_de_write(display, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp); + intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div); + intel_de_write(display, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2); + intel_de_write(display, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen); + intel_de_write(display, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep); + intel_de_write(display, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1); + intel_de_write(display, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2); /* * 4. If the frequency will result in a change to the voltage @@ -1850,7 +1844,7 @@ void intel_mpllb_enable(struct intel_encoder *encoder, */ /* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */ - intel_de_rmw(dev_priv, enable_reg, 0, PLL_ENABLE); + intel_de_rmw(display, enable_reg, 0, PLL_ENABLE); /* * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This @@ -1859,7 +1853,7 @@ void intel_mpllb_enable(struct intel_encoder *encoder, * PLL because that will start the PLL before it has sampled the * divider values. */ - intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), + intel_de_write(display, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN); /* @@ -1867,8 +1861,8 @@ void intel_mpllb_enable(struct intel_encoder *encoder, * is locked at new settings. This register bit is sampling PHY * dp_mpllb_state interface signal. */ - if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5)) - drm_dbg_kms(&dev_priv->drm, "Port %c PLL not locked\n", phy_name(phy)); + if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 5)) + drm_dbg_kms(display->drm, "Port %c PLL not locked\n", phy_name(phy)); /* * 11. If the frequency will result in a change to the voltage @@ -1881,7 +1875,7 @@ void intel_mpllb_enable(struct intel_encoder *encoder, void intel_mpllb_disable(struct intel_encoder *encoder) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); i915_reg_t enable_reg = (phy <= PHY_D ? DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); @@ -1895,20 +1889,20 @@ void intel_mpllb_disable(struct intel_encoder *encoder) */ /* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */ - intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0); + intel_de_rmw(display, enable_reg, PLL_ENABLE, 0); /* * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0". * This will allow the PLL to stop running. */ - intel_de_rmw(i915, SNPS_PHY_MPLLB_DIV(phy), SNPS_PHY_MPLLB_FORCE_EN, 0); + intel_de_rmw(display, SNPS_PHY_MPLLB_DIV(phy), SNPS_PHY_MPLLB_FORCE_EN, 0); /* * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment * (dp_txX_ack) that the new transmitter setting request is completed. */ - if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 5)) - drm_err(&i915->drm, "Port %c PLL not locked\n", phy_name(phy)); + if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 5)) + drm_err(display->drm, "Port %c PLL not locked\n", phy_name(phy)); /* * 6. If the frequency will result in a change to the voltage @@ -1953,16 +1947,16 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, struct intel_mpllb_state *pll_state) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - pll_state->mpllb_cp = intel_de_read(dev_priv, SNPS_PHY_MPLLB_CP(phy)); - pll_state->mpllb_div = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV(phy)); - pll_state->mpllb_div2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV2(phy)); - pll_state->mpllb_sscen = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy)); - pll_state->mpllb_sscstep = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy)); - pll_state->mpllb_fracn1 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy)); - pll_state->mpllb_fracn2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy)); + pll_state->mpllb_cp = intel_de_read(display, SNPS_PHY_MPLLB_CP(phy)); + pll_state->mpllb_div = intel_de_read(display, SNPS_PHY_MPLLB_DIV(phy)); + pll_state->mpllb_div2 = intel_de_read(display, SNPS_PHY_MPLLB_DIV2(phy)); + pll_state->mpllb_sscen = intel_de_read(display, SNPS_PHY_MPLLB_SSCEN(phy)); + pll_state->mpllb_sscstep = intel_de_read(display, SNPS_PHY_MPLLB_SSCSTEP(phy)); + pll_state->mpllb_fracn1 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN1(phy)); + pll_state->mpllb_fracn2 = intel_de_read(display, SNPS_PHY_MPLLB_FRACN2(phy)); /* * REF_CONTROL is under firmware control and never programmed by the @@ -1970,7 +1964,7 @@ void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, * only tells us the expected value for one field in this register, * so we'll only read out those specific bits here. */ - pll_state->ref_control = intel_de_read(dev_priv, SNPS_PHY_REF_CONTROL(phy)) & + pll_state->ref_control = intel_de_read(display, SNPS_PHY_REF_CONTROL(phy)) & SNPS_PHY_REF_CONTROL_REF_RANGE; /* @@ -1982,31 +1976,17 @@ void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN; } -int intel_snps_phy_check_hdmi_link_rate(int clock) -{ - const struct intel_mpllb_state * const *tables = dg2_hdmi_tables; - int i; - - for (i = 0; tables[i]; i++) { - if (clock == tables[i]->clock) - return MODE_OK; - } - - return MODE_CLOCK_RANGE; -} - void intel_mpllb_state_verify(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct intel_mpllb_state mpllb_hw_state = {}; const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->dpll_hw_state.mpllb; struct intel_encoder *encoder; - if (!IS_DG2(i915)) + if (!display->platform.dg2) return; if (!new_crtc_state->hw.active) diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h index bc08b92a7cd9..7f96da22d028 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.h +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h @@ -8,15 +8,15 @@ #include <linux/types.h> -struct drm_i915_private; +enum phy; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; +struct intel_display; struct intel_encoder; struct intel_mpllb_state; -enum phy; -void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv); +void intel_snps_phy_wait_for_calibration(struct intel_display *display); void intel_snps_phy_update_psr_power_state(struct intel_encoder *encoder, bool enable); @@ -30,7 +30,6 @@ void intel_mpllb_readout_hw_state(struct intel_encoder *encoder, int intel_mpllb_calc_port_clock(struct intel_encoder *encoder, const struct intel_mpllb_state *pll_state); -int intel_snps_phy_check_hdmi_link_rate(int clock); void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_mpllb_state_verify(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index e6fadcef58e0..1ad6c8a94b3d 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -66,8 +66,8 @@ static void i9xx_plane_linear_gamma(u16 gamma[8]) static void chv_sprite_update_csc(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum plane_id plane_id = plane->id; /* @@ -138,8 +138,8 @@ chv_sprite_update_csc(const struct intel_plane_state *plane_state) static void vlv_sprite_update_clrc(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum pipe pipe = plane->pipe; enum plane_id plane_id = plane->id; @@ -253,21 +253,6 @@ int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state, return DIV_ROUND_UP(pixel_rate * num, den); } -static unsigned int vlv_sprite_min_alignment(struct intel_plane *plane, - const struct drm_framebuffer *fb, - int color_plane) -{ - switch (fb->modifier) { - case I915_FORMAT_MOD_X_TILED: - return 4 * 1024; - case DRM_FORMAT_MOD_LINEAR: - return 128 * 1024; - default: - MISSING_CASE(fb->modifier); - return 0; - } -} - static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) { u32 sprctl = 0; @@ -356,8 +341,8 @@ static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state, static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum pipe pipe = plane->pipe; enum plane_id plane_id = plane->id; @@ -383,7 +368,7 @@ vlv_sprite_update_noarm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; enum plane_id plane_id = plane->id; int crtc_x = plane_state->uapi.dst.x1; @@ -405,8 +390,7 @@ vlv_sprite_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; enum plane_id plane_id = plane->id; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; @@ -419,7 +403,7 @@ vlv_sprite_update_arm(struct intel_dsb *dsb, linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) + if (display->platform.cherryview && pipe == PIPE_B) chv_sprite_update_csc(plane_state); if (key->flags) { @@ -455,7 +439,7 @@ vlv_sprite_disable_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; enum plane_id plane_id = plane->id; @@ -463,19 +447,29 @@ vlv_sprite_disable_arm(struct intel_dsb *dsb, intel_de_write_fw(display, SPSURF(pipe, plane_id), 0); } +static void vlv_sprite_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + + error->ctl = intel_de_read(display, SPCNTR(crtc->pipe, plane->id)); + error->surf = intel_de_read(display, SPSURF(crtc->pipe, plane->id)); + error->surflive = intel_de_read(display, SPSURFLIVE(crtc->pipe, plane->id)); +} + static bool vlv_sprite_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; enum plane_id plane_id = plane->id; intel_wakeref_t wakeref; bool ret; power_domain = POWER_DOMAIN_PIPE(plane->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; @@ -483,7 +477,7 @@ vlv_sprite_get_hw_state(struct intel_plane *plane, *pipe = plane->pipe; - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } @@ -661,19 +655,17 @@ static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; return fb->format->cpp[0] == 8 && - (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)); + (display->platform.ivybridge || display->platform.haswell); } static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; @@ -681,7 +673,7 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state, sprctl = SPRITE_ENABLE; - if (IS_IVYBRIDGE(dev_priv)) + if (display->platform.ivybridge) sprctl |= SPRITE_TRICKLE_FEED_DISABLE; switch (fb->format->format) { @@ -770,8 +762,8 @@ static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state, static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); enum pipe pipe = plane->pipe; u16 gamma[18]; int i; @@ -803,8 +795,7 @@ ivb_sprite_update_noarm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; @@ -825,7 +816,7 @@ ivb_sprite_update_noarm(struct intel_dsb *dsb, SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x)); intel_de_write_fw(display, SPRSIZE(pipe), SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1)); - if (IS_IVYBRIDGE(dev_priv)) + if (display->platform.ivybridge) intel_de_write_fw(display, SPRSCALE(pipe), sprscale); } @@ -835,8 +826,7 @@ ivb_sprite_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; u32 sprsurf_offset = plane_state->view.color_plane[0].offset; @@ -857,7 +847,7 @@ ivb_sprite_update_arm(struct intel_dsb *dsb, /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET * register */ - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { + if (display->platform.haswell || display->platform.broadwell) { intel_de_write_fw(display, SPROFFSET(pipe), SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x)); } else { @@ -883,29 +873,38 @@ ivb_sprite_disable_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; intel_de_write_fw(display, SPRCTL(pipe), 0); /* Disable the scaler */ - if (IS_IVYBRIDGE(dev_priv)) + if (display->platform.ivybridge) intel_de_write_fw(display, SPRSCALE(pipe), 0); intel_de_write_fw(display, SPRSURF(pipe), 0); } +static void ivb_sprite_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + + error->ctl = intel_de_read(display, SPRCTL(crtc->pipe)); + error->surf = intel_de_read(display, SPRSURF(crtc->pipe)); + error->surflive = intel_de_read(display, SPRSURFLIVE(crtc->pipe)); +} + static bool ivb_sprite_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; bool ret; power_domain = POWER_DOMAIN_PIPE(plane->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; @@ -913,7 +912,7 @@ ivb_sprite_get_hw_state(struct intel_plane *plane, *pipe = plane->pipe; - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } @@ -995,6 +994,11 @@ static unsigned int g4x_sprite_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { + struct intel_display *display = to_intel_display(plane); + + if (intel_scanout_needs_vtd_wa(display)) + return 128 * 1024; + return 4 * 1024; } @@ -1014,8 +1018,7 @@ static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; @@ -1023,7 +1026,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, dvscntr = DVS_ENABLE; - if (IS_SANDYBRIDGE(dev_priv)) + if (display->platform.sandybridge) dvscntr |= DVS_TRICKLE_FEED_DISABLE; switch (fb->format->format) { @@ -1084,8 +1087,8 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum pipe pipe = plane->pipe; u16 gamma[8]; @@ -1114,8 +1117,8 @@ static void ilk_sprite_linear_gamma(u16 gamma[17]) static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum pipe pipe = plane->pipe; u16 gamma[17]; @@ -1144,7 +1147,7 @@ g4x_sprite_update_noarm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; @@ -1174,8 +1177,7 @@ g4x_sprite_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; u32 dvssurf_offset = plane_state->view.color_plane[0].offset; @@ -1207,7 +1209,7 @@ g4x_sprite_update_arm(struct intel_dsb *dsb, intel_de_write_fw(display, DVSSURF(pipe), intel_plane_ggtt_offset(plane_state) + dvssurf_offset); - if (IS_G4X(dev_priv)) + if (display->platform.g4x) g4x_sprite_update_gamma(plane_state); else ilk_sprite_update_gamma(plane_state); @@ -1218,7 +1220,7 @@ g4x_sprite_disable_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; intel_de_write_fw(display, DVSCNTR(pipe), 0); @@ -1227,18 +1229,28 @@ g4x_sprite_disable_arm(struct intel_dsb *dsb, intel_de_write_fw(display, DVSSURF(pipe), 0); } +static void g4x_sprite_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + + error->ctl = intel_de_read(display, DVSCNTR(crtc->pipe)); + error->surf = intel_de_read(display, DVSSURF(crtc->pipe)); + error->surflive = intel_de_read(display, DVSSURFLIVE(crtc->pipe)); +} + static bool g4x_sprite_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; bool ret; power_domain = POWER_DOMAIN_PIPE(plane->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; @@ -1246,7 +1258,7 @@ g4x_sprite_get_hw_state(struct intel_plane *plane, *pipe = plane->pipe; - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } @@ -1272,7 +1284,7 @@ static int g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(crtc_state); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; const struct drm_rect *src = &plane_state->uapi.src; const struct drm_rect *dst = &plane_state->uapi.dst; @@ -1338,9 +1350,7 @@ static int g4x_sprite_check(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(crtc_state); - struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane_state); int min_scale = DRM_PLANE_NO_SCALING; int max_scale = DRM_PLANE_NO_SCALING; int ret; @@ -1349,7 +1359,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state, if (DISPLAY_VER(display) < 7) { min_scale = 1; max_scale = 16 << 16; - } else if (IS_IVYBRIDGE(dev_priv)) { + } else if (display->platform.ivybridge) { min_scale = 1; max_scale = 2 << 16; } @@ -1385,13 +1395,11 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state, int chv_plane_check_rotation(const struct intel_plane_state *plane_state) { - struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane_state); unsigned int rotation = plane_state->hw.rotation; /* CHV ignores the mirror bit when the rotate bit is set :( */ - if (IS_CHERRYVIEW(dev_priv) && + if (display->platform.cherryview && rotation & DRM_MODE_ROTATE_180 && rotation & DRM_MODE_REFLECT_X) { drm_dbg_kms(display->drm, @@ -1593,10 +1601,9 @@ static const struct drm_plane_funcs vlv_sprite_funcs = { }; struct intel_plane * -intel_sprite_plane_create(struct drm_i915_private *dev_priv, +intel_sprite_plane_create(struct intel_display *display, enum pipe pipe, int sprite) { - struct intel_display *display = &dev_priv->display; struct intel_plane *plane; const struct drm_plane_funcs *plane_funcs; unsigned int supported_rotations; @@ -1609,17 +1616,22 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, if (IS_ERR(plane)) return plane; - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + if (display->platform.valleyview || display->platform.cherryview) { plane->update_noarm = vlv_sprite_update_noarm; plane->update_arm = vlv_sprite_update_arm; plane->disable_arm = vlv_sprite_disable_arm; + plane->capture_error = vlv_sprite_capture_error; plane->get_hw_state = vlv_sprite_get_hw_state; plane->check_plane = vlv_sprite_check; plane->max_stride = i965_plane_max_stride; - plane->min_alignment = vlv_sprite_min_alignment; + plane->min_alignment = vlv_plane_min_alignment; plane->min_cdclk = vlv_plane_min_cdclk; - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { + /* FIXME undocumented for VLV/CHV so not sure what's actually needed */ + if (intel_scanout_needs_vtd_wa(display)) + plane->vtd_guard = 128; + + if (display->platform.cherryview && pipe == PIPE_B) { formats = chv_pipe_b_sprite_formats; num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats); } else { @@ -1632,10 +1644,11 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->update_noarm = ivb_sprite_update_noarm; plane->update_arm = ivb_sprite_update_arm; plane->disable_arm = ivb_sprite_disable_arm; + plane->capture_error = ivb_sprite_capture_error; plane->get_hw_state = ivb_sprite_get_hw_state; plane->check_plane = g4x_sprite_check; - if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + if (display->platform.broadwell || display->platform.haswell) { plane->max_stride = hsw_sprite_max_stride; plane->min_cdclk = hsw_plane_min_cdclk; } else { @@ -1645,6 +1658,9 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->min_alignment = g4x_sprite_min_alignment; + if (intel_scanout_needs_vtd_wa(display)) + plane->vtd_guard = 64; + formats = snb_sprite_formats; num_formats = ARRAY_SIZE(snb_sprite_formats); @@ -1653,13 +1669,17 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->update_noarm = g4x_sprite_update_noarm; plane->update_arm = g4x_sprite_update_arm; plane->disable_arm = g4x_sprite_disable_arm; + plane->capture_error = g4x_sprite_capture_error; plane->get_hw_state = g4x_sprite_get_hw_state; plane->check_plane = g4x_sprite_check; plane->max_stride = g4x_sprite_max_stride; plane->min_alignment = g4x_sprite_min_alignment; plane->min_cdclk = g4x_sprite_min_cdclk; - if (IS_SANDYBRIDGE(dev_priv)) { + if (intel_scanout_needs_vtd_wa(display)) + plane->vtd_guard = 64; + + if (display->platform.sandybridge) { formats = snb_sprite_formats; num_formats = ARRAY_SIZE(snb_sprite_formats); @@ -1672,7 +1692,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, } } - if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { + if (display->platform.cherryview && pipe == PIPE_B) { supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X; @@ -1685,7 +1705,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->id = PLANE_SPRITE0 + sprite; plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); - modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); + modifiers = intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILING_X); ret = drm_universal_plane_init(display->drm, &plane->base, 0, plane_funcs, diff --git a/drivers/gpu/drm/i915/display/intel_sprite.h b/drivers/gpu/drm/i915/display/intel_sprite.h index 531079979c05..c33a2808da8c 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.h +++ b/drivers/gpu/drm/i915/display/intel_sprite.h @@ -8,13 +8,13 @@ #include <linux/types.h> -struct drm_i915_private; struct intel_crtc_state; +struct intel_display; struct intel_plane_state; enum pipe; #ifdef I915 -struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, +struct intel_plane *intel_sprite_plane_create(struct intel_display *display, enum pipe pipe, int plane); int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state); int chv_plane_check_rotation(const struct intel_plane_state *plane_state); @@ -26,7 +26,7 @@ int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state, int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); #else -static inline struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv, +static inline struct intel_plane *intel_sprite_plane_create(struct intel_display *display, int pipe, int plane) { return NULL; diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 13811244c82b..b8d14ed8a56e 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -177,21 +177,21 @@ bool intel_tc_port_handles_hpd_glitches(struct intel_digital_port *dig_port) */ bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); struct intel_tc_port *tc = to_tc_port(dig_port); return tc_phy_cold_off_domain(tc) == - intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); + intel_display_power_legacy_aux_domain(display, dig_port->aux_ch); } static intel_wakeref_t __tc_cold_block(struct intel_tc_port *tc, enum intel_display_power_domain *domain) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); *domain = tc_phy_cold_off_domain(tc); - return intel_display_power_get(i915, *domain); + return intel_display_power_get(display, *domain); } static intel_wakeref_t @@ -211,9 +211,9 @@ static void __tc_cold_unblock(struct intel_tc_port *tc, enum intel_display_power_domain domain, intel_wakeref_t wakeref) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); - intel_display_power_put(i915, domain, wakeref); + intel_display_power_put(display, domain, wakeref); } static void @@ -230,21 +230,21 @@ tc_cold_unblock(struct intel_tc_port *tc, intel_wakeref_t wakeref) static void assert_display_core_power_enabled(struct intel_tc_port *tc) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); - drm_WARN_ON(&i915->drm, - !intel_display_power_is_enabled(i915, POWER_DOMAIN_DISPLAY_CORE)); + drm_WARN_ON(display->drm, + !intel_display_power_is_enabled(display, POWER_DOMAIN_DISPLAY_CORE)); } static void assert_tc_cold_blocked(struct intel_tc_port *tc) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); bool enabled; - enabled = intel_display_power_is_enabled(i915, + enabled = intel_display_power_is_enabled(display, tc_phy_cold_off_domain(tc)); - drm_WARN_ON(&i915->drm, !enabled); + drm_WARN_ON(display->drm, !enabled); } static enum intel_display_power_domain @@ -258,10 +258,10 @@ tc_port_power_domain(struct intel_tc_port *tc) static void assert_tc_port_power_enabled(struct intel_tc_port *tc) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); - drm_WARN_ON(&i915->drm, - !intel_display_power_is_enabled(i915, tc_port_power_domain(tc))); + drm_WARN_ON(display->drm, + !intel_display_power_is_enabled(display, tc_port_power_domain(tc))); } static u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port) @@ -296,12 +296,13 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) { + struct intel_display *display = to_intel_display(dig_port); struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); intel_wakeref_t wakeref; u32 val, pin_assignment; - with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); pin_assignment = @@ -321,11 +322,11 @@ static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); intel_wakeref_t wakeref; u32 pin_mask; - with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port); switch (pin_mask) { @@ -342,11 +343,11 @@ static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) static int intel_tc_port_get_max_lane_count(struct intel_digital_port *dig_port) { - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_display *display = to_intel_display(dig_port); intel_wakeref_t wakeref; u32 lane_mask = 0; - with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) lane_mask = intel_tc_port_get_lane_mask(dig_port); switch (lane_mask) { @@ -477,17 +478,18 @@ static void tc_phy_load_fia_params(struct intel_tc_port *tc, bool modular_fia) static enum intel_display_power_domain icl_tc_phy_cold_off_domain(struct intel_tc_port *tc) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); struct intel_digital_port *dig_port = tc->dig_port; if (tc->legacy_port) - return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); + return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch); return POWER_DOMAIN_TC_COLD_OFF; } static u32 icl_tc_phy_hpd_live_status(struct intel_tc_port *tc) { + struct intel_display *display = to_intel_display(tc->dig_port); struct drm_i915_private *i915 = tc_to_i915(tc); struct intel_digital_port *dig_port = tc->dig_port; u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin]; @@ -496,7 +498,7 @@ static u32 icl_tc_phy_hpd_live_status(struct intel_tc_port *tc) u32 pch_isr; u32 mask = 0; - with_intel_display_power(i915, tc_phy_cold_off_domain(tc), wakeref) { + with_intel_display_power(display, tc_phy_cold_off_domain(tc), wakeref) { fia_isr = intel_de_read(i915, PORT_TX_DFLEXDPSP(tc->phy_fia)); pch_isr = intel_de_read(i915, SDEISR); } @@ -730,11 +732,12 @@ tgl_tc_phy_cold_off_domain(struct intel_tc_port *tc) static void tgl_tc_phy_init(struct intel_tc_port *tc) { + struct intel_display *display = to_intel_display(tc->dig_port); struct drm_i915_private *i915 = tc_to_i915(tc); intel_wakeref_t wakeref; u32 val; - with_intel_display_power(i915, tc_phy_cold_off_domain(tc), wakeref) + with_intel_display_power(display, tc_phy_cold_off_domain(tc), wakeref) val = intel_de_read(i915, PORT_TX_DFLEXDPSP(FIA1)); drm_WARN_ON(&i915->drm, val == 0xffffffff); @@ -760,17 +763,18 @@ static const struct intel_tc_phy_ops tgl_tc_phy_ops = { static enum intel_display_power_domain adlp_tc_phy_cold_off_domain(struct intel_tc_port *tc) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); struct intel_digital_port *dig_port = tc->dig_port; if (tc->mode != TC_PORT_TBT_ALT) - return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); + return intel_display_power_legacy_aux_domain(display, dig_port->aux_ch); return POWER_DOMAIN_TC_COLD_OFF; } static u32 adlp_tc_phy_hpd_live_status(struct intel_tc_port *tc) { + struct intel_display *display = to_intel_display(tc->dig_port); struct drm_i915_private *i915 = tc_to_i915(tc); struct intel_digital_port *dig_port = tc->dig_port; enum hpd_pin hpd_pin = dig_port->base.hpd_pin; @@ -781,7 +785,7 @@ static u32 adlp_tc_phy_hpd_live_status(struct intel_tc_port *tc) u32 pch_isr; u32 mask = 0; - with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) { + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { cpu_isr = intel_de_read(i915, GEN11_DE_HPD_ISR); pch_isr = intel_de_read(i915, SDEISR); } @@ -851,22 +855,23 @@ static bool adlp_tc_phy_is_owned(struct intel_tc_port *tc) static void adlp_tc_phy_get_hw_state(struct intel_tc_port *tc) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); enum intel_display_power_domain port_power_domain = tc_port_power_domain(tc); intel_wakeref_t port_wakeref; - port_wakeref = intel_display_power_get(i915, port_power_domain); + port_wakeref = intel_display_power_get(display, port_power_domain); tc->mode = tc_phy_get_current_mode(tc); if (tc->mode != TC_PORT_DISCONNECTED) tc->lock_wakeref = tc_cold_block(tc); - intel_display_power_put(i915, port_power_domain, port_wakeref); + intel_display_power_put(display, port_power_domain, port_wakeref); } static bool adlp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes) { + struct intel_display *display = to_intel_display(tc->dig_port); struct drm_i915_private *i915 = tc_to_i915(tc); enum intel_display_power_domain port_power_domain = tc_port_power_domain(tc); @@ -877,7 +882,7 @@ static bool adlp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes) return true; } - port_wakeref = intel_display_power_get(i915, port_power_domain); + port_wakeref = intel_display_power_get(display, port_power_domain); if (!adlp_tc_phy_take_ownership(tc, true) && !drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_LEGACY)) { @@ -898,7 +903,7 @@ static bool adlp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes) if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes)) goto out_unblock_tc_cold; - intel_display_power_put(i915, port_power_domain, port_wakeref); + intel_display_power_put(display, port_power_domain, port_wakeref); return true; @@ -907,19 +912,19 @@ out_unblock_tc_cold: out_release_phy: adlp_tc_phy_take_ownership(tc, false); out_put_port_power: - intel_display_power_put(i915, port_power_domain, port_wakeref); + intel_display_power_put(display, port_power_domain, port_wakeref); return false; } static void adlp_tc_phy_disconnect(struct intel_tc_port *tc) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); enum intel_display_power_domain port_power_domain = tc_port_power_domain(tc); intel_wakeref_t port_wakeref; - port_wakeref = intel_display_power_get(i915, port_power_domain); + port_wakeref = intel_display_power_get(display, port_power_domain); tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref)); @@ -934,7 +939,7 @@ static void adlp_tc_phy_disconnect(struct intel_tc_port *tc) MISSING_CASE(tc->mode); } - intel_display_power_put(i915, port_power_domain, port_wakeref); + intel_display_power_put(display, port_power_domain, port_wakeref); } static void adlp_tc_phy_init(struct intel_tc_port *tc) @@ -959,6 +964,7 @@ static const struct intel_tc_phy_ops adlp_tc_phy_ops = { */ static u32 xelpdp_tc_phy_hpd_live_status(struct intel_tc_port *tc) { + struct intel_display *display = to_intel_display(tc->dig_port); struct drm_i915_private *i915 = tc_to_i915(tc); struct intel_digital_port *dig_port = tc->dig_port; enum hpd_pin hpd_pin = dig_port->base.hpd_pin; @@ -969,7 +975,7 @@ static u32 xelpdp_tc_phy_hpd_live_status(struct intel_tc_port *tc) u32 pch_isr; u32 mask = 0; - with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) { + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { pica_isr = intel_de_read(i915, PICAINTERRUPT_ISR); pch_isr = intel_de_read(i915, SDEISR); } @@ -1436,25 +1442,25 @@ static void tc_phy_init(struct intel_tc_port *tc) static void intel_tc_port_reset_mode(struct intel_tc_port *tc, int required_lanes, bool force_disconnect) { - struct drm_i915_private *i915 = tc_to_i915(tc); + struct intel_display *display = to_intel_display(tc->dig_port); struct intel_digital_port *dig_port = tc->dig_port; enum tc_port_mode old_tc_mode = tc->mode; - intel_display_power_flush_work(i915); + intel_display_power_flush_work(display); if (!intel_tc_cold_requires_aux_pw(dig_port)) { enum intel_display_power_domain aux_domain; bool aux_powered; aux_domain = intel_aux_power_domain(dig_port); - aux_powered = intel_display_power_is_enabled(i915, aux_domain); - drm_WARN_ON(&i915->drm, aux_powered); + aux_powered = intel_display_power_is_enabled(display, aux_domain); + drm_WARN_ON(display->drm, aux_powered); } tc_phy_disconnect(tc); if (!force_disconnect) tc_phy_connect(tc, required_lanes); - drm_dbg_kms(&i915->drm, "Port %s: TC port mode reset (%s -> %s)\n", + drm_dbg_kms(display->drm, "Port %s: TC port mode reset (%s -> %s)\n", tc->port_name, tc_port_mode_name(old_tc_mode), tc_port_mode_name(tc->mode)); diff --git a/drivers/gpu/drm/i915/display/intel_tdf.h b/drivers/gpu/drm/i915/display/intel_tdf.h index 353cde21f6c2..0862c2bfd9cd 100644 --- a/drivers/gpu/drm/i915/display/intel_tdf.h +++ b/drivers/gpu/drm/i915/display/intel_tdf.h @@ -14,12 +14,12 @@ * the display flip, since display engine is never coherent with CPU/GPU caches. */ -struct drm_i915_private; +struct intel_display; #ifdef I915 -static inline void intel_td_flush(struct drm_i915_private *i915) {} +static inline void intel_td_flush(struct intel_display *display) {} #else -void intel_td_flush(struct drm_i915_private *i915); +void intel_td_flush(struct intel_display *display); #endif #endif diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c index 6e311dcc1a61..5dbe857ea85b 100644 --- a/drivers/gpu/drm/i915/display/intel_tv.c +++ b/drivers/gpu/drm/i915/display/intel_tv.c @@ -957,15 +957,14 @@ static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state static enum drm_mode_status intel_tv_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { struct intel_display *display = to_intel_display(connector->dev); - struct drm_i915_private *i915 = to_i915(connector->dev); const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); int max_dotclk = display->cdclk.max_dotclk_freq; enum drm_mode_status status; - status = intel_cpu_transcoder_mode_valid(i915, mode); + status = intel_cpu_transcoder_mode_valid(display, mode); if (status != MODE_OK) return status; @@ -1436,7 +1435,6 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct intel_tv *intel_tv = enc_to_tv(encoder); const struct intel_tv_connector_state *tv_conn_state = @@ -1543,7 +1541,7 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state, intel_de_write(display, TV_CLR_LEVEL, ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT))); - assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder); + assert_transcoder_disabled(display, pipe_config->cpu_transcoder); /* Filter ctl must be set before TV_WIN_SIZE */ tv_filter_ctl = TV_AUTO_SCALE; diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index a95fb3349eba..7b240ce681a0 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -222,7 +222,9 @@ int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state) * However if queried just before the start of vblank we'll get an * answer that's slightly in the future. */ - if (DISPLAY_VER(display) == 2) + if (DISPLAY_VER(display) >= 20 || display->platform.battlemage) + return 1; + else if (DISPLAY_VER(display) == 2) return -1; else if (HAS_DDI(display) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) return 2; @@ -369,7 +371,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, /* * Already exiting vblank? If so, shift our position - * so it looks like we're already apporaching the full + * so it looks like we're already approaching the full * vblank end. This should make the generated timestamp * more or less match when the active portion will start. */ @@ -507,6 +509,23 @@ void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) wait_for_pipe_scanline_moving(crtc, true); } +static void intel_crtc_active_timings(struct drm_display_mode *mode, + int *vmax_vblank_start, + const struct intel_crtc_state *crtc_state, + bool vrr_enable) +{ + drm_mode_init(mode, &crtc_state->hw.adjusted_mode); + *vmax_vblank_start = 0; + + if (!vrr_enable) + return; + + mode->crtc_vtotal = intel_vrr_vmax_vtotal(crtc_state); + mode->crtc_vblank_end = intel_vrr_vmax_vtotal(crtc_state); + mode->crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); + *vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); +} + void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state, bool vrr_enable) { @@ -517,19 +536,13 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state, int vmax_vblank_start = 0; unsigned long irqflags; - drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); + intel_crtc_active_timings(&adjusted_mode, &vmax_vblank_start, + crtc_state, vrr_enable); - if (vrr_enable) { - drm_WARN_ON(display->drm, - (mode_flags & I915_MODE_FLAG_VRR) == 0); - - adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; - adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; - adjusted_mode.crtc_vblank_start = intel_vrr_vmin_vblank_start(crtc_state); - vmax_vblank_start = intel_vrr_vmax_vblank_start(crtc_state); - } else { + if (vrr_enable) + drm_WARN_ON(display->drm, (mode_flags & I915_MODE_FLAG_VRR) == 0); + else mode_flags &= ~I915_MODE_FLAG_VRR; - } /* * Belts and suspenders locking to guarantee everyone sees 100% @@ -597,6 +610,37 @@ int intel_mode_vtotal(const struct drm_display_mode *mode) return vtotal; } +int intel_mode_vblank_delay(const struct drm_display_mode *mode) +{ + return intel_mode_vblank_start(mode) - intel_mode_vdisplay(mode); +} + +static const struct intel_crtc_state * +pre_commit_crtc_state(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + /* + * During fastsets/etc. the transcoder is still + * running with the old timings at this point. + */ + if (intel_crtc_needs_modeset(new_crtc_state)) + return new_crtc_state; + else + return old_crtc_state; +} + +const struct intel_crtc_state * +intel_pre_commit_crtc_state(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + + return pre_commit_crtc_state(old_crtc_state, new_crtc_state); +} + void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state, struct intel_vblank_evade_ctx *evade) @@ -605,6 +649,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); const struct intel_crtc_state *crtc_state; const struct drm_display_mode *adjusted_mode; + int vblank_delay; evade->crtc = crtc; @@ -612,16 +657,8 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, display->platform.cherryview) && intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI); - /* - * During fastsets/etc. the transcoder is still - * running with the old timings at this point. - * - * TODO: maybe just use the active timings here? - */ - if (intel_crtc_needs_modeset(new_crtc_state)) - crtc_state = new_crtc_state; - else - crtc_state = old_crtc_state; + /* TODO: maybe just use the active timings here? */ + crtc_state = pre_commit_crtc_state(old_crtc_state, new_crtc_state); adjusted_mode = &crtc_state->hw.adjusted_mode; @@ -634,8 +671,12 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state); else evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state); + + vblank_delay = intel_vrr_vblank_delay(crtc_state); } else { evade->vblank_start = intel_mode_vblank_start(adjusted_mode); + + vblank_delay = intel_mode_vblank_delay(adjusted_mode); } /* FIXME needs to be calibrated sensibly */ @@ -653,8 +694,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, */ if (intel_color_uses_dsb(new_crtc_state) || new_crtc_state->update_m_n || new_crtc_state->update_lrr) - evade->min -= intel_mode_vblank_start(adjusted_mode) - - intel_mode_vdisplay(adjusted_mode); + evade->min -= vblank_delay; } /* must be called with vblank interrupt already enabled! */ diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h index 6d7336256982..21fbb08d61d5 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.h +++ b/drivers/gpu/drm/i915/display/intel_vblank.h @@ -11,6 +11,7 @@ struct drm_crtc; struct drm_display_mode; +struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; @@ -24,6 +25,7 @@ int intel_mode_vdisplay(const struct drm_display_mode *mode); int intel_mode_vblank_start(const struct drm_display_mode *mode); int intel_mode_vblank_end(const struct drm_display_mode *mode); int intel_mode_vtotal(const struct drm_display_mode *mode); +int intel_mode_vblank_delay(const struct drm_display_mode *mode); void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state, @@ -42,4 +44,8 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state, bool vrr_enable); int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state); +const struct intel_crtc_state * +intel_pre_commit_crtc_state(struct intel_atomic_state *state, + struct intel_crtc *crtc); + #endif /* __INTEL_VBLANK_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index b355c479eda3..3ed64c17bdff 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -10,7 +10,7 @@ #include <drm/display/drm_dsc_helper.h> #include <drm/drm_fixed.h> -#include "i915_drv.h" +#include "i915_utils.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_types.h" @@ -22,14 +22,13 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) { - const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!HAS_DSC(i915)) + if (!HAS_DSC(display)) return false; - if (DISPLAY_VER(i915) == 11 && cpu_transcoder == TRANSCODER_A) + if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A) return false; return true; @@ -37,9 +36,9 @@ bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state) static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); - if (DISPLAY_VER(i915) >= 12) + if (DISPLAY_VER(display) >= 12) return true; if (cpu_transcoder == TRANSCODER_EDP || @@ -48,7 +47,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder) return false; /* There's no pipe A DSC engine on ICL */ - drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); + drm_WARN_ON(display->drm, crtc->pipe == PIPE_A); return true; } @@ -66,6 +65,13 @@ intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf, intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420); } +static int +get_range_bpg_offset(int bpp_low, int offset_low, int bpp_high, int offset_high, int bpp) +{ + return offset_low + DIV_ROUND_UP((offset_high - offset_low) * (bpp - bpp_low), + (bpp_low - bpp_high)); +} + /* * We are using the method provided in DSC 1.2a C-Model in codec_main.c * Above method use a common formula to derive values for any combination of DSC @@ -83,7 +89,7 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg) int qp_bpc_modifier = (bpc - 8) * 2; int uncompressed_bpg_rate; int first_line_bpg_offset; - u32 res, buf_i, bpp_i; + u32 buf_i, bpp_i; if (vdsc_cfg->slice_height >= 8) first_line_bpg_offset = @@ -99,7 +105,7 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg) * According to DSC 1.2 spec in Section 4.1 if native_420 is set: * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice * height < 8. - * -second_line_offset_adj is 512 as shown by emperical values to yield best chroma + * -second_line_offset_adj is 512 as shown by empirical values to yield best chroma * preservation in second line. * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11 @@ -117,7 +123,6 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg) vdsc_cfg->slice_height - 1); } - /* Our hw supports only 444 modes as of today */ if (bpp >= 12) vdsc_cfg->initial_offset = 2048; else if (bpp >= 10) @@ -163,23 +168,19 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg) intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i); /* Calculate range_bpg_offset */ - if (bpp <= 8) { + if (bpp <= 8) range_bpg_offset = ofs_und4[buf_i]; - } else if (bpp <= 10) { - res = DIV_ROUND_UP(((bpp - 8) * - (ofs_und5[buf_i] - ofs_und4[buf_i])), 2); - range_bpg_offset = ofs_und4[buf_i] + res; - } else if (bpp <= 12) { - res = DIV_ROUND_UP(((bpp - 10) * - (ofs_und6[buf_i] - ofs_und5[buf_i])), 2); - range_bpg_offset = ofs_und5[buf_i] + res; - } else if (bpp <= 16) { - res = DIV_ROUND_UP(((bpp - 12) * - (ofs_und8[buf_i] - ofs_und6[buf_i])), 4); - range_bpg_offset = ofs_und6[buf_i] + res; - } else { + else if (bpp <= 10) + range_bpg_offset = get_range_bpg_offset(8, ofs_und4[buf_i], + 10, ofs_und5[buf_i], bpp); + else if (bpp <= 12) + range_bpg_offset = get_range_bpg_offset(10, ofs_und5[buf_i], + 12, ofs_und6[buf_i], bpp); + else if (bpp <= 16) + range_bpg_offset = get_range_bpg_offset(12, ofs_und6[buf_i], + 16, ofs_und8[buf_i], bpp); + else range_bpg_offset = ofs_und8[buf_i]; - } vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK; @@ -215,21 +216,19 @@ calculate_rc_params(struct drm_dsc_config *vdsc_cfg) intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i); /* Calculate range_bpg_offset */ - if (bpp <= 6) { + if (bpp <= 6) range_bpg_offset = ofs_und6[buf_i]; - } else if (bpp <= 8) { - res = DIV_ROUND_UP(((bpp - 6) * - (ofs_und8[buf_i] - ofs_und6[buf_i])), 2); - range_bpg_offset = ofs_und6[buf_i] + res; - } else if (bpp <= 12) { - range_bpg_offset = ofs_und8[buf_i]; - } else if (bpp <= 15) { - res = DIV_ROUND_UP(((bpp - 12) * - (ofs_und15[buf_i] - ofs_und12[buf_i])), 3); - range_bpg_offset = ofs_und12[buf_i] + res; - } else { + else if (bpp <= 8) + range_bpg_offset = get_range_bpg_offset(6, ofs_und6[buf_i], + 8, ofs_und8[buf_i], bpp); + else if (bpp <= 12) + range_bpg_offset = get_range_bpg_offset(8, ofs_und8[buf_i], + 12, ofs_und12[buf_i], bpp); + else if (bpp <= 15) + range_bpg_offset = get_range_bpg_offset(12, ofs_und12[buf_i], + 15, ofs_und15[buf_i], bpp); + else range_bpg_offset = ofs_und15[buf_i]; - } vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK; @@ -262,8 +261,7 @@ static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) { - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(pipe_config); struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); int err; @@ -276,7 +274,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg); if (err) { - drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n"); + drm_dbg_kms(display->drm, "Slice dimension requirements not met\n"); return err; } @@ -287,7 +285,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 && pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444; - if (DISPLAY_VER(dev_priv) >= 14 && + if (DISPLAY_VER(display) >= 14 && pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) vdsc_cfg->native_420 = true; /* We do not support YcBCr422 as of now */ @@ -308,7 +306,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; if (vdsc_cfg->bits_per_component < 8) { - drm_dbg_kms(&dev_priv->drm, "DSC bpc requirements not met bpc: %d\n", + drm_dbg_kms(display->drm, "DSC bpc requirements not met bpc: %d\n", vdsc_cfg->bits_per_component); return -EINVAL; } @@ -320,7 +318,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) * upto uncompressed bpp-1, hence add calculations for all the rc * parameters */ - if (DISPLAY_VER(dev_priv) >= 13) { + if (DISPLAY_VER(display) >= 13) { calculate_rc_params(vdsc_cfg); } else { if ((compressed_bpp == 8 || @@ -356,7 +354,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) enum intel_display_power_domain intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; /* @@ -370,7 +368,8 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) * the pipe in use. Hence another reference on the pipe power domain * will suffice. (Except no VDSC/joining on ICL pipe A.) */ - if (DISPLAY_VER(i915) == 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A) + if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake && + pipe == PIPE_A) return POWER_DOMAIN_TRANSCODER_VDSC_PW2; else if (is_pipe_dsc(crtc, cpu_transcoder)) return POWER_DOMAIN_PIPE(pipe); @@ -416,26 +415,25 @@ static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state, int pps, u32 pps_val) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); i915_reg_t dsc_reg[3]; int i, vdsc_per_pipe, dsc_reg_num; vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); - drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe); + drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe); intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num); for (i = 0; i < dsc_reg_num; i++) - intel_de_write(i915, dsc_reg[i], pps_val); + intel_de_write(display, dsc_reg[i], pps_val); } static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum pipe pipe = crtc->pipe; @@ -529,7 +527,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) vdsc_cfg->slice_height); intel_dsc_pps_write(crtc_state, 16, pps_val); - if (DISPLAY_VER(dev_priv) >= 14) { + if (DISPLAY_VER(display) >= 14) { /* PPS 17 */ pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset); intel_dsc_pps_write(crtc_state, 17, pps_val); @@ -547,44 +545,44 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) (u32)(vdsc_cfg->rc_buf_thresh[i] << BITS_PER_BYTE * (i % 4)); if (!is_pipe_dsc(crtc, cpu_transcoder)) { - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, + intel_de_write(display, DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW, + intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1, + intel_de_write(display, DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); - intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW, + intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]); if (vdsc_instances_per_pipe > 1) { - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0, + intel_de_write(display, DSCC_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW, + intel_de_write(display, DSCC_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1, + intel_de_write(display, DSCC_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); - intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW, + intel_de_write(display, DSCC_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]); } } else { - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe), + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe), rc_buf_thresh_dword[0]); - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), rc_buf_thresh_dword[1]); - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe), + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe), rc_buf_thresh_dword[2]); - intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), + intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), rc_buf_thresh_dword[3]); if (vdsc_instances_per_pipe > 1) { - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC1_RC_BUF_THRESH_0(pipe), rc_buf_thresh_dword[0]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), rc_buf_thresh_dword[1]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC1_RC_BUF_THRESH_1(pipe), rc_buf_thresh_dword[2]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), rc_buf_thresh_dword[3]); } @@ -601,88 +599,88 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) (vdsc_cfg->rc_range_params[i].range_min_qp << RC_MIN_QP_SHIFT)) << 16 * (i % 2)); if (!is_pipe_dsc(crtc, cpu_transcoder)) { - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0, + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0, rc_range_params_dword[0]); - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW, + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0_UDW, rc_range_params_dword[1]); - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1, + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1, rc_range_params_dword[2]); - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW, + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1_UDW, rc_range_params_dword[3]); - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2, + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2, rc_range_params_dword[4]); - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW, + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2_UDW, rc_range_params_dword[5]); - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3, + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3, rc_range_params_dword[6]); - intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW, + intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3_UDW, rc_range_params_dword[7]); if (vdsc_instances_per_pipe > 1) { - intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0, + intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_0, rc_range_params_dword[0]); - intel_de_write(dev_priv, + intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_0_UDW, rc_range_params_dword[1]); - intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1, + intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_1, rc_range_params_dword[2]); - intel_de_write(dev_priv, + intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_1_UDW, rc_range_params_dword[3]); - intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2, + intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_2, rc_range_params_dword[4]); - intel_de_write(dev_priv, + intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_2_UDW, rc_range_params_dword[5]); - intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3, + intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_3, rc_range_params_dword[6]); - intel_de_write(dev_priv, + intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_3_UDW, rc_range_params_dword[7]); } } else { - intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), + intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), rc_range_params_dword[0]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), rc_range_params_dword[1]); - intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), + intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), rc_range_params_dword[2]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), rc_range_params_dword[3]); - intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), + intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), rc_range_params_dword[4]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), rc_range_params_dword[5]); - intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), + intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), rc_range_params_dword[6]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), rc_range_params_dword[7]); if (vdsc_instances_per_pipe > 1) { - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), rc_range_params_dword[0]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), rc_range_params_dword[1]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), rc_range_params_dword[2]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), rc_range_params_dword[3]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), rc_range_params_dword[4]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), rc_range_params_dword[5]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), rc_range_params_dword[6]); - intel_de_write(dev_priv, + intel_de_write(display, ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), rc_range_params_dword[7]); } @@ -746,8 +744,8 @@ static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_tran void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dss_ctl1_val = 0; if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) { @@ -756,14 +754,15 @@ void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) else dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY; - intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); + intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), + dss_ctl1_val); } } void intel_dsc_enable(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dss_ctl1_val = 0; u32 dss_ctl2_val = 0; int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); @@ -796,28 +795,27 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) if (intel_crtc_is_bigjoiner_primary(crtc_state)) dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE; } - intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); - intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); + intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); + intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); } void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) { + struct intel_display *display = to_intel_display(old_crtc_state); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); /* Disable only if either of them is enabled */ if (old_crtc_state->dsc.compression_enable || old_crtc_state->joiner_pipes) { - intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); - intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); + intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); + intel_de_write(display, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); } } static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps, bool *all_equal) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); i915_reg_t dsc_reg[3]; int i, vdsc_per_pipe, dsc_reg_num; u32 val; @@ -825,16 +823,16 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps, vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); - drm_WARN_ON_ONCE(&i915->drm, dsc_reg_num < vdsc_per_pipe); + drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe); intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num); *all_equal = true; - val = intel_de_read(i915, dsc_reg[0]); + val = intel_de_read(display, dsc_reg[0]); for (i = 1; i < dsc_reg_num; i++) { - if (intel_de_read(i915, dsc_reg[i]) != val) { + if (intel_de_read(display, dsc_reg[i]) != val) { *all_equal = false; break; } @@ -845,22 +843,20 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps, static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc_state); u32 val; bool all_equal; val = intel_dsc_pps_read(crtc_state, pps, &all_equal); - drm_WARN_ON(&i915->drm, !all_equal); + drm_WARN_ON(display->drm, !all_equal); return val; } static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); u32 pps_temp; @@ -946,7 +942,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp); - if (DISPLAY_VER(i915) >= 14) { + if (DISPLAY_VER(display) >= 14) { /* PPS 17 */ pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17); @@ -962,8 +958,8 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state) void intel_dsc_get_config(struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; @@ -974,12 +970,12 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) power_domain = intel_dsc_power_domain(crtc, cpu_transcoder); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return; - dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); - dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); + dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder)); + dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, cpu_transcoder)); crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE; if (!crtc_state->dsc.compression_enable) @@ -994,7 +990,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) intel_dsc_get_pps_config(crtc_state); out: - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); } static void intel_vdsc_dump_state(struct drm_printer *p, int indent, @@ -1019,8 +1015,7 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent, int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct intel_display *display = to_intel_display(crtc); + struct intel_display *display = to_intel_display(crtc_state); int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); int min_cdclk; diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index fd18dd07ae49..684b5d1bc87c 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -59,7 +59,6 @@ void intel_vga_redisable_power_on(struct intel_display *display) void intel_vga_redisable(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref; /* @@ -71,13 +70,13 @@ void intel_vga_redisable(struct intel_display *display) * follow the "don't touch the power well if we don't need it" policy * the rest of the driver uses. */ - wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_VGA); + wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_VGA); if (!wakeref) return; intel_vga_redisable_power_on(display); - intel_display_power_put(i915, POWER_DOMAIN_VGA, wakeref); + intel_display_power_put(display, POWER_DOMAIN_VGA, wakeref); } void intel_vga_reset_io_mem(struct intel_display *display) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 70088e355055..cac49319026d 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -7,9 +7,9 @@ #include "i915_reg.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_dp.h" #include "intel_vrr.h" #include "intel_vrr_regs.h" -#include "intel_dp.h" #define FIXED_POINT_PRECISION 100 #define CMRR_PRECISION_TOLERANCE 10 @@ -75,6 +75,46 @@ intel_vrr_check_modeset(struct intel_atomic_state *state) } } +static int intel_vrr_real_vblank_delay(const struct intel_crtc_state *crtc_state) +{ + return crtc_state->hw.adjusted_mode.crtc_vblank_start - + crtc_state->hw.adjusted_mode.crtc_vdisplay; +} + +static int intel_vrr_extra_vblank_delay(struct intel_display *display) +{ + /* + * On ICL/TGL VRR hardware inserts one extra scanline + * just after vactive, which pushes the vmin decision + * boundary ahead accordingly. We'll include the extra + * scanline in our vblank delay estimates to make sure + * that we never underestimate how long we have until + * the delayed vblank has passed. + */ + return DISPLAY_VER(display) < 13 ? 1 : 0; +} + +int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + + return intel_vrr_real_vblank_delay(crtc_state) + + intel_vrr_extra_vblank_delay(display); +} + +static int intel_vrr_flipline_offset(struct intel_display *display) +{ + /* ICL/TGL hardware imposes flipline>=vmin+1 */ + return DISPLAY_VER(display) < 13 ? 1 : 0; +} + +static int intel_vrr_vmin_flipline(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + + return crtc_state->vrr.vmin + intel_vrr_flipline_offset(display); +} + /* * Without VRR registers get latched at: * vblank_start @@ -98,19 +138,41 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat if (DISPLAY_VER(display) >= 13) return crtc_state->vrr.guardband; else - /* The hw imposes the extra scanline before frame start */ + /* hardware imposes one extra scanline somewhere */ return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1; } +int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + + /* Min vblank actually determined by flipline */ + if (DISPLAY_VER(display) >= 13) + return intel_vrr_vmin_flipline(crtc_state); + else + return intel_vrr_vmin_flipline(crtc_state) + + intel_vrr_real_vblank_delay(crtc_state); +} + +int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + + if (DISPLAY_VER(display) >= 13) + return crtc_state->vrr.vmax; + else + return crtc_state->vrr.vmax + + intel_vrr_real_vblank_delay(crtc_state); +} + int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state) { - /* Min vblank actually determined by flipline that is always >=vmin+1 */ - return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state); + return intel_vrr_vmin_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state); } int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) { - return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); + return intel_vrr_vmax_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state); } static bool @@ -202,15 +264,17 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, if (vmin >= vmax) return; + crtc_state->vrr.vmin = vmin; + crtc_state->vrr.vmax = vmax; + + crtc_state->vrr.flipline = crtc_state->vrr.vmin; + /* * flipline determines the min vblank length the hardware will - * generate, and flipline>=vmin+1, hence we reduce vmin by one - * to make sure we can get the actual min vblank length. + * generate, and on ICL/TGL flipline>=vmin+1, hence we reduce + * vmin by one to make sure we can get the actual min vblank length. */ - crtc_state->vrr.vmin = vmin - 1; - crtc_state->vrr.vmax = vmax; - - crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; + crtc_state->vrr.vmin -= intel_vrr_flipline_offset(display); /* * When panel is VRR capable and userspace has @@ -235,7 +299,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } - if (intel_dp->as_sdp_supported && crtc_state->vrr.enable) { + if (HAS_AS_SDP(display)) { crtc_state->vrr.vsync_start = (crtc_state->hw.adjusted_mode.crtc_vtotal - crtc_state->hw.adjusted_mode.vsync_start); @@ -255,11 +319,20 @@ void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state) if (DISPLAY_VER(display) >= 13) { crtc_state->vrr.guardband = - crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start; + crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start; } else { + /* hardware imposes one extra scanline somewhere */ crtc_state->vrr.pipeline_full = min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start - crtc_state->framestart_delay - 1); + + /* + * vmin/vmax/flipline also need to be adjusted by + * the vblank delay to maintain correct vtotals. + */ + crtc_state->vrr.vmin -= intel_vrr_real_vblank_delay(crtc_state); + crtc_state->vrr.vmax -= intel_vrr_real_vblank_delay(crtc_state); + crtc_state->vrr.flipline -= intel_vrr_real_vblank_delay(crtc_state); } } @@ -315,9 +388,16 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) trans_vrr_ctl(crtc_state)); intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), crtc_state->vrr.flipline - 1); + + if (HAS_AS_SDP(display)) + intel_de_write(display, + TRANS_VRR_VSYNC(display, cpu_transcoder), + VRR_VSYNC_END(crtc_state->vrr.vsync_end) | + VRR_VSYNC_START(crtc_state->vrr.vsync_start)); } -void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) +void intel_vrr_send_push(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; @@ -325,8 +405,49 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) if (!crtc_state->vrr.enable) return; - intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), - TRANS_PUSH_EN | TRANS_PUSH_SEND); + if (dsb) + intel_dsb_nonpost_start(dsb); + + intel_de_write_dsb(display, dsb, + TRANS_PUSH(display, cpu_transcoder), + TRANS_PUSH_EN | TRANS_PUSH_SEND); + + if (dsb) + intel_dsb_nonpost_end(dsb); +} + +void intel_vrr_check_push_sent(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + if (!crtc_state->vrr.enable) + return; + + /* + * Make sure the push send bit has cleared. This should + * already be the case as long as the caller makes sure + * this is called after the delayed vblank has occurred. + */ + if (dsb) { + int wait_us, count; + + wait_us = 2; + count = 1; + + /* + * If the bit hasn't cleared the DSB will + * raise the poll error interrupt. + */ + intel_dsb_poll(dsb, TRANS_PUSH(display, cpu_transcoder), + TRANS_PUSH_SEND, 0, wait_us, count); + } else { + if (intel_vrr_is_push_sent(crtc_state)) + drm_err(display->drm, "[CRTC:%d:%s] VRR push send still pending\n", + crtc->base.base.id, crtc->base.name); + } } bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) @@ -351,12 +472,6 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN); - if (HAS_AS_SDP(display)) - intel_de_write(display, - TRANS_VRR_VSYNC(display, cpu_transcoder), - VRR_VSYNC_END(crtc_state->vrr.vsync_end) | - VRR_VSYNC_START(crtc_state->vrr.vsync_start)); - if (crtc_state->cmrr.enable) { intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | @@ -381,10 +496,6 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) TRANS_VRR_STATUS(display, cpu_transcoder), VRR_STATUS_VRR_EN_LIVE, 1000); intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); - - if (HAS_AS_SDP(display)) - intel_de_write(display, - TRANS_VRR_VSYNC(display, cpu_transcoder), 0); } void intel_vrr_get_config(struct intel_crtc_state *crtc_state) @@ -424,10 +535,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) TRANS_VRR_VMAX(display, cpu_transcoder)) + 1; crtc_state->vrr.vmin = intel_de_read(display, TRANS_VRR_VMIN(display, cpu_transcoder)) + 1; - } - - if (crtc_state->vrr.enable) { - crtc_state->mode_flags |= I915_MODE_FLAG_VRR; if (HAS_AS_SDP(display)) { trans_vrr_vsync = @@ -439,4 +546,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) REG_FIELD_GET(VRR_VSYNC_END_MASK, trans_vrr_vsync); } } + + if (crtc_state->vrr.enable) + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index b3b45c675020..514822577e8a 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -12,6 +12,7 @@ struct drm_connector_state; struct intel_atomic_state; struct intel_connector; struct intel_crtc_state; +struct intel_dsb; bool intel_vrr_is_capable(struct intel_connector *connector); bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh); @@ -22,11 +23,17 @@ void intel_vrr_compute_config(struct intel_crtc_state *crtc_state, void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state); void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state); void intel_vrr_enable(const struct intel_crtc_state *crtc_state); -void intel_vrr_send_push(const struct intel_crtc_state *crtc_state); +void intel_vrr_send_push(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state); +void intel_vrr_check_push_sent(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state); bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state); void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state); void intel_vrr_get_config(struct intel_crtc_state *crtc_state); +int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state); +int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state); int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state); int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state); +int intel_vrr_vblank_delay(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_VRR_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c index d7dc49aecd27..f00f4cfc58e5 100644 --- a/drivers/gpu/drm/i915/display/intel_wm.c +++ b/drivers/gpu/drm/i915/display/intel_wm.c @@ -108,6 +108,12 @@ void intel_wm_get_hw_state(struct drm_i915_private *i915) return i915->display.funcs.wm->get_hw_state(i915); } +void intel_wm_sanitize(struct drm_i915_private *i915) +{ + if (i915->display.funcs.wm->sanitize) + return i915->display.funcs.wm->sanitize(i915); +} + bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { diff --git a/drivers/gpu/drm/i915/display/intel_wm.h b/drivers/gpu/drm/i915/display/intel_wm.h index e97cdca89a5c..7d3a447054b3 100644 --- a/drivers/gpu/drm/i915/display/intel_wm.h +++ b/drivers/gpu/drm/i915/display/intel_wm.h @@ -25,6 +25,7 @@ void intel_optimize_watermarks(struct intel_atomic_state *state, struct intel_crtc *crtc); int intel_compute_global_watermarks(struct intel_atomic_state *state); void intel_wm_get_hw_state(struct drm_i915_private *i915); +void intel_wm_sanitize(struct drm_i915_private *i915); bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); void intel_print_wm_latency(struct drm_i915_private *i915, diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index ae21fce534dc..ee81220a7c88 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -6,6 +6,7 @@ #include "i915_drv.h" #include "i915_reg.h" #include "intel_de.h" +#include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_fb.h" #include "skl_scaler.h" @@ -64,7 +65,7 @@ static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited) /* * Hardware initial phase limited to [-0.5:1.5]. * Since the max hardware scale factor is 3.0, we - * should never actually excdeed 1.0 here. + * should never actually exceed 1.0 here. */ WARN_ON(phase < -0x8000 || phase > 0x18000); @@ -76,28 +77,60 @@ static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited) return ((phase >> 2) & PS_PHASE_MASK) | trip; } -#define SKL_MIN_SRC_W 8 -#define SKL_MAX_SRC_W 4096 -#define SKL_MIN_SRC_H 8 -#define SKL_MAX_SRC_H 4096 -#define SKL_MIN_DST_W 8 -#define SKL_MAX_DST_W 4096 -#define SKL_MIN_DST_H 8 -#define SKL_MAX_DST_H 4096 -#define ICL_MAX_SRC_W 5120 -#define ICL_MAX_SRC_H 4096 -#define ICL_MAX_DST_W 5120 -#define ICL_MAX_DST_H 4096 -#define TGL_MAX_SRC_W 5120 -#define TGL_MAX_SRC_H 8192 -#define TGL_MAX_DST_W 8192 -#define TGL_MAX_DST_H 8192 -#define MTL_MAX_SRC_W 4096 -#define MTL_MAX_SRC_H 8192 -#define MTL_MAX_DST_W 8192 -#define MTL_MAX_DST_H 8192 -#define SKL_MIN_YUV_420_SRC_W 16 -#define SKL_MIN_YUV_420_SRC_H 16 +static void skl_scaler_min_src_size(const struct drm_format_info *format, + u64 modifier, int *min_w, int *min_h) +{ + if (format && intel_format_info_is_yuv_semiplanar(format, modifier)) { + *min_w = 16; + *min_h = 16; + } else { + *min_w = 8; + *min_h = 8; + } +} + +static void skl_scaler_max_src_size(struct intel_crtc *crtc, + int *max_w, int *max_h) +{ + struct intel_display *display = to_intel_display(crtc); + + if (DISPLAY_VER(display) >= 14) { + *max_w = 4096; + *max_h = 8192; + } else if (DISPLAY_VER(display) >= 12) { + *max_w = 5120; + *max_h = 8192; + } else if (DISPLAY_VER(display) == 11) { + *max_w = 5120; + *max_h = 4096; + } else { + *max_w = 4096; + *max_h = 4096; + } +} + +static void skl_scaler_min_dst_size(int *min_w, int *min_h) +{ + *min_w = 8; + *min_h = 8; +} + +static void skl_scaler_max_dst_size(struct intel_crtc *crtc, + int *max_w, int *max_h) +{ + struct intel_display *display = to_intel_display(crtc); + + if (DISPLAY_VER(display) >= 12) { + *max_w = 8192; + *max_h = 8192; + } else if (DISPLAY_VER(display) == 11) { + *max_w = 5120; + *max_h = 4096; + } else { + *max_w = 4096; + *max_h = 4096; + } +} static int skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, @@ -134,7 +167,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable && need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { drm_dbg_kms(display->drm, - "Pipe/Plane scaling not supported with IF-ID mode\n"); + "[CRTC:%d:%s] scaling not supported with IF-ID mode\n", + crtc->base.base.id, crtc->base.name); return -EINVAL; } @@ -154,8 +188,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, scaler_state->scalers[*scaler_id].in_use = false; drm_dbg_kms(display->drm, - "scaler_user index %u.%u: " + "[CRTC:%d:%s] scaler_user index %u.%u: " "Staged freeing scaler id %d scaler_users = 0x%x\n", + crtc->base.base.id, crtc->base.name, crtc->pipe, scaler_user, *scaler_id, scaler_state->scaler_users); *scaler_id = -1; @@ -163,39 +198,11 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, return 0; } - if (format && intel_format_info_is_yuv_semiplanar(format, modifier) && - (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { - drm_dbg_kms(display->drm, - "Planar YUV: src dimensions not met\n"); - return -EINVAL; - } + skl_scaler_min_src_size(format, modifier, &min_src_w, &min_src_h); + skl_scaler_max_src_size(crtc, &max_src_w, &max_src_h); - min_src_w = SKL_MIN_SRC_W; - min_src_h = SKL_MIN_SRC_H; - min_dst_w = SKL_MIN_DST_W; - min_dst_h = SKL_MIN_DST_H; - - if (DISPLAY_VER(display) < 11) { - max_src_w = SKL_MAX_SRC_W; - max_src_h = SKL_MAX_SRC_H; - max_dst_w = SKL_MAX_DST_W; - max_dst_h = SKL_MAX_DST_H; - } else if (DISPLAY_VER(display) < 12) { - max_src_w = ICL_MAX_SRC_W; - max_src_h = ICL_MAX_SRC_H; - max_dst_w = ICL_MAX_DST_W; - max_dst_h = ICL_MAX_DST_H; - } else if (DISPLAY_VER(display) < 14) { - max_src_w = TGL_MAX_SRC_W; - max_src_h = TGL_MAX_SRC_H; - max_dst_w = TGL_MAX_DST_W; - max_dst_h = TGL_MAX_DST_H; - } else { - max_src_w = MTL_MAX_SRC_W; - max_src_h = MTL_MAX_SRC_H; - max_dst_w = MTL_MAX_DST_W; - max_dst_h = MTL_MAX_DST_H; - } + skl_scaler_min_dst_size(&min_dst_w, &min_dst_h); + skl_scaler_max_dst_size(crtc, &max_dst_w, &max_dst_h); /* range checks */ if (src_w < min_src_w || src_h < min_src_h || @@ -203,8 +210,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, src_w > max_src_w || src_h > max_src_h || dst_w > max_dst_w || dst_h > max_dst_h) { drm_dbg_kms(display->drm, - "scaler_user index %u.%u: src %ux%u dst %ux%u " + "[CRTC:%d:%s] scaler_user index %u.%u: src %ux%u dst %ux%u " "size is out of scaler range\n", + crtc->base.base.id, crtc->base.name, crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); return -EINVAL; @@ -220,16 +228,18 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, */ if (pipe_src_w > max_dst_w || pipe_src_h > max_dst_h) { drm_dbg_kms(display->drm, - "scaler_user index %u.%u: pipe src size %ux%u " + "[CRTC:%d:%s] scaler_user index %u.%u: pipe src size %ux%u " "is out of scaler range\n", + crtc->base.base.id, crtc->base.name, crtc->pipe, scaler_user, pipe_src_w, pipe_src_h); return -EINVAL; } /* mark this plane as a scaler user in crtc_state */ scaler_state->scaler_users |= (1 << scaler_user); - drm_dbg_kms(display->drm, "scaler_user index %u.%u: " + drm_dbg_kms(display->drm, "[CRTC:%d:%s] scaler_user index %u.%u: " "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", + crtc->base.base.id, crtc->base.name, crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, scaler_state->scaler_users); @@ -269,14 +279,14 @@ int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); struct drm_framebuffer *fb = plane_state->hw.fb; bool force_detach = !fb || !plane_state->uapi.visible; bool need_scaler = false; /* Pre-gen11 and SDR planes always need a scaler for planar formats. */ - if (!icl_is_hdr_plane(dev_priv, plane->id) && + if (!icl_is_hdr_plane(display, plane->id) && fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) need_scaler = true; @@ -309,15 +319,55 @@ static int intel_allocate_scaler(struct intel_crtc_scaler_state *scaler_state, return -1; } -static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state, +static void +calculate_max_scale(struct intel_crtc *crtc, + bool is_yuv_semiplanar, + int scaler_id, + int *max_hscale, int *max_vscale) +{ + struct intel_display *display = to_intel_display(crtc); + + /* + * FIXME: When two scalers are needed, but only one of + * them needs to downscale, we should make sure that + * the one that needs downscaling support is assigned + * as the first scaler, so we don't reject downscaling + * unnecessarily. + */ + + if (DISPLAY_VER(display) >= 14) { + /* + * On versions 14 and up, only the first + * scaler supports a vertical scaling factor + * of more than 1.0, while a horizontal + * scaling factor of 3.0 is supported. + */ + *max_hscale = 0x30000 - 1; + + if (scaler_id == 0) + *max_vscale = 0x30000 - 1; + else + *max_vscale = 0x10000; + } else if (DISPLAY_VER(display) >= 10 || !is_yuv_semiplanar) { + *max_hscale = 0x30000 - 1; + *max_vscale = 0x30000 - 1; + } else { + *max_hscale = 0x20000 - 1; + *max_vscale = 0x20000 - 1; + } +} + +static int intel_atomic_setup_scaler(struct intel_crtc_state *crtc_state, int num_scalers_need, struct intel_crtc *crtc, const char *name, int idx, struct intel_plane_state *plane_state, int *scaler_id) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; u32 mode; + int hscale = 0; + int vscale = 0; if (*scaler_id < 0) *scaler_id = intel_allocate_scaler(scaler_state, crtc); @@ -334,7 +384,7 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat if (DISPLAY_VER(display) == 9) { mode = SKL_PS_SCALER_MODE_NV12; - } else if (icl_is_hdr_plane(dev_priv, plane->id)) { + } else if (icl_is_hdr_plane(display, plane->id)) { /* * On gen11+'s HDR planes we only use the scaler for * scaling. They have a dedicated chroma upsampler, so @@ -366,45 +416,15 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat mode = SKL_PS_SCALER_MODE_DYN; } - /* - * FIXME: we should also check the scaler factors for pfit, so - * this shouldn't be tied directly to planes. - */ if (plane_state && plane_state->hw.fb) { const struct drm_framebuffer *fb = plane_state->hw.fb; const struct drm_rect *src = &plane_state->uapi.src; const struct drm_rect *dst = &plane_state->uapi.dst; - int hscale, vscale, max_vscale, max_hscale; - - /* - * FIXME: When two scalers are needed, but only one of - * them needs to downscale, we should make sure that - * the one that needs downscaling support is assigned - * as the first scaler, so we don't reject downscaling - * unnecessarily. - */ + int max_hscale, max_vscale; - if (DISPLAY_VER(display) >= 14) { - /* - * On versions 14 and up, only the first - * scaler supports a vertical scaling factor - * of more than 1.0, while a horizontal - * scaling factor of 3.0 is supported. - */ - max_hscale = 0x30000 - 1; - if (*scaler_id == 0) - max_vscale = 0x30000 - 1; - else - max_vscale = 0x10000; - - } else if (DISPLAY_VER(display) >= 10 || - !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { - max_hscale = 0x30000 - 1; - max_vscale = 0x30000 - 1; - } else { - max_hscale = 0x20000 - 1; - max_vscale = 0x20000 - 1; - } + calculate_max_scale(crtc, + intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier), + *scaler_id, &max_hscale, &max_vscale); /* * FIXME: We should change the if-else block above to @@ -417,8 +437,8 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat if (hscale < 0 || vscale < 0) { drm_dbg_kms(display->drm, - "Scaler %d doesn't support required plane scaling\n", - *scaler_id); + "[CRTC:%d:%s] scaler %d doesn't support required plane scaling\n", + crtc->base.base.id, crtc->base.name, *scaler_id); drm_rect_debug_print("src: ", src, true); drm_rect_debug_print("dst: ", dst, false); @@ -426,7 +446,48 @@ static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_stat } } - drm_dbg_kms(display->drm, "Attached scaler id %u.%u to %s:%d\n", + if (crtc_state->pch_pfit.enabled) { + struct drm_rect src; + int max_hscale, max_vscale; + + drm_rect_init(&src, 0, 0, + drm_rect_width(&crtc_state->pipe_src) << 16, + drm_rect_height(&crtc_state->pipe_src) << 16); + + calculate_max_scale(crtc, 0, *scaler_id, + &max_hscale, &max_vscale); + + /* + * When configured for Pipe YUV 420 encoding for port output, + * limit downscaling to less than 1.5 (source/destination) in + * the horizontal direction and 1.0 in the vertical direction. + */ + if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { + max_hscale = 0x18000 - 1; + max_vscale = 0x10000; + } + + hscale = drm_rect_calc_hscale(&src, &crtc_state->pch_pfit.dst, + 0, max_hscale); + vscale = drm_rect_calc_vscale(&src, &crtc_state->pch_pfit.dst, + 0, max_vscale); + + if (hscale < 0 || vscale < 0) { + drm_dbg_kms(display->drm, + "Scaler %d doesn't support required pipe scaling\n", + *scaler_id); + drm_rect_debug_print("src: ", &src, true); + drm_rect_debug_print("dst: ", &crtc_state->pch_pfit.dst, false); + + return -EINVAL; + } + } + + scaler_state->scalers[*scaler_id].hscale = hscale; + scaler_state->scalers[*scaler_id].vscale = vscale; + + drm_dbg_kms(display->drm, "[CRTC:%d:%s] attached scaler id %u.%u to %s:%d\n", + crtc->base.base.id, crtc->base.name, crtc->pipe, *scaler_id, name, idx); scaler_state->scalers[*scaler_id].mode = mode; @@ -441,7 +502,7 @@ static int setup_crtc_scaler(struct intel_atomic_state *state, struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; - return intel_atomic_setup_scaler(scaler_state, + return intel_atomic_setup_scaler(crtc_state, hweight32(scaler_state->scaler_users), crtc, "CRTC", crtc->base.base.id, NULL, &scaler_state->scaler_id); @@ -476,7 +537,7 @@ static int setup_plane_scaler(struct intel_atomic_state *state, if (IS_ERR(plane_state)) return PTR_ERR(plane_state); - return intel_atomic_setup_scaler(scaler_state, + return intel_atomic_setup_scaler(crtc_state, hweight32(scaler_state->scaler_users), crtc, "PLANE", plane->base.base.id, plane_state, &plane_state->scaler_id); @@ -526,7 +587,8 @@ int intel_atomic_setup_scalers(struct intel_atomic_state *state, /* fail if required scalers > available scalers */ if (num_scalers_need > crtc->num_scalers) { drm_dbg_kms(display->drm, - "Too many scaling requests %d > %d\n", + "[CRTC:%d:%s] too many scaling requests %d > %d\n", + crtc->base.base.id, crtc->base.name, num_scalers_need, crtc->num_scalers); return -EINVAL; } @@ -573,43 +635,45 @@ static u16 glk_nearest_filter_coef(int t) * The letter represents the filter tap (D is the center tap) and the number * represents the coefficient set for a phase (0-16). * - * +------------+------------------------+------------------------+ - * |Index value | Data value coeffient 1 | Data value coeffient 2 | - * +------------+------------------------+------------------------+ - * | 00h | B0 | A0 | - * +------------+------------------------+------------------------+ - * | 01h | D0 | C0 | - * +------------+------------------------+------------------------+ - * | 02h | F0 | E0 | - * +------------+------------------------+------------------------+ - * | 03h | A1 | G0 | - * +------------+------------------------+------------------------+ - * | 04h | C1 | B1 | - * +------------+------------------------+------------------------+ - * | ... | ... | ... | - * +------------+------------------------+------------------------+ - * | 38h | B16 | A16 | - * +------------+------------------------+------------------------+ - * | 39h | D16 | C16 | - * +------------+------------------------+------------------------+ - * | 3Ah | F16 | C16 | - * +------------+------------------------+------------------------+ - * | 3Bh | Reserved | G16 | - * +------------+------------------------+------------------------+ + * +------------+--------------------------+--------------------------+ + * |Index value | Data value coefficient 1 | Data value coefficient 2 | + * +------------+--------------------------+--------------------------+ + * | 00h | B0 | A0 | + * +------------+--------------------------+--------------------------+ + * | 01h | D0 | C0 | + * +------------+--------------------------+--------------------------+ + * | 02h | F0 | E0 | + * +------------+--------------------------+--------------------------+ + * | 03h | A1 | G0 | + * +------------+--------------------------+--------------------------+ + * | 04h | C1 | B1 | + * +------------+--------------------------+--------------------------+ + * | ... | ... | ... | + * +------------+--------------------------+--------------------------+ + * | 38h | B16 | A16 | + * +------------+--------------------------+--------------------------+ + * | 39h | D16 | C16 | + * +------------+--------------------------+--------------------------+ + * | 3Ah | F16 | C16 | + * +------------+--------------------------+--------------------------+ + * | 3Bh | Reserved | G16 | + * +------------+--------------------------+--------------------------+ * - * To enable nearest-neighbor scaling: program scaler coefficents with + * To enable nearest-neighbor scaling: program scaler coefficients with * the center tap (Dxx) values set to 1 and all other values set to 0 as per * SCALER_COEFFICIENT_FORMAT * */ static void glk_program_nearest_filter_coefs(struct intel_display *display, + struct intel_dsb *dsb, enum pipe pipe, int id, int set) { int i; - intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(pipe, id, set), - PS_COEF_INDEX_AUTO_INC); + intel_de_write_dsb(display, dsb, + GLK_PS_COEF_INDEX_SET(pipe, id, set), + PS_COEF_INDEX_AUTO_INC); for (i = 0; i < 17 * 7; i += 2) { u32 tmp; @@ -621,11 +685,12 @@ static void glk_program_nearest_filter_coefs(struct intel_display *display, t = glk_coef_tap(i + 1); tmp |= glk_nearest_filter_coef(t) << 16; - intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(pipe, id, set), - tmp); + intel_de_write_dsb(display, dsb, + GLK_PS_COEF_DATA_SET(pipe, id, set), tmp); } - intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0); + intel_de_write_dsb(display, dsb, + GLK_PS_COEF_INDEX_SET(pipe, id, set), 0); } static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set) @@ -641,14 +706,15 @@ static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set) return PS_FILTER_MEDIUM; } -static void skl_scaler_setup_filter(struct intel_display *display, enum pipe pipe, +static void skl_scaler_setup_filter(struct intel_display *display, + struct intel_dsb *dsb, enum pipe pipe, int id, int set, enum drm_scaling_filter filter) { switch (filter) { case DRM_SCALING_FILTER_DEFAULT: break; case DRM_SCALING_FILTER_NEAREST_NEIGHBOR: - glk_program_nearest_filter_coefs(display, pipe, id, set); + glk_program_nearest_filter_coefs(display, dsb, pipe, id, set); break; default: MISSING_CASE(filter); @@ -695,7 +761,9 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state) ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode | skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0); - skl_scaler_setup_filter(display, pipe, id, 0, + trace_intel_pipe_scaler_update_arm(crtc, id, x, y, width, height); + + skl_scaler_setup_filter(display, NULL, pipe, id, 0, crtc_state->hw.scaling_filter); intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl); @@ -711,12 +779,12 @@ void skl_pfit_enable(const struct intel_crtc_state *crtc_state) } void -skl_program_plane_scaler(struct intel_plane *plane, +skl_program_plane_scaler(struct intel_dsb *dsb, + struct intel_plane *plane, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; enum pipe pipe = plane->pipe; int scaler_id = plane_state->scaler_id; @@ -740,7 +808,7 @@ skl_program_plane_scaler(struct intel_plane *plane, /* TODO: handle sub-pixel coordinates */ if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && - !icl_is_hdr_plane(dev_priv, plane->id)) { + !icl_is_hdr_plane(display, plane->id)) { y_hphase = skl_scaler_calc_phase(1, hscale, false); y_vphase = skl_scaler_calc_phase(1, vscale, false); @@ -759,33 +827,41 @@ skl_program_plane_scaler(struct intel_plane *plane, ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode | skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0); - skl_scaler_setup_filter(display, pipe, scaler_id, 0, + trace_intel_plane_scaler_update_arm(plane, scaler_id, + crtc_x, crtc_y, crtc_w, crtc_h); + + skl_scaler_setup_filter(display, dsb, pipe, scaler_id, 0, plane_state->hw.scaling_filter); - intel_de_write_fw(display, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); - intel_de_write_fw(display, SKL_PS_VPHASE(pipe, scaler_id), - PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); - intel_de_write_fw(display, SKL_PS_HPHASE(pipe, scaler_id), - PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); - intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, scaler_id), - PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y)); - intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, scaler_id), - PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h)); + intel_de_write_dsb(display, dsb, SKL_PS_CTRL(pipe, scaler_id), + ps_ctrl); + intel_de_write_dsb(display, dsb, SKL_PS_VPHASE(pipe, scaler_id), + PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); + intel_de_write_dsb(display, dsb, SKL_PS_HPHASE(pipe, scaler_id), + PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); + intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(pipe, scaler_id), + PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y)); + intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(pipe, scaler_id), + PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h)); } -static void skl_detach_scaler(struct intel_crtc *crtc, int id) +static void skl_detach_scaler(struct intel_dsb *dsb, + struct intel_crtc *crtc, int id) { struct intel_display *display = to_intel_display(crtc); - intel_de_write_fw(display, SKL_PS_CTRL(crtc->pipe, id), 0); - intel_de_write_fw(display, SKL_PS_WIN_POS(crtc->pipe, id), 0); - intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, id), 0); + trace_intel_scaler_disable_arm(crtc, id); + + intel_de_write_dsb(display, dsb, SKL_PS_CTRL(crtc->pipe, id), 0); + intel_de_write_dsb(display, dsb, SKL_PS_WIN_POS(crtc->pipe, id), 0); + intel_de_write_dsb(display, dsb, SKL_PS_WIN_SZ(crtc->pipe, id), 0); } /* * This function detaches (aka. unbinds) unused scalers in hardware */ -void skl_detach_scalers(const struct intel_crtc_state *crtc_state) +void skl_detach_scalers(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); const struct intel_crtc_scaler_state *scaler_state = @@ -795,7 +871,7 @@ void skl_detach_scalers(const struct intel_crtc_state *crtc_state) /* loop through and disable scalers that aren't in use */ for (i = 0; i < crtc->num_scalers; i++) { if (!scaler_state->scalers[i].in_use) - skl_detach_scaler(crtc, i); + skl_detach_scaler(dsb, crtc, i); } } @@ -805,7 +881,7 @@ void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state) int i; for (i = 0; i < crtc->num_scalers; i++) - skl_detach_scaler(crtc, i); + skl_detach_scaler(NULL, crtc, i); } void skl_scaler_get_config(struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h index 4d2e2dbb1666..355ea15260ca 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.h +++ b/drivers/gpu/drm/i915/display/skl_scaler.h @@ -8,6 +8,7 @@ struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; +struct intel_dsb; struct intel_plane; struct intel_plane_state; @@ -21,10 +22,12 @@ int intel_atomic_setup_scalers(struct intel_atomic_state *state, void skl_pfit_enable(const struct intel_crtc_state *crtc_state); -void skl_program_plane_scaler(struct intel_plane *plane, +void skl_program_plane_scaler(struct intel_dsb *dsb, + struct intel_plane *plane, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); -void skl_detach_scalers(const struct intel_crtc_state *crtc_state); +void skl_detach_scalers(struct intel_dsb *dsb, + const struct intel_crtc_state *crtc_state); void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state); void skl_scaler_get_config(struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index ff9764cac1e7..70e550539bb2 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -106,8 +106,6 @@ static const u32 icl_sdr_y_plane_formats[] = { DRM_FORMAT_Y216, DRM_FORMAT_XYUV8888, DRM_FORMAT_XVYU2101010, - DRM_FORMAT_XVYU12_16161616, - DRM_FORMAT_XVYU16161616, }; static const u32 icl_sdr_uv_plane_formats[] = { @@ -134,8 +132,6 @@ static const u32 icl_sdr_uv_plane_formats[] = { DRM_FORMAT_Y216, DRM_FORMAT_XYUV8888, DRM_FORMAT_XVYU2101010, - DRM_FORMAT_XVYU12_16161616, - DRM_FORMAT_XVYU16161616, }; static const u32 icl_hdr_plane_formats[] = { @@ -237,21 +233,19 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) } } -static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) +static u8 icl_nv12_y_plane_mask(struct intel_display *display) { - struct intel_display *display = &i915->display; - if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) return BIT(PLANE_4) | BIT(PLANE_5); else return BIT(PLANE_6) | BIT(PLANE_7); } -bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, +bool icl_is_nv12_y_plane(struct intel_display *display, enum plane_id plane_id) { - return DISPLAY_VER(dev_priv) >= 11 && - icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id); + return DISPLAY_VER(display) >= 11 && + icl_nv12_y_plane_mask(display) & BIT(plane_id); } u8 icl_hdr_plane_mask(void) @@ -259,9 +253,9 @@ u8 icl_hdr_plane_mask(void) return BIT(PLANE_1) | BIT(PLANE_2) | BIT(PLANE_3); } -bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) +bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id) { - return DISPLAY_VER(dev_priv) >= 11 && + return DISPLAY_VER(display) >= 11 && icl_hdr_plane_mask() & BIT(plane_id); } @@ -516,11 +510,84 @@ skl_plane_max_stride(struct intel_plane *plane, max_pixels, max_bytes); } +static bool tgl_plane_can_async_flip(u64 modifier) +{ + switch (modifier) { + case DRM_FORMAT_MOD_LINEAR: + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_4_TILED: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: + case I915_FORMAT_MOD_4_TILED_BMG_CCS: + case I915_FORMAT_MOD_4_TILED_LNL_CCS: + return true; + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: + return false; + default: + return false; + } +} + +static bool icl_plane_can_async_flip(u64 modifier) +{ + switch (modifier) { + case DRM_FORMAT_MOD_LINEAR: + /* + * FIXME: Async on Linear buffer is supported on ICL + * but with additional alignment and fbc restrictions + * need to be taken care of. + */ + return false; + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Yf_TILED: + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + return true; + default: + return false; + } +} + +static bool skl_plane_can_async_flip(u64 modifier) +{ + switch (modifier) { + case DRM_FORMAT_MOD_LINEAR: + return false; + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Yf_TILED: + return true; + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Yf_TILED_CCS: + /* + * Display WA #0731: skl + * WaDisableRCWithAsyncFlip: skl + * "When render decompression is enabled, hardware + * internally converts the Async flips to Sync flips." + * + * Display WA #1159: glk + * "Async flip with render compression may result in + * intermittent underrun corruption." + */ + return false; + default: + return false; + } +} + static u32 tgl_plane_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int color_plane) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); /* PLANE_SURF GGTT -> DPT alignment */ int mult = intel_fb_uses_dpt(fb) ? 512 : 1; @@ -528,28 +595,30 @@ static u32 tgl_plane_min_alignment(struct intel_plane *plane, if (intel_fb_is_ccs_aux_plane(fb, color_plane)) return mult * 4 * 1024; + /* + * FIXME ADL sees GGTT/DMAR faults with async + * flips unless we align to 16k at least. + * Figure out what's going on here... + */ + if (display->platform.alderlake_p && + intel_plane_can_async_flip(plane, fb->modifier)) + return mult * 16 * 1024; + switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_4_TILED: - /* - * FIXME ADL sees GGTT/DMAR faults with async - * flips unless we align to 16k at least. - * Figure out what's going on here... - */ - if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915)) - return mult * 16 * 1024; return mult * 4 * 1024; - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: - case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: - case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: - case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: case I915_FORMAT_MOD_4_TILED_BMG_CCS: case I915_FORMAT_MOD_4_TILED_LNL_CCS: /* @@ -574,6 +643,10 @@ static u32 skl_plane_min_alignment(struct intel_plane *plane, if (color_plane != 0) return 4 * 1024; + /* + * VT-d needs at least 256k alignment, + * but that's already covered below. + */ switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: case I915_FORMAT_MOD_X_TILED: @@ -609,7 +682,7 @@ icl_program_input_csc(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; enum plane_id plane_id = plane->id; @@ -754,7 +827,7 @@ static void skl_write_plane_wm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; @@ -800,7 +873,7 @@ skl_plane_disable_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; @@ -814,7 +887,7 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; if (!crtc_state->enable_psr2_sel_fetch) @@ -828,12 +901,11 @@ icl_plane_disable_arm(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; - if (icl_is_hdr_plane(dev_priv, plane_id)) + if (icl_is_hdr_plane(display, plane_id)) intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id), 0); skl_write_plane_wm(dsb, plane, crtc_state); @@ -847,22 +919,22 @@ static bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; enum plane_id plane_id = plane->id; intel_wakeref_t wakeref; bool ret; power_domain = POWER_DOMAIN_PIPE(plane->pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return false; - ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; + ret = intel_de_read(display, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; *pipe = plane->pipe; - intel_display_power_put(dev_priv, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); return ret; } @@ -1024,7 +1096,7 @@ static u32 skl_plane_ctl_rotate(unsigned int rotate) break; /* * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr - * while i915 HW rotation is clockwise, thats why this swapping. + * while i915 HW rotation is clockwise, that's why this swapping. */ case DRM_MODE_ROTATE_90: return PLANE_CTL_ROTATE_270; @@ -1079,10 +1151,10 @@ static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state) static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); u32 plane_ctl = 0; - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(display) >= 10) return plane_ctl; if (crtc_state->gamma_enable) @@ -1097,8 +1169,7 @@ static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; @@ -1106,7 +1177,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, plane_ctl = PLANE_CTL_ENABLE; - if (DISPLAY_VER(dev_priv) < 10) { + if (DISPLAY_VER(display) < 10) { plane_ctl |= skl_plane_ctl_alpha(plane_state); plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; @@ -1121,7 +1192,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, plane_ctl |= skl_plane_ctl_tiling(fb->modifier); plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK); - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) plane_ctl |= icl_plane_ctl_flip(rotation & DRM_MODE_REFLECT_MASK); @@ -1131,7 +1202,7 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; /* Wa_22012358565:adl-p */ - if (DISPLAY_VER(dev_priv) == 13) + if (DISPLAY_VER(display) == 13) plane_ctl |= adlp_plane_ctl_arb_slots(plane_state); return plane_ctl; @@ -1139,10 +1210,10 @@ static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state); u32 plane_color_ctl = 0; - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) return plane_color_ctl; if (crtc_state->gamma_enable) @@ -1157,8 +1228,7 @@ static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); u32 plane_color_ctl = 0; @@ -1166,7 +1236,7 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); - if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { + if (fb->format->is_yuv && !icl_is_hdr_plane(display, plane->id)) { switch (plane_state->hw.color_encoding) { case DRM_COLOR_YCBCR_BT709: plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709; @@ -1196,7 +1266,7 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, static u32 skl_surf_address(const struct intel_plane_state *plane_state, int color_plane) { - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; u32 offset = plane_state->view.color_plane[color_plane].offset; @@ -1205,12 +1275,12 @@ static u32 skl_surf_address(const struct intel_plane_state *plane_state, * The DPT object contains only one vma, so the VMA's offset * within the DPT is always 0. */ - drm_WARN_ON(&i915->drm, plane_state->dpt_vma && + drm_WARN_ON(display->drm, plane_state->dpt_vma && intel_dpt_offset(plane_state->dpt_vma)); - drm_WARN_ON(&i915->drm, offset & 0x1fffff); + drm_WARN_ON(display->drm, offset & 0x1fffff); return offset >> 9; } else { - drm_WARN_ON(&i915->drm, offset & 0xfff); + drm_WARN_ON(display->drm, offset & 0xfff); return offset; } } @@ -1229,10 +1299,10 @@ static u32 skl_plane_surf(const struct intel_plane_state *plane_state, return plane_surf; } -static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, - int color_plane) +u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, + int color_plane) { - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; int aux_plane = skl_main_to_aux_plane(fb, color_plane); u32 aux_dist; @@ -1243,7 +1313,7 @@ static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, aux_dist = skl_surf_address(plane_state, aux_plane) - skl_surf_address(plane_state, color_plane); - if (DISPLAY_VER(i915) < 12) + if (DISPLAY_VER(display) < 12) aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane)); return aux_dist; @@ -1281,7 +1351,7 @@ static void icl_plane_csc_load_black(struct intel_dsb *dsb, struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; @@ -1305,8 +1375,7 @@ static void icl_plane_csc_load_black(struct intel_dsb *dsb, static int icl_plane_color_plane(const struct intel_plane_state *plane_state) { - /* Program the UV plane on planar master */ - if (plane_state->planar_linked_plane && !plane_state->planar_slave) + if (plane_state->planar_linked_plane && !plane_state->is_y_plane) return 1; else return 0; @@ -1318,7 +1387,7 @@ skl_plane_update_noarm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; u32 stride = skl_plane_stride(plane_state, 0); @@ -1349,8 +1418,7 @@ skl_plane_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; u32 x = plane_state->view.color_plane[0].x; @@ -1365,7 +1433,7 @@ skl_plane_update_arm(struct intel_dsb *dsb, crtc_state->async_flip_planes & BIT(plane->id)) plane_ctl |= PLANE_CTL_ASYNC_FLIP; - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(display) >= 10) plane_color_ctl = plane_state->color_ctl | glk_plane_color_ctl_crtc(crtc_state); @@ -1386,7 +1454,7 @@ skl_plane_update_arm(struct intel_dsb *dsb, PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) | PLANE_OFFSET_X(plane_state->view.color_plane[1].x)); - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(display) >= 10) intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); @@ -1398,7 +1466,7 @@ skl_plane_update_arm(struct intel_dsb *dsb, * TODO: split into noarm+arm pair */ if (plane_state->scaler_id >= 0) - skl_program_plane_scaler(plane, crtc_state, plane_state); + skl_program_plane_scaler(dsb, plane, crtc_state, plane_state); /* * The control register self-arms if the plane was previously @@ -1417,7 +1485,7 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_dsb *dsb, const struct intel_plane_state *plane_state, int color_plane) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; const struct drm_rect *clip; u32 val; @@ -1463,8 +1531,7 @@ icl_plane_update_noarm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; int color_plane = icl_plane_color_plane(plane_state); @@ -1512,18 +1579,18 @@ icl_plane_update_noarm(struct intel_dsb *dsb, } /* FLAT CCS doesn't need to program AUX_DIST */ - if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20) + if (!HAS_FLAT_CCS(to_i915(display->drm)) && DISPLAY_VER(display) < 20) intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id), skl_plane_aux_dist(plane_state, color_plane)); - if (icl_is_hdr_plane(dev_priv, plane_id)) + if (icl_is_hdr_plane(display, plane_id)) intel_de_write_dsb(display, dsb, PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl); intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); - if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) + if (fb->format->is_yuv && icl_is_hdr_plane(display, plane_id)) icl_program_input_csc(dsb, plane, plane_state); skl_write_plane_wm(dsb, plane, crtc_state); @@ -1543,7 +1610,7 @@ static void icl_plane_update_sel_fetch_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; if (!crtc_state->enable_psr2_sel_fetch) @@ -1562,7 +1629,7 @@ icl_plane_update_arm(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; int color_plane = icl_plane_color_plane(plane_state); @@ -1579,7 +1646,7 @@ icl_plane_update_arm(struct intel_dsb *dsb, * TODO: split into noarm+arm pair */ if (plane_state->scaler_id >= 0) - skl_program_plane_scaler(plane, crtc_state, plane_state); + skl_program_plane_scaler(dsb, plane, crtc_state, plane_state); icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state); @@ -1594,6 +1661,17 @@ icl_plane_update_arm(struct intel_dsb *dsb, skl_plane_surf(plane_state, color_plane)); } +static void skl_plane_capture_error(struct intel_crtc *crtc, + struct intel_plane *plane, + struct intel_plane_error *error) +{ + struct intel_display *display = to_intel_display(plane); + + error->ctl = intel_de_read(display, PLANE_CTL(crtc->pipe, plane->id)); + error->surf = intel_de_read(display, PLANE_SURF(crtc->pipe, plane->id)); + error->surflive = intel_de_read(display, PLANE_SURFLIVE(crtc->pipe, plane->id)); +} + static void skl_plane_async_flip(struct intel_dsb *dsb, struct intel_plane *plane, @@ -1601,7 +1679,7 @@ skl_plane_async_flip(struct intel_dsb *dsb, const struct intel_plane_state *plane_state, bool async_flip) { - struct intel_display *display = to_intel_display(plane->base.dev); + struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; u32 plane_ctl = plane_state->ctl, plane_surf; @@ -1637,8 +1715,8 @@ static bool intel_format_is_p01x(u32 format) static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; @@ -1647,16 +1725,17 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && intel_fb_is_ccs_modifier(fb->modifier)) { - drm_dbg_kms(&dev_priv->drm, - "RC support only with 0/180 degree rotation (%x)\n", - rotation); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] RC support only with 0/180 degree rotation (%x)\n", + plane->base.base.id, plane->base.name, rotation); return -EINVAL; } if (rotation & DRM_MODE_REFLECT_X && fb->modifier == DRM_FORMAT_MOD_LINEAR) { - drm_dbg_kms(&dev_priv->drm, - "horizontal flip is not supported with linear surface formats\n"); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] horizontal flip is not supported with linear surface formats\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -1665,16 +1744,18 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, */ if (rotation & DRM_MODE_REFLECT_X && intel_fb_is_tile4_modifier(fb->modifier) && - DISPLAY_VER(dev_priv) >= 20) { - drm_dbg_kms(&dev_priv->drm, - "horizontal flip is not supported with tile4 surface formats\n"); + DISPLAY_VER(display) >= 20) { + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] horizontal flip is not supported with tile4 surface formats\n", + plane->base.base.id, plane->base.name); return -EINVAL; } if (drm_rotation_90_or_270(rotation)) { if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) { - drm_dbg_kms(&dev_priv->drm, - "Y/Yf tiling required for 90/270!\n"); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] Y/Yf tiling required for 90/270!\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -1684,7 +1765,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, */ switch (fb->format->format) { case DRM_FORMAT_RGB565: - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) break; fallthrough; case DRM_FORMAT_C8: @@ -1697,9 +1778,9 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, case DRM_FORMAT_Y216: case DRM_FORMAT_XVYU12_16161616: case DRM_FORMAT_XVYU16161616: - drm_dbg_kms(&dev_priv->drm, - "Unsupported pixel format %p4cc for 90/270!\n", - &fb->format->format); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] unsupported pixel format %p4cc for 90/270!\n", + plane->base.base.id, plane->base.name, &fb->format->format); return -EINVAL; default: break; @@ -1711,17 +1792,19 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && fb->modifier != DRM_FORMAT_MOD_LINEAR && fb->modifier != I915_FORMAT_MOD_X_TILED) { - drm_dbg_kms(&dev_priv->drm, - "Y/Yf tiling not supported in IF-ID mode\n"); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] Y/Yf tiling not supported in IF-ID mode\n", + plane->base.base.id, plane->base.name); return -EINVAL; } /* Wa_1606054188:tgl,adl-s */ - if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) && + if ((display->platform.alderlake_s || display->platform.tigerlake) && plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && intel_format_is_p01x(fb->format->format)) { - drm_dbg_kms(&dev_priv->drm, - "Source color keying not supported with P01x formats\n"); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] source color keying not supported with P01x formats\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -1731,8 +1814,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = - to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); int crtc_x = plane_state->uapi.dst.x1; int crtc_w = drm_rect_width(&plane_state->uapi.dst); int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); @@ -1746,10 +1829,11 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s * than the cursor ending less than 4 pixels from the left edge of the * screen may cause FIFO underflow and display corruption. */ - if (DISPLAY_VER(dev_priv) == 10 && + if (DISPLAY_VER(display) == 10 && (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { - drm_dbg_kms(&dev_priv->drm, - "requested plane X %s position %d invalid (valid range %d-%d)\n", + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] requested plane X %s position %d invalid (valid range %d-%d)\n", + plane->base.base.id, plane->base.name, crtc_x + crtc_w < 4 ? "end" : "start", crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, 4, pipe_src_w - 4); @@ -1761,7 +1845,8 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state) { - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; @@ -1771,14 +1856,16 @@ static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_s src_w & 3 && (rotation == DRM_MODE_ROTATE_270 || rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) { - drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n"); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] src width must be multiple of 4 for rotated planar YUV\n", + plane->base.base.id, plane->base.name); return -EINVAL; } return 0; } -static int skl_plane_max_scale(struct drm_i915_private *dev_priv, +static int skl_plane_max_scale(struct intel_display *display, const struct drm_framebuffer *fb) { /* @@ -1787,7 +1874,7 @@ static int skl_plane_max_scale(struct drm_i915_private *dev_priv, * the best case. * FIXME need to properly check this later. */ - if (DISPLAY_VER(dev_priv) >= 10 || + if (DISPLAY_VER(display) >= 10 || !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) return 0x30000 - 1; else @@ -1876,8 +1963,8 @@ skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, int *x, int *y, u32 *offset) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; int aux_plane = skl_main_to_aux_plane(fb, 0); u32 aux_offset = plane_state->view.color_plane[aux_plane].offset; @@ -1886,7 +1973,7 @@ int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, intel_add_fb_offsets(x, y, plane_state, 0); *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0); - if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) + if (drm_WARN_ON(display->drm, alignment && !is_power_of_2(alignment))) return -EINVAL; /* @@ -1910,8 +1997,9 @@ int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) { if (*offset == 0) { - drm_dbg_kms(&dev_priv->drm, - "Unable to find suitable display surface offset due to X-tiling\n"); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] unable to find suitable display surface offset due to X-tiling\n", + plane->base.base.id, plane->base.name); return -EINVAL; } @@ -1926,8 +2014,8 @@ int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, static int skl_check_main_surface(struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; int x = plane_state->uapi.src.x1 >> 16; @@ -1943,8 +2031,9 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) int ret; if (w > max_width || w < min_width || h > max_height || h < 1) { - drm_dbg_kms(&dev_priv->drm, - "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", + plane->base.base.id, plane->base.name, w, h, min_width, max_width, max_height); return -EINVAL; } @@ -1970,16 +2059,17 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) if (x != plane_state->view.color_plane[aux_plane].x || y != plane_state->view.color_plane[aux_plane].y) { - drm_dbg_kms(&dev_priv->drm, - "Unable to find suitable display surface offset due to CCS\n"); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] unable to find suitable display surface offset due to CCS\n", + plane->base.base.id, plane->base.name); return -EINVAL; } } - if (DISPLAY_VER(dev_priv) >= 13) - drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535); + if (DISPLAY_VER(display) >= 13) + drm_WARN_ON(display->drm, x > 65535 || y > 65535); else - drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191); + drm_WARN_ON(display->drm, x > 8191 || y > 8191); plane_state->view.color_plane[0].offset = offset; plane_state->view.color_plane[0].x = x; @@ -1997,8 +2087,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; int uv_plane = 1; @@ -2014,8 +2104,9 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) /* FIXME not quite sure how/if these apply to the chroma plane */ if (w > max_width || h > max_height) { - drm_dbg_kms(&i915->drm, - "CbCr source size %dx%d too big (limit %dx%d)\n", + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] CbCr source size %dx%d too big (limit %dx%d)\n", + plane->base.base.id, plane->base.name, w, h, max_width, max_height); return -EINVAL; } @@ -2048,16 +2139,17 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) if (x != plane_state->view.color_plane[ccs_plane].x || y != plane_state->view.color_plane[ccs_plane].y) { - drm_dbg_kms(&i915->drm, - "Unable to find suitable display surface offset due to CCS\n"); + drm_dbg_kms(display->drm, + "[PLANE:%d:%s] unable to find suitable display surface offset due to CCS\n", + plane->base.base.id, plane->base.name); return -EINVAL; } } - if (DISPLAY_VER(i915) >= 13) - drm_WARN_ON(&i915->drm, x > 65535 || y > 65535); + if (DISPLAY_VER(display) >= 13) + drm_WARN_ON(display->drm, x > 65535 || y > 65535); else - drm_WARN_ON(&i915->drm, x > 8191 || y > 8191); + drm_WARN_ON(display->drm, x > 8191 || y > 8191); plane_state->view.color_plane[uv_plane].offset = offset; plane_state->view.color_plane[uv_plane].x = x; @@ -2143,9 +2235,13 @@ static int skl_check_plane_surface(struct intel_plane_state *plane_state) static bool skl_fb_scalable(const struct drm_framebuffer *fb) { + struct intel_display *display; + if (!fb) return false; + display = to_intel_display(fb->dev); + switch (fb->format->format) { case DRM_FORMAT_C8: return false; @@ -2153,7 +2249,7 @@ static bool skl_fb_scalable(const struct drm_framebuffer *fb) case DRM_FORMAT_ARGB16161616F: case DRM_FORMAT_XBGR16161616F: case DRM_FORMAT_ABGR16161616F: - return DISPLAY_VER(to_i915(fb->dev)) >= 11; + return DISPLAY_VER(display) >= 11; default: return true; } @@ -2161,24 +2257,61 @@ static bool skl_fb_scalable(const struct drm_framebuffer *fb) static void check_protection(struct intel_plane_state *plane_state) { - struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *i915 = to_i915(plane->base.dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; struct drm_gem_object *obj = intel_fb_bo(fb); - if (DISPLAY_VER(i915) < 11) + if (DISPLAY_VER(display) < 11) return; - plane_state->decrypt = intel_pxp_key_check(i915->pxp, obj, false) == 0; + plane_state->decrypt = intel_pxp_key_check(obj, false) == 0; plane_state->force_black = intel_bo_is_protected(obj) && !plane_state->decrypt; } +static void +make_damage_viewport_relative(struct intel_plane_state *plane_state) +{ + const struct drm_framebuffer *fb = plane_state->hw.fb; + const struct drm_rect *src = &plane_state->uapi.src; + unsigned int rotation = plane_state->hw.rotation; + struct drm_rect *damage = &plane_state->damage; + + if (!drm_rect_visible(damage)) + return; + + if (!fb || !plane_state->uapi.visible) { + plane_state->damage = DRM_RECT_INIT(0, 0, 0, 0); + return; + } + + if (drm_rotation_90_or_270(rotation)) { + drm_rect_rotate(damage, fb->width, fb->height, + DRM_MODE_ROTATE_270); + drm_rect_translate(damage, -(src->y1 >> 16), -(src->x1 >> 16)); + } else { + drm_rect_translate(damage, -(src->x1 >> 16), -(src->y1 >> 16)); + } +} + +static void clip_damage(struct intel_plane_state *plane_state) +{ + struct drm_rect *damage = &plane_state->damage; + struct drm_rect src; + + if (!drm_rect_visible(damage)) + return; + + drm_rect_fp_to_int(&src, &plane_state->uapi.src); + drm_rect_translate(damage, src.x1, src.y1); + drm_rect_intersect(damage, &src); +} + static int skl_plane_check(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; int min_scale = DRM_PLANE_NO_SCALING; int max_scale = DRM_PLANE_NO_SCALING; @@ -2191,7 +2324,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, /* use scaler when colorkey is not required */ if (!plane_state->ckey.flags && skl_fb_scalable(fb)) { min_scale = 1; - max_scale = skl_plane_max_scale(dev_priv, fb); + max_scale = skl_plane_max_scale(display, fb); } ret = intel_atomic_plane_check_clipping(plane_state, crtc_state, @@ -2199,6 +2332,8 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, if (ret) return ret; + make_damage_viewport_relative(plane_state); + ret = skl_check_plane_surface(plane_state); if (ret) return ret; @@ -2214,6 +2349,8 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, if (ret) return ret; + clip_damage(plane_state); + ret = skl_plane_check_nv12_rotation(plane_state); if (ret) return ret; @@ -2221,17 +2358,19 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, check_protection(plane_state); /* HW only has 8 bits pixel precision, disable plane if invisible */ - if (!(plane_state->hw.alpha >> 8)) + if (!(plane_state->hw.alpha >> 8)) { plane_state->uapi.visible = false; + plane_state->damage = DRM_RECT_INIT(0, 0, 0, 0); + } plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(display) >= 10) plane_state->color_ctl = glk_plane_color_ctl(crtc_state, plane_state); if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && - icl_is_hdr_plane(dev_priv, plane->id)) + icl_is_hdr_plane(display, plane->id)) /* Enable and use MPEG-2 chroma siting */ plane_state->cus_ctl = PLANE_CUS_ENABLE | PLANE_CUS_HPHASE_0 | @@ -2242,42 +2381,74 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, return 0; } +void icl_link_nv12_planes(struct intel_plane_state *uv_plane_state, + struct intel_plane_state *y_plane_state) +{ + struct intel_display *display = to_intel_display(uv_plane_state); + struct intel_plane *uv_plane = to_intel_plane(uv_plane_state->uapi.plane); + struct intel_plane *y_plane = to_intel_plane(y_plane_state->uapi.plane); + + drm_WARN_ON(display->drm, icl_is_nv12_y_plane(display, uv_plane->id)); + drm_WARN_ON(display->drm, !icl_is_nv12_y_plane(display, y_plane->id)); + + y_plane_state->ctl |= PLANE_CTL_YUV420_Y_PLANE; + + if (icl_is_hdr_plane(display, uv_plane->id)) { + switch (y_plane->id) { + case PLANE_7: + uv_plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; + break; + case PLANE_6: + uv_plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; + break; + case PLANE_5: + uv_plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; + break; + case PLANE_4: + uv_plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; + break; + default: + MISSING_CASE(y_plane->id); + } + } +} + static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) { return pipe - PIPE_A + INTEL_FBC_A; } -static bool skl_plane_has_fbc(struct drm_i915_private *i915, +static bool skl_plane_has_fbc(struct intel_display *display, enum intel_fbc_id fbc_id, enum plane_id plane_id) { - if ((DISPLAY_RUNTIME_INFO(i915)->fbc_mask & BIT(fbc_id)) == 0) + if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0) return false; - if (DISPLAY_VER(i915) >= 20) - return icl_is_hdr_plane(i915, plane_id); + if (DISPLAY_VER(display) >= 20) + return icl_is_hdr_plane(display, plane_id); else return plane_id == PLANE_1; } -static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv, +static struct intel_fbc *skl_plane_fbc(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) { enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe); - if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id)) - return dev_priv->display.fbc[fbc_id]; + if (skl_plane_has_fbc(display, fbc_id, plane_id)) + return display->fbc[fbc_id]; else return NULL; } -static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, +static bool skl_plane_has_planar(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) { /* Display WA #0870: skl, bxt */ - if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) + if (display->platform.skylake || display->platform.broxton) return false; - if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C) + if (DISPLAY_VER(display) == 9 && pipe == PIPE_C) return false; if (plane_id != PLANE_1 && plane_id != PLANE_2) @@ -2286,11 +2457,11 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, return true; } -static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, +static const u32 *skl_get_plane_formats(struct intel_display *display, enum pipe pipe, enum plane_id plane_id, int *num_formats) { - if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { + if (skl_plane_has_planar(display, pipe, plane_id)) { *num_formats = ARRAY_SIZE(skl_planar_formats); return skl_planar_formats; } else { @@ -2299,11 +2470,11 @@ static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, } } -static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, +static const u32 *glk_get_plane_formats(struct intel_display *display, enum pipe pipe, enum plane_id plane_id, int *num_formats) { - if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { + if (skl_plane_has_planar(display, pipe, plane_id)) { *num_formats = ARRAY_SIZE(glk_planar_formats); return glk_planar_formats; } else { @@ -2312,14 +2483,14 @@ static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, } } -static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, +static const u32 *icl_get_plane_formats(struct intel_display *display, enum pipe pipe, enum plane_id plane_id, int *num_formats) { - if (icl_is_hdr_plane(dev_priv, plane_id)) { + if (icl_is_hdr_plane(display, plane_id)) { *num_formats = ARRAY_SIZE(icl_hdr_plane_formats); return icl_hdr_plane_formats; - } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) { + } else if (icl_is_nv12_y_plane(display, plane_id)) { *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats); return icl_sdr_y_plane_formats; } else { @@ -2537,64 +2708,78 @@ skl_plane_disable_flip_done(struct intel_plane *plane) spin_unlock_irq(&i915->irq_lock); } -static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, +static bool skl_plane_has_rc_ccs(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) { - /* Wa_22011186057 */ - if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) - return false; + return pipe != PIPE_C && + (plane_id == PLANE_1 || plane_id == PLANE_2); +} - if (DISPLAY_VER(i915) >= 11) - return true; +static u8 skl_plane_caps(struct intel_display *display, + enum pipe pipe, enum plane_id plane_id) +{ + u8 caps = INTEL_PLANE_CAP_TILING_X | + INTEL_PLANE_CAP_TILING_Y | + INTEL_PLANE_CAP_TILING_Yf; - if (IS_GEMINILAKE(i915)) - return pipe != PIPE_C; + if (skl_plane_has_rc_ccs(display, pipe, plane_id)) + caps |= INTEL_PLANE_CAP_CCS_RC; - return pipe != PIPE_C && - (plane_id == PLANE_1 || plane_id == PLANE_2); + return caps; } -static bool tgl_plane_has_mc_ccs(struct drm_i915_private *i915, - enum plane_id plane_id) +static bool glk_plane_has_rc_ccs(struct intel_display *display, + enum pipe pipe) { - if (DISPLAY_VER(i915) < 12) - return false; + return pipe != PIPE_C; +} - /* Wa_14010477008 */ - if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || - (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0))) - return false; +static u8 glk_plane_caps(struct intel_display *display, + enum pipe pipe, enum plane_id plane_id) +{ + u8 caps = INTEL_PLANE_CAP_TILING_X | + INTEL_PLANE_CAP_TILING_Y | + INTEL_PLANE_CAP_TILING_Yf; + + if (glk_plane_has_rc_ccs(display, pipe)) + caps |= INTEL_PLANE_CAP_CCS_RC; - /* Wa_22011186057 */ - if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) + return caps; +} + +static u8 icl_plane_caps(struct intel_display *display, + enum pipe pipe, enum plane_id plane_id) +{ + return INTEL_PLANE_CAP_TILING_X | + INTEL_PLANE_CAP_TILING_Y | + INTEL_PLANE_CAP_TILING_Yf | + INTEL_PLANE_CAP_CCS_RC; +} + +static bool tgl_plane_has_mc_ccs(struct intel_display *display, + enum plane_id plane_id) +{ + /* Wa_14010477008 */ + if (display->platform.dg1 || display->platform.rocketlake || + (display->platform.tigerlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_D0))) return false; return plane_id < PLANE_6; } -static u8 skl_get_plane_caps(struct drm_i915_private *i915, - enum pipe pipe, enum plane_id plane_id) +static u8 tgl_plane_caps(struct intel_display *display, + enum pipe pipe, enum plane_id plane_id) { - struct intel_display *display = &i915->display; - u8 caps = INTEL_PLANE_CAP_TILING_X; + u8 caps = INTEL_PLANE_CAP_TILING_X | + INTEL_PLANE_CAP_CCS_RC | + INTEL_PLANE_CAP_CCS_RC_CC; - if (DISPLAY_VER(display) < 13 || display->platform.alderlake_p) - caps |= INTEL_PLANE_CAP_TILING_Y; - if (DISPLAY_VER(display) < 12) - caps |= INTEL_PLANE_CAP_TILING_Yf; if (HAS_4TILE(display)) caps |= INTEL_PLANE_CAP_TILING_4; + else + caps |= INTEL_PLANE_CAP_TILING_Y; - if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(i915)) - return caps; - - if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) { - caps |= INTEL_PLANE_CAP_CCS_RC; - if (DISPLAY_VER(display) >= 12) - caps |= INTEL_PLANE_CAP_CCS_RC_CC; - } - - if (tgl_plane_has_mc_ccs(i915, plane_id)) + if (tgl_plane_has_mc_ccs(display, plane_id)) caps |= INTEL_PLANE_CAP_CCS_MC; if (DISPLAY_VER(display) >= 14 && display->platform.dgfx) @@ -2604,7 +2789,7 @@ static u8 skl_get_plane_caps(struct drm_i915_private *i915, } struct intel_plane * -skl_universal_plane_create(struct drm_i915_private *dev_priv, +skl_universal_plane_create(struct intel_display *display, enum pipe pipe, enum plane_id plane_id) { const struct drm_plane_funcs *plane_funcs; @@ -2616,6 +2801,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, const u32 *formats; int num_formats; int ret; + u8 caps; plane = intel_plane_alloc(); if (IS_ERR(plane)) @@ -2625,21 +2811,21 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->id = plane_id; plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id); - intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane); + intel_fbc_add_plane(skl_plane_fbc(display, pipe, plane_id), plane); - if (DISPLAY_VER(dev_priv) >= 30) { + if (DISPLAY_VER(display) >= 30) { plane->max_width = xe3_plane_max_width; plane->max_height = icl_plane_max_height; plane->min_cdclk = icl_plane_min_cdclk; - } else if (DISPLAY_VER(dev_priv) >= 11) { + } else if (DISPLAY_VER(display) >= 11) { plane->min_width = icl_plane_min_width; - if (icl_is_hdr_plane(dev_priv, plane_id)) + if (icl_is_hdr_plane(display, plane_id)) plane->max_width = icl_hdr_plane_max_width; else plane->max_width = icl_sdr_plane_max_width; plane->max_height = icl_plane_max_height; plane->min_cdclk = icl_plane_min_cdclk; - } else if (DISPLAY_VER(dev_priv) >= 10) { + } else if (DISPLAY_VER(display) >= 10) { plane->max_width = glk_plane_max_width; plane->max_height = skl_plane_max_height; plane->min_cdclk = glk_plane_min_cdclk; @@ -2649,17 +2835,20 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->min_cdclk = skl_plane_min_cdclk; } - if (DISPLAY_VER(dev_priv) >= 13) + if (DISPLAY_VER(display) >= 13) plane->max_stride = adl_plane_max_stride; else plane->max_stride = skl_plane_max_stride; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) plane->min_alignment = tgl_plane_min_alignment; else plane->min_alignment = skl_plane_min_alignment; - if (DISPLAY_VER(dev_priv) >= 11) { + if (intel_scanout_needs_vtd_wa(display)) + plane->vtd_guard = DISPLAY_VER(display) >= 10 ? 168 : 136; + + if (DISPLAY_VER(display) >= 11) { plane->update_noarm = icl_plane_update_noarm; plane->update_arm = icl_plane_update_arm; plane->disable_arm = icl_plane_disable_arm; @@ -2668,29 +2857,37 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->update_arm = skl_plane_update_arm; plane->disable_arm = skl_plane_disable_arm; } + plane->capture_error = skl_plane_capture_error; plane->get_hw_state = skl_plane_get_hw_state; plane->check_plane = skl_plane_check; - if (plane_id == PLANE_1) { - plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(dev_priv, 9, 10); + if (HAS_ASYNC_FLIPS(display) && plane_id == PLANE_1) { + plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(display, 9, 10); plane->async_flip = skl_plane_async_flip; plane->enable_flip_done = skl_plane_enable_flip_done; plane->disable_flip_done = skl_plane_disable_flip_done; + + if (DISPLAY_VER(display) >= 12) + plane->can_async_flip = tgl_plane_can_async_flip; + else if (DISPLAY_VER(display) == 11) + plane->can_async_flip = icl_plane_can_async_flip; + else + plane->can_async_flip = skl_plane_can_async_flip; } - if (DISPLAY_VER(dev_priv) >= 11) - formats = icl_get_plane_formats(dev_priv, pipe, + if (DISPLAY_VER(display) >= 11) + formats = icl_get_plane_formats(display, pipe, plane_id, &num_formats); - else if (DISPLAY_VER(dev_priv) >= 10) - formats = glk_get_plane_formats(dev_priv, pipe, + else if (DISPLAY_VER(display) >= 10) + formats = glk_get_plane_formats(display, pipe, plane_id, &num_formats); else - formats = skl_get_plane_formats(dev_priv, pipe, + formats = skl_get_plane_formats(display, pipe, plane_id, &num_formats); - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) plane_funcs = &tgl_plane_funcs; - else if (DISPLAY_VER(dev_priv) == 11) + else if (DISPLAY_VER(display) == 11) plane_funcs = &icl_plane_funcs; else plane_funcs = &skl_plane_funcs; @@ -2700,10 +2897,24 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane_type = DRM_PLANE_TYPE_OVERLAY; - modifiers = intel_fb_plane_get_modifiers(dev_priv, - skl_get_plane_caps(dev_priv, pipe, plane_id)); + if (DISPLAY_VER(display) >= 12) + caps = tgl_plane_caps(display, pipe, plane_id); + else if (DISPLAY_VER(display) == 11) + caps = icl_plane_caps(display, pipe, plane_id); + else if (DISPLAY_VER(display) == 10) + caps = glk_plane_caps(display, pipe, plane_id); + else + caps = skl_plane_caps(display, pipe, plane_id); + + /* FIXME: xe has problems with AUX */ + if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(to_i915(display->drm))) + caps &= ~(INTEL_PLANE_CAP_CCS_RC | + INTEL_PLANE_CAP_CCS_RC_CC | + INTEL_PLANE_CAP_CCS_MC); - ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, + modifiers = intel_fb_plane_get_modifiers(display, caps); + + ret = drm_universal_plane_init(display->drm, &plane->base, 0, plane_funcs, formats, num_formats, modifiers, plane_type, @@ -2715,14 +2926,14 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, if (ret) goto fail; - if (DISPLAY_VER(dev_priv) >= 13) + if (DISPLAY_VER(display) >= 13) supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; else supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) supported_rotations |= DRM_MODE_REFLECT_X; drm_plane_create_rotation_property(&plane->base, @@ -2731,7 +2942,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709); - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(display) >= 10) supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020); drm_plane_create_color_properties(&plane->base, @@ -2749,10 +2960,10 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, drm_plane_create_zpos_immutable_property(&plane->base, plane_id); - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) drm_plane_enable_fb_damage_clips(&plane->base); - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) drm_plane_create_scaling_filter_property(&plane->base, BIT(DRM_SCALING_FILTER_DEFAULT) | BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); @@ -2773,8 +2984,6 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, { struct intel_display *display = to_intel_display(crtc); struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); struct intel_plane *plane = to_intel_plane(crtc->base.primary); enum plane_id plane_id = plane->id; enum pipe pipe; @@ -2788,35 +2997,36 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, if (!plane->get_hw_state(plane, &pipe)) return; - drm_WARN_ON(dev, pipe != crtc->pipe); + drm_WARN_ON(display->drm, pipe != crtc->pipe); if (crtc_state->joiner_pipes) { - drm_dbg_kms(&dev_priv->drm, - "Unsupported joiner configuration for initial FB\n"); + drm_dbg_kms(display->drm, + "[CRTC:%d:%s] Unsupported joiner configuration for initial FB\n", + crtc->base.base.id, crtc->base.name); return; } intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); if (!intel_fb) { - drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); + drm_dbg_kms(display->drm, "failed to alloc fb\n"); return; } fb = &intel_fb->base; - fb->dev = dev; + fb->dev = display->drm; - val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id)); + val = intel_de_read(display, PLANE_CTL(pipe, plane_id)); - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL; else pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL; - if (DISPLAY_VER(dev_priv) >= 10) { + if (DISPLAY_VER(display) >= 10) { u32 color_ctl; - color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id)); + color_ctl = intel_de_read(display, PLANE_COLOR_CTL(pipe, plane_id)); alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl); } else { alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val); @@ -2838,14 +3048,14 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, case PLANE_CTL_TILED_Y: plane_config->tiling = I915_TILING_Y; if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE) - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER(display) >= 14) fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS; - else if (DISPLAY_VER(dev_priv) >= 12) + else if (DISPLAY_VER(display) >= 12) fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; else fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE) - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER(display) >= 14) fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS; else fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; @@ -2877,15 +3087,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, goto error; } - if (!dev_priv->display.params.enable_dpt && - intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) { - drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial FB\n"); + if (!display->params.enable_dpt && + intel_fb_modifier_uses_dpt(display, fb->modifier)) { + drm_dbg_kms(display->drm, "DPT disabled, skipping initial FB\n"); goto error; } /* * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr - * while i915 HW rotation is clockwise, thats why this swapping. + * while i915 HW rotation is clockwise, that's why this swapping. */ switch (val & PLANE_CTL_ROTATE_MASK) { case PLANE_CTL_ROTATE_0: @@ -2902,24 +3112,24 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, break; } - if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL) + if (DISPLAY_VER(display) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL) plane_config->rotation |= DRM_MODE_REFLECT_X; /* 90/270 degree rotation would require extra work */ if (drm_rotation_90_or_270(plane_config->rotation)) goto error; - base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK; + base = intel_de_read(display, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK; plane_config->base = base; - offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)); - drm_WARN_ON(&dev_priv->drm, offset != 0); + offset = intel_de_read(display, PLANE_OFFSET(pipe, plane_id)); + drm_WARN_ON(display->drm, offset != 0); - val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id)); + val = intel_de_read(display, PLANE_SIZE(pipe, plane_id)); fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1; fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1; - val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id)); + val = intel_de_read(display, PLANE_STRIDE(pipe, plane_id)); stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0); fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult; @@ -2928,11 +3138,12 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, plane_config->size = fb->pitches[0] * aligned_height; - drm_dbg_kms(&dev_priv->drm, - "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", - crtc->base.name, plane->base.name, fb->width, fb->height, - fb->format->cpp[0] * 8, base, fb->pitches[0], - plane_config->size); + drm_dbg_kms(display->drm, + "[CRTC:%d:%s][PLANE:%d:%s] with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", + crtc->base.base.id, crtc->base.name, + plane->base.base.id, plane->base.name, + fb->width, fb->height, fb->format->cpp[0] * 8, + base, fb->pitches[0], plane_config->size); plane_config->fb = intel_fb; return; @@ -2944,7 +3155,7 @@ error: bool skl_fixup_initial_plane_config(struct intel_crtc *crtc, const struct intel_initial_plane_config *plane_config) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_plane *plane = to_intel_plane(crtc->base.primary); const struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); @@ -2964,7 +3175,7 @@ bool skl_fixup_initial_plane_config(struct intel_crtc *crtc, if (plane_config->base == base) return false; - intel_de_write(i915, PLANE_SURF(pipe, plane_id), base); + intel_de_write(display, PLANE_SURF(pipe, plane_id), base); return true; } diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h b/drivers/gpu/drm/i915/display/skl_universal_plane.h index 541489479135..5e2451c21eeb 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h @@ -8,8 +8,8 @@ #include <linux/types.h> -struct drm_i915_private; struct intel_crtc; +struct intel_display; struct intel_initial_plane_config; struct intel_plane_state; struct skl_ddb_entry; @@ -19,7 +19,7 @@ enum pipe; enum plane_id; struct intel_plane * -skl_universal_plane_create(struct drm_i915_private *dev_priv, +skl_universal_plane_create(struct intel_display *display, enum pipe pipe, enum plane_id plane_id); void skl_get_initial_plane_config(struct intel_crtc *crtc, @@ -32,9 +32,15 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha); int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, int *x, int *y, u32 *offset); -bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, +void icl_link_nv12_planes(struct intel_plane_state *uv_plane_state, + struct intel_plane_state *y_plane_state); + +bool icl_is_nv12_y_plane(struct intel_display *display, enum plane_id plane_id); u8 icl_hdr_plane_mask(void); -bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id); +bool icl_is_hdr_plane(struct intel_display *display, enum plane_id plane_id); + +u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state, + int color_plane); #endif diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index f4458d1185b3..621e97943542 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -52,13 +52,13 @@ struct skl_wm_params { u32 dbuf_block_size; }; -u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915) +u8 intel_enabled_dbuf_slices_mask(struct intel_display *display) { u8 enabled_slices = 0; enum dbuf_slice slice; - for_each_dbuf_slice(i915, slice) { - if (intel_de_read(i915, DBUF_CTL_S(slice)) & DBUF_POWER_STATE) + for_each_dbuf_slice(display, slice) { + if (intel_de_read(display, DBUF_CTL_S(slice)) & DBUF_POWER_STATE) enabled_slices |= BIT(slice); } @@ -584,7 +584,7 @@ u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915, /* * Per plane DDB entry can in a really worst case be on multiple slices - * but single entry is anyway contigious. + * but single entry is anyway contiguous. */ while (start_slice <= end_slice) { slice_mask |= BIT(start_slice); @@ -836,6 +836,7 @@ static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, struct skl_ddb_entry *ddb_y, u16 *min_ddb, u16 *interim_ddb) { + struct intel_display *display = to_intel_display(crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); enum intel_display_power_domain power_domain; enum pipe pipe = crtc->pipe; @@ -843,7 +844,7 @@ static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, enum plane_id plane_id; power_domain = POWER_DOMAIN_PIPE(pipe); - wakeref = intel_display_power_get_if_enabled(i915, power_domain); + wakeref = intel_display_power_get_if_enabled(display, power_domain); if (!wakeref) return; @@ -855,7 +856,7 @@ static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, &min_ddb[plane_id], &interim_ddb[plane_id]); - intel_display_power_put(i915, power_domain, wakeref); + intel_display_power_put(display, power_domain, wakeref); } struct dbuf_slice_conf_entry { @@ -2259,8 +2260,8 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, struct skl_plane_wm *wm = &crtc_state->wm.skl.raw.planes[plane_id]; int ret; - /* Watermarks calculated in master */ - if (plane_state->planar_slave) + /* Watermarks calculated on UV plane */ + if (plane_state->is_y_plane) return 0; memset(wm, 0, sizeof(*wm)); @@ -2292,6 +2293,90 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state, return 0; } +static int +cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_atomic_state *state = + to_intel_atomic_state(crtc_state->uapi.state); + const struct intel_cdclk_state *cdclk_state; + + cdclk_state = intel_atomic_get_cdclk_state(state); + if (IS_ERR(cdclk_state)) { + drm_WARN_ON(display->drm, PTR_ERR(cdclk_state)); + return 1; + } + + return min(1, DIV_ROUND_UP(crtc_state->pixel_rate, + 2 * cdclk_state->logical.cdclk)); +} + +static int +dsc_prefill_latency(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + const struct intel_crtc_scaler_state *scaler_state = + &crtc_state->scaler_state; + int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal, + crtc_state->hw.adjusted_mode.clock); + int num_scaler_users = hweight32(scaler_state->scaler_users); + int chroma_downscaling_factor = + crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; + u32 dsc_prefill_latency = 0; + + if (!crtc_state->dsc.compression_enable || + !num_scaler_users || + num_scaler_users > crtc->num_scalers) + return dsc_prefill_latency; + + dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10); + + for (int i = 0; i < num_scaler_users; i++) { + u64 hscale_k, vscale_k; + + hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16); + vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16); + dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k, + 1000000); + } + + dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state); + + return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency); +} + +static int +scaler_prefill_latency(const struct intel_crtc_state *crtc_state) +{ + const struct intel_crtc_scaler_state *scaler_state = + &crtc_state->scaler_state; + int num_scaler_users = hweight32(scaler_state->scaler_users); + int scaler_prefill_latency = 0; + int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal, + crtc_state->hw.adjusted_mode.clock); + + if (!num_scaler_users) + return scaler_prefill_latency; + + scaler_prefill_latency = 4 * linetime; + + if (num_scaler_users > 1) { + u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16); + u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16); + int chroma_downscaling_factor = + crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1; + int latency; + + latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k * + chroma_downscaling_factor), 1000000); + scaler_prefill_latency += latency; + } + + scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state); + + return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, scaler_prefill_latency); +} + static bool skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, int wm0_lines, int latency) @@ -2299,9 +2384,10 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - /* FIXME missing scaler and DSC pre-fill time */ return crtc_state->framestart_delay + intel_usecs_to_scanlines(adjusted_mode, latency) + + scaler_prefill_latency(crtc_state) + + dsc_prefill_latency(crtc_state) + wm0_lines > adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start; } @@ -3074,6 +3160,7 @@ static void skl_wm_get_hw_state(struct drm_i915_private *i915) dbuf_state->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw); + dbuf_state->active_pipes = 0; for_each_intel_crtc(display->drm, crtc) { struct intel_crtc_state *crtc_state = @@ -3085,8 +3172,10 @@ static void skl_wm_get_hw_state(struct drm_i915_private *i915) memset(&crtc_state->wm.skl.optimal, 0, sizeof(crtc_state->wm.skl.optimal)); - if (crtc_state->hw.active) + if (crtc_state->hw.active) { skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); + dbuf_state->active_pipes |= BIT(pipe); + } crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal; memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe])); @@ -3204,7 +3293,7 @@ adjust_wm_latency(struct drm_i915_private *i915, * WaWmMemoryReadLatency * * punit doesn't take into account the read latency so we need - * to add proper adjustement to each valid level we retrieve + * to add proper adjustment to each valid level we retrieve * from the punit when level 0 response data is 0us. */ if (wm[0] == 0) { @@ -3618,7 +3707,7 @@ void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state) void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_dbuf_state *new_dbuf_state = intel_atomic_get_new_dbuf_state(state); const struct intel_dbuf_state *old_dbuf_state = @@ -3636,12 +3725,12 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state) WARN_ON(!new_dbuf_state->base.changed); - gen9_dbuf_slices_update(i915, new_slices); + gen9_dbuf_slices_update(display, new_slices); } void intel_dbuf_post_plane_update(struct intel_atomic_state *state) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_dbuf_state *new_dbuf_state = intel_atomic_get_new_dbuf_state(state); const struct intel_dbuf_state *old_dbuf_state = @@ -3659,7 +3748,7 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state) WARN_ON(!new_dbuf_state->base.changed); - gen9_dbuf_slices_update(i915, new_slices); + gen9_dbuf_slices_update(display, new_slices); } static void skl_mbus_sanitize(struct drm_i915_private *i915) @@ -3754,14 +3843,56 @@ static void skl_dbuf_sanitize(struct drm_i915_private *i915) } } -static void skl_wm_get_hw_state_and_sanitize(struct drm_i915_private *i915) +static void skl_wm_sanitize(struct drm_i915_private *i915) { - skl_wm_get_hw_state(i915); - skl_mbus_sanitize(i915); skl_dbuf_sanitize(i915); } +void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(crtc); + struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); + struct intel_dbuf_state *dbuf_state = + to_intel_dbuf_state(display->dbuf.obj.state); + enum pipe pipe = crtc->pipe; + + if (DISPLAY_VER(display) < 9) + return; + + dbuf_state->active_pipes &= ~BIT(pipe); + + dbuf_state->weight[pipe] = 0; + dbuf_state->slices[pipe] = 0; + + memset(&dbuf_state->ddb[pipe], 0, sizeof(dbuf_state->ddb[pipe])); + + memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); +} + +void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc, + struct intel_plane *plane) +{ + struct intel_display *display = to_intel_display(crtc); + struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); + + if (DISPLAY_VER(display) < 9) + return; + + skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0); + skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[plane->id], 0, 0); + + crtc_state->wm.skl.plane_min_ddb[plane->id] = 0; + crtc_state->wm.skl.plane_interim_ddb[plane->id] = 0; + + memset(&crtc_state->wm.skl.raw.planes[plane->id], 0, + sizeof(crtc_state->wm.skl.raw.planes[plane->id])); + memset(&crtc_state->wm.skl.optimal.planes[plane->id], 0, + sizeof(crtc_state->wm.skl.optimal.planes[plane->id])); +} + void intel_wm_state_verify(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -3792,7 +3923,7 @@ void intel_wm_state_verify(struct intel_atomic_state *state, skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y, hw->min_ddb, hw->interim_ddb); - hw_enabled_slices = intel_enabled_dbuf_slices_mask(i915); + hw_enabled_slices = intel_enabled_dbuf_slices_mask(display); if (DISPLAY_VER(i915) >= 11 && hw_enabled_slices != i915->display.dbuf.enabled_slices) @@ -3889,7 +4020,8 @@ void intel_wm_state_verify(struct intel_atomic_state *state, static const struct intel_wm_funcs skl_wm_funcs = { .compute_global_watermarks = skl_compute_wm, - .get_hw_state = skl_wm_get_hw_state_and_sanitize, + .get_hw_state = skl_wm_get_hw_state, + .sanitize = skl_wm_sanitize, }; void skl_wm_init(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h index 8659f89427f2..d9cff6c54310 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.h +++ b/drivers/gpu/drm/i915/display/skl_watermark.h @@ -17,12 +17,13 @@ struct intel_atomic_state; struct intel_bw_state; struct intel_crtc; struct intel_crtc_state; +struct intel_display; struct intel_plane; struct intel_plane_state; struct skl_pipe_wm; struct skl_wm_level; -u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915); +u8 intel_enabled_dbuf_slices_mask(struct intel_display *display); void intel_sagv_pre_plane_update(struct intel_atomic_state *state); void intel_sagv_post_plane_update(struct intel_atomic_state *state); @@ -40,6 +41,10 @@ bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, void intel_wm_state_verify(struct intel_atomic_state *state, struct intel_crtc *crtc); +void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc); +void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc, + struct intel_plane *plane); + void skl_watermark_ipc_init(struct drm_i915_private *i915); void skl_watermark_ipc_update(struct drm_i915_private *i915); bool skl_watermark_ipc_enabled(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index d49e9b3c7627..af717df83197 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -59,7 +59,7 @@ static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, 8 * 100), lane_count); } -/* return pixels equvalent to txbyteclkhs */ +/* return pixels equivalent to txbyteclkhs */ static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, u16 burst_mode_ratio) { @@ -283,7 +283,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder, if (ret) return ret; - ret = intel_panel_fitting(pipe_config, conn_state); + ret = intel_pfit_compute_config(pipe_config, conn_state); if (ret) return ret; @@ -739,7 +739,7 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, intel_dsi_wait_panel_power_cycle(intel_dsi); - intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); + intel_set_cpu_fifo_underrun_reporting(display, pipe, true); /* * The BIOS may leave the PLL in a wonky state where it doesn't @@ -947,7 +947,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, drm_dbg_kms(display->drm, "\n"); - wakeref = intel_display_power_get_if_enabled(dev_priv, + wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); if (!wakeref) return false; @@ -1007,7 +1007,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, } out_put_power: - intel_display_power_put(dev_priv, encoder->power_domain, wakeref); + intel_display_power_put(display, encoder->power_domain, wakeref); return active; } @@ -1541,14 +1541,14 @@ static const struct drm_encoder_funcs intel_dsi_funcs = { }; static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { - struct drm_i915_private *i915 = to_i915(connector->dev); + struct intel_display *display = to_intel_display(connector->dev); - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { + if (display->platform.valleyview || display->platform.cherryview) { enum drm_mode_status status; - status = intel_cpu_transcoder_mode_valid(i915, mode); + status = intel_cpu_transcoder_mode_valid(display, mode); if (status != MODE_OK) return status; } diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c index 59a50647f2c3..2ed47e7d1051 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c @@ -459,7 +459,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port, /* * rx divider value needs to be updated in the - * two differnt bit fields in the register hence splitting the + * two different bit fields in the register hence splitting the * rx divider value accordingly */ rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2; @@ -590,9 +590,9 @@ void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); } -static void assert_dsi_pll(struct drm_i915_private *i915, bool state) +static void assert_dsi_pll(struct intel_display *display, bool state) { - struct intel_display *display = &i915->display; + struct drm_i915_private *i915 = to_i915(display->drm); bool cur_state; vlv_cck_get(i915); @@ -604,12 +604,12 @@ static void assert_dsi_pll(struct drm_i915_private *i915, bool state) str_on_off(state), str_on_off(cur_state)); } -void assert_dsi_pll_enabled(struct drm_i915_private *i915) +void assert_dsi_pll_enabled(struct intel_display *display) { - assert_dsi_pll(i915, true); + assert_dsi_pll(display, true); } -void assert_dsi_pll_disabled(struct drm_i915_private *i915) +void assert_dsi_pll_disabled(struct intel_display *display) { - assert_dsi_pll(i915, false); + assert_dsi_pll(display, false); } diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h index fbe5113dbeb9..f975660fa609 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h @@ -11,6 +11,7 @@ enum port; struct drm_i915_private; struct intel_crtc_state; +struct intel_display; struct intel_encoder; int vlv_dsi_pll_compute(struct intel_encoder *encoder, @@ -22,7 +23,6 @@ u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, struct intel_crtc_state *config); void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port); -bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv); int bxt_dsi_pll_compute(struct intel_encoder *encoder, struct intel_crtc_state *config); void bxt_dsi_pll_enable(struct intel_encoder *encoder, @@ -33,13 +33,19 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port); #ifdef I915 -void assert_dsi_pll_enabled(struct drm_i915_private *i915); -void assert_dsi_pll_disabled(struct drm_i915_private *i915); +bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv); +void assert_dsi_pll_enabled(struct intel_display *display); +void assert_dsi_pll_disabled(struct intel_display *display); #else -static inline void assert_dsi_pll_enabled(struct drm_i915_private *i915) +static inline bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) { + return false; } -static inline void assert_dsi_pll_disabled(struct drm_i915_private *i915) +static inline void assert_dsi_pll_enabled(struct intel_display *display) +{ +} + +static inline void assert_dsi_pll_disabled(struct intel_display *display) { } #endif diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c index c0543c35cd6a..ab1af978911b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c @@ -238,7 +238,7 @@ static int proto_context_set_persistence(struct drm_i915_private *i915, * * However, if we cannot reset an engine by itself, we cannot * cleanup a hanging persistent context without causing - * colateral damage, and we should not pretend we can by + * collateral damage, and we should not pretend we can by * exposing the interface. */ if (!intel_has_reset_engine(to_gt(i915))) @@ -1589,7 +1589,7 @@ static int __context_set_persistence(struct i915_gem_context *ctx, bool state) * * However, if we cannot reset an engine by itself, we cannot * cleanup a hanging persistent context without causing - * colateral damage, and we should not pretend we can by + * collateral damage, and we should not pretend we can by * exposing the interface. */ if (!intel_has_reset_engine(to_gt(ctx->i915))) @@ -2328,7 +2328,7 @@ finalize_create_context_locked(struct drm_i915_file_private *file_priv, /* * One for the xarray and one for the caller. We need to grab - * the reference *prior* to making the ctx visble to userspace + * the reference *prior* to making the ctx visible to userspace * in gem_context_register(), as at any point after that * userspace can try to race us with another thread destroying * the context under our feet. diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h index b6d97da63d1f..67ac2586a0f3 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h @@ -245,9 +245,9 @@ struct i915_gem_context { * Execbuf uses the I915_EXEC_RING_MASK as an index into this * array to select which HW context + engine to execute on. For * the default array, the user_ring_map[] is used to translate - * the legacy uABI onto the approprate index (e.g. both + * the legacy uABI onto the appropriate index (e.g. both * I915_EXEC_DEFAULT and I915_EXEC_RENDER select the same - * context, and I915_EXEC_BSD is weird). For a use defined + * context, and I915_EXEC_BSD is weird). For a user defined * array, execbuf uses I915_EXEC_RING_MASK as a plain index. * * User defined by I915_CONTEXT_PARAM_ENGINE (when the @@ -276,7 +276,7 @@ struct i915_gem_context { * @vm: unique address space (GTT) * * In full-ppgtt mode, each context has its own address space ensuring - * complete seperation of one client from all others. + * complete separation of one client from all others. * * In other modes, this is a NULL pointer with the expectation that * the caller uses the shared global GTT. diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index 19156ba4b9ef..c3e6a325872d 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -193,7 +193,7 @@ i915_gem_dumb_create(struct drm_file *file, args->pitch = ALIGN(args->width * cpp, 64); /* align stride to page size so that we can remap */ - if (args->pitch > intel_plane_fb_max_stride(to_i915(dev), format, + if (args->pitch > intel_plane_fb_max_stride(dev, format, DRM_FORMAT_MOD_LINEAR)) args->pitch = ALIGN(args->pitch, 4096); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 3770828f2eaf..75a143d996e0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -18,8 +18,6 @@ #include "i915_gem_object_frontbuffer.h" #include "i915_vma.h" -#define VTD_GUARD (168u * I915_GTT_PAGE_SIZE) /* 168 or tile-row PTE padding */ - static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj) { struct drm_i915_private *i915 = to_i915(obj->base.dev); @@ -276,7 +274,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, * For objects created by userspace through GEM_CREATE with pat_index * set by set_pat extension, simply return 0 here without touching * the cache setting, because such objects should have an immutable - * cache setting by desgin and always managed by userspace. + * cache setting by design and always managed by userspace. */ if (i915_gem_object_has_cache_level(obj, cache_level)) return 0; @@ -424,7 +422,7 @@ out: struct i915_vma * i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, struct i915_gem_ww_ctx *ww, - u32 alignment, + u32 alignment, unsigned int guard, const struct i915_gtt_view *view, unsigned int flags) { @@ -453,15 +451,8 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, return ERR_PTR(ret); /* VT-d may overfetch before/after the vma, so pad with scratch */ - if (intel_scanout_needs_vtd_wa(i915)) { - unsigned int guard = VTD_GUARD; - - if (i915_gem_object_is_tiled(obj)) - guard = max(guard, - i915_gem_object_get_tile_row_size(obj)); - - flags |= PIN_OFFSET_GUARD | guard; - } + if (guard) + flags |= PIN_OFFSET_GUARD | (guard * I915_GTT_PAGE_SIZE); /* * As the user may map the buffer once pinned in the display plane diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index f151640c1d13..7796c4119ef5 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -303,7 +303,7 @@ struct i915_execbuffer { struct intel_gt_buffer_pool_node *batch_pool; /** pool node for batch buffer */ /** - * Indicate either the size of the hastable used to resolve + * Indicate either the size of the hashtable used to resolve * relocation handles, or if negative that we are using a direct * index into the execobj[]. */ @@ -915,7 +915,7 @@ static struct i915_vma *eb_lookup_vma(struct i915_execbuffer *eb, u32 handle) */ if (i915_gem_context_uses_protected_content(eb->gem_context) && i915_gem_object_is_protected(obj)) { - err = intel_pxp_key_check(eb->i915->pxp, intel_bo_to_drm_bo(obj), true); + err = intel_pxp_key_check(intel_bo_to_drm_bo(obj), true); if (err) { i915_gem_object_put(obj); return ERR_PTR(err); @@ -2543,7 +2543,7 @@ static int eb_pin_timeline(struct i915_execbuffer *eb, struct intel_context *ce, /* * Error path, cannot use intel_context_timeline_lock as - * that is user interruptable and this clean up step + * that is user interruptible and this clean up step * must be done. */ mutex_lock(&ce->timeline->mutex); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index 21274aa9bddd..c3dabb857960 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -164,6 +164,9 @@ static unsigned int tile_row_pages(const struct drm_i915_gem_object *obj) * 4 - Support multiple fault handlers per object depending on object's * backing storage (a.k.a. MMAP_OFFSET). * + * 5 - Support multiple partial mmaps(mmap part of BO + unmap a offset, multiple + * times with different size and offset). + * * Restrictions: * * * snoopable objects cannot be accessed via the GTT. It can cause machine @@ -191,7 +194,7 @@ static unsigned int tile_row_pages(const struct drm_i915_gem_object *obj) */ int i915_gem_mmap_gtt_version(void) { - return 4; + return 5; } static inline struct i915_gtt_view diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c index 58e6c680fe0d..356530b599ce 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c @@ -873,6 +873,30 @@ bool i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj) return lmem_placement; } +static int i915_gem_vmap_object(struct drm_gem_object *gem_obj, + struct iosys_map *map) +{ + struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); + void *vaddr; + + vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB); + if (IS_ERR(vaddr)) + return PTR_ERR(vaddr); + + iosys_map_set_vaddr(map, vaddr); + + return 0; +} + +static void i915_gem_vunmap_object(struct drm_gem_object *gem_obj, + struct iosys_map *map) +{ + struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); + + i915_gem_object_flush_map(obj); + i915_gem_object_unpin_map(obj); +} + void i915_gem_init__objects(struct drm_i915_private *i915) { INIT_WORK(&i915->mm.free_work, __i915_gem_free_work); @@ -896,6 +920,8 @@ static const struct drm_gem_object_funcs i915_gem_object_funcs = { .free = i915_gem_free_object, .close = i915_gem_close_object, .export = i915_gem_prime_export, + .vmap = i915_gem_vmap_object, + .vunmap = i915_gem_vunmap_object, }; /** diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index bb713e096db2..a5f34542135c 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -776,7 +776,7 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); struct i915_vma * __must_check i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, struct i915_gem_ww_ctx *ww, - u32 alignment, + u32 alignment, unsigned int guard, const struct i915_gtt_view *view, unsigned int flags); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c b/drivers/gpu/drm/i915/gem/i915_gem_region.c index b09b74a2448b..636768d0f57e 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_region.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c @@ -82,7 +82,7 @@ __i915_gem_object_create_region(struct intel_memory_region *mem, /* * Anything smaller than the min_page_size can't be freely inserted into - * the GTT, due to alignemnt restrictions. For such special objects, + * the GTT, due to alignment restrictions. For such special objects, * make sure we force memcpy based suspend-resume. In the future we can * revisit this, either by allowing special mis-aligned objects in the * migration path, or by mapping all of LMEM upfront using cheap 1G diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c index fe69f2c8527d..ae3343c81a64 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c @@ -209,8 +209,6 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj) struct address_space *mapping = obj->base.filp->f_mapping; unsigned int max_segment = i915_sg_segment_size(i915->drm.dev); struct sg_table *st; - struct sgt_iter sgt_iter; - struct page *page; int ret; /* @@ -239,9 +237,7 @@ rebuild_st: * for PAGE_SIZE chunks instead may be helpful. */ if (max_segment > PAGE_SIZE) { - for_each_sgt_page(page, sgt_iter, st) - put_page(page); - sg_free_table(st); + shmem_sg_free_table(st, mapping, false, false); kfree(st); max_segment = PAGE_SIZE; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c index 9117e9422844..aec41f0f098f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shrinker.c @@ -25,7 +25,7 @@ static bool swap_available(void) static bool can_release_pages(struct drm_i915_gem_object *obj) { - /* Consider only shrinkable ojects. */ + /* Consider only shrinkable objects. */ if (!i915_gem_object_is_shrinkable(obj)) return false; @@ -261,7 +261,7 @@ skip: * i915_gem_shrink_all - Shrink buffer object caches completely * @i915: i915 device * - * This is a simple wraper around i915_gem_shrink() to aggressively shrink all + * This is a simple wrapper around i915_gem_shrink() to aggressively shrink all * caches completely. It also first waits for and retires all outstanding * requests to also be able to release backing storage for active objects. * diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c index d9eb84c1d2f1..5ac23ff3feff 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c @@ -39,7 +39,7 @@ * Since neither of this applies for new tiling layouts on modern platforms like * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled. * Anything else can be handled in userspace entirely without the kernel's - * invovlement. + * involvement. */ /** diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c index 10d8673641f7..1f4814968868 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c @@ -994,7 +994,7 @@ void i915_ttm_adjust_lru(struct drm_i915_gem_object *obj) * If we need to place an LMEM resource which doesn't need CPU * access then we should try not to victimize mappable objects * first, since we likely end up stealing more of the mappable - * portion. And likewise when we try to find space for a mappble + * portion. And likewise when we try to find space for a mappable * object, we know not to ever victimize objects that don't * occupy any mappable pages. */ diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c index 041dab543b78..2f6b33edb9c9 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c @@ -603,7 +603,7 @@ int i915_ttm_move(struct ttm_buffer_object *bo, bool evict, * sequence, where at the end we can do the move for real. * * The special case here is when the dst_mem is TTM_PL_SYSTEM, - * which doens't require any kind of move, so it should be safe + * which doesn't require any kind of move, so it should be safe * to skip all the below and call ttm_bo_move_null() here, where * the caller in __i915_ttm_get_pages() will take care of the * rest, since we should have a valid ttm_tt. diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c index 84d41e6ccf05..bd08605a1611 100644 --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c @@ -1781,7 +1781,7 @@ static int igt_tmpfs_fallback(void *arg) /* * Make sure that we don't burst into a ball of flames upon falling back - * to tmpfs, which we rely on if on the off-chance we encouter a failure + * to tmpfs, which we rely on if on the off-chance we encounter a failure * when setting up gemfs. */ diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c index 99a9ade73956..804f74084bd4 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c @@ -1342,7 +1342,7 @@ static int igt_mmap_migrate(void *arg) } /* - * Allocate in the mappable portion, should be no suprises here. + * Allocate in the mappable portion, should be no surprises here. */ err = __igt_mmap_migrate(mixed, ARRAY_SIZE(mixed), mr, 0); if (err) diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.c b/drivers/gpu/drm/i915/gem/selftests/mock_context.c index 2b0327cc47c2..fd8babb513e5 100644 --- a/drivers/gpu/drm/i915/gem/selftests/mock_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.c @@ -108,44 +108,6 @@ err_ctx: } struct i915_gem_context * -live_context_for_engine(struct intel_engine_cs *engine, struct file *file) -{ - struct i915_gem_engines *engines; - struct i915_gem_context *ctx; - struct intel_sseu null_sseu = {}; - struct intel_context *ce; - - engines = alloc_engines(1); - if (!engines) - return ERR_PTR(-ENOMEM); - - ctx = live_context(engine->i915, file); - if (IS_ERR(ctx)) { - __free_engines(engines, 0); - return ctx; - } - - ce = intel_context_create(engine); - if (IS_ERR(ce)) { - __free_engines(engines, 0); - return ERR_CAST(ce); - } - - intel_context_set_gem(ce, ctx, null_sseu); - engines->engines[0] = ce; - engines->num_engines = 1; - - mutex_lock(&ctx->engines_mutex); - i915_gem_context_set_user_engines(ctx); - engines = rcu_replace_pointer(ctx->engines, engines, 1); - mutex_unlock(&ctx->engines_mutex); - - engines_idle_release(ctx, engines); - - return ctx; -} - -struct i915_gem_context * kernel_context(struct drm_i915_private *i915, struct i915_address_space *vm) { diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.h b/drivers/gpu/drm/i915/gem/selftests/mock_context.h index 7a02fd9b5866..bc8fb37d2d24 100644 --- a/drivers/gpu/drm/i915/gem/selftests/mock_context.h +++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.h @@ -23,9 +23,6 @@ void mock_context_close(struct i915_gem_context *ctx); struct i915_gem_context * live_context(struct drm_i915_private *i915, struct file *file); -struct i915_gem_context * -live_context_for_engine(struct intel_engine_cs *engine, struct file *file); - struct i915_gem_context *kernel_context(struct drm_i915_private *i915, struct i915_address_space *vm); void kernel_context_close(struct i915_gem_context *ctx); diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c b/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c index 075657018739..5cd58e0f0dcf 100644 --- a/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.c @@ -103,8 +103,7 @@ static struct dma_buf *mock_dmabuf(int npages) struct dma_buf *dmabuf; int i; - mock = kmalloc(sizeof(*mock) + npages * sizeof(struct page *), - GFP_KERNEL); + mock = kmalloc(struct_size(mock, pages, npages), GFP_KERNEL); if (!mock) return ERR_PTR(-ENOMEM); diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c index 4904d0f4162c..8116fd5987e2 100644 --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c @@ -179,7 +179,7 @@ u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs) return __gen2_emit_breadcrumb(rq, cs, 8, 8); } -/* Just userspace ABI convention to limit the wa batch bo to a resonable size */ +/* Just userspace ABI convention to limit the wa batch bo to a reasonable size */ #define I830_BATCH_LIMIT SZ_256K #define I830_TLB_ENTRIES (2) #define I830_WA_SIZE max(I830_TLB_ENTRIES * SZ_4K, I830_BATCH_LIMIT) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 4d30a86016f2..b721bbd23356 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -308,7 +308,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class) /* * There is a discrepancy here between the size reported * by the register and the size of the context layout - * in the docs. Both are described as authorative! + * in the docs. Both are described as authoritative! * * The discrepancy is on the order of a few cachelines, * but the total is under one page (4k), which is our @@ -677,7 +677,7 @@ void intel_engines_release(struct intel_gt *gt) * in case we aborted before completely initialising the engines. */ GEM_BUG_ON(intel_gt_pm_is_awake(gt)); - if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) + if (!intel_gt_gpu_reset_clobbers_display(gt)) intel_gt_reset_all_engines(gt); /* Decouple the backend; but keep the layout for late GPU resets */ @@ -769,9 +769,8 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt) if (MEDIA_VER_FULL(i915) < IP_VER(12, 55)) media_fuse = ~media_fuse; - vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK; - vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >> - GEN11_GT_VEBOX_DISABLE_SHIFT; + vdbox_mask = REG_FIELD_GET(GEN11_GT_VDBOX_DISABLE_MASK, media_fuse); + vebox_mask = REG_FIELD_GET(GEN11_GT_VEBOX_DISABLE_MASK, media_fuse); if (MEDIA_VER_FULL(i915) >= IP_VER(12, 55)) { fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1); @@ -845,7 +844,7 @@ static void engine_mask_apply_compute_fuses(struct intel_gt *gt) * Note that we have a catch-22 situation where we need to be able to access * the blitter forcewake domain to read the engine fuses, but at the same time * we need to know which engines are available on the system to know which - * forcewake domains are present. We solve this by intializing the forcewake + * forcewake domains are present. We solve this by initializing the forcewake * domains based on the full engine mask in the platform capabilities before * calling this function and pruning the domains for fused-off engines * afterwards. @@ -1411,7 +1410,7 @@ create_ggtt_bind_context(struct intel_engine_cs *engine) /* * MI_UPDATE_GTT can insert up to 511 PTE entries and there could be multiple - * bind requets at a time so get a bigger ring. + * bind requests at a time so get a bigger ring. */ return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_512K, I915_GEM_HWS_GGTT_BIND_ADDR, @@ -1533,7 +1532,7 @@ int intel_engines_init(struct intel_gt *gt) /** * intel_engine_cleanup_common - cleans up the engine state created by - * the common initiailizers. + * the common initializers. * @engine: Engine to cleanup. * * This cleans up everything created by the common helpers. diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index fe1f85e5dda3..155b6255a63e 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -237,7 +237,7 @@ struct intel_engine_execlists { */ struct i915_request * const *active; /** - * @inflight: the set of contexts submitted and acknowleged by HW + * @inflight: the set of contexts submitted and acknowledged by HW * * The set of inflight contexts is managed by reading CS events * from the HW. On a context-switch event (not preemption), we @@ -260,7 +260,7 @@ struct intel_engine_execlists { unsigned int port_mask; /** - * @virtual: Queue of requets on a virtual engine, sorted by priority. + * @virtual: Queue of requests on a virtual engine, sorted by priority. * Each RB entry is a struct i915_priolist containing a list of requests * of the same priority. */ diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 4a80ffa1b962..03baa7fa0a27 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2502,7 +2502,7 @@ static void execlists_irq_handler(struct intel_engine_cs *engine, u16 iir) ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI)); ENGINE_TRACE(engine, "semaphore yield: %08x\n", engine->execlists.yield); - if (del_timer(&engine->execlists.timer)) + if (timer_delete(&engine->execlists.timer)) tasklet = true; } @@ -3370,8 +3370,8 @@ static void execlists_set_default_submission(struct intel_engine_cs *engine) static void execlists_shutdown(struct intel_engine_cs *engine) { /* Synchronise with residual timers and any softirq they raise */ - del_timer_sync(&engine->execlists.timer); - del_timer_sync(&engine->execlists.preempt); + timer_delete_sync(&engine->execlists.timer); + timer_delete_sync(&engine->execlists.preempt); tasklet_kill(&engine->sched_engine->tasklet); } diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index 0ffba50981e3..0c723e7c71a2 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -328,6 +328,7 @@ static bool fence_is_active(const struct i915_fence_reg *fence) static struct i915_fence_reg *fence_find(struct i915_ggtt *ggtt) { + struct intel_display *display = &ggtt->vm.i915->display; struct i915_fence_reg *active = NULL; struct i915_fence_reg *fence, *fn; @@ -353,7 +354,7 @@ static struct i915_fence_reg *fence_find(struct i915_ggtt *ggtt) } /* Wait for completion of pending flips which consume fences */ - if (intel_has_pending_fb_unpin(ggtt->vm.i915)) + if (intel_has_pending_fb_unpin(display)) return ERR_PTR(-EAGAIN); return ERR_PTR(-ENOBUFS); @@ -749,7 +750,7 @@ static void swizzle_page(struct page *page) char *vaddr; int i; - vaddr = kmap(page); + vaddr = kmap_local_page(page); for (i = 0; i < PAGE_SIZE; i += 128) { memcpy(temp, &vaddr[i], 64); @@ -757,7 +758,7 @@ static void swizzle_page(struct page *page) memcpy(&vaddr[i + 64], temp, 64); } - kunmap(page); + kunmap_local(vaddr); } /** diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index c4a351ebf395..3d3b1ba76e2b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -302,25 +302,48 @@ static void gen6_check_faults(struct intel_gt *gt) { struct intel_engine_cs *engine; enum intel_engine_id id; - unsigned long fault; for_each_engine(engine, gt, id) { + u32 fault; + fault = GEN6_RING_FAULT_REG_READ(engine); + if (fault & RING_FAULT_VALID) { gt_dbg(gt, "Unexpected fault\n" - "\tAddr: 0x%08lx\n" + "\tAddr: 0x%08x\n" "\tAddress space: %s\n" - "\tSource ID: %ld\n" - "\tType: %ld\n", - fault & PAGE_MASK, + "\tSource ID: %d\n" + "\tType: %d\n", + fault & RING_FAULT_VADDR_MASK, fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", - RING_FAULT_SRCID(fault), - RING_FAULT_FAULT_TYPE(fault)); + REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault), + REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault)); } } } +static void gen8_report_fault(struct intel_gt *gt, u32 fault, + u32 fault_data0, u32 fault_data1) +{ + u64 fault_addr; + + fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | + ((u64)fault_data0 << 12); + + gt_dbg(gt, "Unexpected fault\n" + "\tAddr: 0x%08x_%08x\n" + "\tAddress space: %s\n" + "\tEngine ID: %d\n" + "\tSource ID: %d\n" + "\tType: %d\n", + upper_32_bits(fault_addr), lower_32_bits(fault_addr), + fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT", + REG_FIELD_GET(RING_FAULT_ENGINE_ID_MASK, fault), + REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault), + REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault)); +} + static void xehp_check_faults(struct intel_gt *gt) { u32 fault; @@ -333,28 +356,10 @@ static void xehp_check_faults(struct intel_gt *gt) * toward the primary instance. */ fault = intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG); - if (fault & RING_FAULT_VALID) { - u32 fault_data0, fault_data1; - u64 fault_addr; - - fault_data0 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0); - fault_data1 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1); - - fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | - ((u64)fault_data0 << 12); - - gt_dbg(gt, "Unexpected fault\n" - "\tAddr: 0x%08x_%08x\n" - "\tAddress space: %s\n" - "\tEngine ID: %d\n" - "\tSource ID: %d\n" - "\tType: %d\n", - upper_32_bits(fault_addr), lower_32_bits(fault_addr), - fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT", - GEN8_RING_FAULT_ENGINE_ID(fault), - RING_FAULT_SRCID(fault), - RING_FAULT_FAULT_TYPE(fault)); - } + if (fault & RING_FAULT_VALID) + gen8_report_fault(gt, fault, + intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0), + intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1)); } static void gen8_check_faults(struct intel_gt *gt) @@ -374,28 +379,10 @@ static void gen8_check_faults(struct intel_gt *gt) } fault = intel_uncore_read(uncore, fault_reg); - if (fault & RING_FAULT_VALID) { - u32 fault_data0, fault_data1; - u64 fault_addr; - - fault_data0 = intel_uncore_read(uncore, fault_data0_reg); - fault_data1 = intel_uncore_read(uncore, fault_data1_reg); - - fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) | - ((u64)fault_data0 << 12); - - gt_dbg(gt, "Unexpected fault\n" - "\tAddr: 0x%08x_%08x\n" - "\tAddress space: %s\n" - "\tEngine ID: %d\n" - "\tSource ID: %d\n" - "\tType: %d\n", - upper_32_bits(fault_addr), lower_32_bits(fault_addr), - fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT", - GEN8_RING_FAULT_ENGINE_ID(fault), - RING_FAULT_SRCID(fault), - RING_FAULT_FAULT_TYPE(fault)); - } + if (fault & RING_FAULT_VALID) + gen8_report_fault(gt, fault, + intel_uncore_read(uncore, fault_data0_reg), + intel_uncore_read(uncore, fault_data1_reg)); } void intel_gt_check_and_clear_faults(struct intel_gt *gt) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c index 6e63505fe478..6c499692d61e 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c @@ -35,9 +35,7 @@ static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore, u32 f24_mhz = 24000000; u32 f25_mhz = 25000000; u32 f38_4_mhz = 38400000; - u32 crystal_clock = - (rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >> - GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT; + u32 crystal_clock = rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK; switch (crystal_clock) { case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ: @@ -80,8 +78,7 @@ static u32 gen11_read_clock_frequency(struct intel_uncore *uncore) * register increments from this frequency (it might * increment only every few clock cycle). */ - freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT); + freq >>= 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0); } return freq; @@ -102,8 +99,7 @@ static u32 gen9_read_clock_frequency(struct intel_uncore *uncore) * register increments from this frequency (it might * increment only every few clock cycle). */ - freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >> - CTC_SHIFT_PARAMETER_SHIFT); + freq >>= 3 - REG_FIELD_GET(CTC_SHIFT_PARAMETER_MASK, ctc_reg); } return freq; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c index 1240d44eeb85..75e802e10be2 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c @@ -480,7 +480,7 @@ void gen8_gt_irq_postinstall(struct intel_gt *gt) gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(1), ~gt_interrupts[1], gt_interrupts[1]); /* * RPS interrupts will get enabled/disabled on demand when RPS itself - * is enabled/disabled. Same wil be the case for GuC interrupts. + * is enabled/disabled. Same will be the case for GuC interrupts. */ gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(2), gt->pm_imr, gt->pm_ier); gen2_irq_init(uncore, GEN8_GT_IRQ_REGS(3), ~gt_interrupts[3], gt_interrupts[3]); diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c index b8912bd6c08e..a60822e2b5d4 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c @@ -121,9 +121,8 @@ void intel_gt_mcr_init(struct intel_gt *gt) gt->info.mslice_mask = intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask, GEN_DSS_PER_MSLICE); - gt->info.mslice_mask |= - (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & - GEN12_MEML3_EN_MASK); + gt->info.mslice_mask |= REG_FIELD_GET(GEN12_MEML3_EN_MASK, + intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3)); if (!gt->info.mslice_mask) /* should be impossible! */ gt_warn(gt, "mslice mask all zero!\n"); @@ -239,7 +238,7 @@ static u32 rw_with_mcr_steering_fw(struct intel_gt *gt, * to remain in multicast mode for reads. There's no real * downside to this, so we'll just go ahead and do so on all * platforms; we'll only clear the multicast bit from the mask - * when exlicitly doing a write operation. + * when explicitly doing a write operation. */ if (rw_flag == FW_REG_WRITE) mcr_mask |= GEN11_MCR_MULTICAST; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index c08fdb65cc69..3182f19b9837 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -70,6 +70,7 @@ static int __gt_unpark(struct intel_wakeref *wf) { struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref); struct drm_i915_private *i915 = gt->i915; + struct intel_display *display = &i915->display; GT_TRACE(gt, "\n"); @@ -84,7 +85,7 @@ static int __gt_unpark(struct intel_wakeref *wf) * Work around it by grabbing a GT IRQ power domain whilst there is any * GT activity, preventing any DC state transitions. */ - gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ); + gt->awake = intel_display_power_get(display, POWER_DOMAIN_GT_IRQ); GEM_BUG_ON(!gt->awake); intel_rc6_unpark(>->rc6); @@ -103,6 +104,7 @@ static int __gt_park(struct intel_wakeref *wf) struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref); intel_wakeref_t wakeref = fetch_and_zero(>->awake); struct drm_i915_private *i915 = gt->i915; + struct intel_display *display = &i915->display; GT_TRACE(gt, "\n"); @@ -120,7 +122,7 @@ static int __gt_park(struct intel_wakeref *wf) /* Defer dropping the display power well for 100ms, it's slow! */ GEM_BUG_ON(!wakeref); - intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref); + intel_display_power_put_async(display, POWER_DOMAIN_GT_IRQ, wakeref); return 0; } @@ -156,7 +158,7 @@ void intel_gt_pm_init(struct intel_gt *gt) static bool reset_engines(struct intel_gt *gt) { - if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) + if (intel_gt_gpu_reset_clobbers_display(gt)) return false; return intel_gt_reset_all_engines(gt) == 0; diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 6dba65e54cdb..7421ed18d8d1 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -30,18 +30,15 @@ /* RPM unit config (Gen8+) */ #define RPM_CONFIG0 _MMIO(0xd00) -#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 -#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) -#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0 -#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1 -#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 -#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) -#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 -#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 -#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 -#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 -#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1 -#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT) +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3) +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0) +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1) +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 2) +#define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ REG_FIELD_PREP(GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 3) +#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_BIT(3) +#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 0) +#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ REG_FIELD_PREP(GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK, 1) +#define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) #define RPM_CONFIG1 _MMIO(0xd04) #define GEN10_GT_NOA_ENABLE (1 << 9) @@ -326,6 +323,12 @@ _RING_FAULT_REG_VCS, \ _RING_FAULT_REG_VECS, \ _RING_FAULT_REG_BCS)) +#define RING_FAULT_VADDR_MASK REG_GENMASK(31, 12) /* pre-bdw */ +#define RING_FAULT_ENGINE_ID_MASK REG_GENMASK(16, 12) /* bdw+ */ +#define RING_FAULT_GTTSEL_MASK REG_BIT(11) /* pre-bdw */ +#define RING_FAULT_SRCID_MASK REG_GENMASK(10, 3) +#define RING_FAULT_FAULT_TYPE_MASK REG_GENMASK(2, 1) /* ivb+ */ +#define RING_FAULT_VALID REG_BIT(0) #define ERROR_GEN6 _MMIO(0x40a0) @@ -385,6 +388,8 @@ #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) +#define FAULT_GTT_SEL REG_BIT(4) +#define FAULT_VA_HIGH_BITS REG_GENMASK(3, 0) #define GEN11_GACB_PERF_CTRL _MMIO(0x4b80) #define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0) @@ -409,6 +414,9 @@ #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) +#define GEN8_WM_CHICKEN2 MCR_REG(0x5584) +#define WAIT_ON_DEPTH_STALL_DONE_DISABLE REG_BIT(5) + #define GEN9_WM_CHICKEN3 _MMIO(0x5588) #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9) @@ -504,11 +512,12 @@ #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) +#define GEN9_PGCTL_SS_ACK(subslice) REG_BIT(2 + (subslice) * 2) +#define GEN9_PGCTL_SLICE_ACK REG_BIT(0) + #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ ((slice) % 3) * 0x4) -#define GEN9_PGCTL_SLICE_ACK (1 << 0) -#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) -#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) +#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? REG_GENMASK(6, 0) : REG_GENMASK(4, 0)) #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ @@ -516,14 +525,14 @@ #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ ((slice) % 3) * 0x8) -#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) -#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) -#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) -#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) -#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) -#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) -#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) -#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) +#define GEN9_PGCTL_SSB_EU311_ACK REG_BIT(14) +#define GEN9_PGCTL_SSB_EU210_ACK REG_BIT(12) +#define GEN9_PGCTL_SSB_EU19_ACK REG_BIT(10) +#define GEN9_PGCTL_SSB_EU08_ACK REG_BIT(8) +#define GEN9_PGCTL_SSA_EU311_ACK REG_BIT(6) +#define GEN9_PGCTL_SSA_EU210_ACK REG_BIT(4) +#define GEN9_PGCTL_SSA_EU19_ACK REG_BIT(2) +#define GEN9_PGCTL_SSA_EU08_ACK REG_BIT(0) #define VF_PREEMPTION _MMIO(0x83a4) #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) @@ -580,7 +589,7 @@ #define GEN10_L3BANK_MASK 0x0F /* on Xe_HP the same fuses indicates mslices instead of L3 banks */ #define GEN12_MAX_MSLICES 4 -#define GEN12_MEML3_EN_MASK 0x0F +#define GEN12_MEML3_EN_MASK REG_GENMASK(3, 0) #define HSW_PAVP_FUSE1 _MMIO(0x911c) #define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24) @@ -590,37 +599,30 @@ #define HSW_F1_EU_DIS_6EUS 2 #define GEN8_FUSE2 _MMIO(0x9120) -#define GEN8_F2_SS_DIS_SHIFT 21 -#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) -#define GEN8_F2_S_ENA_SHIFT 25 -#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) -#define GEN9_F2_SS_DIS_SHIFT 20 -#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) -#define GEN10_F2_S_ENA_SHIFT 22 -#define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT) -#define GEN10_F2_SS_DIS_SHIFT 18 -#define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT) +#define GEN10_F2_S_ENA_MASK REG_GENMASK(27, 22) +#define GEN10_F2_SS_DIS_MASK REG_GENMASK(21, 18) +#define GEN8_F2_S_ENA_MASK REG_GENMASK(27, 25) +#define GEN9_F2_SS_DIS_MASK REG_GENMASK(23, 20) +#define GEN8_F2_SS_DIS_MASK REG_GENMASK(23, 21) #define GEN8_EU_DISABLE0 _MMIO(0x9134) #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4) #define GEN11_EU_DISABLE _MMIO(0x9134) -#define GEN8_EU_DIS0_S0_MASK 0xffffff -#define GEN8_EU_DIS0_S1_SHIFT 24 -#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) -#define GEN11_EU_DIS_MASK 0xFF +#define GEN8_EU_DIS0_S1_MASK REG_GENMASK(31, 24) +#define GEN8_EU_DIS0_S0_MASK REG_GENMASK(23, 0) +#define GEN11_EU_DIS_MASK REG_GENMASK(7, 0) #define XEHP_EU_ENABLE _MMIO(0x9134) -#define XEHP_EU_ENA_MASK 0xFF +#define XEHP_EU_ENA_MASK REG_GENMASK(7, 0) #define GEN8_EU_DISABLE1 _MMIO(0x9138) -#define GEN8_EU_DIS1_S1_MASK 0xffff -#define GEN8_EU_DIS1_S2_SHIFT 16 -#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) +#define GEN8_EU_DIS1_S2_MASK REG_GENMASK(31, 16) +#define GEN8_EU_DIS1_S1_MASK REG_GENMASK(15, 0) #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138) -#define GEN11_GT_S_ENA_MASK 0xFF +#define GEN11_GT_S_ENA_MASK REG_GENMASK(7, 0) #define GEN8_EU_DISABLE2 _MMIO(0x913c) -#define GEN8_EU_DIS2_S2_MASK 0xff +#define GEN8_EU_DIS2_S2_MASK REG_GENMASK(7, 0) #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913c) #define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913c) @@ -628,9 +630,8 @@ #define GEN10_EU_DISABLE3 _MMIO(0x9140) #define GEN10_EU_DIS_SS_MASK 0xff #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140) -#define GEN11_GT_VDBOX_DISABLE_MASK 0xff -#define GEN11_GT_VEBOX_DISABLE_SHIFT 16 -#define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT) +#define GEN11_GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16) +#define GEN11_GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0) #define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144) #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148) @@ -878,11 +879,10 @@ /* GPM unit config (Gen9+) */ #define CTC_MODE _MMIO(0xa26c) -#define CTC_SOURCE_PARAMETER_MASK 1 -#define CTC_SOURCE_CRYSTAL_CLOCK 0 -#define CTC_SOURCE_DIVIDE_LOGIC 1 -#define CTC_SHIFT_PARAMETER_SHIFT 1 -#define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT) +#define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) +#define CTC_SOURCE_PARAMETER_MASK REG_BIT(0) +#define CTC_SOURCE_CRYSTAL_CLOCK REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 0) +#define CTC_SOURCE_DIVIDE_LOGIC REG_FIELD_PREP(CTC_SOURCE_PARAMETER_MASK, 1) /* GPM MSG_IDLE */ #define MSG_IDLE_CS _MMIO(0x8000) @@ -926,12 +926,12 @@ #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) -#define CHV_SS_PG_ENABLE (1 << 1) -#define CHV_EU08_PG_ENABLE (1 << 9) -#define CHV_EU19_PG_ENABLE (1 << 17) -#define CHV_EU210_PG_ENABLE (1 << 25) +#define CHV_EU210_PG_ENABLE REG_BIT(25) +#define CHV_EU19_PG_ENABLE REG_BIT(17) +#define CHV_EU08_PG_ENABLE REG_BIT(9) +#define CHV_SS_PG_ENABLE REG_BIT(1) #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) -#define CHV_EU311_PG_ENABLE (1 << 1) +#define CHV_EU311_PG_ENABLE REG_BIT(1) #define GEN7_SARCHKMD _MMIO(0xb000) #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31) @@ -1035,17 +1035,12 @@ #define XEHP_FAULT_TLB_DATA0 MCR_REG(0xceb8) #define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc) #define XEHP_FAULT_TLB_DATA1 MCR_REG(0xcebc) -#define FAULT_VA_HIGH_BITS (0xf << 0) -#define FAULT_GTT_SEL (1 << 4) +/* see GEN8_FAULT_TLB_DATA0/1 */ #define GEN12_RING_FAULT_REG _MMIO(0xcec4) #define XEHP_RING_FAULT_REG MCR_REG(0xcec4) #define XELPMP_RING_FAULT_REG _MMIO(0xcec4) -#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) -#define RING_FAULT_GTTSEL_MASK (1 << 11) -#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) -#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) -#define RING_FAULT_VALID (1 << 0) +/* see GEN8_RING_FAULT_REG */ #define GEN12_GFX_TLB_INV_CR _MMIO(0xced8) #define XEHP_GFX_TLB_INV_CR MCR_REG(0xced8) @@ -1434,16 +1429,12 @@ #define XEHP_CCS_MODE_CSLICE(cslice, ccs) (ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH)) #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168) -#define CHV_FGT_DISABLE_SS0 (1 << 10) -#define CHV_FGT_DISABLE_SS1 (1 << 11) -#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 -#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) -#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 -#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) -#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 -#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) -#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 -#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R1_MASK REG_GENMASK(31, 28) +#define CHV_FGT_EU_DIS_SS1_R0_MASK REG_GENMASK(27, 24) +#define CHV_FGT_EU_DIS_SS0_R1_MASK REG_GENMASK(23, 20) +#define CHV_FGT_EU_DIS_SS0_R0_MASK REG_GENMASK(19, 16) +#define CHV_FGT_DISABLE_SS1 REG_BIT(11) +#define CHV_FGT_DISABLE_SS0 REG_BIT(10) #define BCS_SWCTRL _MMIO(0x22200) #define BCS_SRC_Y REG_BIT(0) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c index d7784650e4d9..1154cd2b7c34 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c @@ -464,6 +464,45 @@ static ssize_t slpc_ignore_eff_freq_store(struct kobject *kobj, return err ?: count; } +static ssize_t slpc_power_profile_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buff) +{ + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name); + struct intel_guc_slpc *slpc = >->uc.guc.slpc; + + switch (slpc->power_profile) { + case SLPC_POWER_PROFILES_BASE: + return sysfs_emit(buff, "[%s] %s\n", "base", "power_saving"); + case SLPC_POWER_PROFILES_POWER_SAVING: + return sysfs_emit(buff, "%s [%s]\n", "base", "power_saving"); + } + + return sysfs_emit(buff, "%u\n", slpc->power_profile); +} + +static ssize_t slpc_power_profile_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buff, size_t count) +{ + struct intel_gt *gt = intel_gt_sysfs_get_drvdata(kobj, attr->attr.name); + struct intel_guc_slpc *slpc = >->uc.guc.slpc; + char power_saving[] = "power_saving"; + char base[] = "base"; + int err; + u32 val; + + if (!strncmp(buff, power_saving, sizeof(power_saving) - 1)) + val = SLPC_POWER_PROFILES_POWER_SAVING; + else if (!strncmp(buff, base, sizeof(base) - 1)) + val = SLPC_POWER_PROFILES_BASE; + else + return -EINVAL; + + err = intel_guc_slpc_set_power_profile(slpc, val); + return err ?: count; +} + struct intel_gt_bool_throttle_attr { struct attribute attr; ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr, @@ -668,6 +707,7 @@ INTEL_GT_ATTR_RO(media_RP0_freq_mhz); INTEL_GT_ATTR_RO(media_RPn_freq_mhz); INTEL_GT_ATTR_RW(slpc_ignore_eff_freq); +INTEL_GT_ATTR_RW(slpc_power_profile); static const struct attribute *media_perf_power_attrs[] = { &attr_media_freq_factor.attr, @@ -864,6 +904,13 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj) gt_warn(gt, "failed to create ignore_eff_freq sysfs (%pe)", ERR_PTR(ret)); } + if (intel_uc_uses_guc_slpc(>->uc)) { + ret = sysfs_create_file(kobj, &attr_slpc_power_profile.attr); + if (ret) + gt_warn(gt, "failed to create slpc_power_profile sysfs (%pe)", + ERR_PTR(ret)); + } + if (i915_mmio_reg_valid(intel_gt_perf_limit_reasons_reg(gt))) { ret = sysfs_create_files(kobj, throttle_reason_attrs); if (ret) diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c index 6f7af4077135..aff5aca591e6 100644 --- a/drivers/gpu/drm/i915/gt/intel_migrate.c +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c @@ -304,7 +304,7 @@ struct intel_context *intel_migrate_create_context(struct intel_migrate *m) struct intel_context *ce; /* - * We randomly distribute contexts across the engines upon constrction, + * We randomly distribute contexts across the engines upon construction, * as they all share the same pinned vm, and so in order to allow * multiple blits to run in parallel, we must construct each blit * to use a different range of the vm for its GTT. This has to be @@ -646,7 +646,7 @@ calculate_chunk_sz(struct drm_i915_private *i915, bool src_is_lmem, * When CHUNK_SZ is passed all the pages upto CHUNK_SZ * will be taken for the blt. in Flat-ccs supported * platform Smem obj will have more pages than required - * for main meory hence limit it to the required size + * for main memory hence limit it to the required size * for main memory */ return min_t(u64, bytes_to_cpy, CHUNK_SZ); diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index d791d63d49b4..cf41d325712e 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -675,7 +675,7 @@ void intel_mocs_init(struct intel_gt *gt) __init_mocs_table(gt->uncore, &table, global_mocs_offset()); /* - * Initialize the L3CC table as part of mocs initalization to make + * Initialize the L3CC table as part of mocs initialization to make * sure the LNCFCMOCSx registers are programmed for the subsequent * memory transactions including guc transactions */ diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 9378d5901c49..9ca42589da4d 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -117,21 +117,10 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) GEN6_RC_CTL_RC6_ENABLE | GEN6_RC_CTL_EI_MODE(1); - /* - * BSpec 52698 - Render powergating must be off. - * FIXME BSpec is outdated, disabling powergating for MTL is just - * temporary wa and should be removed after fixing real cause - * of forcewake timeouts. - */ - if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) - pg_enable = - GEN9_MEDIA_PG_ENABLE | - GEN11_MEDIA_SAMPLER_PG_ENABLE; - else - pg_enable = - GEN9_RENDER_PG_ENABLE | - GEN9_MEDIA_PG_ENABLE | - GEN11_MEDIA_SAMPLER_PG_ENABLE; + pg_enable = + GEN9_RENDER_PG_ENABLE | + GEN9_MEDIA_PG_ENABLE | + GEN11_MEDIA_SAMPLER_PG_ENABLE; if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) { for (i = 0; i < I915_MAX_VCS; i++) diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index aae5a081cb53..dbdcfe130ad4 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -986,7 +986,7 @@ static void __intel_gt_set_wedged(struct intel_gt *gt) awake = reset_prepare(gt); /* Even if the GPU reset fails, it should still stop the engines */ - if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) + if (!intel_gt_gpu_reset_clobbers_display(gt)) intel_gt_reset_all_engines(gt); for_each_engine(engine, gt, id) @@ -1098,7 +1098,7 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt) dma_fence_default_wait(fence, false, MAX_SCHEDULE_TIMEOUT); dma_fence_put(fence); - /* Restart iteration after droping lock */ + /* Restart iteration after dropping lock */ spin_lock(&timelines->lock); tl = list_entry(&timelines->active_list, typeof(*tl), link); } @@ -1106,14 +1106,13 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt) /* We must reset pending GPU events before restoring our submission */ ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */ - if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) + if (!intel_gt_gpu_reset_clobbers_display(gt)) ok = intel_gt_reset_all_engines(gt) == 0; if (!ok) { /* * Warn CI about the unrecoverable wedged condition. * Time for a reboot. */ - gt_err(gt, "Unrecoverable wedged condition\n"); add_taint_for_CI(gt->i915, TAINT_WARN); return false; } @@ -1178,6 +1177,13 @@ static int resume(struct intel_gt *gt) return 0; } +bool intel_gt_gpu_reset_clobbers_display(struct intel_gt *gt) +{ + struct drm_i915_private *i915 = gt->i915; + + return INTEL_INFO(i915)->gpu_reset_clobbers_display; +} + /** * intel_gt_reset - reset chip after a hang * @gt: #intel_gt to reset @@ -1234,7 +1240,7 @@ void intel_gt_reset(struct intel_gt *gt, goto error; } - if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) + if (intel_gt_gpu_reset_clobbers_display(gt)) intel_irq_suspend(gt->i915); if (do_reset(gt, stalled_mask)) { @@ -1242,7 +1248,7 @@ void intel_gt_reset(struct intel_gt *gt, goto taint; } - if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) + if (intel_gt_gpu_reset_clobbers_display(gt)) intel_irq_resume(gt->i915); intel_overlay_reset(display); @@ -1265,10 +1271,8 @@ void intel_gt_reset(struct intel_gt *gt, } ret = resume(gt); - if (ret) { - gt_err(gt, "Failed to resume (%d)\n", ret); + if (ret) goto taint; - } finish: reset_finish(gt, awake); @@ -1396,6 +1400,11 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg) return err; } +static void display_reset_modeset_stuck(void *gt) +{ + intel_gt_set_wedged(gt); +} + static void intel_gt_reset_global(struct intel_gt *gt, u32 engine_mask, const char *reason) @@ -1413,15 +1422,33 @@ static void intel_gt_reset_global(struct intel_gt *gt, /* Use a watchdog to ensure that our reset completes */ intel_wedge_on_timeout(&w, gt, 60 * HZ) { - intel_display_reset_prepare(gt->i915); + struct drm_i915_private *i915 = gt->i915; + struct intel_display *display = &i915->display; + bool need_display_reset; + bool reset_display; + + need_display_reset = intel_gt_gpu_reset_clobbers_display(gt) && + intel_has_gpu_reset(gt); + + reset_display = intel_display_reset_test(display) || + need_display_reset; + + if (reset_display) + reset_display = intel_display_reset_prepare(display, + display_reset_modeset_stuck, + gt); intel_gt_reset(gt, engine_mask, reason); - intel_display_reset_finish(gt->i915); + if (reset_display) + intel_display_reset_finish(display, !need_display_reset); } if (!test_bit(I915_WEDGED, >->reset.flags)) kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event); + else + drm_dev_wedged_event(>->i915->drm, + DRM_WEDGE_RECOVERY_REBIND | DRM_WEDGE_RECOVERY_BUS_RESET); } /** @@ -1482,7 +1509,7 @@ void intel_gt_handle_error(struct intel_gt *gt, intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) { local_bh_disable(); for_each_engine_masked(engine, gt, engine_mask, tmp) { - BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE); + BUILD_BUG_ON(I915_RESET_BACKOFF >= I915_RESET_ENGINE); if (test_and_set_bit(I915_RESET_ENGINE + engine->id, >->reset.flags)) continue; @@ -1611,7 +1638,6 @@ void intel_gt_set_wedged_on_init(struct intel_gt *gt) set_bit(I915_WEDGED_ON_INIT, >->reset.flags); /* Wedged on init is non-recoverable */ - gt_err(gt, "Non-recoverable wedged on init\n"); add_taint_for_CI(gt->i915, TAINT_WARN); } diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h index c00de353075c..724ea6d64f33 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.h +++ b/drivers/gpu/drm/i915/gt/intel_reset.h @@ -28,6 +28,8 @@ void intel_gt_handle_error(struct intel_gt *gt, const char *fmt, ...); #define I915_ERROR_CAPTURE BIT(0) +bool intel_gt_gpu_reset_clobbers_display(struct intel_gt *gt); + void intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask, const char *reason); diff --git a/drivers/gpu/drm/i915/gt/intel_reset_types.h b/drivers/gpu/drm/i915/gt/intel_reset_types.h index 80351f0a856c..4f5fd393af6f 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset_types.h +++ b/drivers/gpu/drm/i915/gt/intel_reset_types.h @@ -41,8 +41,7 @@ struct intel_reset { */ unsigned long flags; #define I915_RESET_BACKOFF 0 -#define I915_RESET_MODESET 1 -#define I915_RESET_ENGINE 2 +#define I915_RESET_ENGINE 1 #define I915_WEDGED_ON_INIT (BITS_PER_LONG - 3) #define I915_WEDGED_ON_FINI (BITS_PER_LONG - 2) #define I915_WEDGED (BITS_PER_LONG - 1) diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 458e29d89978..6e9977b2d180 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -242,7 +242,7 @@ static int xcs_resume(struct intel_engine_cs *engine) /* * In case of resets fails because engine resumes from * incorrect RING_HEAD and then GPU may be then fed - * to invalid instrcutions, which may lead to unrecoverable + * to invalid instructions, which may lead to unrecoverable * hang. So at first write doesn't succeed then try again. */ ENGINE_WRITE_FW(engine, RING_HEAD, ring->head); diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index fa304ea088e4..64e9317f58fb 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -161,7 +161,7 @@ static void rps_start_timer(struct intel_rps *rps) static void rps_stop_timer(struct intel_rps *rps) { - del_timer_sync(&rps->timer); + timer_delete_sync(&rps->timer); rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp); cancel_work_sync(&rps->work); } @@ -1025,6 +1025,10 @@ void intel_rps_boost(struct i915_request *rq) if (rps_uses_slpc(rps)) { slpc = rps_to_slpc(rps); + /* Waitboost should not be done with power saving profile */ + if (slpc->power_profile == SLPC_POWER_PROFILES_POWER_SAVING) + return; + if (slpc->min_freq_softlimit >= slpc->boost_freq) return; diff --git a/drivers/gpu/drm/i915/gt/intel_rps_types.h b/drivers/gpu/drm/i915/gt/intel_rps_types.h index 6507fa3f6d1e..5135b90a2a40 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps_types.h +++ b/drivers/gpu/drm/i915/gt/intel_rps_types.h @@ -40,7 +40,7 @@ enum { /** * struct intel_rps_freq_caps - rps freq capabilities * @rp0_freq: non-overclocked max frequency - * @rp1_freq: "less than" RP0 power/freqency + * @rp1_freq: "less than" RP0 power/frequency * @min_freq: aka RPn, minimum frequency * * Freq caps exposed by HW, values are in "hw units" and intel_gpu_freq() @@ -90,7 +90,7 @@ struct intel_rps { u8 boost_freq; /* Frequency to request when wait boosting */ u8 idle_freq; /* Frequency to request when we are idle */ u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ - u8 rp1_freq; /* "less than" RP0 power/freqency */ + u8 rp1_freq; /* "less than" RP0 power/frequency */ u8 rp0_freq; /* Non-overclocked max frequency. */ u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c b/drivers/gpu/drm/i915/gt/intel_sa_media.c index 8c1dbcbcbc4f..2945526d52d1 100644 --- a/drivers/gpu/drm/i915/gt/intel_sa_media.c +++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c @@ -27,7 +27,7 @@ int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr, /* * Standalone media shares the general MMIO space with the primary - * GT. We'll re-use the primary GT's mapping. + * GT. We'll reuse the primary GT's mapping. */ uncore->regs = intel_uncore_regs(&i915->uncore); if (drm_WARN_ON(&i915->drm, uncore->regs == NULL)) diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index c8fadf58d836..9501d323d0d3 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -236,7 +236,8 @@ static void xehp_sseu_info_init(struct intel_gt *gt) GEN12_GT_COMPUTE_DSS_ENABLE, XEHPC_GT_COMPUTE_DSS_ENABLE_EXT); - eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK; + eu_en_fuse = REG_FIELD_GET(XEHP_EU_ENA_MASK, + intel_uncore_read(uncore, XEHP_EU_ENABLE)); if (HAS_ONE_EU_PER_FUSE_BIT(gt->i915)) eu_en = eu_en_fuse; @@ -269,15 +270,15 @@ static void gen12_sseu_info_init(struct intel_gt *gt) * Although gen12 architecture supported multiple slices, TGL, RKL, * DG1, and ADL only had a single slice. */ - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & - GEN11_GT_S_ENA_MASK; + s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK, + intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE)); drm_WARN_ON(>->i915->drm, s_en != 0x1); g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE); /* one bit per pair of EUs */ - eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & - GEN11_EU_DIS_MASK); + eu_en_fuse = ~REG_FIELD_GET(GEN11_EU_DIS_MASK, + intel_uncore_read(uncore, GEN11_EU_DISABLE)); for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) if (eu_en_fuse & BIT(eu)) @@ -306,14 +307,14 @@ static void gen11_sseu_info_init(struct intel_gt *gt) * Although gen11 architecture supported multiple slices, ICL and * EHL/JSL only had a single slice in practice. */ - s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & - GEN11_GT_S_ENA_MASK; + s_en = REG_FIELD_GET(GEN11_GT_S_ENA_MASK, + intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE)); drm_WARN_ON(>->i915->drm, s_en != 0x1); ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE); - eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & - GEN11_EU_DIS_MASK); + eu_en = ~REG_FIELD_GET(GEN11_EU_DIS_MASK, + intel_uncore_read(uncore, GEN11_EU_DISABLE)); gen11_compute_sseu_info(sseu, ss_en, eu_en); @@ -335,10 +336,8 @@ static void cherryview_sseu_info_init(struct intel_gt *gt) if (!(fuse & CHV_FGT_DISABLE_SS0)) { u8 disabled_mask = - ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> - CHV_FGT_EU_DIS_SS0_R0_SHIFT) | - (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> - CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); + REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R0_MASK, fuse) | + REG_FIELD_GET(CHV_FGT_EU_DIS_SS0_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS0_R0_MASK); sseu->subslice_mask.hsw[0] |= BIT(0); sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF); @@ -346,10 +345,8 @@ static void cherryview_sseu_info_init(struct intel_gt *gt) if (!(fuse & CHV_FGT_DISABLE_SS1)) { u8 disabled_mask = - ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> - CHV_FGT_EU_DIS_SS1_R0_SHIFT) | - (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> - CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); + REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R0_MASK, fuse) | + REG_FIELD_GET(CHV_FGT_EU_DIS_SS1_R1_MASK, fuse) << hweight32(CHV_FGT_EU_DIS_SS1_R0_MASK); sseu->subslice_mask.hsw[0] |= BIT(1); sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF); @@ -385,7 +382,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt) int s, ss; fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); - sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; + sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2); /* BXT has a single slice and at most 3 subslices. */ intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3, @@ -396,8 +393,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt) * to each of the enabled slices. */ subslice_mask = (1 << sseu->max_subslices) - 1; - subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> - GEN9_F2_SS_DIS_SHIFT); + subslice_mask &= ~REG_FIELD_GET(GEN9_F2_SS_DIS_MASK, fuse2); /* * Iterate through enabled slices and subslices to @@ -490,7 +486,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt) u32 eu_disable0, eu_disable1, eu_disable2; fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); - sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; + sseu->slice_mask = REG_FIELD_GET(GEN8_F2_S_ENA_MASK, fuse2); intel_sseu_set_info(sseu, 3, 3, 8); /* @@ -498,18 +494,18 @@ static void bdw_sseu_info_init(struct intel_gt *gt) * to each of the enabled slices. */ subslice_mask = GENMASK(sseu->max_subslices - 1, 0); - subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> - GEN8_F2_SS_DIS_SHIFT); + subslice_mask &= ~REG_FIELD_GET(GEN8_F2_SS_DIS_MASK, fuse2); eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0); eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1); eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2); - eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK; - eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) | - ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) << - (32 - GEN8_EU_DIS0_S1_SHIFT)); - eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) | - ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) << - (32 - GEN8_EU_DIS1_S2_SHIFT)); + eu_disable[0] = + REG_FIELD_GET(GEN8_EU_DIS0_S0_MASK, eu_disable0); + eu_disable[1] = + REG_FIELD_GET(GEN8_EU_DIS0_S1_MASK, eu_disable0) | + REG_FIELD_GET(GEN8_EU_DIS1_S1_MASK, eu_disable1) << hweight32(GEN8_EU_DIS0_S1_MASK); + eu_disable[2] = + REG_FIELD_GET(GEN8_EU_DIS1_S2_MASK, eu_disable1) | + REG_FIELD_GET(GEN8_EU_DIS2_S2_MASK, eu_disable2) << hweight32(GEN8_EU_DIS1_S2_MASK); /* * Iterate through enabled slices and subslices to @@ -687,7 +683,7 @@ u32 intel_sseu_make_rpcs(struct intel_gt *gt, * According to documentation software must consider the configuration * as 2x4x8 and hardware will translate this to 1x8x8. * - * Furthemore, even though SScount is three bits, maximum documented + * Furthermore, even though SScount is three bits, maximum documented * value for it is four. From this some rules/restrictions follow: * * 1. diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 570c91878189..116683ebe074 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -691,16 +691,17 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, struct drm_i915_private *i915 = engine->i915; /* - * Wa_1409142259:tgl,dg1,adl-p + * Wa_1409142259:tgl,dg1,adl-p,adl-n * Wa_1409347922:tgl,dg1,adl-p * Wa_1409252684:tgl,dg1,adl-p * Wa_1409217633:tgl,dg1,adl-p * Wa_1409207793:tgl,dg1,adl-p - * Wa_1409178076:tgl,dg1,adl-p - * Wa_1408979724:tgl,dg1,adl-p - * Wa_14010443199:tgl,rkl,dg1,adl-p - * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p - * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p + * Wa_1409178076:tgl,dg1,adl-p,adl-n + * Wa_1408979724:tgl,dg1,adl-p,adl-n + * Wa_14010443199:tgl,rkl,dg1,adl-p,adl-n + * Wa_14010698770:tgl,rkl,dg1,adl-s,adl-p,adl-n + * Wa_1409342910:tgl,rkl,dg1,adl-s,adl-p,adl-n + * Wa_22010465259:tgl,rkl,dg1,adl-s,adl-p,adl-n */ wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, GEN12_DISABLE_CPS_AWARE_COLOR_PIPE); @@ -741,6 +742,12 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, /* Wa_1606376872 */ wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC); } + + /* + * This bit must be set to enable performance optimization for fast + * clears. + */ + wa_mcr_write_or(wal, GEN8_WM_CHICKEN2, WAIT_ON_DEPTH_STALL_DONE_DISABLE); } static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, @@ -1318,7 +1325,7 @@ xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) * We'll do our default/implicit steering based on GSLICE (in the * sliceid field) and DSS (in the subsliceid field). If we can * find overlap between the valid MSLICE and/or LNCF values with - * a suitable GSLICE, then we can just re-use the default value and + * a suitable GSLICE, then we can just reuse the default value and * skip and explicit steering at runtime. * * We only need to look for overlap between GSLICE/MSLICE/LNCF to find diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c index c0637bf799a3..64315b714743 100644 --- a/drivers/gpu/drm/i915/gt/mock_engine.c +++ b/drivers/gpu/drm/i915/gt/mock_engine.c @@ -297,7 +297,7 @@ static void mock_reset_cancel(struct intel_engine_cs *engine) struct i915_request *rq; unsigned long flags; - del_timer_sync(&mock->hw_delay); + timer_delete_sync(&mock->hw_delay); spin_lock_irqsave(&engine->sched_engine->lock, flags); @@ -432,7 +432,7 @@ void mock_engine_flush(struct intel_engine_cs *engine) container_of(engine, typeof(*mock), base); struct i915_request *request, *rn; - del_timer_sync(&mock->hw_delay); + timer_delete_sync(&mock->hw_delay); spin_lock_irq(&mock->hw_lock); list_for_each_entry_safe(request, rn, &mock->hw_queue, mock.link) diff --git a/drivers/gpu/drm/i915/gt/selftest_execlists.c b/drivers/gpu/drm/i915/gt/selftest_execlists.c index 81c31396eceb..0454eb1814bb 100644 --- a/drivers/gpu/drm/i915/gt/selftest_execlists.c +++ b/drivers/gpu/drm/i915/gt/selftest_execlists.c @@ -53,7 +53,7 @@ static int wait_for_submit(struct intel_engine_cs *engine, if (i915_request_completed(rq)) /* that was quick! */ return 0; - /* Wait until the HW has acknowleged the submission (or err) */ + /* Wait until the HW has acknowledged the submission (or err) */ intel_engine_flush_submission(engine); if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) return 0; @@ -1198,7 +1198,7 @@ static int live_timeslice_rewind(void *arg) ENGINE_TRACE(engine, "forcing tasklet for rewind\n"); while (i915_request_is_active(rq[A2])) { /* semaphore yield! */ /* Wait for the timeslice to kick in */ - del_timer(&engine->execlists.timer); + timer_delete(&engine->execlists.timer); tasklet_hi_schedule(&engine->sched_engine->tasklet); intel_engine_flush_submission(engine); } @@ -2357,7 +2357,7 @@ static int __cancel_fail(struct live_preempt_cancel *arg) /* force preempt reset [failure] */ while (!engine->execlists.pending[0]) intel_engine_flush_submission(engine); - del_timer_sync(&engine->execlists.preempt); + timer_delete_sync(&engine->execlists.preempt); intel_engine_flush_submission(engine); cancel_reset_timeout(engine); diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 9d3aeb237295..f057c16410e7 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -548,7 +548,7 @@ static int igt_reset_fail_engine(void *arg) struct intel_engine_cs *engine; enum intel_engine_id id; - /* Check that we can recover from engine-reset failues */ + /* Check that we can recover from engine-reset failures */ if (!intel_has_reset_engine(gt)) return 0; diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index e17b8777d21d..22e750108c5f 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -63,7 +63,7 @@ static int wait_for_submit(struct intel_engine_cs *engine, if (i915_request_completed(rq)) /* that was quick! */ return 0; - /* Wait until the HW has acknowleged the submission (or err) */ + /* Wait until the HW has acknowledged the submission (or err) */ intel_engine_flush_submission(engine); if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) return 0; diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c b/drivers/gpu/drm/i915/gt/selftest_migrate.c index 1bf7b88d9a9d..401bee030dbc 100644 --- a/drivers/gpu/drm/i915/gt/selftest_migrate.c +++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c @@ -660,7 +660,7 @@ static int live_emit_pte_full_ring(void *arg) out_rq: i915_request_add(rq); /* GEM_BUG_ON(rq->reserved_space > ring->space)? */ - del_timer_sync(&st.timer); + timer_delete_sync(&st.timer); destroy_timer_on_stack(&st.timer); out_unpin: intel_context_unpin(ce); diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c index 27b6d51ef145..908483ab0bc8 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c @@ -222,7 +222,7 @@ int live_rc6_ctx_wa(void *arg) i915_reset_engine_count(error, engine); const u32 *res; - /* Use a sacrifical context */ + /* Use a sacrificial context */ ce = intel_context_create(engine); if (IS_ERR(ce)) { err = PTR_ERR(ce); diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c index c207a4fb03bf..73bc91c6ea07 100644 --- a/drivers/gpu/drm/i915/gt/selftest_rps.c +++ b/drivers/gpu/drm/i915/gt/selftest_rps.c @@ -22,7 +22,7 @@ #include "selftests/igt_spinner.h" #include "selftests/librapl.h" -/* Try to isolate the impact of cstates from determing frequency response */ +/* Try to isolate the impact of cstates from determining frequency response */ #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */ static void dummy_rps_work(struct work_struct *wrk) @@ -477,12 +477,13 @@ int live_rps_control(void *arg) limit, intel_gpu_freq(rps, limit), min, max, ktime_to_ns(min_dt), ktime_to_ns(max_dt)); - if (limit == rps->min_freq) { - pr_err("%s: GPU throttled to minimum!\n", - engine->name); + if (limit != rps->max_freq) { + u32 throttle = intel_uncore_read(gt->uncore, + intel_gt_perf_limit_reasons_reg(gt)); + + pr_warn("%s: GPU throttled with reasons 0x%08x\n", + engine->name, throttle & GT0_PERF_LIMIT_REASONS_MASK); show_pstate_limits(rps); - err = -ENODEV; - break; } if (igt_flush_test(gt->i915)) { @@ -1115,7 +1116,7 @@ static u64 measure_power(struct intel_rps *rps, int *freq) for (i = 0; i < 5; i++) x[i] = __measure_power(5); - *freq = (*freq + intel_rps_read_actual_frequency(rps)) / 2; + *freq = (*freq + read_cagf(rps)) / 2; /* A simple triangle filter for better result stability */ sort(x, 5, sizeof(*x), cmp_u64, NULL); diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c b/drivers/gpu/drm/i915/gt/selftest_slpc.c index e218b229681f..e61bb0bad12c 100644 --- a/drivers/gpu/drm/i915/gt/selftest_slpc.c +++ b/drivers/gpu/drm/i915/gt/selftest_slpc.c @@ -95,6 +95,21 @@ static int slpc_restore_freq(struct intel_guc_slpc *slpc, u32 min, u32 max) return 0; } +static u64 slpc_measure_power(struct intel_rps *rps, int *freq) +{ + u64 x[5]; + int i; + + for (i = 0; i < 5; i++) + x[i] = __measure_power(5); + + *freq = (*freq + intel_rps_read_actual_frequency(rps)) / 2; + + /* A simple triangle filter for better result stability */ + sort(x, 5, sizeof(*x), cmp_u64, NULL); + return div_u64(x[1] + 2 * x[2] + x[3], 4); +} + static u64 measure_power_at_freq(struct intel_gt *gt, int *freq, u64 *power) { int err = 0; @@ -103,7 +118,7 @@ static u64 measure_power_at_freq(struct intel_gt *gt, int *freq, u64 *power) if (err) return err; *freq = intel_rps_read_actual_frequency(>->rps); - *power = measure_power(>->rps, freq); + *power = slpc_measure_power(>->rps, freq); return err; } diff --git a/drivers/gpu/drm/i915/gt/shaders/README b/drivers/gpu/drm/i915/gt/shaders/README index e7e96d7073c7..22f8dabed434 100644 --- a/drivers/gpu/drm/i915/gt/shaders/README +++ b/drivers/gpu/drm/i915/gt/shaders/README @@ -10,7 +10,7 @@ i915/gt/shaders/clear_kernel directory. The generated .c files should never be modified directly. Instead, any modification needs to be done on the on their respective ASM files and build instructions below -needes to be followed. +needs to be followed. Building ======== @@ -24,7 +24,7 @@ on building. Please make sure your Mesa tool is compiled with "-Dtools=intel" and "-Ddri-drivers=i965", and run this script from IGT source root directory" -The instructions bellow assume: +The instructions below assume: * IGT gpu tools source code is located on your home directory (~) as ~/igt * Mesa source code is located on your home directory (~) as ~/mesa and built under the ~/mesa/build directory @@ -43,4 +43,4 @@ igt $ ./scripts/generate_clear_kernel.sh -g ivb \ ~/igt/lib/i915/shaders/clear_kernel/hsw.asm ~ $ cd ~/igt igt $ ./scripts/generate_clear_kernel.sh -g hsw \ - -m ~/mesa/build/src/intel/tools/i965_asm
\ No newline at end of file + -m ~/mesa/build/src/intel/tools/i965_asm diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm index 5fdf384bb621..6c0c89daf96c 100644 --- a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm +++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/hsw.asm @@ -24,7 +24,7 @@ mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N }; * DW 1.4 - Rsvd (intended for context ID) * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count) - * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count) + * DW 1.7 - Rsvd MBZ (intended for Total Thread Count) * * Binding Table * diff --git a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm index 97c7ac9e3854..27c28e63d6cc 100644 --- a/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm +++ b/drivers/gpu/drm/i915/gt/shaders/clear_kernel/ivb.asm @@ -24,7 +24,7 @@ mov(1) f0.1<1>UW g1.2<0,1,0>UW { align1 1N }; * DW 1.4 - Rsvd (intended for context ID) * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count) - * DW 1.7 - Rsvd MBZ (inteded for Total Thread Count) + * DW 1.7 - Rsvd MBZ (intended for Total Thread Count) * * Binding Table * diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.c b/drivers/gpu/drm/i915/gt/shmem_utils.c index bb696b29ee2c..365c4b8b04f4 100644 --- a/drivers/gpu/drm/i915/gt/shmem_utils.c +++ b/drivers/gpu/drm/i915/gt/shmem_utils.c @@ -108,7 +108,7 @@ static int __shmem_rw(struct file *file, loff_t off, if (IS_ERR(page)) return PTR_ERR(page); - vaddr = kmap(page); + vaddr = kmap_local_page(page); if (write) { memcpy(vaddr + offset_in_page(off), ptr, this); set_page_dirty(page); @@ -116,7 +116,7 @@ static int __shmem_rw(struct file *file, loff_t off, memcpy(ptr, vaddr + offset_in_page(off), this); } mark_page_accessed(page); - kunmap(page); + kunmap_local(vaddr); put_page(page); len -= this; @@ -143,11 +143,11 @@ int shmem_read_to_iosys_map(struct file *file, loff_t off, if (IS_ERR(page)) return PTR_ERR(page); - vaddr = kmap(page); + vaddr = kmap_local_page(page); iosys_map_memcpy_to(map, map_off, vaddr + offset_in_page(off), this); mark_page_accessed(page); - kunmap(page); + kunmap_local(vaddr); put_page(page); len -= this; diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h index c34674e797c6..6de87ae5669e 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h @@ -228,6 +228,11 @@ struct slpc_optimized_strategies { #define SLPC_OPTIMIZED_STRATEGY_COMPUTE REG_BIT(0) +enum slpc_power_profiles { + SLPC_POWER_PROFILES_BASE = 0x0, + SLPC_POWER_PROFILES_POWER_SAVING = 0x1 +}; + /** * DOC: SLPC H2G MESSAGE FORMAT * diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h index 1fc0c17b1230..803c0379d97d 100644 --- a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h +++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h @@ -81,7 +81,7 @@ struct guc_debug_capture_list { * * intel_guc_capture module uses these structures to maintain static * tables (per unique platform) that consists of lists of registers - * (offsets, names, flags,...) that are used at the ADS regisration + * (offsets, names, flags,...) that are used at the ADS registration * time as well as during runtime processing and reporting of error- * capture states generated by GuC just prior to engine reset events. */ @@ -200,7 +200,7 @@ struct intel_guc_state_capture { * dynamically allocate new nodes when receiving the G2H notification * because the event handlers for all G2H event-processing is called * by the ct processing worker queue and when that queue is being - * processed, there is no absoluate guarantee that we are not in the + * processed, there is no absolute guarantee that we are not in the * midst of a GT reset operation (which doesn't allow allocations). */ struct list_head cachelist; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 5949ff0b0161..9df80c325fc1 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -690,7 +690,7 @@ int intel_guc_suspend(struct intel_guc *guc) * H2G MMIO command completes. * * Don't abort on a failure code from the GuC. Keep going and do the - * clean up in santize() and re-initialisation on resume and hopefully + * clean up in sanitize() and re-initialisation on resume and hopefully * the error here won't be problematic. */ ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h index 57b903132776..053780f562c1 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h @@ -295,7 +295,7 @@ struct intel_guc { */ struct work_struct dead_guc_worker; /** - * @last_dead_guc_jiffies: timestamp of previous 'dead guc' occurrance + * @last_dead_guc_jiffies: timestamp of previous 'dead guc' occurrence * used to prevent a fundamentally broken system from continuously * reloading the GuC. */ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c index fe53e8eccf4b..e7ccfa520df3 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c @@ -259,13 +259,14 @@ static int guc_wait_ucode(struct intel_guc *guc) } else if (delta_ms > 200) { guc_warn(guc, "excessive init time: %lldms! [status = 0x%08X, count = %d, ret = %d]\n", delta_ms, status, count, ret); - guc_warn(guc, "excessive init time: [freq = %dMHz, before = %dMHz, perf_limit_reasons = 0x%08X]\n", - intel_rps_read_actual_frequency(>->rps), before_freq, + guc_warn(guc, "excessive init time: [freq = %dMHz -> %dMHz vs %dMHz, perf_limit_reasons = 0x%08X]\n", + before_freq, intel_rps_read_actual_frequency(>->rps), + intel_rps_get_requested_frequency(>->rps), intel_uncore_read(uncore, intel_gt_perf_limit_reasons_reg(gt))); } else { - guc_dbg(guc, "init took %lldms, freq = %dMHz, before = %dMHz, status = 0x%08X, count = %d, ret = %d\n", - delta_ms, intel_rps_read_actual_frequency(>->rps), - before_freq, status, count, ret); + guc_dbg(guc, "init took %lldms, freq = %dMHz -> %dMHz vs %dMHz, status = 0x%08X, count = %d, ret = %d\n", + delta_ms, before_freq, intel_rps_read_actual_frequency(>->rps), + intel_rps_get_requested_frequency(>->rps), status, count, ret); } return ret; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h index 4ce6e2332a63..eded00f0c7e1 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h @@ -408,7 +408,7 @@ enum guc_capture_type { GUC_CAPTURE_LIST_TYPE_MAX, }; -/* Class indecies for capture_class and capture_instance arrays */ +/* Class indices for capture_class and capture_instance arrays */ enum { GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0, GUC_CAPTURE_LIST_CLASS_VIDEO = 1, diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c index b67a15f74276..868195c33f5b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.c @@ -7,6 +7,7 @@ #include "gt/intel_hwconfig.h" #include "i915_drv.h" #include "i915_memcpy.h" +#include "intel_guc_print.h" /* * GuC has a blob containing hardware configuration information (HWConfig). @@ -42,6 +43,8 @@ static int __guc_action_get_hwconfig(struct intel_guc *guc, }; int ret; + guc_dbg(guc, "Querying HW config table: size = %d, offset = 0x%08X\n", + ggtt_size, ggtt_offset); ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0); if (ret == -ENXIO) return -ENOENT; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c index 706fffca698b..d5ee6e5e1443 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c @@ -15,6 +15,34 @@ #include "gt/intel_gt_regs.h" #include "gt/intel_rps.h" +/** + * DOC: SLPC - Dynamic Frequency management + * + * Single Loop Power Control (SLPC) is a GuC algorithm that manages + * GT frequency based on busyness and how KMD initializes it. SLPC is + * almost completely in control after initialization except for a few + * scenarios mentioned below. + * + * KMD uses the concept of waitboost to ramp frequency to RP0 when there + * are pending submissions for a context. It achieves this by sending GuC a + * request to update the min frequency to RP0. Waitboost is disabled + * when the request retires. + * + * Another form of frequency control happens through per-context hints. + * A context can be marked as low latency during creation. That will ensure + * that SLPC uses an aggressive frequency ramp when that context is active. + * + * Power profiles add another level of control to these mechanisms. + * When power saving profile is chosen, SLPC will use conservative + * thresholds to ramp frequency, thus saving power. KMD will disable + * waitboosts as well, which achieves further power savings. Base profile + * is default and ensures balanced performance for any workload. + * + * Lastly, users have some level of control through sysfs, where min/max + * frequency values can be altered and the use of efficient freq + * can be toggled. + */ + static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc) { return container_of(slpc, struct intel_guc, slpc); @@ -265,6 +293,8 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc) slpc->num_boosts = 0; slpc->media_ratio_mode = SLPC_MEDIA_RATIO_MODE_DYNAMIC_CONTROL; + slpc->power_profile = SLPC_POWER_PROFILES_BASE; + mutex_init(&slpc->lock); INIT_WORK(&slpc->boost_work, slpc_boost_work); @@ -357,21 +387,29 @@ static u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc) GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER); } -static void slpc_shared_data_reset(struct slpc_shared_data *data) +static void slpc_shared_data_reset(struct intel_guc_slpc *slpc) { - memset(data, 0, sizeof(struct slpc_shared_data)); + struct drm_i915_private *i915 = slpc_to_i915(slpc); + struct slpc_shared_data *data = slpc->vaddr; + memset(data, 0, sizeof(struct slpc_shared_data)); data->header.size = sizeof(struct slpc_shared_data); /* Enable only GTPERF task, disable others */ slpc_mem_set_enabled(data, SLPC_PARAM_TASK_ENABLE_GTPERF, SLPC_PARAM_TASK_DISABLE_GTPERF); - slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_BALANCER, - SLPC_PARAM_TASK_DISABLE_BALANCER); + /* + * Don't allow balancer related algorithms on platforms before + * Xe_LPG, where GuC started to restrict it to TDP limited scenarios. + */ + if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)) { + slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_BALANCER, + SLPC_PARAM_TASK_DISABLE_BALANCER); - slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_DCC, - SLPC_PARAM_TASK_DISABLE_DCC); + slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_DCC, + SLPC_PARAM_TASK_DISABLE_DCC); + } } /** @@ -567,6 +605,34 @@ int intel_guc_slpc_set_media_ratio_mode(struct intel_guc_slpc *slpc, u32 val) return ret; } +int intel_guc_slpc_set_power_profile(struct intel_guc_slpc *slpc, u32 val) +{ + struct drm_i915_private *i915 = slpc_to_i915(slpc); + intel_wakeref_t wakeref; + int ret = 0; + + if (val > SLPC_POWER_PROFILES_POWER_SAVING) + return -EINVAL; + + mutex_lock(&slpc->lock); + wakeref = intel_runtime_pm_get(&i915->runtime_pm); + + ret = slpc_set_param(slpc, + SLPC_PARAM_POWER_PROFILE, + val); + if (ret) + guc_err(slpc_to_guc(slpc), + "Failed to set power profile to %d: %pe\n", + val, ERR_PTR(ret)); + else + slpc->power_profile = val; + + intel_runtime_pm_put(&i915->runtime_pm, wakeref); + mutex_unlock(&slpc->lock); + + return ret; +} + void intel_guc_pm_intrmsk_enable(struct intel_gt *gt) { u32 pm_intrmsk_mbz = 0; @@ -686,7 +752,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) GEM_BUG_ON(!slpc->vma); - slpc_shared_data_reset(slpc->vaddr); + slpc_shared_data_reset(slpc); ret = slpc_reset(slpc); if (unlikely(ret < 0)) { @@ -728,6 +794,13 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc) /* Enable SLPC Optimized Strategy for compute */ intel_guc_slpc_set_strategy(slpc, SLPC_OPTIMIZED_STRATEGY_COMPUTE); + /* Set cached value of power_profile */ + ret = intel_guc_slpc_set_power_profile(slpc, slpc->power_profile); + if (unlikely(ret)) { + guc_probe_error(guc, "Failed to set SLPC power profile: %pe\n", ERR_PTR(ret)); + return ret; + } + return 0; } @@ -791,6 +864,23 @@ int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p drm_printf(p, "\tSLPC state: %s\n", slpc_get_state_string(slpc)); drm_printf(p, "\tGTPERF task active: %s\n", str_yes_no(slpc_tasks->status & SLPC_GTPERF_TASK_ENABLED)); + drm_printf(p, "\tDCC enabled: %s\n", + str_yes_no(slpc_tasks->status & + SLPC_DCC_TASK_ENABLED)); + drm_printf(p, "\tDCC in: %s\n", + str_yes_no(slpc_tasks->status & SLPC_IN_DCC)); + drm_printf(p, "\tBalancer enabled: %s\n", + str_yes_no(slpc_tasks->status & + SLPC_BALANCER_ENABLED)); + drm_printf(p, "\tIBC enabled: %s\n", + str_yes_no(slpc_tasks->status & + SLPC_IBC_TASK_ENABLED)); + drm_printf(p, "\tBalancer IA LMT enabled: %s\n", + str_yes_no(slpc_tasks->status & + SLPC_BALANCER_IA_LMT_ENABLED)); + drm_printf(p, "\tBalancer IA LMT active: %s\n", + str_yes_no(slpc_tasks->status & + SLPC_BALANCER_IA_LMT_ACTIVE)); drm_printf(p, "\tMax freq: %u MHz\n", slpc_decode_max_freq(slpc)); drm_printf(p, "\tMin freq: %u MHz\n", diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h index 1cb5fd44f05c..fc9f761b4372 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h @@ -46,5 +46,6 @@ void intel_guc_slpc_boost(struct intel_guc_slpc *slpc); void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc); int intel_guc_slpc_set_ignore_eff_freq(struct intel_guc_slpc *slpc, bool val); int intel_guc_slpc_set_strategy(struct intel_guc_slpc *slpc, u32 val); +int intel_guc_slpc_set_power_profile(struct intel_guc_slpc *slpc, u32 val); #endif diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h index a88651331497..83673b10ac4e 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h @@ -33,6 +33,9 @@ struct intel_guc_slpc { u32 max_freq_softlimit; bool ignore_eff_freq; + /* Base or power saving */ + u32 power_profile; + /* cached media ratio mode */ u32 media_ratio_mode; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 12f1ba7ca9c1..f8cb7c630d5b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1223,7 +1223,7 @@ __extend_last_switch(struct intel_guc *guc, u64 *prev_start, u32 new_start) * determine validity of these values. Instead we read the values multiple times * until they are consistent. In test runs, 3 attempts results in consistent * values. The upper bound is set to 6 attempts and may need to be tuned as per - * any new occurences. + * any new occurrences. */ static void __get_engine_usage_record(struct intel_engine_cs *engine, u32 *last_in, u32 *id, u32 *total) @@ -1285,15 +1285,12 @@ static void guc_update_engine_gt_clks(struct intel_engine_cs *engine) static u32 gpm_timestamp_shift(struct intel_gt *gt) { intel_wakeref_t wakeref; - u32 reg, shift; + u32 reg; with_intel_runtime_pm(gt->uncore->rpm, wakeref) reg = intel_uncore_read(gt->uncore, RPM_CONFIG0); - shift = (reg & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> - GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT; - - return 3 - shift; + return 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg); } static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now) @@ -1469,6 +1466,19 @@ static void __reset_guc_busyness_stats(struct intel_guc *guc) spin_unlock_irqrestore(&guc->timestamp.lock, flags); } +static void __update_guc_busyness_running_state(struct intel_guc *guc) +{ + struct intel_gt *gt = guc_to_gt(guc); + struct intel_engine_cs *engine; + enum intel_engine_id id; + unsigned long flags; + + spin_lock_irqsave(&guc->timestamp.lock, flags); + for_each_engine(engine, gt, id) + engine->stats.guc.running = false; + spin_unlock_irqrestore(&guc->timestamp.lock, flags); +} + static void __update_guc_busyness_stats(struct intel_guc *guc) { struct intel_gt *gt = guc_to_gt(guc); @@ -1619,6 +1629,9 @@ void intel_guc_busyness_park(struct intel_gt *gt) if (!guc_submission_initialized(guc)) return; + /* Assume no engines are running and set running state to false */ + __update_guc_busyness_running_state(guc); + /* * There is a race with suspend flow where the worker runs after suspend * and causes an unclaimed register access warning. Cancel the worker @@ -2995,7 +3008,7 @@ static int __guc_context_pin(struct intel_context *ce, /* * GuC context gets pinned in guc_request_alloc. See that function for - * explaination of why. + * explanation of why. */ return lrc_pin(ce, engine, vaddr); @@ -3433,10 +3446,10 @@ static inline int guc_lrc_desc_unpin(struct intel_context *ce) */ ret = deregister_context(ce, ce->guc_id.id); if (ret) { - spin_lock(&ce->guc_state.lock); + spin_lock_irqsave(&ce->guc_state.lock, flags); set_context_registered(ce); clr_context_destroyed(ce); - spin_unlock(&ce->guc_state.lock); + spin_unlock_irqrestore(&ce->guc_state.lock, flags); /* * As gt-pm is awake at function entry, intel_wakeref_put_async merely decrements * the wakeref immediately but per function spec usage call this after unlock. @@ -5519,12 +5532,20 @@ static inline void guc_log_context(struct drm_printer *p, { drm_printf(p, "GuC lrc descriptor %u:\n", ce->guc_id.id); drm_printf(p, "\tHW Context Desc: 0x%08x\n", ce->lrc.lrca); - drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n", - ce->ring->head, - ce->lrc_reg_state[CTX_RING_HEAD]); - drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n", - ce->ring->tail, - ce->lrc_reg_state[CTX_RING_TAIL]); + if (intel_context_pin_if_active(ce)) { + drm_printf(p, "\t\tLRC Head: Internal %u, Memory %u\n", + ce->ring->head, + ce->lrc_reg_state[CTX_RING_HEAD]); + drm_printf(p, "\t\tLRC Tail: Internal %u, Memory %u\n", + ce->ring->tail, + ce->lrc_reg_state[CTX_RING_TAIL]); + intel_context_unpin(ce); + } else { + drm_printf(p, "\t\tLRC Head: Internal %u, Memory not pinned\n", + ce->ring->head); + drm_printf(p, "\t\tLRC Tail: Internal %u, Memory not pinned\n", + ce->ring->tail); + } drm_printf(p, "\t\tContext Pin Count: %u\n", atomic_read(&ce->pin_count)); drm_printf(p, "\t\tGuC ID Ref Count: %u\n", diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c index b3cbf85c00cb..456d3372eef8 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c @@ -231,8 +231,8 @@ static void delayed_huc_load_init(struct intel_huc *huc) sw_fence_dummy_notify); i915_sw_fence_commit(&huc->delayed_load.fence); - hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - huc->delayed_load.timer.function = huc_delayed_load_timer_callback; + hrtimer_setup(&huc->delayed_load.timer, huc_delayed_load_timer_callback, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); } static void delayed_huc_load_fini(struct intel_huc *huc) @@ -317,6 +317,11 @@ void intel_huc_init_early(struct intel_huc *huc) } } +void intel_huc_fini_late(struct intel_huc *huc) +{ + delayed_huc_load_fini(huc); +} + #define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy") static int check_huc_loading_mode(struct intel_huc *huc) { @@ -414,12 +419,6 @@ out: void intel_huc_fini(struct intel_huc *huc) { - /* - * the fence is initialized in init_early, so we need to clean it up - * even if HuC loading is off. - */ - delayed_huc_load_fini(huc); - if (huc->heci_pkt) i915_vma_unpin_and_release(&huc->heci_pkt, 0); @@ -489,13 +488,15 @@ int intel_huc_wait_for_auth_complete(struct intel_huc *huc, if (delta_ms > 50) { huc_warn(huc, "excessive auth time: %lldms! [status = 0x%08X, count = %d, ret = %d]\n", delta_ms, huc->status[type].reg.reg, count, ret); - huc_warn(huc, "excessive auth time: [freq = %dMHz, before = %dMHz, perf_limit_reasons = 0x%08X]\n", - intel_rps_read_actual_frequency(>->rps), before_freq, + huc_warn(huc, "excessive auth time: [freq = %dMHz -> %dMHz vs %dMHz, perf_limit_reasons = 0x%08X]\n", + before_freq, intel_rps_read_actual_frequency(>->rps), + intel_rps_get_requested_frequency(>->rps), intel_uncore_read(uncore, intel_gt_perf_limit_reasons_reg(gt))); } else { - huc_dbg(huc, "auth took %lldms, freq = %dMHz, before = %dMHz, status = 0x%08X, count = %d, ret = %d\n", - delta_ms, intel_rps_read_actual_frequency(>->rps), - before_freq, huc->status[type].reg.reg, count, ret); + huc_dbg(huc, "auth took %lldms, freq = %dMHz -> %dMHz vs %dMHz, status = 0x%08X, count = %d, ret = %d\n", + delta_ms, before_freq, intel_rps_read_actual_frequency(>->rps), + intel_rps_get_requested_frequency(>->rps), + huc->status[type].reg.reg, count, ret); } /* mark the load process as complete even if the wait failed */ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h index d5e441b9e08d..921ad4b1687f 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h @@ -55,6 +55,7 @@ struct intel_huc { int intel_huc_sanitize(struct intel_huc *huc); void intel_huc_init_early(struct intel_huc *huc); +void intel_huc_fini_late(struct intel_huc *huc); int intel_huc_init(struct intel_huc *huc); void intel_huc_fini(struct intel_huc *huc); int intel_huc_auth(struct intel_huc *huc, enum intel_huc_authentication_type type); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c index 5b8080ec5315..4a3493e8d433 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c @@ -136,6 +136,7 @@ void intel_uc_init_late(struct intel_uc *uc) void intel_uc_driver_late_release(struct intel_uc *uc) { + intel_huc_fini_late(&uc->huc); } /** @@ -512,7 +513,7 @@ static int __uc_init_hw(struct intel_uc *uc) ERR_PTR(ret), attempts); } - /* Did we succeded or run out of retries? */ + /* Did we succeed or run out of retries? */ if (ret) goto err_log_capture; diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c index 26fdc392fce6..83801c992488 100644 --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc_hangcheck.c @@ -64,7 +64,7 @@ static int intel_hang_guc(void *arg) old_beat = engine->props.heartbeat_interval_ms; ret = intel_engine_set_heartbeat(engine, BEAT_INTERVAL); if (ret) { - gt_err(gt, "Failed to boost heatbeat interval: %pe\n", ERR_PTR(ret)); + gt_err(gt, "Failed to boost heartbeat interval: %pe\n", ERR_PTR(ret)); goto err; } diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 6439c8e91a8d..f25ee2953baf 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1906,7 +1906,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm; unsigned long start_offset = 0; - /* get the start gm address of the batch buffer */ + /* Get the start gm address of the batch buffer */ gma = get_gma_bb_from_cmd(s, 1); if (gma == INTEL_GVT_INVALID_ADDR) return -EFAULT; @@ -1921,15 +1921,16 @@ static int perform_bb_shadow(struct parser_exec_state *s) bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true; - /* the start_offset stores the batch buffer's start gma's - * offset relative to page boundary. so for non-privileged batch + /* + * The start_offset stores the batch buffer's start gma's + * offset relative to page boundary. So for non-privileged batch * buffer, the shadowed gem object holds exactly the same page - * layout as original gem object. This is for the convience of + * layout as original gem object. This is for the convenience of * replacing the whole non-privilged batch buffer page to this - * shadowed one in PPGTT at the same gma address. (this replacing + * shadowed one in PPGTT at the same gma address. (This replacing * action is not implemented yet now, but may be necessary in * future). - * for prileged batch buffer, we just change start gma address to + * For prileged batch buffer, we just change start gma address to * that of shadowed page. */ if (bb->ppgtt) @@ -1976,7 +1977,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) /* * ip_va saves the virtual address of the shadow batch buffer, while * ip_gma saves the graphics address of the original batch buffer. - * As the shadow batch buffer is just a copy from the originial one, + * As the shadow batch buffer is just a copy from the original one, * it should be right to use shadow batch buffer'va and original batch * buffer's gma in pair. After all, we don't want to pin the shadow * buffer here (too early). diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 95570cabdf27..1e1af5e545a4 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -97,7 +97,7 @@ int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) return 0; } -static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { +static const unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { { /* EDID with 1024x768 as its resolution */ /*Header*/ @@ -581,8 +581,7 @@ static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, vgpu->display.port_num = port_num; /* Init hrtimer based on default refresh rate */ - hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); - vblank_timer->timer.function = vblank_timer_fn; + hrtimer_setup(&vblank_timer->timer, vblank_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); vblank_timer->vrefresh_k = port->vrefresh_k; vblank_timer->period = DIV64_U64_ROUND_CLOSEST(NSEC_PER_SEC * MSEC_PER_SEC, vblank_timer->vrefresh_k); diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c index 9efc3ca0ce82..4f599af766b0 100644 --- a/drivers/gpu/drm/i915/gvt/dmabuf.c +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c @@ -436,7 +436,7 @@ int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args) dmabuf_obj_get(dmabuf_obj); } ret = 0; - gvt_dbg_dpy("vgpu%d: re-use dmabuf_obj ref %d, id %d\n", + gvt_dbg_dpy("vgpu%d: reuse dmabuf_obj ref %d, id %d\n", vgpu->id, kref_read(&dmabuf_obj->kref), gfx_plane_info->dmabuf_id); mutex_unlock(&vgpu->dmabuf_lock); diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c index 0a357ca42db1..89147d33168c 100644 --- a/drivers/gpu/drm/i915/gvt/edid.c +++ b/drivers/gpu/drm/i915/gvt/edid.c @@ -298,7 +298,7 @@ static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, int byte_count = byte_left; u32 reg_data = 0; - /* Data can only be recevied if previous settings correct */ + /* Data can only be received if previous settings correct */ if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) { if (byte_left <= 0) { memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 15cce973e1ae..f9f7ef131371 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -398,120 +398,3 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, plane->y_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)); return 0; } - -#define SPRITE_FORMAT_NUM (1 << 3) - -static const struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = { - [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"}, - [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"}, - [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"}, - [0x4] = {DRM_FORMAT_AYUV, 32, - "YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"}, -}; - -/** - * intel_vgpu_decode_sprite_plane - Decode sprite plane - * @vgpu: input vgpu - * @plane: sprite plane to save decoded info - * This function is called for decoding plane - * - * Returns: - * 0 on success, non-zero if failed. - */ -int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, - struct intel_vgpu_sprite_plane_format *plane) -{ - u32 val, fmt; - u32 color_order, yuv_order; - int drm_format; - int pipe; - - pipe = get_active_pipe(vgpu); - if (pipe >= I915_MAX_PIPES) - return -ENODEV; - - val = vgpu_vreg_t(vgpu, SPRCTL(pipe)); - plane->enabled = !!(val & SPRITE_ENABLE); - if (!plane->enabled) - return -ENODEV; - - plane->tiled = !!(val & SPRITE_TILED); - color_order = !!(val & SPRITE_RGB_ORDER_RGBX); - yuv_order = (val & SPRITE_YUV_ORDER_MASK) >> - _SPRITE_YUV_ORDER_SHIFT; - - fmt = (val & SPRITE_FORMAT_MASK) >> _SPRITE_FMT_SHIFT; - if (!sprite_pixel_formats[fmt].bpp) { - gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt); - return -EINVAL; - } - plane->hw_format = fmt; - plane->bpp = sprite_pixel_formats[fmt].bpp; - drm_format = sprite_pixel_formats[fmt].drm_format; - - /* Order of RGB values in an RGBxxx buffer may be ordered RGB or - * BGR depending on the state of the color_order field - */ - if (!color_order) { - if (drm_format == DRM_FORMAT_XRGB2101010) - drm_format = DRM_FORMAT_XBGR2101010; - else if (drm_format == DRM_FORMAT_XRGB8888) - drm_format = DRM_FORMAT_XBGR8888; - } - - if (drm_format == DRM_FORMAT_YUV422) { - switch (yuv_order) { - case 0: - drm_format = DRM_FORMAT_YUYV; - break; - case 1: - drm_format = DRM_FORMAT_UYVY; - break; - case 2: - drm_format = DRM_FORMAT_YVYU; - break; - case 3: - drm_format = DRM_FORMAT_VYUY; - break; - default: - /* yuv_order has only 2 bits */ - break; - } - } - - plane->drm_format = drm_format; - - plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK; - if (!vgpu_gmadr_is_valid(vgpu, plane->base)) - return -EINVAL; - - plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base); - if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) { - gvt_vgpu_err("Translate sprite plane gma 0x%x to gpa fail\n", - plane->base); - return -EINVAL; - } - - plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) & - _SPRITE_STRIDE_MASK; - - val = vgpu_vreg_t(vgpu, SPRSIZE(pipe)); - plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >> - _SPRITE_SIZE_HEIGHT_SHIFT; - plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >> - _SPRITE_SIZE_WIDTH_SHIFT; - plane->height += 1; /* raw height is one minus the real value */ - plane->width += 1; /* raw width is one minus the real value */ - - val = vgpu_vreg_t(vgpu, SPRPOS(pipe)); - plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT; - plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT; - - val = vgpu_vreg_t(vgpu, SPROFFSET(pipe)); - plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >> - _SPRITE_OFFSET_START_X_SHIFT; - plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >> - _SPRITE_OFFSET_START_Y_SHIFT; - - return 0; -} diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.h b/drivers/gpu/drm/i915/gvt/fb_decoder.h index fa6503900c84..436d43c0087b 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.h +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.h @@ -156,7 +156,5 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, struct intel_vgpu_primary_plane_format *plane); int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, struct intel_vgpu_cursor_plane_format *plane); -int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, - struct intel_vgpu_sprite_plane_format *plane); #endif diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 1bce1493b86f..2fa7ca19ba5d 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -71,72 +71,6 @@ bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size) return false; } -/* translate a guest gmadr to host gmadr */ -int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr) -{ - struct drm_i915_private *i915 = vgpu->gvt->gt->i915; - - if (drm_WARN(&i915->drm, !vgpu_gmadr_is_valid(vgpu, g_addr), - "invalid guest gmadr %llx\n", g_addr)) - return -EACCES; - - if (vgpu_gmadr_is_aperture(vgpu, g_addr)) - *h_addr = vgpu_aperture_gmadr_base(vgpu) - + (g_addr - vgpu_aperture_offset(vgpu)); - else - *h_addr = vgpu_hidden_gmadr_base(vgpu) - + (g_addr - vgpu_hidden_offset(vgpu)); - return 0; -} - -/* translate a host gmadr to guest gmadr */ -int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr) -{ - struct drm_i915_private *i915 = vgpu->gvt->gt->i915; - - if (drm_WARN(&i915->drm, !gvt_gmadr_is_valid(vgpu->gvt, h_addr), - "invalid host gmadr %llx\n", h_addr)) - return -EACCES; - - if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr)) - *g_addr = vgpu_aperture_gmadr_base(vgpu) - + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt)); - else - *g_addr = vgpu_hidden_gmadr_base(vgpu) - + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt)); - return 0; -} - -int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, - unsigned long *h_index) -{ - u64 h_addr; - int ret; - - ret = intel_gvt_ggtt_gmadr_g2h(vgpu, g_index << I915_GTT_PAGE_SHIFT, - &h_addr); - if (ret) - return ret; - - *h_index = h_addr >> I915_GTT_PAGE_SHIFT; - return 0; -} - -int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, - unsigned long *g_index) -{ - u64 g_addr; - int ret; - - ret = intel_gvt_ggtt_gmadr_h2g(vgpu, h_index << I915_GTT_PAGE_SHIFT, - &g_addr); - if (ret) - return ret; - - *g_index = g_addr >> I915_GTT_PAGE_SHIFT; - return 0; -} - #define gtt_type_is_entry(type) \ (type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \ && type != GTT_TYPE_PPGTT_PTE_ENTRY \ @@ -1259,7 +1193,7 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu, gvt_vdbg_mm("shadow 64K gtt entry\n"); /* * The layout of 64K page is special, the page size is - * controlled by uper PDE. To be simple, we always split + * controlled by upper PDE. To be simple, we always split * 64K page to smaller 4K pages in shadow PT. */ return split_64KB_gtt_entry(vgpu, spt, index, &se); diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 2c95aeef4e41..01d890999f25 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -452,8 +452,10 @@ void intel_vgpu_free_resource(struct intel_vgpu *vgpu); void intel_vgpu_write_fence(struct intel_vgpu *vgpu, u32 fence, u64 value); -/* Macros for easily accessing vGPU virtual/shadow register. - Explicitly seperate use for typed MMIO reg or real offset.*/ +/* + * Macros for easily accessing vGPU virtual/shadow register. + * Explicitly separate use for typed MMIO reg or real offset. + */ #define vgpu_vreg_t(vgpu, reg) \ (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) #define vgpu_vreg(vgpu, offset) \ @@ -531,12 +533,6 @@ int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num); gvt_gmadr_is_hidden(gvt, gmadr)) bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); -int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); -int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); -int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, - unsigned long *h_index); -int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, - unsigned long *g_index); void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, bool primary); @@ -702,7 +698,7 @@ static inline void intel_gvt_mmio_set_cmd_write_patch( * @offset: register offset * * Returns: - * True if GPU commmand write to an MMIO should be patched + * True if GPU command write to an MMIO should be patched. */ static inline bool intel_gvt_mmio_is_cmd_write_patch( struct intel_gvt *gvt, unsigned int offset) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 241cff0fc683..4efee6797873 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -689,11 +689,11 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) u32 new_rate = 0; u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k); - /* Calcuate pixel clock by (ls_clk * M / N) */ + /* Calculate pixel clock by (ls_clk * M / N) */ pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); pixel_clk *= MSEC_PER_SEC; - /* Calcuate refresh rate by (pixel_clk / (h_total * v_total)) */ + /* Calculate refresh rate by (pixel_clk / (h_total * v_total)) */ new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1)); if (*old_rate != new_rate) @@ -2001,7 +2001,7 @@ static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after * vGPU reset if in resuming. * In S0ix exit, the device power state also transite from D3 to D0 as - * S3 resume, but no vGPU reset (triggered by QEMU devic model). After + * S3 resume, but no vGPU reset (triggered by QEMU device model). After * S0ix exit, all engines continue to work. However the d3_entered * remains set which will break next vGPU reset logic (miss the expected * PPGTT invalidation). @@ -3119,23 +3119,6 @@ int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, } /** - * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be - * force-nopriv register - * - * @gvt: a GVT device - * @offset: register offset - * - * Returns: - * True if the register is in force-nonpriv whitelist; - * False if outside; - */ -bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, - unsigned int offset) -{ - return in_whitelist(offset); -} - -/** * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers * @vgpu: a vGPU * @offset: register offset diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index b27ff77bfb50..69830a5c49d3 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -142,7 +142,7 @@ static int gvt_pin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, int ret; /* - * We pin the pages one-by-one to avoid allocating a big arrary + * We pin the pages one-by-one to avoid allocating a big array * on stack to hold pfns. */ for (npage = 0; npage < total_pages; npage++) { diff --git a/drivers/gpu/drm/i915/gvt/mmio.h b/drivers/gpu/drm/i915/gvt/mmio.h index 32ebacb078e8..3dc912aba80b 100644 --- a/drivers/gpu/drm/i915/gvt/mmio.h +++ b/drivers/gpu/drm/i915/gvt/mmio.h @@ -96,9 +96,6 @@ int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes); -bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, - unsigned int offset); - int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, void *pdata, unsigned int bytes, bool is_read); diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index 273db14fd5fc..2f7208843367 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -53,7 +53,7 @@ struct engine_mmio { u32 value; }; -/* Raw offset is appened to each line for convenience. */ +/* Raw offset is append to each line for convenience. */ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = { {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */ {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ @@ -576,8 +576,8 @@ void intel_gvt_switch_mmio(struct intel_vgpu *pre, /** * We are using raw mmio access wrapper to improve the - * performace for batch mmio read/write, so we need - * handle forcewake mannually. + * performance for batch mmio read/write, so we need + * handle forcewake manually. */ intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); switch_mmio(pre, next, engine); diff --git a/drivers/gpu/drm/i915/gvt/opregion.c b/drivers/gpu/drm/i915/gvt/opregion.c index 509f9ccae3a9..dbad4d853d3a 100644 --- a/drivers/gpu/drm/i915/gvt/opregion.c +++ b/drivers/gpu/drm/i915/gvt/opregion.c @@ -222,7 +222,6 @@ int intel_vgpu_init_opregion(struct intel_vgpu *vgpu) u8 *buf; struct opregion_header *header; struct vbt v; - const char opregion_signature[16] = OPREGION_SIGNATURE; gvt_dbg_core("init vgpu%d opregion\n", vgpu->id); vgpu_opregion(vgpu)->va = (void *)__get_free_pages(GFP_KERNEL | @@ -236,8 +235,10 @@ int intel_vgpu_init_opregion(struct intel_vgpu *vgpu) /* emulated opregion with VBT mailbox only */ buf = (u8 *)vgpu_opregion(vgpu)->va; header = (struct opregion_header *)buf; - memcpy(header->signature, opregion_signature, - sizeof(opregion_signature)); + + static_assert(sizeof(header->signature) == sizeof(OPREGION_SIGNATURE) - 1); + memcpy(header->signature, OPREGION_SIGNATURE, sizeof(header->signature)); + header->size = 0x8; header->opregion_ver = 0x02000000; header->mboxes = MBOX_VBT; diff --git a/drivers/gpu/drm/i915/gvt/sched_policy.c b/drivers/gpu/drm/i915/gvt/sched_policy.c index c077fb4674f0..9f97f743aa71 100644 --- a/drivers/gpu/drm/i915/gvt/sched_policy.c +++ b/drivers/gpu/drm/i915/gvt/sched_policy.c @@ -286,8 +286,7 @@ static int tbs_sched_init(struct intel_gvt *gvt) return -ENOMEM; INIT_LIST_HEAD(&data->lru_runq_head); - hrtimer_init(&data->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); - data->timer.function = tbs_timer_fn; + hrtimer_setup(&data->timer, tbs_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); data->period = GVT_DEFAULT_TIME_SLICE; data->gvt = gvt; diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c index 23f2cc397ec9..6e87c10bc454 100644 --- a/drivers/gpu/drm/i915/gvt/scheduler.c +++ b/drivers/gpu/drm/i915/gvt/scheduler.c @@ -77,7 +77,7 @@ static void update_shadow_pdps(struct intel_vgpu_workload *workload) } /* - * when populating shadow ctx from guest, we should not overrride oa related + * When populating shadow ctx from guest, we should not override oa related * registers, so that they will not be overlapped by guest oa configs. Thus * made it possible to capture oa data from host for both host and guests. */ @@ -528,9 +528,10 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) int ret; list_for_each_entry(bb, &workload->shadow_bb, list) { - /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va + /* + * For privilege batch buffer and not wa_ctx, the bb_start_cmd_va * is only updated into ring_scan_buffer, not real ring address - * allocated in later copy_workload_to_ring_buffer. pls be noted + * allocated in later copy_workload_to_ring_buffer. Please be noted * shadow_ring_buffer_va is now pointed to real ring buffer va * in copy_workload_to_ring_buffer. */ @@ -546,7 +547,7 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) * here, rather than switch to shadow bb's gma * address, we directly use original batch buffer's * gma address, and send original bb to hardware - * directly + * directly. */ if (!bb->ppgtt) { i915_gem_ww_ctx_init(&ww, false); @@ -1774,7 +1775,7 @@ intel_vgpu_create_workload(struct intel_vgpu *vgpu, } /** - * intel_vgpu_queue_workload - Qeue a vGPU workload + * intel_vgpu_queue_workload - Queue a vGPU workload * @workload: the workload to queue in */ void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload) diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index 63c751ca4119..11260392234a 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -78,7 +78,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu) * vGPU type name is defined as GVTg_Vx_y which contains the physical GPU * generation type (e.g V4 as BDW server, V5 as SKL server). * - * Depening on the physical SKU resource, we might see vGPU types like + * Depending on the physical SKU resource, we might see vGPU types like * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create different types of * vGPU on same physical GPU depending on available resource. Each vGPU * type will have a different number of avail_instance to indicate how @@ -417,7 +417,7 @@ out_unlock: * the whole vGPU to default state as when it is created. This vGPU function * is required both for functionary and security concerns.The ultimate goal * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we - * assign a vGPU to a virtual machine we must isse such reset first. + * assign a vGPU to a virtual machine we must issue such reset first. * * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec. @@ -428,7 +428,7 @@ out_unlock: * * The parameter dev_level is to identify if we will do DMLR or GT reset. * The parameter engine_mask is to specific the engines that need to be - * resetted. If value ALL_ENGINES is given for engine_mask, it means + * reset. If value ALL_ENGINES is given for engine_mask, it means * the caller requests a full GT reset that we will reset all virtual * GPU engines. For FLR, engine_mask is ignored. */ diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 1c2a97f593c7..0d9e263913ff 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -411,9 +411,6 @@ static int i915_runtime_pm_status(struct seq_file *m, void *unused) if (!HAS_RUNTIME_PM(dev_priv)) seq_puts(m, "Runtime power management not supported\n"); - seq_printf(m, "Runtime power status: %s\n", - str_enabled_disabled(!dev_priv->display.power.domains.init_wakeref)); - seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake)); seq_printf(m, "IRQs disabled: %s\n", str_yes_no(!intel_irqs_enabled(dev_priv))); diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index c2ae37d6b94d..ce3cc93ea211 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -41,12 +41,13 @@ #include <linux/vt.h> #include <drm/drm_atomic_helper.h> +#include <drm/drm_client.h> +#include <drm/drm_client_event.h> #include <drm/drm_ioctl.h> #include <drm/drm_managed.h> #include <drm/drm_probe_helper.h> #include "display/i9xx_display_sr.h" -#include "display/intel_acpi.h" #include "display/intel_bw.h" #include "display/intel_cdclk.h" #include "display/intel_crtc.h" @@ -201,7 +202,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) static void sanitize_gpu(struct drm_i915_private *i915) { - if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) { + if (!intel_gt_gpu_reset_clobbers_display(to_gt(i915))) { struct intel_gt *gt; unsigned int i; @@ -657,8 +658,6 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) intel_power_domains_enable(display); intel_runtime_pm_enable(&dev_priv->runtime_pm); - intel_register_dsm_handler(); - if (i915_switcheroo_register(dev_priv)) drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); } @@ -675,8 +674,6 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) i915_switcheroo_unregister(dev_priv); - intel_unregister_dsm_handler(); - intel_runtime_pm_disable(&dev_priv->runtime_pm); intel_power_domains_disable(display); @@ -973,7 +970,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915) intel_runtime_pm_disable(&i915->runtime_pm); intel_power_domains_disable(display); - intel_fbdev_set_suspend(&i915->drm, FBINFO_STATE_SUSPENDED, true); + drm_client_dev_suspend(&i915->drm, false); if (HAS_DISPLAY(i915)) { drm_kms_helper_poll_disable(&i915->drm); intel_display_driver_disable_user_access(display); @@ -1056,7 +1053,7 @@ static int i915_drm_suspend(struct drm_device *dev) /* We do a lot of poking in a lot of registers, make sure they work * properly. */ intel_power_domains_disable(display); - intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); + drm_client_dev_suspend(dev, false); if (HAS_DISPLAY(dev_priv)) { drm_kms_helper_poll_disable(dev); intel_display_driver_disable_user_access(display); @@ -1075,7 +1072,7 @@ static int i915_drm_suspend(struct drm_device *dev) intel_encoder_suspend_all(&dev_priv->display); /* Must be called before GGTT is suspended. */ - intel_dpt_suspend(dev_priv); + intel_dpt_suspend(display); i915_ggtt_suspend(to_gt(dev_priv)->ggtt); i9xx_display_sr_save(display); @@ -1130,7 +1127,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) * leave the device in D0 on those platforms and hope the BIOS will * power down the device properly. The issue was seen on multiple old * GENs with different BIOS vendors, so having an explicit blacklist - * is inpractical; apply the workaround on everything pre GEN6. The + * is impractical; apply the workaround on everything pre GEN6. The * platforms where the issue was seen: * Lenovo Thinkpad X301, X61s, X60, T60, X41 * Fujitsu FSC S7110 @@ -1192,7 +1189,7 @@ static int i915_drm_resume(struct drm_device *dev) setup_private_pat(gt); /* Must be called after GGTT is resumed. */ - intel_dpt_resume(dev_priv); + intel_dpt_resume(display); intel_dmc_resume(display); @@ -1242,7 +1239,7 @@ static int i915_drm_resume(struct drm_device *dev) intel_opregion_resume(display); - intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); + drm_client_dev_resume(dev, false); intel_power_domains_enable(display); @@ -1812,6 +1809,8 @@ static const struct drm_driver i915_drm_driver = { .dumb_create = i915_gem_dumb_create, .dumb_map_offset = i915_gem_dumb_mmap_offset, + INTEL_FBDEV_DRIVER_OPS, + .ioctls = i915_ioctls, .num_ioctls = ARRAY_SIZE(i915_ioctls), .fops = &i915_driver_fops, diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b96b8de12756..54538b6f85df 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -274,7 +274,6 @@ struct drm_i915_private { /* PCH chipset type */ enum intel_pch pch_type; - unsigned short pch_id; unsigned long gem_quirks; @@ -306,6 +305,7 @@ struct drm_i915_private { INTEL_DRAM_DDR5, INTEL_DRAM_LPDDR5, INTEL_DRAM_GDDR, + INTEL_DRAM_GDDR_ECC, } type; u8 num_qgv_points; u8 num_psf_gv_points; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 070ab6546987..8c8d43451f35 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1146,11 +1146,11 @@ int i915_gem_init(struct drm_i915_private *dev_priv) int ret; /* - * In the proccess of replacing cache_level with pat_index a tricky + * In the process of replacing cache_level with pat_index a tricky * dependency is created on the definition of the enum i915_cache_level. - * in case this enum is changed, PTE encode would be broken. + * In case this enum is changed, PTE encode would be broken. * Add a WARNING here. And remove when we completely quit using this - * enum + * enum. */ BUILD_BUG_ON(I915_CACHE_NONE != 0 || I915_CACHE_LLC != 1 || diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 819ab933bb10..a6613eed3398 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -2490,7 +2490,7 @@ void i915_gpu_error_debugfs_register(struct drm_i915_private *i915) } static ssize_t error_state_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *attr, char *buf, + const struct bin_attribute *attr, char *buf, loff_t off, size_t count) { @@ -2526,7 +2526,7 @@ static ssize_t error_state_read(struct file *filp, struct kobject *kobj, } static ssize_t error_state_write(struct file *file, struct kobject *kobj, - struct bin_attribute *attr, char *buf, + const struct bin_attribute *attr, char *buf, loff_t off, size_t count) { struct device *kdev = kobj_to_dev(kobj); @@ -2542,8 +2542,8 @@ static const struct bin_attribute error_state_attr = { .attr.name = "error", .attr.mode = S_IRUSR | S_IWUSR, .size = 0, - .read = error_state_read, - .write = error_state_write, + .read_new = error_state_read, + .write_new = error_state_write, }; void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h index 78a8928562a9..749e1c55613e 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.h +++ b/drivers/gpu/drm/i915/i915_gpu_error.h @@ -224,8 +224,6 @@ struct i915_gpu_error { /* Protected by the above dev->gpu_error.lock. */ struct i915_gpu_coredump *first_error; - atomic_t pending_fb_pin; - /** Number of times the device has been reset (global) */ atomic_t reset_count; diff --git a/drivers/gpu/drm/i915/i915_gtt_view_types.h b/drivers/gpu/drm/i915/i915_gtt_view_types.h new file mode 100644 index 000000000000..c084f67bc880 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_gtt_view_types.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2025 Intel Corporation */ + +#ifndef __I915_GTT_VIEW_TYPES_H__ +#define __I915_GTT_VIEW_TYPES_H__ + +#include <linux/types.h> + +struct intel_remapped_plane_info { + /* in gtt pages */ + u32 offset:31; + u32 linear:1; + union { + /* in gtt pages for !linear */ + struct { + u16 width; + u16 height; + u16 src_stride; + u16 dst_stride; + }; + + /* in gtt pages for linear */ + u32 size; + }; +} __packed; + +struct intel_rotation_info { + struct intel_remapped_plane_info plane[2]; +} __packed; + +struct intel_partial_info { + u64 offset; + unsigned int size; +} __packed; + +struct intel_remapped_info { + struct intel_remapped_plane_info plane[4]; + /* in gtt pages */ + u32 plane_alignment; +} __packed; + +enum i915_gtt_view_type { + I915_GTT_VIEW_NORMAL = 0, + I915_GTT_VIEW_ROTATED = sizeof(struct intel_rotation_info), + I915_GTT_VIEW_PARTIAL = sizeof(struct intel_partial_info), + I915_GTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info), +}; + +struct i915_gtt_view { + enum i915_gtt_view_type type; + union { + /* Members need to contain no holes/padding */ + struct intel_partial_info partial; + struct intel_rotation_info rotated; + struct intel_remapped_info remapped; + }; +}; + +#endif /* __I915_GTT_VIEW_TYPES_H__ */ diff --git a/drivers/gpu/drm/i915/i915_iosf_mbi.h b/drivers/gpu/drm/i915/i915_iosf_mbi.h index 8f81b7603d37..317075d0da4e 100644 --- a/drivers/gpu/drm/i915/i915_iosf_mbi.h +++ b/drivers/gpu/drm/i915/i915_iosf_mbi.h @@ -31,12 +31,6 @@ iosf_mbi_unregister_pmic_bus_access_notifier_unlocked(struct notifier_block *nb) { return 0; } - -static inline -int iosf_mbi_unregister_pmic_bus_access_notifier(struct notifier_block *nb) -{ - return 0; -} #endif #endif /* __I915_IOSF_MBI_H__ */ diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 7920ad9585ae..37ca4a35daf2 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -120,6 +120,29 @@ void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs, intel_uncore_posting_read(uncore, regs.imr); } +void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs) +{ + intel_uncore_write(uncore, regs.emr, 0xffffffff); + intel_uncore_posting_read(uncore, regs.emr); + + intel_uncore_write(uncore, regs.eir, 0xffffffff); + intel_uncore_posting_read(uncore, regs.eir); + intel_uncore_write(uncore, regs.eir, 0xffffffff); + intel_uncore_posting_read(uncore, regs.eir); +} + +void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs, + u32 emr_val) +{ + intel_uncore_write(uncore, regs.eir, 0xffffffff); + intel_uncore_posting_read(uncore, regs.eir); + intel_uncore_write(uncore, regs.eir, 0xffffffff); + intel_uncore_posting_read(uncore, regs.eir); + + intel_uncore_write(uncore, regs.emr, emr_val); + intel_uncore_posting_read(uncore, regs.emr); +} + /** * ivb_parity_work - Workqueue called when a parity error interrupt * occurred. @@ -207,6 +230,7 @@ out: static irqreturn_t valleyview_irq_handler(int irq, void *arg) { struct drm_i915_private *dev_priv = arg; + struct intel_display *display = &dev_priv->display; irqreturn_t ret = IRQ_NONE; if (!intel_irqs_enabled(dev_priv)) @@ -217,6 +241,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) do { u32 iir, gt_iir, pm_iir; + u32 eir = 0, dpinvgtt = 0; u32 pipe_stats[I915_MAX_PIPES] = {}; u32 hotplug_status = 0; u32 ier = 0; @@ -254,13 +279,16 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) if (iir & I915_DISPLAY_PORT_INTERRUPT) hotplug_status = i9xx_hpd_irq_ack(dev_priv); + if (iir & I915_MASTER_ERROR_INTERRUPT) + vlv_display_error_irq_ack(display, &eir, &dpinvgtt); + /* Call regardless, as some status bits might not be * signalled in IIR */ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); if (iir & (I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT)) - intel_lpe_audio_irq_handler(dev_priv); + intel_lpe_audio_irq_handler(display); /* * VLV_IIR is single buffered, and reflects the level @@ -280,6 +308,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) if (hotplug_status) i9xx_hpd_irq_handler(dev_priv, hotplug_status); + if (iir & I915_MASTER_ERROR_INTERRUPT) + vlv_display_error_irq_handler(display, eir, dpinvgtt); + valleyview_pipestat_irq_handler(dev_priv, pipe_stats); } while (0); @@ -293,6 +324,7 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) static irqreturn_t cherryview_irq_handler(int irq, void *arg) { struct drm_i915_private *dev_priv = arg; + struct intel_display *display = &dev_priv->display; irqreturn_t ret = IRQ_NONE; if (!intel_irqs_enabled(dev_priv)) @@ -303,6 +335,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) do { u32 master_ctl, iir; + u32 eir = 0, dpinvgtt = 0; u32 pipe_stats[I915_MAX_PIPES] = {}; u32 hotplug_status = 0; u32 ier = 0; @@ -336,6 +369,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) if (iir & I915_DISPLAY_PORT_INTERRUPT) hotplug_status = i9xx_hpd_irq_ack(dev_priv); + if (iir & I915_MASTER_ERROR_INTERRUPT) + vlv_display_error_irq_ack(display, &eir, &dpinvgtt); + /* Call regardless, as some status bits might not be * signalled in IIR */ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); @@ -343,7 +379,7 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) if (iir & (I915_LPE_PIPE_A_INTERRUPT | I915_LPE_PIPE_B_INTERRUPT | I915_LPE_PIPE_C_INTERRUPT)) - intel_lpe_audio_irq_handler(dev_priv); + intel_lpe_audio_irq_handler(display); /* * VLV_IIR is single buffered, and reflects the level @@ -358,6 +394,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) if (hotplug_status) i9xx_hpd_irq_handler(dev_priv, hotplug_status); + if (iir & I915_MASTER_ERROR_INTERRUPT) + vlv_display_error_irq_handler(display, eir, dpinvgtt); + valleyview_pipestat_irq_handler(dev_priv, pipe_stats); } while (0); @@ -813,10 +852,10 @@ static u32 i9xx_error_mask(struct drm_i915_private *i915) * so we just have to mask off all page table errors via EMR. */ if (HAS_FBC(i915)) - return ~I915_ERROR_MEMORY_REFRESH; + return I915_ERROR_MEMORY_REFRESH; else - return ~(I915_ERROR_PAGE_TABLE | - I915_ERROR_MEMORY_REFRESH); + return I915_ERROR_PAGE_TABLE | + I915_ERROR_MEMORY_REFRESH; } static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, @@ -865,6 +904,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv) i9xx_display_irq_reset(dev_priv); + gen2_error_reset(uncore, GEN2_ERROR_REGS); gen2_irq_reset(uncore, GEN2_IRQ_REGS); dev_priv->irq_mask = ~0u; } @@ -874,7 +914,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv) struct intel_uncore *uncore = &dev_priv->uncore; u32 enable_mask; - intel_uncore_write(uncore, EMR, i9xx_error_mask(dev_priv)); + gen2_error_init(uncore, GEN2_ERROR_REGS, ~i9xx_error_mask(dev_priv)); dev_priv->irq_mask = ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | @@ -970,6 +1010,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv) i9xx_display_irq_reset(dev_priv); + gen2_error_reset(uncore, GEN2_ERROR_REGS); gen2_irq_reset(uncore, GEN2_IRQ_REGS); dev_priv->irq_mask = ~0u; } @@ -984,13 +1025,13 @@ static u32 i965_error_mask(struct drm_i915_private *i915) * so we can always enable the page table errors. */ if (IS_G4X(i915)) - return ~(GM45_ERROR_PAGE_TABLE | - GM45_ERROR_MEM_PRIV | - GM45_ERROR_CP_PRIV | - I915_ERROR_MEMORY_REFRESH); + return GM45_ERROR_PAGE_TABLE | + GM45_ERROR_MEM_PRIV | + GM45_ERROR_CP_PRIV | + I915_ERROR_MEMORY_REFRESH; else - return ~(I915_ERROR_PAGE_TABLE | - I915_ERROR_MEMORY_REFRESH); + return I915_ERROR_PAGE_TABLE | + I915_ERROR_MEMORY_REFRESH; } static void i965_irq_postinstall(struct drm_i915_private *dev_priv) @@ -998,7 +1039,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv) struct intel_uncore *uncore = &dev_priv->uncore; u32 enable_mask; - intel_uncore_write(uncore, EMR, i965_error_mask(dev_priv)); + gen2_error_init(uncore, GEN2_ERROR_REGS, ~i965_error_mask(dev_priv)); dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | @@ -1231,7 +1272,7 @@ int intel_irq_install(struct drm_i915_private *dev_priv) } /** - * intel_irq_uninstall - finilizes all irq handling + * intel_irq_uninstall - finalizes all irq handling * @dev_priv: i915 device instance * * This stops interrupt and hotplug handling and unregisters and frees all diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h index 0457f6402e05..58789b264575 100644 --- a/drivers/gpu/drm/i915/i915_irq.h +++ b/drivers/gpu/drm/i915/i915_irq.h @@ -47,4 +47,8 @@ void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs); void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs, u32 imr_val, u32 ier_val); +void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs); +void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs, + u32 emr_val); + #endif /* __I915_IRQ_H__ */ diff --git a/drivers/gpu/drm/i915/i915_module.c b/drivers/gpu/drm/i915/i915_module.c index 7ed6d70389af..5862754c662c 100644 --- a/drivers/gpu/drm/i915/i915_module.c +++ b/drivers/gpu/drm/i915/i915_module.c @@ -24,7 +24,7 @@ static int i915_check_nomodeset(void) bool use_kms = true; /* - * Enable KMS by default, unless explicitly overriden by + * Enable KMS by default, unless explicitly overridden by * either the i915.modeset parameter or by the * nomodeset boot option. */ @@ -71,8 +71,6 @@ static const struct { { .init = i915_vma_resource_module_init, .exit = i915_vma_resource_module_exit }, { .init = i915_mock_selftests }, - { .init = i915_pmu_init, - .exit = i915_pmu_exit }, { .init = i915_pci_register_driver, .exit = i915_pci_unregister_driver }, { .init = i915_perf_sysctl_register, diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 5384d1bb4923..de0b413600a1 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -548,7 +548,8 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream) bool pollin; u32 partial_report_size; - /* We have to consider the (unlikely) possibility that read() errors + /* + * We have to consider the (unlikely) possibility that read() errors * could result in an OA buffer reset which might reset the head and * tail state. */ @@ -557,7 +558,8 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream) hw_tail = stream->perf->ops.oa_hw_tail_read(stream); hw_tail -= gtt_offset; - /* The tail pointer increases in 64 byte increments, not in report_size + /* + * The tail pointer increases in 64 byte increments, not in report_size * steps. Also the report size may not be a power of 2. Compute * potentially partially landed report in the OA buffer */ @@ -569,8 +571,9 @@ static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream) tail = hw_tail; - /* Walk the stream backward until we find a report with report - * id and timestmap not at 0. Since the circular buffer pointers + /* + * Walk the stream backward until we find a report with report + * id and timestamp not at 0. Since the circular buffer pointers * progress by increments of 64 bytes and that reports can be up * to 256 bytes long, we can't tell whether a report has fully * landed in memory before the report id and timestamp of the @@ -3359,9 +3362,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, "opening stream oa config uuid=%s\n", stream->oa_config->uuid); - hrtimer_init(&stream->poll_check_timer, - CLOCK_MONOTONIC, HRTIMER_MODE_REL); - stream->poll_check_timer.function = oa_poll_check_timer_cb; + hrtimer_setup(&stream->poll_check_timer, oa_poll_check_timer_cb, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); init_waitqueue_head(&stream->poll_wq); spin_lock_init(&stream->oa_buffer.ptr_lock); mutex_init(&stream->lock); @@ -3849,7 +3851,7 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf, } /* - * Asking for SSEU configuration is a priviliged operation. + * Asking for SSEU configuration is a privileged operation. */ if (props->has_sseu) privileged_op = true; @@ -4478,14 +4480,16 @@ static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr) static u32 mask_reg_value(u32 reg, u32 val) { - /* HALF_SLICE_CHICKEN2 is programmed with a the + /* + * HALF_SLICE_CHICKEN2 is programmed with a the * WaDisableSTUnitPowerOptimization workaround. Make sure the value * programmed by userspace doesn't change this. */ if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2)) val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE); - /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function + /* + * WAIT_FOR_RC6_EXIT has only one bit fulfilling the function * indicated by its name and a bunch of selection fields used by OA * configs. */ diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index e55db036be1b..e5a188ce3185 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -28,9 +28,6 @@ BIT(I915_SAMPLE_WAIT) | \ BIT(I915_SAMPLE_SEMA)) -static cpumask_t i915_pmu_cpumask; -static unsigned int i915_pmu_target_cpu = -1; - static struct i915_pmu *event_to_pmu(struct perf_event *event) { return container_of(event->pmu, struct i915_pmu, base); @@ -642,10 +639,6 @@ static int i915_pmu_event_init(struct perf_event *event) if (event->cpu < 0) return -EINVAL; - /* only allow running on one cpu at a time */ - if (!cpumask_test_cpu(event->cpu, &i915_pmu_cpumask)) - return -EINVAL; - if (is_engine_event(event)) ret = engine_event_init(event); else @@ -891,11 +884,6 @@ static void i915_pmu_event_del(struct perf_event *event, int flags) i915_pmu_event_stop(event, PERF_EF_UPDATE); } -static int i915_pmu_event_event_idx(struct perf_event *event) -{ - return 0; -} - struct i915_str_attribute { struct device_attribute attr; const char *str; @@ -940,23 +928,6 @@ static ssize_t i915_pmu_event_show(struct device *dev, return sprintf(buf, "config=0x%lx\n", eattr->val); } -static ssize_t cpumask_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - return cpumap_print_to_pagebuf(true, buf, &i915_pmu_cpumask); -} - -static DEVICE_ATTR_RO(cpumask); - -static struct attribute *i915_cpumask_attrs[] = { - &dev_attr_cpumask.attr, - NULL, -}; - -static const struct attribute_group i915_pmu_cpumask_attr_group = { - .attrs = i915_cpumask_attrs, -}; - #define __event(__counter, __name, __unit) \ { \ .counter = (__counter), \ @@ -1173,100 +1144,18 @@ static void free_event_attributes(struct i915_pmu *pmu) pmu->pmu_attr = NULL; } -static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node) -{ - struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node); - - /* Select the first online CPU as a designated reader. */ - if (cpumask_empty(&i915_pmu_cpumask)) - cpumask_set_cpu(cpu, &i915_pmu_cpumask); - - return 0; -} - -static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node) -{ - struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node); - unsigned int target = i915_pmu_target_cpu; - - /* - * Unregistering an instance generates a CPU offline event which we must - * ignore to avoid incorrectly modifying the shared i915_pmu_cpumask. - */ - if (!pmu->registered) - return 0; - - if (cpumask_test_and_clear_cpu(cpu, &i915_pmu_cpumask)) { - target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu); - - /* Migrate events if there is a valid target */ - if (target < nr_cpu_ids) { - cpumask_set_cpu(target, &i915_pmu_cpumask); - i915_pmu_target_cpu = target; - } - } - - if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) { - perf_pmu_migrate_context(&pmu->base, cpu, target); - pmu->cpuhp.cpu = target; - } - - return 0; -} - -static enum cpuhp_state cpuhp_state = CPUHP_INVALID; - -int i915_pmu_init(void) -{ - int ret; - - ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, - "perf/x86/intel/i915:online", - i915_pmu_cpu_online, - i915_pmu_cpu_offline); - if (ret < 0) - pr_notice("Failed to setup cpuhp state for i915 PMU! (%d)\n", - ret); - else - cpuhp_state = ret; - - return 0; -} - -void i915_pmu_exit(void) -{ - if (cpuhp_state != CPUHP_INVALID) - cpuhp_remove_multi_state(cpuhp_state); -} - -static int i915_pmu_register_cpuhp_state(struct i915_pmu *pmu) -{ - if (cpuhp_state == CPUHP_INVALID) - return -EINVAL; - - return cpuhp_state_add_instance(cpuhp_state, &pmu->cpuhp.node); -} - -static void i915_pmu_unregister_cpuhp_state(struct i915_pmu *pmu) -{ - cpuhp_state_remove_instance(cpuhp_state, &pmu->cpuhp.node); -} - void i915_pmu_register(struct drm_i915_private *i915) { struct i915_pmu *pmu = &i915->pmu; const struct attribute_group *attr_groups[] = { &i915_pmu_format_attr_group, &pmu->events_attr_group, - &i915_pmu_cpumask_attr_group, NULL }; int ret = -ENOMEM; spin_lock_init(&pmu->lock); - hrtimer_init(&pmu->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - pmu->timer.function = i915_sample; - pmu->cpuhp.cpu = -1; + hrtimer_setup(&pmu->timer, i915_sample, CLOCK_MONOTONIC, HRTIMER_MODE_REL); init_rc6(pmu); if (IS_DGFX(i915)) { @@ -1295,28 +1184,22 @@ void i915_pmu_register(struct drm_i915_private *i915) pmu->base.module = THIS_MODULE; pmu->base.task_ctx_nr = perf_invalid_context; + pmu->base.scope = PERF_PMU_SCOPE_SYS_WIDE; pmu->base.event_init = i915_pmu_event_init; pmu->base.add = i915_pmu_event_add; pmu->base.del = i915_pmu_event_del; pmu->base.start = i915_pmu_event_start; pmu->base.stop = i915_pmu_event_stop; pmu->base.read = i915_pmu_event_read; - pmu->base.event_idx = i915_pmu_event_event_idx; ret = perf_pmu_register(&pmu->base, pmu->name, -1); if (ret) goto err_groups; - ret = i915_pmu_register_cpuhp_state(pmu); - if (ret) - goto err_unreg; - pmu->registered = true; return; -err_unreg: - perf_pmu_unregister(&pmu->base); err_groups: kfree(pmu->base.attr_groups); err_attr: @@ -1340,8 +1223,6 @@ void i915_pmu_unregister(struct drm_i915_private *i915) hrtimer_cancel(&pmu->timer); - i915_pmu_unregister_cpuhp_state(pmu); - perf_pmu_unregister(&pmu->base); kfree(pmu->base.attr_groups); if (IS_DGFX(i915)) diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h index 8e66d63d0c9f..5826cc81858c 100644 --- a/drivers/gpu/drm/i915/i915_pmu.h +++ b/drivers/gpu/drm/i915/i915_pmu.h @@ -57,13 +57,6 @@ struct i915_pmu_sample { struct i915_pmu { /** - * @cpuhp: Struct used for CPU hotplug handling. - */ - struct { - struct hlist_node node; - unsigned int cpu; - } cpuhp; - /** * @base: PMU base. */ struct pmu base; @@ -103,7 +96,7 @@ struct i915_pmu { /** * @timer_last: * - * Timestmap of the previous timer invocation. + * Timestamp of the previous timer invocation. */ ktime_t timer_last; @@ -155,15 +148,11 @@ struct i915_pmu { }; #ifdef CONFIG_PERF_EVENTS -int i915_pmu_init(void); -void i915_pmu_exit(void); void i915_pmu_register(struct drm_i915_private *i915); void i915_pmu_unregister(struct drm_i915_private *i915); void i915_pmu_gt_parked(struct intel_gt *gt); void i915_pmu_gt_unparked(struct intel_gt *gt); #else -static inline int i915_pmu_init(void) { return 0; } -static inline void i915_pmu_exit(void) {} static inline void i915_pmu_register(struct drm_i915_private *i915) {} static inline void i915_pmu_unregister(struct drm_i915_private *i915) {} static inline void i915_pmu_gt_parked(struct intel_gt *gt) {} diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 765e6c0528fb..c5064eebe063 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -84,7 +84,7 @@ * Try to name registers according to the specs. If the register name changes in * the specs from platform to another, stick to the original name. * - * Try to re-use existing register macro definitions. Only add new macros for + * Try to reuse existing register macro definitions. Only add new macros for * new register offsets, or when the register contents have changed enough to * warrant a full redefinition. * @@ -372,8 +372,29 @@ #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070) #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074) +#define ILK_GTT_FAULT _MMIO(0x44040) /* ilk/snb */ +#define GTT_FAULT_INVALID_GTT_PTE (1 << 7) +#define GTT_FAULT_INVALID_PTE_DATA (1 << 6) +#define GTT_FAULT_CURSOR_B_FAULT (1 << 5) +#define GTT_FAULT_CURSOR_A_FAULT (1 << 4) +#define GTT_FAULT_SPRITE_B_FAULT (1 << 3) +#define GTT_FAULT_SPRITE_A_FAULT (1 << 2) +#define GTT_FAULT_PRIMARY_B_FAULT (1 << 1) +#define GTT_FAULT_PRIMARY_A_FAULT (1 << 0) + #define GEN7_ERR_INT _MMIO(0x44040) #define ERR_INT_POISON (1 << 31) +#define ERR_INT_INVALID_GTT_PTE (1 << 29) +#define ERR_INT_INVALID_PTE_DATA (1 << 28) +#define ERR_INT_SPRITE_C_FAULT (1 << 23) +#define ERR_INT_PRIMARY_C_FAULT (1 << 22) +#define ERR_INT_CURSOR_C_FAULT (1 << 21) +#define ERR_INT_SPRITE_B_FAULT (1 << 20) +#define ERR_INT_PRIMARY_B_FAULT (1 << 19) +#define ERR_INT_CURSOR_B_FAULT (1 << 18) +#define ERR_INT_SPRITE_A_FAULT (1 << 17) +#define ERR_INT_PRIMARY_A_FAULT (1 << 16) +#define ERR_INT_CURSOR_A_FAULT (1 << 15) #define ERR_INT_MMIO_UNCLAIMED (1 << 13) #define ERR_INT_PIPE_CRC_DONE_C (1 << 8) #define ERR_INT_FIFO_UNDERRUN_C (1 << 6) @@ -451,6 +472,19 @@ #define GM45_ERROR_CP_PRIV (1 << 3) #define I915_ERROR_MEMORY_REFRESH (1 << 1) #define I915_ERROR_INSTRUCTION (1 << 0) + +#define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR) + +#define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0) +#define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4) +#define VLV_ESR _MMIO(VLV_DISPLAY_BASE + 0x20b8) +#define VLV_ERROR_GUNIT_TLB_DATA (1 << 6) +#define VLV_ERROR_GUNIT_TLB_PTE (1 << 5) +#define VLV_ERROR_PAGE_TABLE (1 << 4) +#define VLV_ERROR_CLAIM (1 << 0) + +#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR) + #define INSTPM _MMIO(0x20c0) #define INSTPM_SELF_EN (1 << 12) /* 915GM only */ #define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts @@ -492,8 +526,9 @@ #define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) #define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) -/* Make render/texture TLB fetches lower priorty than associated data - * fetches. This is not turned on by default +/* + * Make render/texture TLB fetches lower priority than associated data + * fetches. This is not turned on by default. */ #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) @@ -1350,38 +1385,6 @@ /* ADL and later: */ #define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23) -/* Panel fitting */ -#define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) -#define PFIT_ENABLE REG_BIT(31) -#define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */ -#define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe)) -#define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */ -#define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0) -#define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1) -#define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2) -#define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3) -#define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */ -#define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0) -#define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1) -#define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2) -#define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */ -#define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1) -#define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */ -#define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */ -#define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1) -#define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */ -#define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */ - -#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) -#define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */ -#define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x)) -#define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */ -#define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x)) -#define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */ -#define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */ - -#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) - #define PCH_GTC_CTL _MMIO(0xe7000) #define PCH_GTC_ENABLE (1 << 31) @@ -1876,44 +1879,6 @@ #define _PIPEB_LINK_N2 0x6104c #define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) -/* CPU panel fitter */ -/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ -#define _PFA_CTL_1 0x68080 -#define _PFB_CTL_1 0x68880 -#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) -#define PF_ENABLE REG_BIT(31) -#define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */ -#define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe)) -#define PF_FILTER_MASK REG_GENMASK(24, 23) -#define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0) -#define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1) -#define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2) -#define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3) - -#define _PFA_WIN_SZ 0x68074 -#define _PFB_WIN_SZ 0x68874 -#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) -#define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16) -#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w)) -#define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0) -#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h)) - -#define _PFA_WIN_POS 0x68070 -#define _PFB_WIN_POS 0x68870 -#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) -#define PF_WIN_XPOS_MASK REG_GENMASK(31, 16) -#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x)) -#define PF_WIN_YPOS_MASK REG_GENMASK(15, 0) -#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y)) - -#define _PFA_VSCALE 0x68084 -#define _PFB_VSCALE 0x68884 -#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) - -#define _PFA_HSCALE 0x68090 -#define _PFB_HSCALE 0x68890 -#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) - /* * Skylake scalers */ @@ -3197,6 +3162,10 @@ #define _TRANS_DP2_VFREQLOW_D 0x630a8 #define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B) +#define _DP_MIN_HBLANK_CTL_A 0x600ac +#define _DP_MIN_HBLANK_CTL_B 0x610ac +#define DP_MIN_HBLANK_CTL(trans) _MMIO_TRANS(trans, _DP_MIN_HBLANK_CTL_A, _DP_MIN_HBLANK_CTL_B) + /* SNB eDP training params */ /* SNB A-stepping */ #define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) @@ -3565,6 +3534,7 @@ enum skl_power_gate { #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 #define TRANS_DDI_FUNC_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A) #define PORT_SYNC_MODE_ENABLE REG_BIT(4) +#define CMTG_SECONDARY_MODE REG_BIT(3) #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) @@ -3619,24 +3589,29 @@ enum skl_power_gate { #define _DDI_BUF_CTL_B 0x64100 /* Known as DDI_CTL_DE in MTL+ */ #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) -#define DDI_BUF_CTL_ENABLE (1 << 31) +#define DDI_BUF_CTL_ENABLE REG_BIT(31) #define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29) #define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28) -#define DDI_BUF_TRANS_SELECT(n) ((n) << 24) -#define DDI_BUF_EMP_MASK (0xf << 24) -#define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) +#define DDI_BUF_EMP_MASK REG_GENMASK(27, 24) +#define DDI_BUF_TRANS_SELECT(n) REG_FIELD_PREP(DDI_BUF_EMP_MASK, (n)) +#define DDI_BUF_PHY_LINK_RATE_MASK REG_GENMASK(23, 20) +#define DDI_BUF_PHY_LINK_RATE(r) REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, (r)) #define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18) #define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0) #define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1) #define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2) -#define DDI_BUF_PORT_REVERSAL (1 << 16) -#define DDI_BUF_IS_IDLE (1 << 7) +#define DDI_BUF_PORT_REVERSAL REG_BIT(16) +#define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8) +#define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \ + (symbols)) +#define DDI_BUF_IS_IDLE REG_BIT(7) #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) -#define DDI_A_4_LANES (1 << 4) -#define DDI_PORT_WIDTH(width) (((width) - 1) << 1) -#define DDI_PORT_WIDTH_MASK (7 << 1) +#define DDI_A_4_LANES REG_BIT(4) +#define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) +#define DDI_PORT_WIDTH(width) REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \ + ((width) == 3 ? 4 : (width) - 1)) #define DDI_PORT_WIDTH_SHIFT 1 -#define DDI_INIT_DISPLAY_DETECTED (1 << 0) +#define DDI_INIT_DISPLAY_DETECTED REG_BIT(0) /* DDI Buffer Translations */ #define _DDI_BUF_TRANS_A 0x64E00 @@ -4190,8 +4165,8 @@ enum skl_power_gate { _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B) #define _VLV_PIPE_MSA_MISC_A 0x70048 -#define VLV_PIPE_MSA_MISC(pipe) \ - _MMIO_PIPE2(dev_priv, pipe, _VLV_PIPE_MSA_MISC_A) +#define VLV_PIPE_MSA_MISC(__display, pipe) \ + _MMIO_PIPE2(__display, pipe, _VLV_PIPE_MSA_MISC_A) #define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31) #define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */ diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h index e251bcc0c89f..94a8f902689e 100644 --- a/drivers/gpu/drm/i915/i915_reg_defs.h +++ b/drivers/gpu/drm/i915/i915_reg_defs.h @@ -294,4 +294,12 @@ struct i915_irq_regs { #define I915_IRQ_REGS(_imr, _ier, _iir) \ ((const struct i915_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) }) +struct i915_error_regs { + i915_reg_t emr; + i915_reg_t eir; +}; + +#define I915_ERROR_REGS(_emr, _eir) \ + ((const struct i915_error_regs){ .emr = (_emr), .eir = (_eir) }) + #endif /* __I915_REG_DEFS__ */ diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 8f62cfa23fb7..c3d27eadc0a7 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -293,8 +293,7 @@ static void __rq_init_watchdog(struct i915_request *rq) { struct i915_request_watchdog *wdg = &rq->watchdog; - hrtimer_init(&wdg->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - wdg->timer.function = __rq_watchdog_expired; + hrtimer_setup(&wdg->timer, __rq_watchdog_expired, CLOCK_MONOTONIC, HRTIMER_MODE_REL); } static void __rq_arm_watchdog(struct i915_request *rq) @@ -473,7 +472,7 @@ static bool __request_in_flight(const struct i915_request *signal) * to avoid tearing.] * * Note that the read of *execlists->active may race with the promotion - * of execlists->pending[] to execlists->inflight[], overwritting + * of execlists->pending[] to execlists->inflight[], overwriting * the value at *execlists->active. This is fine. The promotion implies * that we received an ACK from the HW, and so the context is not * stuck -- if we do not see ourselves in *active, the inflight status diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h index 0ac55b2e4223..5f7e8138ec14 100644 --- a/drivers/gpu/drm/i915/i915_request.h +++ b/drivers/gpu/drm/i915/i915_request.h @@ -161,7 +161,7 @@ enum { * parent-child relationship (parallel submission, multi-lrc) that * hit an error while generating requests in the execbuf IOCTL. * Indicates this request should be skipped as another request in - * submission / relationship encoutered an error. + * submission / relationship encountered an error. */ I915_FENCE_FLAG_SKIP_PARALLEL, @@ -187,7 +187,7 @@ enum { * RCU lookup of it that may race against reallocation of the struct * from the slab freelist. We intentionally do not zero the structure on * allocation so that the lookup can use the dangling pointers (and is - * cogniscent that those pointers may be wrong). Instead, everything that + * cognisant that those pointers may be wrong). Instead, everything that * needs to be initialised must be done so explicitly. * * The requests are reference counted. diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index 8775beab9cb8..f936e8f1f129 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -60,7 +60,7 @@ static int l3_access_valid(struct drm_i915_private *i915, loff_t offset) static ssize_t i915_l3_read(struct file *filp, struct kobject *kobj, - struct bin_attribute *attr, char *buf, + const struct bin_attribute *attr, char *buf, loff_t offset, size_t count) { struct device *kdev = kobj_to_dev(kobj); @@ -88,7 +88,7 @@ i915_l3_read(struct file *filp, struct kobject *kobj, static ssize_t i915_l3_write(struct file *filp, struct kobject *kobj, - struct bin_attribute *attr, char *buf, + const struct bin_attribute *attr, char *buf, loff_t offset, size_t count) { struct device *kdev = kobj_to_dev(kobj); @@ -140,8 +140,8 @@ i915_l3_write(struct file *filp, struct kobject *kobj, static const struct bin_attribute dpf_attrs = { .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)}, .size = GEN7_L3LOG_SIZE, - .read = i915_l3_read, - .write = i915_l3_write, + .read_new = i915_l3_read, + .write_new = i915_l3_write, .mmap = NULL, .private = (void *)0 }; @@ -149,8 +149,8 @@ static const struct bin_attribute dpf_attrs = { static const struct bin_attribute dpf_attrs_1 = { .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)}, .size = GEN7_L3LOG_SIZE, - .read = i915_l3_read, - .write = i915_l3_write, + .read_new = i915_l3_read, + .write_new = i915_l3_write, .mmap = NULL, .private = (void *)1 }; diff --git a/drivers/gpu/drm/i915/i915_utils.c b/drivers/gpu/drm/i915/i915_utils.c index 2576f8f6c0f6..b60c28fbd207 100644 --- a/drivers/gpu/drm/i915/i915_utils.c +++ b/drivers/gpu/drm/i915/i915_utils.c @@ -52,7 +52,7 @@ void cancel_timer(struct timer_list *t) if (!timer_active(t)) return; - del_timer(t); + timer_delete(t); WRITE_ONCE(t->expires, 0); } diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 776f8cc51b2f..632e316f8b05 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -26,7 +26,7 @@ #include <linux/dma-fence-array.h> #include <drm/drm_gem.h> -#include "display/intel_display.h" +#include "display/intel_fb.h" #include "display/intel_frontbuffer.h" #include "gem/i915_gem_lmem.h" #include "gem/i915_gem_object_frontbuffer.h" @@ -778,8 +778,8 @@ bool i915_gem_valid_gtt_space(struct i915_vma *vma, unsigned long color) * @flags: mask of PIN_* flags to use * * First we try to allocate some free space that meets the requirements for - * the VMA. Failiing that, if the flags permit, it will evict an old VMA, - * preferrably the oldest idle entry to make room for the new VMA. + * the VMA. Failing that, if the flags permit, it will evict an old VMA, + * preferably the oldest idle entry to make room for the new VMA. * * Returns: * 0 on success, negative error code otherwise. @@ -877,7 +877,7 @@ i915_vma_insert(struct i915_vma *vma, struct i915_gem_ww_ctx *ww, * objects which need to be tightly packed into the low 32bits. * * Note that we assume that GGTT are limited to 4GiB for the - * forseeable future. See also i915_ggtt_offset(). + * foreseeable future. See also i915_ggtt_offset(). */ if (upper_32_bits(end - 1) && vma->page_sizes.sg > I915_GTT_PAGE_SIZE && @@ -1001,7 +1001,7 @@ rotate_pages(struct drm_i915_gem_object *obj, unsigned int offset, /* * The DE ignores the PTEs for the padding tiles, the sg entry - * here is just a conenience to indicate how many padding PTEs + * here is just a convenience to indicate how many padding PTEs * to insert at this spot. */ sg_set_page(sg, NULL, left, 0); diff --git a/drivers/gpu/drm/i915/i915_vma_types.h b/drivers/gpu/drm/i915/i915_vma_types.h index 559de74d0b11..a499a3bea874 100644 --- a/drivers/gpu/drm/i915/i915_vma_types.h +++ b/drivers/gpu/drm/i915/i915_vma_types.h @@ -32,6 +32,8 @@ #include "gem/i915_gem_object_types.h" +#include "i915_gtt_view_types.h" + /** * DOC: Global GTT views * @@ -95,46 +97,6 @@ struct i915_vma_resource; -struct intel_remapped_plane_info { - /* in gtt pages */ - u32 offset:31; - u32 linear:1; - union { - /* in gtt pages for !linear */ - struct { - u16 width; - u16 height; - u16 src_stride; - u16 dst_stride; - }; - - /* in gtt pages for linear */ - u32 size; - }; -} __packed; - -struct intel_remapped_info { - struct intel_remapped_plane_info plane[4]; - /* in gtt pages */ - u32 plane_alignment; -} __packed; - -struct intel_rotation_info { - struct intel_remapped_plane_info plane[2]; -} __packed; - -struct intel_partial_info { - u64 offset; - unsigned int size; -} __packed; - -enum i915_gtt_view_type { - I915_GTT_VIEW_NORMAL = 0, - I915_GTT_VIEW_ROTATED = sizeof(struct intel_rotation_info), - I915_GTT_VIEW_PARTIAL = sizeof(struct intel_partial_info), - I915_GTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info), -}; - static inline void assert_i915_gem_gtt_types(void) { BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 2 * sizeof(u32) + 8 * sizeof(u16)); @@ -160,16 +122,6 @@ static inline void assert_i915_gem_gtt_types(void) } } -struct i915_gtt_view { - enum i915_gtt_view_type type; - union { - /* Members need to contain no holes/padding */ - struct intel_partial_info partial; - struct intel_rotation_info rotated; - struct intel_remapped_info remapped; - }; -}; - /** * DOC: Virtual Memory Address * diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index f76642886569..387b26400169 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -682,7 +682,7 @@ static void i85x_init_clock_gating(struct drm_i915_private *i915) * Have FBC ignore 3D activity since we use software * render tracking, and otherwise a pure 3D workload * (even if it just renders a single frame and then does - * abosultely nothing) would not allow FBC to recompress + * absolutely nothing) would not allow FBC to recompress * until a 2D blit occurs. */ intel_uncore_write(&i915->uncore, SCPD0, diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c index a5383a2bc64b..dae9dce7d1b3 100644 --- a/drivers/gpu/drm/i915/intel_gvt.c +++ b/drivers/gpu/drm/i915/intel_gvt.c @@ -265,7 +265,7 @@ void intel_gvt_driver_remove(struct drm_i915_private *dev_priv) } /** - * intel_gvt_resume - GVT resume routine wapper + * intel_gvt_resume - GVT resume routine wrapper * * @dev_priv: drm i915 private * * diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index ee1cd2126f97..76d84cbb8361 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -18,6 +18,7 @@ #include "display/intel_fbc_regs.h" #include "display/intel_fdi_regs.h" #include "display/intel_lvds_regs.h" +#include "display/intel_pfit_regs.h" #include "display/intel_psr_regs.h" #include "display/intel_sprite_regs.h" #include "display/skl_universal_plane_regs.h" @@ -1260,7 +1261,7 @@ static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter) /** * intel_gvt_iterate_mmio_table - Iterate the GVT MMIO table - * @iter: the interator + * @iter: the iterator * * This function is called for iterating the GVT MMIO table when i915 is * taking the snapshot of the HW and GVT is building MMIO tracking table. diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 1a47ecfd3fd8..8d9f4c410546 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -375,7 +375,7 @@ void intel_runtime_pm_enable(struct intel_runtime_pm *rpm) * leave the device suspended skipping the driver's suspend handlers * if the device was already runtime suspended. This is needed due to * the difference in our runtime and system suspend sequence and - * becaue the HDA driver may require us to enable the audio power + * because the HDA driver may require us to enable the audio power * domain during system suspend. */ dev_pm_set_driver_flags(kdev, DPM_FLAG_NO_DIRECT_COMPLETE); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h b/drivers/gpu/drm/i915/intel_runtime_pm.h index e22669d61e95..7428bd8fa67f 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.h +++ b/drivers/gpu/drm/i915/intel_runtime_pm.h @@ -31,7 +31,7 @@ struct drm_printer; * it can be changed with the standard runtime PM files from sysfs. * * The irqs_disabled variable becomes true exactly after we disable the IRQs and - * goes back to false exactly before we reenable the IRQs. We use this variable + * goes back to false exactly before we re-enable the IRQs. We use this variable * to check if someone is trying to enable/disable IRQs while they're supposed * to be disabled. This shouldn't happen and we'll print some error messages in * case it happens. diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index eed4937c3ff3..48a10ff80148 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -2103,8 +2103,7 @@ static int __fw_domain_init(struct intel_uncore *uncore, d->mask = BIT(domain_id); - hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); - d->timer.function = intel_uncore_fw_release_timer; + hrtimer_setup(&d->timer, intel_uncore_fw_release_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); uncore->fw_domains |= BIT(domain_id); @@ -2477,7 +2476,7 @@ static int sanity_check_mmio_access(struct intel_uncore *uncore) /* * Sanitycheck that MMIO access to the device is working properly. If - * the CPU is unable to communcate with a PCI device, BAR reads will + * the CPU is unable to communicate with a PCI device, BAR reads will * return 0xFFFFFFFF. Let's make sure the device isn't in this state * before we start trying to access registers. * diff --git a/drivers/gpu/drm/i915/intel_wakeref.c b/drivers/gpu/drm/i915/intel_wakeref.c index 87f246047312..07e81be4d392 100644 --- a/drivers/gpu/drm/i915/intel_wakeref.c +++ b/drivers/gpu/drm/i915/intel_wakeref.c @@ -163,7 +163,7 @@ void intel_wakeref_auto(struct intel_wakeref_auto *wf, unsigned long timeout) unsigned long flags; if (!timeout) { - if (del_timer_sync(&wf->timer)) + if (timer_delete_sync(&wf->timer)) wakeref_auto_timeout(&wf->timer); return; } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c index 9cf169665d7c..f8da693ad3ce 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c @@ -460,11 +460,11 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp) intel_pxp_irq_disable(pxp); } -int intel_pxp_key_check(struct intel_pxp *pxp, - struct drm_gem_object *_obj, - bool assign) +int intel_pxp_key_check(struct drm_gem_object *_obj, bool assign) { struct drm_i915_gem_object *obj = to_intel_bo(_obj); + struct drm_i915_private *i915 = to_i915(_obj->dev); + struct intel_pxp *pxp = i915->pxp; if (!intel_pxp_is_active(pxp)) return -ENODEV; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h index 4ed97db5e7c6..7b19109845a3 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h @@ -31,9 +31,7 @@ int intel_pxp_get_backend_timeout_ms(struct intel_pxp *pxp); int intel_pxp_start(struct intel_pxp *pxp); void intel_pxp_end(struct intel_pxp *pxp); -int intel_pxp_key_check(struct intel_pxp *pxp, - struct drm_gem_object *obj, - bool assign); +int intel_pxp_key_check(struct drm_gem_object *obj, bool assign); void intel_pxp_invalidate(struct intel_pxp *pxp); diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h index 329b4fcdc040..929c20e98300 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h @@ -41,7 +41,7 @@ struct pxp43_huc_auth_out { /* PXP-Input-Packet: Init PXP session */ struct pxp43_create_arb_in { struct pxp_cmd_header header; - /* header.stream_id fields for vesion 4.3 of Init PXP session: */ + /* header.stream_id fields for version 4.3 of Init PXP session: */ #define PXP43_INIT_SESSION_VALID BIT(0) #define PXP43_INIT_SESSION_APPTYPE BIT(1) #define PXP43_INIT_SESSION_APPID GENMASK(17, 2) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h index 07864b584cf4..febdbcd8d61e 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h @@ -21,7 +21,7 @@ struct drm_i915_private; */ struct intel_pxp { /** - * @ctrl_gt: poiner to the tile that owns the controls for PXP subsystem assets that + * @ctrl_gt: pointer to the tile that owns the controls for PXP subsystem assets that * the VDBOX, the KCR engine (and GSC CS depending on the platform) */ struct intel_gt *ctrl_gt; diff --git a/drivers/gpu/drm/i915/selftests/i915_gem.c b/drivers/gpu/drm/i915/selftests/i915_gem.c index 0727492576be..ad650f67114a 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem.c @@ -45,13 +45,15 @@ static void trash_stolen(struct drm_i915_private *i915) struct i915_ggtt *ggtt = to_gt(i915)->ggtt; const u64 slot = ggtt->error_capture.start; const resource_size_t size = resource_size(&i915->dsm.stolen); + struct rnd_state prng; unsigned long page; - u32 prng = 0x12345678; /* XXX: fsck. needs some more thought... */ if (!i915_ggtt_has_aperture(ggtt)) return; + prandom_seed_state(&prng, 0x12345678); + for (page = 0; page < size; page += PAGE_SIZE) { const dma_addr_t dma = i915->dsm.stolen.start + page; u32 __iomem *s; @@ -64,8 +66,7 @@ static void trash_stolen(struct drm_i915_private *i915) s = io_mapping_map_atomic_wc(&ggtt->iomap, slot); for (x = 0; x < PAGE_SIZE / sizeof(u32); x++) { - prng = next_pseudo_random32(prng); - iowrite32(prng, &s[x]); + iowrite32(prandom_u32_state(&prng), &s[x]); } io_mapping_unmap_atomic(s); } @@ -80,7 +81,7 @@ static void simulate_hibernate(struct drm_i915_private *i915) wakeref = intel_runtime_pm_get(&i915->runtime_pm); /* - * As a final sting in the tail, invalidate stolen. Under a real S4, + * As a final string in the tail, invalidate stolen. Under a real S4, * stolen is lost and needs to be refilled on resume. However, under * CI we merely do S4-device testing (as full S4 is too unreliable * for automated testing across a cluster), so to simulate the effect diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c index 5c397a2df70e..7ab4c4e60264 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c @@ -168,7 +168,7 @@ static int igt_ppgtt_alloc(void *arg) return PTR_ERR(ppgtt); if (!ppgtt->vm.allocate_va_range) - goto err_ppgtt_cleanup; + goto ppgtt_vm_put; /* * While we only allocate the page tables here and so we could @@ -236,7 +236,7 @@ err_ppgtt_cleanup: goto retry; } i915_gem_ww_ctx_fini(&ww); - +ppgtt_vm_put: i915_vm_put(&ppgtt->vm); return err; } @@ -287,7 +287,8 @@ static int lowlevel_hole(struct i915_address_space *vm, GEM_BUG_ON(count * BIT_ULL(aligned_size) > vm->total); GEM_BUG_ON(hole_start + count * BIT_ULL(aligned_size) > hole_end); - /* Ignore allocation failures (i.e. don't report them as + /* + * Ignore allocation failures (i.e. don't report them as * a test failure) as we are purposefully allocating very * large objects without checking that we have sufficient * memory. We expect to hit -ENOMEM. @@ -446,7 +447,8 @@ static int fill_hole(struct i915_address_space *vm, list_add(&obj->st_link, &objects); - /* Align differing sized objects against the edges, and + /* + * Align differing sized objects against the edges, and * check we don't walk off into the void when binding * them into the GTT. */ @@ -831,7 +833,8 @@ static int drunk_hole(struct i915_address_space *vm, return -ENOMEM; GEM_BUG_ON(!order); - /* Ignore allocation failures (i.e. don't report them as + /* + * Ignore allocation failures (i.e. don't report them as * a test failure) as we are purposefully allocating very * large objects without checking that we have sufficient * memory. We expect to hit -ENOMEM. @@ -964,7 +967,7 @@ static int __shrink_hole(struct i915_address_space *vm, break; if (igt_timeout(end_time, - "%s timed out at ofset %llx [%llx - %llx]\n", + "%s timed out at offset %llx [%llx - %llx]\n", __func__, addr, hole_start, hole_end)) { err = -EINTR; break; @@ -1011,7 +1014,7 @@ static int shrink_boom(struct i915_address_space *vm, /* * Catch the case which shrink_hole seems to miss. The setup here * requires invoking the shrinker as we do the alloc_pt/alloc_pd, while - * ensuring that all vma assiocated with the respective pd/pdp are + * ensuring that all vma associated with the respective pd/pdp are * unpinned at the time. */ @@ -1537,9 +1540,10 @@ static int igt_gtt_reserve(void *arg) u64 total; int err = -ENODEV; - /* i915_gem_gtt_reserve() tries to reserve the precise range + /* + * i915_gem_gtt_reserve() tries to reserve the precise range * for the node, and evicts if it has to. So our test checks that - * it can give us the requsted space and prevent overlaps. + * it can give us the requested space and prevent overlaps. */ /* Start by filling the GGTT */ @@ -1743,7 +1747,8 @@ static int igt_gtt_insert(void *arg) u64 total; int err = -ENODEV; - /* i915_gem_gtt_insert() tries to allocate some free space in the GTT + /* + * i915_gem_gtt_insert() tries to allocate some free space in the GTT * to the node, evicting if required. */ diff --git a/drivers/gpu/drm/i915/selftests/i915_selftest.c b/drivers/gpu/drm/i915/selftests/i915_selftest.c index fee76c1d2f45..889281819c5b 100644 --- a/drivers/gpu/drm/i915/selftests/i915_selftest.c +++ b/drivers/gpu/drm/i915/selftests/i915_selftest.c @@ -23,7 +23,9 @@ #include <linux/random.h> +#include "gt/intel_gt.h" #include "gt/intel_gt_pm.h" +#include "gt/intel_gt_regs.h" #include "gt/uc/intel_gsc_fw.h" #include "i915_driver.h" @@ -253,11 +255,27 @@ int i915_mock_selftests(void) int i915_live_selftests(struct pci_dev *pdev) { struct drm_i915_private *i915 = pdev_to_i915(pdev); + struct intel_uncore *uncore = &i915->uncore; int err; + u32 pg_enable; + intel_wakeref_t wakeref; if (!i915_selftest.live) return 0; + /* + * FIXME Disable render powergating, this is temporary wa and should be removed + * after fixing real cause of forcewake timeouts. + */ + with_intel_runtime_pm(uncore->rpm, wakeref) { + if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 00), IP_VER(12, 74))) { + pg_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE); + if (pg_enable & GEN9_RENDER_PG_ENABLE) + intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, + pg_enable & ~GEN9_RENDER_PG_ENABLE); + } + } + __wait_gsc_proxy_completed(i915); __wait_gsc_huc_load_completed(i915); diff --git a/drivers/gpu/drm/i915/selftests/i915_vma.c b/drivers/gpu/drm/i915/selftests/i915_vma.c index 71b52d5efef4..7c4111e60f2e 100644 --- a/drivers/gpu/drm/i915/selftests/i915_vma.c +++ b/drivers/gpu/drm/i915/selftests/i915_vma.c @@ -159,7 +159,8 @@ static int igt_vma_create(void *arg) LIST_HEAD(objects); int err = -ENOMEM; - /* Exercise creating many vma amonst many objections, checking the + /* + * Exercise creating many vma amongst many objections, checking the * vma creation and lookup routines. */ @@ -292,7 +293,8 @@ static int igt_vma_pin1(void *arg) VALID(8192, PIN_GLOBAL | PIN_OFFSET_BIAS | (ggtt->mappable_end - 4096)), #if !IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) - /* Misusing BIAS is a programming error (it is not controllable + /* + * Misusing BIAS is a programming error (it is not controllable * from userspace) so when debugging is enabled, it explodes. * However, the tests are still quite interesting for checking * variable start, end and size. @@ -312,7 +314,8 @@ static int igt_vma_pin1(void *arg) struct i915_vma *vma; int err = -EINVAL; - /* Exercise all the weird and wonderful i915_vma_pin requests, + /* + * Exercise all the weird and wonderful i915_vma_pin requests, * focusing on error handling of boundary conditions. */ @@ -577,7 +580,8 @@ static int igt_vma_rotate_remap(void *arg) const unsigned int max_pages = 64; int err = -ENOMEM; - /* Create VMA for many different combinations of planes and check + /* + * Create VMA for many different combinations of planes and check * that the page layout within the rotated VMA match our expectations. */ @@ -804,7 +808,8 @@ static int igt_vma_partial(void *arg) struct i915_vma *vma; int err = -ENOMEM; - /* Create lots of different VMA for the object and check that + /* + * Create lots of different VMA for the object and check that * we are returned the same VMA when we later request the same range. */ diff --git a/drivers/gpu/drm/i915/selftests/lib_sw_fence.c b/drivers/gpu/drm/i915/selftests/lib_sw_fence.c index bf2752cc1e0b..d5ecc68155da 100644 --- a/drivers/gpu/drm/i915/selftests/lib_sw_fence.c +++ b/drivers/gpu/drm/i915/selftests/lib_sw_fence.c @@ -74,7 +74,7 @@ void timed_fence_init(struct timed_fence *tf, unsigned long expires) void timed_fence_fini(struct timed_fence *tf) { - if (del_timer_sync(&tf->timer)) + if (timer_delete_sync(&tf->timer)) i915_sw_fence_commit(&tf->fence); destroy_timer_on_stack(&tf->timer); diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index 9e310f4099f4..f60eedb0e92c 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -687,6 +687,10 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915) drm_WARN_ON(&i915->drm, !IS_DGFX(i915)); dram_info->type = INTEL_DRAM_GDDR; break; + case 9: + drm_WARN_ON(&i915->drm, !IS_DGFX(i915)); + dram_info->type = INTEL_DRAM_GDDR_ECC; + break; default: MISSING_CASE(val); return -EINVAL; diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c index 842db43e46c0..82dc7fbd1a3e 100644 --- a/drivers/gpu/drm/i915/soc/intel_pch.c +++ b/drivers/gpu/drm/i915/soc/intel_pch.c @@ -7,6 +7,36 @@ #include "i915_utils.h" #include "intel_pch.h" +#define INTEL_PCH_DEVICE_ID_MASK 0xff80 +#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 +#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 +#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 +#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 +#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 +#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80 +#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80 +#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 +#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 +#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280 +#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300 +#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80 +#define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280 +#define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680 +#define INTEL_PCH_CMP_V_DEVICE_ID_TYPE 0xA380 +#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480 +#define INTEL_PCH_ICP2_DEVICE_ID_TYPE 0x3880 +#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00 +#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080 +#define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380 +#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80 +#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80 +#define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180 +#define INTEL_PCH_ADP3_DEVICE_ID_TYPE 0x7A00 +#define INTEL_PCH_ADP4_DEVICE_ID_TYPE 0x5480 +#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 +#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 +#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ + /* Map PCH device id to PCH type, or PCH_NONE if unknown. */ static enum intel_pch intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) @@ -33,14 +63,14 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); drm_WARN_ON(&dev_priv->drm, IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv)); - return PCH_LPT; + return PCH_LPT_H; case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found LynxPoint LP PCH\n"); drm_WARN_ON(&dev_priv->drm, !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); drm_WARN_ON(&dev_priv->drm, !IS_HASWELL_ULT(dev_priv) && !IS_BROADWELL_ULT(dev_priv)); - return PCH_LPT; + return PCH_LPT_LP; case INTEL_PCH_WPT_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint PCH\n"); drm_WARN_ON(&dev_priv->drm, @@ -48,7 +78,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) drm_WARN_ON(&dev_priv->drm, IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv)); /* WPT is LPT compatible */ - return PCH_LPT; + return PCH_LPT_H; case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint LP PCH\n"); drm_WARN_ON(&dev_priv->drm, @@ -56,7 +86,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) drm_WARN_ON(&dev_priv->drm, !IS_HASWELL_ULT(dev_priv) && !IS_BROADWELL_ULT(dev_priv)); /* WPT is LPT compatible */ - return PCH_LPT; + return PCH_LPT_LP; case INTEL_PCH_SPT_DEVICE_ID_TYPE: drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint PCH\n"); drm_WARN_ON(&dev_priv->drm, @@ -243,7 +273,7 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) * underneath. This is a requirement from virtualization team. * * In some virtualized environments (e.g. XEN), there is irrelevant - * ISA bridge in the system. To work reliably, we should scan trhough + * ISA bridge in the system. To work reliably, we should scan through * all the ISA bridge devices and check for the first match, instead * of only checking the first one. */ @@ -256,13 +286,11 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) pch_type = intel_pch_type(dev_priv, id); if (pch_type != PCH_NONE) { dev_priv->pch_type = pch_type; - dev_priv->pch_id = id; break; } else if (intel_is_virt_pch(id, pch->subsystem_vendor, pch->subsystem_device)) { intel_virt_detect_pch(dev_priv, &id, &pch_type); dev_priv->pch_type = pch_type; - dev_priv->pch_id = id; break; } } @@ -275,12 +303,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) drm_dbg_kms(&dev_priv->drm, "Display disabled, reverting to NOP PCH\n"); dev_priv->pch_type = PCH_NOP; - dev_priv->pch_id = 0; } else if (!pch) { if (i915_run_as_guest() && HAS_DISPLAY(dev_priv)) { intel_virt_detect_pch(dev_priv, &id, &pch_type); dev_priv->pch_type = pch_type; - dev_priv->pch_id = id; } else { drm_dbg_kms(&dev_priv->drm, "No PCH found.\n"); } diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h index 89e89ede265d..635aea7a5539 100644 --- a/drivers/gpu/drm/i915/soc/intel_pch.h +++ b/drivers/gpu/drm/i915/soc/intel_pch.h @@ -19,7 +19,8 @@ enum intel_pch { PCH_NONE = 0, /* No PCH present */ PCH_IBX, /* Ibexpeak PCH */ PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ - PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ + PCH_LPT_H, /* Lynxpoint/Wildcatpoint H PCH */ + PCH_LPT_LP, /* Lynxpoint/Wildcatpoint LP PCH */ PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */ PCH_CNP, /* Cannon/Comet Lake PCH */ PCH_ICP, /* Ice Lake/Jasper Lake PCH */ @@ -33,38 +34,7 @@ enum intel_pch { PCH_LNL, }; -#define INTEL_PCH_DEVICE_ID_MASK 0xff80 -#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 -#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 -#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 -#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 -#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 -#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80 -#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80 -#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 -#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 -#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280 -#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300 -#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80 -#define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280 -#define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680 -#define INTEL_PCH_CMP_V_DEVICE_ID_TYPE 0xA380 -#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480 -#define INTEL_PCH_ICP2_DEVICE_ID_TYPE 0x3880 -#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00 -#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080 -#define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380 -#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80 -#define INTEL_PCH_ADP_DEVICE_ID_TYPE 0x7A80 -#define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180 -#define INTEL_PCH_ADP3_DEVICE_ID_TYPE 0x7A00 -#define INTEL_PCH_ADP4_DEVICE_ID_TYPE 0x5480 -#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 -#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 -#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ - #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) -#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) @@ -72,13 +42,10 @@ enum intel_pch { #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) -#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) -#define HAS_PCH_LPT_LP(dev_priv) \ - (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \ - INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) -#define HAS_PCH_LPT_H(dev_priv) \ - (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \ - INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE) +#define HAS_PCH_LPT_H(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT_H) +#define HAS_PCH_LPT_LP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT_LP) +#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT_H || \ + INTEL_PCH_TYPE(dev_priv) == PCH_LPT_LP) #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) |