diff options
132 files changed, 4301 insertions, 2251 deletions
diff --git a/Documentation/admin-guide/ramoops.rst b/Documentation/admin-guide/ramoops.rst index 8f107d8c9261..e9f85142182d 100644 --- a/Documentation/admin-guide/ramoops.rst +++ b/Documentation/admin-guide/ramoops.rst @@ -69,7 +69,7 @@ Setting the ramoops parameters can be done in several different manners: mem=128M ramoops.mem_address=0x8000000 ramoops.ecc=1 B. Use Device Tree bindings, as described in - ``Documentation/devicetree/bindings/reserved-memory/ramoops.txt``. + ``Documentation/devicetree/bindings/reserved-memory/ramoops.yaml``. For example:: reserved-memory { diff --git a/Documentation/devicetree/bindings/Makefile b/Documentation/devicetree/bindings/Makefile index a072e95de626..c9abfbe3f0aa 100644 --- a/Documentation/devicetree/bindings/Makefile +++ b/Documentation/devicetree/bindings/Makefile @@ -9,6 +9,11 @@ DT_SCHEMA_MIN_VERSION = 2021.2.1 PHONY += check_dtschema_version check_dtschema_version: + @which $(DT_DOC_CHECKER) >/dev/null || \ + { echo "Error: '$(DT_DOC_CHECKER)' not found!" >&2; \ + echo "Ensure dtschema python package is installed and in your PATH." >&2; \ + echo "Current PATH is:" >&2; \ + echo "$$PATH" >&2; false; } @{ echo $(DT_SCHEMA_MIN_VERSION); \ $(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -Vc >/dev/null || \ { echo "ERROR: dtschema minimum version is v$(DT_SCHEMA_MIN_VERSION)" >&2; false; } @@ -22,13 +27,20 @@ $(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE # Use full schemas when checking %.example.dts DT_TMP_SCHEMA := $(obj)/processed-schema-examples.json -find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \ +find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \ -name 'processed-schema*' ! \ -name '*.example.dt.yaml' \) +ifeq ($(DT_SCHEMA_FILES),) +find_cmd = $(find_all_cmd) +else +find_cmd = echo $(addprefix $(srctree)/, $(DT_SCHEMA_FILES)) +endif + quiet_cmd_yamllint = LINT $(src) cmd_yamllint = ($(find_cmd) | \ - xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true + xargs -n200 -P$$(nproc) \ + $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint >&2) || true quiet_cmd_chk_bindings = CHKDT $@ cmd_chk_bindings = ($(find_cmd) | \ @@ -38,7 +50,7 @@ quiet_cmd_mk_schema = SCHEMA $@ cmd_mk_schema = f=$$(mktemp) ; \ $(if $(DT_MK_SCHEMA_FLAGS), \ printf '%s\n' $(real-prereqs), \ - $(find_cmd)) > $$f ; \ + $(find_all_cmd)) > $$f ; \ $(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \ rm -f $$f @@ -48,7 +60,7 @@ define rule_chkdt $(call cmd,mk_schema) endef -DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_cmd))) +DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd))) override DTC_FLAGS := \ -Wno-avoid_unnecessary_addr_size \ diff --git a/Documentation/devicetree/bindings/arm/arm,cci-400.yaml b/Documentation/devicetree/bindings/arm/arm,cci-400.yaml new file mode 100644 index 000000000000..4682f991a5c8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,cci-400.yaml @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,cci-400.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM CCI Cache Coherent Interconnect Device Tree Binding + +maintainers: + - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> + +description: > + ARM multi-cluster systems maintain intra-cluster coherency through a cache + coherent interconnect (CCI) that is capable of monitoring bus transactions + and manage coherency, TLB invalidations and memory barriers. + + It allows snooping and distributed virtual memory message broadcast across + clusters, through memory mapped interface, with a global control register + space and multiple sets of interface control registers, one per slave + interface. + +properties: + $nodename: + pattern: "^cci(@[0-9a-f]+)?$" + + compatible: + enum: + - arm,cci-400 + - arm,cci-500 + - arm,cci-550 + + reg: + maxItems: 1 + description: > + Specifies base physical address of CCI control registers common to all + interfaces. + + "#address-cells": true + "#size-cells": true + ranges: true + +patternProperties: + "^slave-if@[0-9a-f]+$": + type: object + + properties: + compatible: + const: arm,cci-400-ctrl-if + + interface-type: + enum: + - ace + - ace-lite + + reg: + maxItems: 1 + + required: + - compatible + - interface-type + - reg + + additionalProperties: false + + "^pmu@[0-9a-f]+$": + type: object + + properties: + compatible: + oneOf: + - const: arm,cci-400-pmu,r0 + - const: arm,cci-400-pmu,r1 + - const: arm,cci-400-pmu + deprecated: true + description: > + Permitted only where OS has secure access to CCI registers + - const: arm,cci-500-pmu,r0 + - const: arm,cci-550-pmu,r0 + + interrupts: + minItems: 1 + maxItems: 8 + description: > + List of counter overflow interrupts, one per counter. The interrupts + must be specified starting with the cycle counter overflow interrupt, + followed by counter0 overflow interrupt, counter1 overflow + interrupt,... ,counterN overflow interrupt. + + The CCI PMU has an interrupt signal for each counter. The number of + interrupts must be equal to the number of counters. + + reg: + maxItems: 1 + + required: + - compatible + - interrupts + - reg + + additionalProperties: false + +required: + - "#address-cells" + - "#size-cells" + - compatible + - ranges + - reg + +additionalProperties: false + +examples: + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; + model = "V2P-CA15_CA7"; + arm,hbi = <0x249>; + interrupt-parent = <&gic>; + + /* + * This CCI node corresponds to a CCI component whose control + * registers sits at address 0x000000002c090000. + * + * CCI slave interface @0x000000002c091000 is connected to dma + * controller dma0. + * + * CCI slave interface @0x000000002c094000 is connected to CPUs + * {CPU0, CPU1}; + * + * CCI slave interface @0x000000002c095000 is connected to CPUs + * {CPU2, CPU3}; + */ + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + cci-control-port = <&cci_control1>; + reg = <0x0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + cci-control-port = <&cci_control1>; + reg = <0x1>; + }; + + CPU2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + cci-control-port = <&cci_control2>; + reg = <0x100>; + }; + + CPU3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + cci-control-port = <&cci_control2>; + reg = <0x101>; + }; + }; + + dma0: dma@3000000 { + /* compatible = "arm,pl330", "arm,primecell"; */ + cci-control-port = <&cci_control0>; + reg = <0x0 0x3000000 0x0 0x1000>; + interrupts = <10>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + cci@2c090000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x2c090000 0 0x1000>; + ranges = <0x0 0x0 0x2c090000 0x10000>; + + cci_control0: slave-if@1000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace-lite"; + reg = <0x1000 0x1000>; + }; + + cci_control1: slave-if@4000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x4000 0x1000>; + }; + + cci_control2: slave-if@5000 { + compatible = "arm,cci-400-ctrl-if"; + interface-type = "ace"; + reg = <0x5000 0x1000>; + }; + + pmu@9000 { + compatible = "arm,cci-400-pmu"; + reg = <0x9000 0x5000>; + interrupts = <0 101 4>, + <0 102 4>, + <0 103 4>, + <0 104 4>, + <0 105 4>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml index 55ef656d1192..a4b4452afc1d 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -119,22 +119,6 @@ properties: - const: arm,foundation-aarch64 - const: arm,vexpress - arm,hbi: - $ref: '/schemas/types.yaml#/definitions/uint32' - description: This indicates the ARM HBI (Hardware Board ID), this is - ARM's unique board model ID, visible on the PCB's silkscreen. - - arm,vexpress,site: - description: As Versatile Express can be configured in number of physically - different setups, the device tree should describe platform topology. - For this reason the root node and main motherboard node must define this - property, describing the physical location of the children nodes. - 0 means motherboard site, while 1 and 2 are daughterboard sites, and - 0xf means "sisterboard" which is the site containing the main CPU tile. - $ref: '/schemas/types.yaml#/definitions/uint32' - minimum: 0 - maximum: 15 - arm,vexpress,position: description: When daughterboards are stacked on one site, their position in the stack be be described this attribute. @@ -154,9 +138,9 @@ patternProperties: description: Static Memory Bus (SMB) node, if this exists it describes the connection between the motherboard and any tiles. Sometimes the compatible is placed directly under this node, sometimes it is placed - in a subnode named "motherboard". Sometimes the compatible includes + in a subnode named "motherboard-bus". Sometimes the compatible includes "arm,vexpress,v2?-p1" sometimes (on software models) is is just - "simple-bus". If the compatible is placed in the "motherboard" node, + "simple-bus". If the compatible is placed in the "motherboard-bus" node, it is stricter and always has two compatibles. type: object $ref: '/schemas/simple-bus.yaml' @@ -170,7 +154,9 @@ patternProperties: - arm,vexpress,v2p-p1 - const: simple-bus - const: simple-bus - motherboard: + + patternProperties: + '^motherboard-bus@': type: object description: The motherboard description provides a single "motherboard" node using 2 address cells corresponding to the Static Memory Bus @@ -183,6 +169,8 @@ patternProperties: const: 2 "#size-cells": const: 1 + ranges: true + compatible: items: - enum: @@ -196,8 +184,28 @@ patternProperties: - rs1 - rs2 + arm,hbi: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: This indicates the ARM HBI (Hardware Board ID), this is + ARM's unique board model ID, visible on the PCB's silkscreen. + + arm,vexpress,site: + description: As Versatile Express can be configured in number of physically + different setups, the device tree should describe platform topology. + For this reason the root node and main motherboard node must define this + property, describing the physical location of the children nodes. + 0 means motherboard site, while 1 and 2 are daughterboard sites, and + 0xf means "sisterboard" which is the site containing the main CPU tile. + $ref: '/schemas/types.yaml#/definitions/uint32' + minimum: 0 + maximum: 15 + required: - compatible + + additionalProperties: + type: object + required: - compatible diff --git a/Documentation/devicetree/bindings/arm/cci-control-port.yaml b/Documentation/devicetree/bindings/arm/cci-control-port.yaml new file mode 100644 index 000000000000..c9114866213f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cci-control-port.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/cci-control-port.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CCI Interconnect Bus Masters binding + +maintainers: + - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> + +description: | + Masters in the device tree connected to a CCI port (inclusive of CPUs + and their cpu nodes). + +select: true + +properties: + cci-control-port: + $ref: /schemas/types.yaml#/definitions/phandle + +additionalProperties: true + +examples: + - | + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + cci-control-port = <&cci_control1>; + reg = <0>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt deleted file mode 100644 index 9600761f2d5b..000000000000 --- a/Documentation/devicetree/bindings/arm/cci.txt +++ /dev/null @@ -1,224 +0,0 @@ -======================================================= -ARM CCI cache coherent interconnect binding description -======================================================= - -ARM multi-cluster systems maintain intra-cluster coherency through a -cache coherent interconnect (CCI) that is capable of monitoring bus -transactions and manage coherency, TLB invalidations and memory barriers. - -It allows snooping and distributed virtual memory message broadcast across -clusters, through memory mapped interface, with a global control register -space and multiple sets of interface control registers, one per slave -interface. - -* CCI interconnect node - - Description: Describes a CCI cache coherent Interconnect component - - Node name must be "cci". - Node's parent must be the root node /, and the address space visible - through the CCI interconnect is the same as the one seen from the - root node (ie from CPUs perspective as per DT standard). - Every CCI node has to define the following properties: - - - compatible - Usage: required - Value type: <string> - Definition: must contain one of the following: - "arm,cci-400" - "arm,cci-500" - "arm,cci-550" - - - reg - Usage: required - Value type: Integer cells. A register entry, expressed as a pair - of cells, containing base and size. - Definition: A standard property. Specifies base physical - address of CCI control registers common to all - interfaces. - - - ranges: - Usage: required - Value type: Integer cells. An array of range entries, expressed - as a tuple of cells, containing child address, - parent address and the size of the region in the - child address space. - Definition: A standard property. Follow rules in the Devicetree - Specification for hierarchical bus addressing. CCI - interfaces addresses refer to the parent node - addressing scheme to declare their register bases. - - CCI interconnect node can define the following child nodes: - - - CCI control interface nodes - - Node name must be "slave-if". - Parent node must be CCI interconnect node. - - A CCI control interface node must contain the following - properties: - - - compatible - Usage: required - Value type: <string> - Definition: must be set to - "arm,cci-400-ctrl-if" - - - interface-type: - Usage: required - Value type: <string> - Definition: must be set to one of {"ace", "ace-lite"} - depending on the interface type the node - represents. - - - reg: - Usage: required - Value type: Integer cells. A register entry, expressed - as a pair of cells, containing base and - size. - Definition: the base address and size of the - corresponding interface programming - registers. - - - CCI PMU node - - Parent node must be CCI interconnect node. - - A CCI pmu node must contain the following properties: - - - compatible - Usage: required - Value type: <string> - Definition: Must contain one of: - "arm,cci-400-pmu,r0" - "arm,cci-400-pmu,r1" - "arm,cci-400-pmu" - DEPRECATED, permitted only where OS has - secure access to CCI registers - "arm,cci-500-pmu,r0" - "arm,cci-550-pmu,r0" - - reg: - Usage: required - Value type: Integer cells. A register entry, expressed - as a pair of cells, containing base and - size. - Definition: the base address and size of the - corresponding interface programming - registers. - - - interrupts: - Usage: required - Value type: Integer cells. Array of interrupt specifier - entries, as defined in - ../interrupt-controller/interrupts.txt. - Definition: list of counter overflow interrupts, one per - counter. The interrupts must be specified - starting with the cycle counter overflow - interrupt, followed by counter0 overflow - interrupt, counter1 overflow interrupt,... - ,counterN overflow interrupt. - - The CCI PMU has an interrupt signal for each - counter. The number of interrupts must be - equal to the number of counters. - -* CCI interconnect bus masters - - Description: masters in the device tree connected to a CCI port - (inclusive of CPUs and their cpu nodes). - - A CCI interconnect bus master node must contain the following - properties: - - - cci-control-port: - Usage: required - Value type: <phandle> - Definition: a phandle containing the CCI control interface node - the master is connected to. - -Example: - - cpus { - #size-cells = <0>; - #address-cells = <1>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - cci-control-port = <&cci_control1>; - reg = <0x0>; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - cci-control-port = <&cci_control1>; - reg = <0x1>; - }; - - CPU2: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - cci-control-port = <&cci_control2>; - reg = <0x100>; - }; - - CPU3: cpu@101 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - cci-control-port = <&cci_control2>; - reg = <0x101>; - }; - - }; - - dma0: dma@3000000 { - compatible = "arm,pl330", "arm,primecell"; - cci-control-port = <&cci_control0>; - reg = <0x0 0x3000000 0x0 0x1000>; - interrupts = <10>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; - - cci@2c090000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0 0x2c090000 0 0x1000>; - ranges = <0x0 0x0 0x2c090000 0x10000>; - - cci_control0: slave-if@1000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace-lite"; - reg = <0x1000 0x1000>; - }; - - cci_control1: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control2: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu"; - reg = <0x9000 0x5000>; - interrupts = <0 101 4>, - <0 102 4>, - <0 103 4>, - <0 104 4>, - <0 105 4>; - }; - }; - -This CCI node corresponds to a CCI component whose control registers sits -at address 0x000000002c090000. -CCI slave interface @0x000000002c091000 is connected to dma controller dma0. -CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1}; -CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3}; diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 9a2432a88074..35b552ce8803 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -240,6 +240,8 @@ properties: DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. + cci-control-port: true + dynamic-power-coefficient: $ref: '/schemas/types.yaml#/definitions/uint32' description: diff --git a/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt b/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt deleted file mode 100644 index 780d0392a66b..000000000000 --- a/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.txt +++ /dev/null @@ -1,20 +0,0 @@ -Trusted Foundations -------------------- - -Boards that use the Trusted Foundations secure monitor can signal its -presence by declaring a node compatible with "tlm,trusted-foundations" -under the /firmware/ node - -Required properties: -- compatible: "tlm,trusted-foundations" -- tlm,version-major: major version number of Trusted Foundations firmware -- tlm,version-minor: minor version number of Trusted Foundations firmware - -Example: - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; diff --git a/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.yaml b/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.yaml new file mode 100644 index 000000000000..9d1857c0aa07 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/firmware/tlm,trusted-foundations.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/firmware/tlm,trusted-foundations.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Trusted Foundations + +description: | + Boards that use the Trusted Foundations secure monitor can signal its + presence by declaring a node compatible under the /firmware/ node + +maintainers: + - Stephen Warren <swarren@nvidia.com> + +properties: + $nodename: + const: trusted-foundations + + compatible: + const: tlm,trusted-foundations + + tlm,version-major: + $ref: /schemas/types.yaml#/definitions/uint32 + description: major version number of Trusted Foundations firmware + + tlm,version-minor: + $ref: /schemas/types.yaml#/definitions/uint32 + description: minor version number of Trusted Foundations firmware + +required: + - compatible + - tlm,version-major + - tlm,version-minor + +additionalProperties: false + +examples: + - | + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; diff --git a/Documentation/devicetree/bindings/bus/palmbus.yaml b/Documentation/devicetree/bindings/bus/palmbus.yaml new file mode 100644 index 000000000000..f5cbfaf52d53 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/palmbus.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/palmbus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink PalmBus Device Tree Bindings + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + The ralink palmbus controller can be found in all ralink MIPS + SoCs. It provides an external bus for connecting multiple + external devices to the SoC. + +properties: + $nodename: + pattern: "^palmbus(@[0-9a-f]+)?$" + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + compatible: + const: palmbus + + reg: + maxItems: 1 + + ranges: true + +patternProperties: + # All other properties should be child nodes with unit-address and 'reg' + "@[0-9a-f]+$": + type: object + properties: + reg: + maxItems: 1 + + required: + - reg + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/mips-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + palmbus@1e000000 { + compatible = "palmbus"; + reg = <0x1e000000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e000000 0x0fffff>; + + gpio@600 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "mediatek,mt7621-gpio"; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 95>; + interrupt-controller; + reg = <0x600 0x100>; + interrupt-parent = <&gic>; + interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt deleted file mode 100644 index c984143d08d2..000000000000 --- a/Documentation/devicetree/bindings/bus/ti-sysc.txt +++ /dev/null @@ -1,139 +0,0 @@ -Texas Instruments sysc interconnect target module wrapper binding - -Texas Instruments SoCs can have a generic interconnect target module -hardware for devices connected to various interconnects such as L3 -interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc -is mostly used for interaction between module and PRCM. It participates -in the OCP Disconnect Protocol but other than that is mostly independent -of the interconnect. - -Each interconnect target module can have one or more devices connected to -it. There is a set of control registers for managing interconnect target -module clocks, idle modes and interconnect level resets for the module. - -These control registers are sprinkled into the unused register address -space of the first child device IP block managed by the interconnect -target module and typically are named REVISION, SYSCONFIG and SYSSTATUS. - -Required standard properties: - -- compatible shall be one of the following generic types: - - "ti,sysc" - "ti,sysc-omap2" - "ti,sysc-omap4" - "ti,sysc-omap4-simple" - - or one of the following derivative types for hardware - needing special workarounds: - - "ti,sysc-omap2-timer" - "ti,sysc-omap4-timer" - "ti,sysc-omap3430-sr" - "ti,sysc-omap3630-sr" - "ti,sysc-omap4-sr" - "ti,sysc-omap3-sham" - "ti,sysc-omap-aes" - "ti,sysc-mcasp" - "ti,sysc-dra7-mcasp" - "ti,sysc-usb-host-fs" - "ti,sysc-dra7-mcan" - "ti,sysc-pruss" - -- reg shall have register areas implemented for the interconnect - target module in question such as revision, sysc and syss - -- reg-names shall contain the register names implemented for the - interconnect target module in question such as - "rev, "sysc", and "syss" - -- ranges shall contain the interconnect target module IO range - available for one or more child device IP blocks managed - by the interconnect target module, the ranges may include - multiple ranges such as device L4 range for control and - parent L3 range for DMA access - -Optional properties: - -- ti,sysc-mask shall contain mask of supported register bits for the - SYSCONFIG register as documented in the Technical Reference - Manual (TRM) for the interconnect target module - -- ti,sysc-midle list of master idle modes supported by the interconnect - target module as documented in the TRM for SYSCONFIG - register MIDLEMODE bits - -- ti,sysc-sidle list of slave idle modes supported by the interconnect - target module as documented in the TRM for SYSCONFIG - register SIDLEMODE bits - -- ti,sysc-delay-us delay needed after OCP softreset before accssing - SYSCONFIG register again - -- ti,syss-mask optional mask of reset done status bits as described in the - TRM for SYSSTATUS registers, typically 1 with some devices - having separate reset done bits for children like OHCI and - EHCI - -- clocks clock specifier for each name in the clock-names as - specified in the binding documentation for ti-clkctrl, - typically available for all interconnect targets on TI SoCs - based on omap4 except if it's read-only register in hwauto - mode as for example omap4 L4_CFG_CLKCTRL - -- clock-names should contain at least "fck", and optionally also "ick" - depending on the SoC and the interconnect target module, - some interconnect target modules also need additional - optional clocks that can be specified as listed in TRM - for the related CLKCTRL register bits 8 to 15 such as - "dbclk" or "clk32k" depending on their role - -- ti,hwmods optional TI interconnect module name to use legacy - hwmod platform data - -- ti,no-reset-on-init interconnect target module should not be reset at init - -- ti,no-idle-on-init interconnect target module should not be idled at init - -- ti,no-idle interconnect target module should not be idled - -Example: Single instance of MUSB controller on omap4 using interconnect ranges -using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000): - - target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */ - compatible = "ti,sysc-omap2"; - ti,hwmods = "usb_otg_hs"; - reg = <0x2b400 0x4>, - <0x2b404 0x4>, - <0x2b408 0x4>; - reg-names = "rev", "sysc", "syss"; - clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; - clock-names = "fck"; - ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; - ti,sysc-midle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>; - ti,sysc-sidle = <SYSC_IDLE_FORCE>, - <SYSC_IDLE_NO>, - <SYSC_IDLE_SMART>, - <SYSC_IDLE_SMART_WKUP>; - ti,syss-mask = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2b000 0x1000>; - - usb_otg_hs: otg@0 { - compatible = "ti,omap4-musb"; - reg = <0x0 0x7ff>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - usb-phy = <&usb2_phy>; - ... - }; - }; - -Note that other SoCs, such as am335x can have multiple child devices. On am335x -there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA -instance as children of a single interconnect target module. diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.yaml b/Documentation/devicetree/bindings/bus/ti-sysc.yaml new file mode 100644 index 000000000000..bd40213302da --- /dev/null +++ b/Documentation/devicetree/bindings/bus/ti-sysc.yaml @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/ti-sysc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments interconnect target module binding + +maintainers: + - Tony Lindgren <tony@atomide.com> + +description: + Texas Instruments SoCs can have a generic interconnect target module + for devices connected to various interconnects such as L3 interconnect + using Arteris NoC, and L4 interconnect using Sonics s3220. This module + is mostly used for interaction between module and Power, Reset and Clock + Manager PRCM. It participates in the OCP Disconnect Protocol, but other + than that it is mostly independent of the interconnect. + + Each interconnect target module can have one or more devices connected to + it. There is a set of control registers for managing the interconnect target + module clocks, idle modes and interconnect level resets. + + The interconnect target module control registers are sprinkled into the + unused register address space of the first child device IP block managed by + the interconnect target module. Typically the register names are REVISION, + SYSCONFIG and SYSSTATUS. + +properties: + $nodename: + pattern: "^target-module(@[0-9a-f]+)?$" + + compatible: + oneOf: + - items: + - enum: + - ti,sysc-omap2 + - ti,sysc-omap2 + - ti,sysc-omap4 + - ti,sysc-omap4-simple + - ti,sysc-omap2-timer + - ti,sysc-omap4-timer + - ti,sysc-omap3430-sr + - ti,sysc-omap3630-sr + - ti,sysc-omap4-sr + - ti,sysc-omap3-sham + - ti,sysc-omap-aes + - ti,sysc-mcasp + - ti,sysc-dra7-mcasp + - ti,sysc-usb-host-fs + - ti,sysc-dra7-mcan + - ti,sysc-pruss + - const: ti,sysc + - items: + - const: ti,sysc + + reg: + description: + Interconnect target module control registers consisting of + REVISION, SYSCONFIG and SYSSTATUS registers as defined in the + Technical Reference Manual for the SoC. + minItems: 1 + maxItems: 3 + + reg-names: + description: + Interconnect target module control register names consisting + of "rev", "sysc" and "syss". + oneOf: + - minItems: 1 + items: + - const: rev + - const: sysc + - const: syss + - items: + - const: rev + - const: syss + - enum: [ sysc, syss ] + + power-domains: + description: Target module power domain if available. + maxItems: 1 + + clocks: + description: + Target module clocks consisting of one functional clock, one + interface clock, and up to 8 module specific optional clocks. + Some modules may have only the functional clock, and some have + no configurable clocks. + minItems: 1 + maxItems: 4 + + clock-names: + description: + Target module clock names like "fck", "ick", "optck1", "optck2" + if the clocks are configurable. + oneOf: + - enum: [ ick, fck, sys_clk ] + - items: + - const: fck + - enum: [ ick. dbclk, osc, sys_clk, dss_clk, ahclkx ] + - items: + - const: fck + - const: phy-clk + - const: phy-clk-div + - items: + - const: fck + - const: hdmi_clk + - const: sys_clk + - const: tv_clk + - items: + - const: fck + - const: ahclkx + - const: ahclkr + + resets: + description: + Target module reset bit in the RSTCTRL register if wired for the module. + Note that the other reset bits should be mapped for the child device + driver to use. + maxItems: 1 + + reset-names: + description: + Target module reset names in the RSTCTRL register, typically named + "rstctrl" if only one reset bit is wired for the module. + items: + - const: rstctrl + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + ranges: true + + dma-ranges: true + + ti,sysc-mask: + description: Mask of supported register bits for the SYSCONFIG register + $ref: /schemas/types.yaml#/definitions/uint32 + + ti,sysc-midle: + description: List of hardware supported idle modes + $ref: /schemas/types.yaml#/definitions/uint32-array + + ti,sysc-sidle: + description: List of hardware supported idle modes + $ref: /schemas/types.yaml#/definitions/uint32-array + + ti,syss-mask: + description: Mask of supported register bits for the SYSSTATUS register + $ref: /schemas/types.yaml#/definitions/uint32 + + ti,sysc-delay-us: + description: Delay needed after OCP softreset before accessing SYCONFIG + default: 0 + minimum: 0 + maximum: 2 + + ti,no-reset-on-init: + description: Interconnect target module shall not be reset at init + type: boolean + + ti,no-idle-on-init: + description: Interconnect target module shall not be idled at init + type: boolean + + ti,no-idle: + description: Interconnect target module shall not be idled + type: boolean + + ti,hwmods: + description: Interconnect module name to use with legacy hwmod data + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + +required: + - compatible + - '#address-cells' + - '#size-cells' + - ranges + +additionalProperties: + type: object + +examples: + - | + #include <dt-bindings/bus/ti-sysc.h> + #include <dt-bindings/clock/omap4.h> + + target-module@2b000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + ti,hwmods = "usb_otg_hs"; + reg = <0x2b400 0x4>, + <0x2b404 0x4>, + <0x2b408 0x4>; + reg-names = "rev", "sysc", "syss"; + clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>; + clock-names = "fck"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2b000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt index 3fbeb3733c48..58fc8a6cebc7 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt @@ -174,7 +174,7 @@ Example: compatible = "rockchip,rk3399-dmc"; devfreq-events = <&dfi>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_DDRCLK>; + clocks = <&cru SCLK_DDRC>; clock-names = "dmc_clk"; operating-points-v2 = <&dmc_opp_table>; center-supply = <&ppvar_centerlogic>; diff --git a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt index 3e64075ac7ec..3b3d0bbfcfff 100644 --- a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt +++ b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt @@ -60,7 +60,7 @@ Example: blue-and-red-wiring = "crossed"; port { - lcdc_0: endpoint@0 { + lcdc_0: endpoint { remote-endpoint = <&hdmi_0>; }; }; @@ -75,7 +75,7 @@ Example: pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; port { - hdmi_0: endpoint@0 { + hdmi_0: endpoint { remote-endpoint = <&lcdc_0>; }; }; diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml index d88bd93f4b80..10ec78ca1c65 100644 --- a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml @@ -160,8 +160,8 @@ examples: <&xlnx_dpdma 2>, <&xlnx_dpdma 3>; - phys = <&psgtr 1 PHY_TYPE_DP 0 3 27000000>, - <&psgtr 0 PHY_TYPE_DP 1 3 27000000>; + phys = <&psgtr 1 PHY_TYPE_DP 0 3>, + <&psgtr 0 PHY_TYPE_DP 1 3>; phy-names = "dp-phy0", "dp-phy1"; }; diff --git a/Documentation/devicetree/bindings/display/xylon,logicvc-display.yaml b/Documentation/devicetree/bindings/display/xylon,logicvc-display.yaml new file mode 100644 index 000000000000..fc02c5d50ce4 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xylon,logicvc-display.yaml @@ -0,0 +1,301 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 Bootlin +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Xylon LogiCVC display controller + +maintainers: + - Paul Kocialkowski <paul.kocialkowski@bootlin.com> + +description: | + The Xylon LogiCVC is a display controller that supports multiple layers. + It is usually implemented as programmable logic and was optimized for use + with Xilinx Zynq-7000 SoCs and Xilinx FPGAs. + + Because the controller is intended for use in a FPGA, most of the + configuration of the controller takes place at logic configuration bitstream + synthesis time. As a result, many of the device-tree bindings are meant to + reflect the synthesis configuration and must not be configured differently. + Matching synthesis parameters are provided when applicable. + + Layers are declared in the "layers" sub-node and have dedicated configuration. + In version 3 of the controller, each layer has fixed memory offset and address + starting from the video memory base address for its framebuffer. In version 4, + framebuffers are configured with a direct memory address instead. + +properties: + compatible: + enum: + - xylon,logicvc-3.02.a-display + - xylon,logicvc-4.01.a-display + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + items: + # vclk is required and must be provided as first item. + - const: vclk + # Other clocks are optional and can be provided in any order. + - enum: + - vclk2 + - lvdsclk + - lvdsclkn + - enum: + - vclk2 + - lvdsclk + - lvdsclkn + - enum: + - vclk2 + - lvdsclk + - lvdsclkn + + interrupts: + maxItems: 1 + + memory-region: + maxItems: 1 + + xylon,display-interface: + enum: + # Parallel RGB interface (C_DISPLAY_INTERFACE == 0) + - parallel-rgb + # ITU-T BR656 interface (C_DISPLAY_INTERFACE == 1) + - bt656 + # 4-bit LVDS interface (C_DISPLAY_INTERFACE == 2) + - lvds-4bits + # 3-bit LVDS interface (C_DISPLAY_INTERFACE == 4) + - lvds-3bits + # DVI interface (C_DISPLAY_INTERFACE == 5) + - dvi + description: Display output interface (C_DISPLAY_INTERFACE). + + xylon,display-colorspace: + enum: + # RGB colorspace (C_DISPLAY_COLOR_SPACE == 0) + - rgb + # YUV 4:2:2 colorspace (C_DISPLAY_COLOR_SPACE == 1) + - yuv422 + # YUV 4:4:4 colorspace (C_DISPLAY_COLOR_SPACE == 2) + - yuv444 + description: Display output colorspace (C_DISPLAY_COLOR_SPACE). + + xylon,display-depth: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: Display output depth (C_PIXEL_DATA_WIDTH). + + xylon,row-stride: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: Fixed number of pixels in a framebuffer row (C_ROW_STRIDE). + + xylon,dithering: + $ref: "/schemas/types.yaml#/definitions/flag" + description: Dithering module is enabled (C_XCOLOR) + + xylon,background-layer: + $ref: "/schemas/types.yaml#/definitions/flag" + description: | + The last layer is used to display a black background (C_USE_BACKGROUND). + The layer must still be registered. + + xylon,layers-configurable: + $ref: "/schemas/types.yaml#/definitions/flag" + description: | + Configuration of layers' size, position and offset is enabled + (C_USE_SIZE_POSITION). + + layers: + type: object + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^layer@[0-9]+$": + type: object + + properties: + reg: + maxItems: 1 + + xylon,layer-depth: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: Layer depth (C_LAYER_X_DATA_WIDTH). + + xylon,layer-colorspace: + enum: + # RGB colorspace (C_LAYER_X_TYPE == 0) + - rgb + # YUV packed colorspace (C_LAYER_X_TYPE == 0) + - yuv + description: Layer colorspace (C_LAYER_X_TYPE). + + xylon,layer-alpha-mode: + enum: + # Alpha is configured layer-wide (C_LAYER_X_ALPHA_MODE == 0) + - layer + # Alpha is configured per-pixel (C_LAYER_X_ALPHA_MODE == 1) + - pixel + description: Alpha mode for the layer (C_LAYER_X_ALPHA_MODE). + + xylon,layer-base-offset: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: | + Offset in number of lines (C_LAYER_X_OFFSET) starting from the + video RAM base (C_VMEM_BASEADDR), only for version 3. + + xylon,layer-buffer-offset: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: | + Offset in number of lines (C_BUFFER_*_OFFSET) starting from the + layer base offset for the second buffer used in double-buffering. + + xylon,layer-primary: + $ref: "/schemas/types.yaml#/definitions/flag" + description: | + Layer should be registered as a primary plane (exactly one is + required). + + additionalProperties: false + + required: + - reg + - xylon,layer-depth + - xylon,layer-colorspace + - xylon,layer-alpha-mode + + required: + - "#address-cells" + - "#size-cells" + - layer@0 + + additionalProperties: false + + description: | + The description of the display controller layers, containing layer + sub-nodes that each describe a registered layer. + + port: + $ref: /schemas/graph.yaml#/properties/port + description: | + Video output port, typically connected to a panel or bridge. + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - xylon,display-interface + - xylon,display-colorspace + - xylon,display-depth + - xylon,row-stride + - layers + - port + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + logicvc: logicvc@43c00000 { + compatible = "xylon,logicvc-3.02.a", "syscon", "simple-mfd"; + reg = <0x43c00000 0x6000>; + + #address-cells = <1>; + #size-cells = <1>; + + logicvc_display: display@0 { + compatible = "xylon,logicvc-3.02.a-display"; + reg = <0x0 0x6000>; + + memory-region = <&logicvc_cma>; + + clocks = <&logicvc_vclk 0>, <&logicvc_lvdsclk 0>; + clock-names = "vclk", "lvdsclk"; + + interrupt-parent = <&intc>; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + + xylon,display-interface = "lvds-4bits"; + xylon,display-colorspace = "rgb"; + xylon,display-depth = <16>; + xylon,row-stride = <1024>; + + xylon,layers-configurable; + + layers { + #address-cells = <1>; + #size-cells = <0>; + + layer@0 { + reg = <0>; + xylon,layer-depth = <16>; + xylon,layer-colorspace = "rgb"; + xylon,layer-alpha-mode = "layer"; + xylon,layer-base-offset = <0>; + xylon,layer-buffer-offset = <480>; + xylon,layer-primary; + }; + + layer@1 { + reg = <1>; + xylon,layer-depth = <16>; + xylon,layer-colorspace = "rgb"; + xylon,layer-alpha-mode = "layer"; + xylon,layer-base-offset = <2400>; + xylon,layer-buffer-offset = <480>; + }; + + layer@2 { + reg = <2>; + xylon,layer-depth = <16>; + xylon,layer-colorspace = "rgb"; + xylon,layer-alpha-mode = "layer"; + xylon,layer-base-offset = <960>; + xylon,layer-buffer-offset = <480>; + }; + + layer@3 { + reg = <3>; + xylon,layer-depth = <16>; + xylon,layer-colorspace = "rgb"; + xylon,layer-alpha-mode = "layer"; + xylon,layer-base-offset = <480>; + xylon,layer-buffer-offset = <480>; + }; + + layer@4 { + reg = <4>; + xylon,layer-depth = <16>; + xylon,layer-colorspace = "rgb"; + xylon,layer-alpha-mode = "layer"; + xylon,layer-base-offset = <8192>; + xylon,layer-buffer-offset = <480>; + }; + }; + + port { + #address-cells = <1>; + #size-cells = <0>; + + logicvc_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml index ff6ec65145cf..c078796ae1b5 100644 --- a/Documentation/devicetree/bindings/example-schema.yaml +++ b/Documentation/devicetree/bindings/example-schema.yaml @@ -119,7 +119,7 @@ properties: # valid for this binding. clock-frequency: - # The type is set in the core schema. Per device schema only need to set + # The type is set in the core schema. Per-device schema only need to set # constraints on the possible values. minimum: 100 maximum: 400000 @@ -133,24 +133,24 @@ properties: # *-supply is always a single phandle, so nothing more to define. foo-supply: true - # Vendor specific properties + # Vendor-specific properties # - # Vendor specific properties have slightly different schema requirements than + # Vendor-specific properties have slightly different schema requirements than # common properties. They must have at least a type definition and # 'description'. vendor,int-property: - description: Vendor specific properties must have a description + description: Vendor-specific properties must have a description $ref: /schemas/types.yaml#/definitions/uint32 enum: [2, 4, 6, 8, 10] vendor,bool-property: - description: Vendor specific properties must have a description. Boolean + description: Vendor-specific properties must have a description. Boolean properties are one case where the json-schema 'type' keyword can be used directly. type: boolean vendor,string-array-property: - description: Vendor specific properties should reference a type in the + description: Vendor-specific properties should reference a type in the core schema. $ref: /schemas/types.yaml#/definitions/string-array items: @@ -158,7 +158,7 @@ properties: - enum: [baz, boo] vendor,property-in-standard-units-microvolt: - description: Vendor specific properties having a standard unit suffix + description: Vendor-specific properties having a standard unit suffix don't need a type. enum: [ 100, 200, 300 ] diff --git a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml new file mode 100644 index 000000000000..396101a223e7 --- /dev/null +++ b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gnss/u-blox,neo-6m.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: U-blox GNSS Receiver Device Tree Bindings + +maintainers: + - Johan Hovold <johan@kernel.org> + +description: > + The U-blox GNSS receivers can use UART, DDC (I2C), SPI and USB interfaces. + +properties: + compatible: + enum: + - u-blox,neo-6m + - u-blox,neo-8 + - u-blox,neo-m8 + + reg: + description: > + The DDC Slave Address, SPI chip select address, the number of the USB hub + port or the USB host-controller port to which this device is attached, + depending on the bus used. Required for the DDC, SPI or USB busses. + + vcc-supply: + description: > + Main voltage regulator + + timepulse-gpios: + maxItems: 1 + description: > + Time pulse GPIO + + u-blox,extint-gpios: + maxItems: 1 + description: > + GPIO connected to the "external interrupt" input pin + + v-bckp-supply: + description: > + Backup voltage regulator + + current-speed: true + +required: + - compatible + - vcc-supply + +additionalProperties: false + +examples: + - | + serial { + gnss { + compatible = "u-blox,neo-8"; + v-bckp-supply = <&gnss_v_bckp_reg>; + vcc-supply = <&gnss_vcc_reg>; + }; + }; diff --git a/Documentation/devicetree/bindings/gnss/u-blox.txt b/Documentation/devicetree/bindings/gnss/u-blox.txt deleted file mode 100644 index 7cdefd058fe0..000000000000 --- a/Documentation/devicetree/bindings/gnss/u-blox.txt +++ /dev/null @@ -1,45 +0,0 @@ -u-blox GNSS Receiver DT binding - -The u-blox GNSS receivers can use UART, DDC (I2C), SPI and USB interfaces. - -Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic -properties. - -Required properties: - -- compatible : Must be one of - - "u-blox,neo-6m" - "u-blox,neo-8" - "u-blox,neo-m8" - -- vcc-supply : Main voltage regulator - -Required properties (DDC): -- reg : DDC (I2C) slave address - -Required properties (SPI): -- reg : SPI chip select address - -Required properties (USB): -- reg : Number of the USB hub port or the USB host-controller port - to which this device is attached - -Optional properties: - -- timepulse-gpios : Time pulse GPIO -- u-blox,extint-gpios : GPIO connected to the "external interrupt" input pin -- v-bckp-supply : Backup voltage regulator - -Example: - -serial@1234 { - compatible = "ns16550a"; - - gnss { - compatible = "u-blox,neo-8"; - - v-bckp-supply = <&gnss_v_bckp_reg>; - vcc-supply = <&gnss_vcc_reg>; - }; -}; diff --git a/Documentation/devicetree/bindings/input/cap11xx.txt b/Documentation/devicetree/bindings/input/cap11xx.txt deleted file mode 100644 index 8c67a0b5058d..000000000000 --- a/Documentation/devicetree/bindings/input/cap11xx.txt +++ /dev/null @@ -1,78 +0,0 @@ -Device tree bindings for Microchip CAP11xx based capacitive touch sensors - -The node for this device must be a child of a I2C controller node, as the -device communication via I2C only. - -Required properties: - - compatible: Must contain one of: - "microchip,cap1106" - "microchip,cap1126" - "microchip,cap1188" - - reg: The I2C slave address of the device. - - interrupts: Property describing the interrupt line the - device's ALERT#/CM_IRQ# pin is connected to. - The device only has one interrupt source. - -Optional properties: - - autorepeat: Enables the Linux input system's autorepeat - feature on the input device. - - microchip,sensor-gain: Defines the gain of the sensor circuitry. This - effectively controls the sensitivity, as a - smaller delta capacitance is required to - generate the same delta count values. - Valid values are 1, 2, 4, and 8. - By default, a gain of 1 is set. - - microchip,irq-active-high: By default the interrupt pin is active low - open drain. This property allows using the active - high push-pull output. - - linux,keycodes: Specifies an array of numeric keycode values to - be used for the channels. If this property is - omitted, KEY_A, KEY_B, etc are used as - defaults. The array must have exactly six - entries. - -Example: - -i2c_controller { - cap1106@28 { - compatible = "microchip,cap1106"; - interrupt-parent = <&gpio1>; - interrupts = <0 0>; - reg = <0x28>; - autorepeat; - microchip,sensor-gain = <2>; - - linux,keycodes = <103>, /* KEY_UP */ - <106>, /* KEY_RIGHT */ - <108>, /* KEY_DOWN */ - <105>, /* KEY_LEFT */ - <109>, /* KEY_PAGEDOWN */ - <104>; /* KEY_PAGEUP */ - - #address-cells = <1>; - #size-cells = <0>; - - usr@0 { - label = "cap11xx:green:usr0"; - reg = <0>; - }; - - usr@1 { - label = "cap11xx:green:usr1"; - reg = <1>; - }; - - alive@2 { - label = "cap11xx:green:alive"; - reg = <2>; - linux,default_trigger = "heartbeat"; - }; - }; -} diff --git a/Documentation/devicetree/bindings/input/elan,ekth3000.yaml b/Documentation/devicetree/bindings/input/elan,ekth3000.yaml new file mode 100644 index 000000000000..2a9bb6ace021 --- /dev/null +++ b/Documentation/devicetree/bindings/input/elan,ekth3000.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/elan,ekth3000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Elantech I2C Touchpad + +maintainers: + - Dmitry Torokhov <dmitry.torokhov@gmail.com> + +allOf: + - $ref: touchscreen/touchscreen.yaml# + +properties: + compatible: + const: elan,ekth3000 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + wakeup-source: + type: boolean + description: touchpad can be used as a wakeup source + + vcc-supply: + description: a phandle for the regulator supplying 3.3V power + + elan,trackpoint: + type: boolean + description: touchpad can support a trackpoint + + elan,clickpad: + type: boolean + description: touchpad is a clickpad (the entire surface is a button) + + elan,middle-button: + type: boolean + description: touchpad has a physical middle button + + elan,x_traces: + $ref: /schemas/types.yaml#/definitions/uint32 + description: number of antennas on the x axis + + elan,y_traces: + $ref: /schemas/types.yaml#/definitions/uint32 + description: number of antennas on the y axis + + touchscreen-size-x: true + + touchscreen-size-y: true + + touchscreen-x-mm: true + + touchscreen-y-mm: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupt-parent = <&gpio4>; + interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + }; diff --git a/Documentation/devicetree/bindings/input/elan_i2c.txt b/Documentation/devicetree/bindings/input/elan_i2c.txt deleted file mode 100644 index 9963247706f2..000000000000 --- a/Documentation/devicetree/bindings/input/elan_i2c.txt +++ /dev/null @@ -1,44 +0,0 @@ -Elantech I2C Touchpad - -Required properties: -- compatible: must be "elan,ekth3000". -- reg: I2C address of the chip. -- interrupts: interrupt to which the chip is connected (see interrupt - binding[0]). - -Optional properties: -- wakeup-source: touchpad can be used as a wakeup source. -- pinctrl-names: should be "default" (see pinctrl binding [1]). -- pinctrl-0: a phandle pointing to the pin settings for the device (see - pinctrl binding [1]). -- vcc-supply: a phandle for the regulator supplying 3.3V power. -- elan,trackpoint: touchpad can support a trackpoint (boolean) -- elan,clickpad: touchpad is a clickpad (the entire surface is a button) -- elan,middle-button: touchpad has a physical middle button -- elan,x_traces: number of antennas on the x axis -- elan,y_traces: number of antennas on the y axis -- some generic touchscreen properties [2]: - * touchscreen-size-x - * touchscreen-size-y - * touchscreen-x-mm - * touchscreen-y-mm - - -[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt -[2]: Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt - -Example: - &i2c1 { - /* ... */ - - touchpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - interrupt-parent = <&gpio4>; - interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - /* ... */ - }; diff --git a/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml b/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml new file mode 100644 index 000000000000..fa0f37a90ac9 --- /dev/null +++ b/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/input/microchip,cap11xx.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device tree bindings for Microchip CAP11xx based capacitive touch sensors + +description: | + The Microchip CAP1xxx Family of RightTouchTM multiple-channel capacitive + touch controllers and LED drivers. The device communication via I2C only. + +maintainers: + - Rob Herring <robh@kernel.org> + +properties: + compatible: + enum: + - microchip,cap1106 + - microchip,cap1126 + - microchip,cap1188 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + interrupts: + maxItems: 1 + description: | + Property describing the interrupt line the + device's ALERT#/CM_IRQ# pin is connected to. + The device only has one interrupt source. + + autorepeat: + description: | + Enables the Linux input system's autorepeat feature on the input device. + + linux,keycodes: + minItems: 6 + maxItems: 6 + description: | + Specifies an array of numeric keycode values to + be used for the channels. If this property is + omitted, KEY_A, KEY_B, etc are used as defaults. + The array must have exactly six entries. + + microchip,sensor-gain: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1 + enum: [1, 2, 4, 8] + description: | + Defines the gain of the sensor circuitry. This + effectively controls the sensitivity, as a + smaller delta capacitance is required to + generate the same delta count values. + + microchip,irq-active-high: + type: boolean + description: | + By default the interrupt pin is active low + open drain. This property allows using the active + high push-pull output. + +patternProperties: + "^led@[0-7]$": + type: object + description: CAP11xx LEDs + $ref: /schemas/leds/common.yaml# + + properties: + reg: + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + label: true + + linux,default-trigger: true + + default-state: true + + required: + - reg + + additionalProperties: false + +allOf: + - $ref: input.yaml + - if: + properties: + compatible: + contains: + enum: + - microchip,cap1106 + then: + patternProperties: + "^led@[0-7]$": false + +required: + - compatible + - interrupts + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + cap1188@28 { + compatible = "microchip,cap1188"; + interrupt-parent = <&gpio1>; + interrupts = <0 0>; + reg = <0x28>; + autorepeat; + microchip,sensor-gain = <2>; + + linux,keycodes = <103>, /* KEY_UP */ + <106>, /* KEY_RIGHT */ + <108>, /* KEY_DOWN */ + <105>, /* KEY_LEFT */ + <109>, /* KEY_PAGEDOWN */ + <104>; /* KEY_PAGEUP */ + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + label = "cap11xx:green:usr0"; + reg = <0>; + }; + + led@1 { + label = "cap11xx:green:usr1"; + reg = <1>; + }; + + led@2 { + label = "cap11xx:green:alive"; + reg = <2>; + linux,default-trigger = "heartbeat"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/silead,gsl1680.yaml b/Documentation/devicetree/bindings/input/touchscreen/silead,gsl1680.yaml new file mode 100644 index 000000000000..eec6f7f6f0a3 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/silead,gsl1680.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/silead,gsl1680.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silead GSL1680 Touchscreen Controller Device Tree Bindings + +maintainers: + - Dmitry Torokhov <dmitry.torokhov@gmail.com> + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - silead,gsl1680 + - silead,gsl1688 + - silead,gsl3670 + - silead,gsl3675 + - silead,gsl3692 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-gpios: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: > + File basename for board specific firmware + + silead,max-fingers: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 5 + description: > + Maximum number of fingers the touchscreen can detect + + silead,home-button: + type: boolean + description: > + Does the device have a capacitive home-button build into the + touchscreen? + + avdd-supply: + description: > + Regulator phandle for controller AVDD + + vddio-supply: + description: > + Regulator phandle for controller VDDIO + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - power-gpios + - touchscreen-size-x + - touchscreen-size-y + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@40 { + compatible = "silead,gsl1680"; + reg = <0x40>; + interrupt-parent = <&pio>; + interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; + power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + silead,max-fingers = <5>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt b/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt deleted file mode 100644 index d67e558e5ab5..000000000000 --- a/Documentation/devicetree/bindings/input/touchscreen/silead_gsl1680.txt +++ /dev/null @@ -1,44 +0,0 @@ -* GSL 1680 touchscreen controller - -Required properties: -- compatible : Must be one of the following, depending on the model: - "silead,gsl1680" - "silead,gsl1688" - "silead,gsl3670" - "silead,gsl3675" - "silead,gsl3692" -- reg : I2C slave address of the chip (0x40) -- interrupts : interrupt specification for the gsl1680 interrupt -- power-gpios : Specification for the pin connected to the gsl1680's - shutdown input. This needs to be driven high to take the - gsl1680 out of its low power state -- touchscreen-size-x : See touchscreen.txt -- touchscreen-size-y : See touchscreen.txt - -Optional properties: -- firmware-name : File basename (string) for board specific firmware -- touchscreen-inverted-x : See touchscreen.txt -- touchscreen-inverted-y : See touchscreen.txt -- touchscreen-swapped-x-y : See touchscreen.txt -- silead,max-fingers : maximum number of fingers the touchscreen can detect -- silead,home-button : Boolean, set to true on devices which have a - capacitive home-button build into the touchscreen -- vddio-supply : regulator phandle for controller VDDIO -- avdd-supply : regulator phandle for controller AVDD - -Example: - -i2c@00000000 { - gsl1680: touchscreen@40 { - compatible = "silead,gsl1680"; - reg = <0x40>; - interrupt-parent = <&pio>; - interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; - power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; - touchscreen-size-x = <480>; - touchscreen-size-y = <800>; - touchscreen-inverted-x; - touchscreen-swapped-x-y; - silead,max-fingers = <5>; - }; -}; diff --git a/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml new file mode 100644 index 000000000000..449d6067ec88 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MSI controller + +maintainers: + - Marc Zyngier <maz@kernel.org> + +description: | + An MSI controller signals interrupts to a CPU when a write is made + to an MMIO address by some master. An MSI controller may feature a + number of doorbells. + +properties: + "#msi-cells": + description: | + The number of cells in an msi-specifier, required if not zero. + + Typically this will encode information related to sideband data, + and will not encode doorbells or payloads as these can be + configured dynamically. + + The meaning of the msi-specifier is defined by the device tree + binding of the specific MSI controller. + enum: [0, 1] + + msi-controller: + description: + Identifies the node as an MSI controller. + $ref: /schemas/types.yaml#/definitions/flag + + msi-ranges: + description: + A list of <phandle intspec span> tuples, where "phandle" is the + parent interrupt controller, "intspec" is the starting/base + interrupt specifier and "span" is the size of the + range. Multiple ranges can be provided. + $ref: /schemas/types.yaml#/definitions/phandle-array + +dependencies: + "#msi-cells": [ msi-controller ] + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/leds/register-bit-led.txt b/Documentation/devicetree/bindings/leds/register-bit-led.txt deleted file mode 100644 index c7af6f70a97b..000000000000 --- a/Documentation/devicetree/bindings/leds/register-bit-led.txt +++ /dev/null @@ -1,94 +0,0 @@ -Device Tree Bindings for Register Bit LEDs - -Register bit leds are used with syscon multifunctional devices -where single bits in a certain register can turn on/off a -single LED. The register bit LEDs appear as children to the -syscon device, with the proper compatible string. For the -syscon bindings see: -Documentation/devicetree/bindings/mfd/syscon.yaml - -Each LED is represented as a sub-node of the syscon device. Each -node's name represents the name of the corresponding LED. - -LED sub-node properties: - -Required properties: -- compatible : must be "register-bit-led" -- offset : register offset to the register controlling this LED -- mask : bit mask for the bit controlling this LED in the register - typically 0x01, 0x02, 0x04 ... - -Optional properties: -- label : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- linux,default-trigger : (optional) - see Documentation/devicetree/bindings/leds/common.txt -- default-state: (optional) The initial state of the LED - see Documentation/devicetree/bindings/leds/common.txt - -Example: - -syscon: syscon@10000000 { - compatible = "arm,realview-pb1176-syscon", "syscon"; - reg = <0x10000000 0x1000>; - - led@8.0 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x01>; - label = "versatile:0"; - linux,default-trigger = "heartbeat"; - default-state = "on"; - }; - led@8.1 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x02>; - label = "versatile:1"; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - led@8.2 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x04>; - label = "versatile:2"; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - led@8.3 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x08>; - label = "versatile:3"; - default-state = "off"; - }; - led@8.4 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x10>; - label = "versatile:4"; - default-state = "off"; - }; - led@8.5 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x20>; - label = "versatile:5"; - default-state = "off"; - }; - led@8.6 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x40>; - label = "versatile:6"; - default-state = "off"; - }; - led@8.7 { - compatible = "register-bit-led"; - offset = <0x08>; - mask = <0x80>; - label = "versatile:7"; - default-state = "off"; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/register-bit-led.yaml b/Documentation/devicetree/bindings/leds/register-bit-led.yaml new file mode 100644 index 000000000000..79b8fc0f9d23 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/register-bit-led.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/register-bit-led.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device Tree Bindings for Register Bit LEDs + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: |+ + Register bit leds are used with syscon multifunctional devices where single + bits in a certain register can turn on/off a single LED. The register bit LEDs + appear as children to the syscon device, with the proper compatible string. + For the syscon bindings see: + Documentation/devicetree/bindings/mfd/syscon.yaml + +allOf: + - $ref: /schemas/leds/common.yaml# + +properties: + $nodename: + description: + The unit-address is in the form of @<reg addr>,<bit offset> + pattern: '^led@[0-9a-f]+,[0-9a-f]{1,2}$' + + compatible: + const: register-bit-led + + reg: + description: + The register address and size + maxItems: 1 + + mask: + description: + bit mask for the bit controlling this LED in the register + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + [ 0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x100, 0x200, 0x400, 0x800, + 0x1000, 0x2000, 0x4000, 0x8000, 0x10000, 0x20000, 0x40000, 0x80000, + 0x100000, 0x200000, 0x400000, 0x800000, 0x1000000, 0x2000000, 0x4000000, + 0x8000000, 0x10000000, 0x20000000, 0x40000000, 0x80000000 ] + + offset: + description: + register offset to the register controlling this LED + $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true + +required: + - compatible + - mask + - reg + +unevaluatedProperties: false + +examples: + - | + + syscon@10000000 { + compatible = "arm,realview-pb1176-syscon", "syscon"; + reg = <0x10000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000000 0x1000>; + + led@8,0 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x01>; + label = "versatile:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@8,1 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x02>; + label = "versatile:1"; + default-state = "off"; + }; + led@8,2 { + compatible = "register-bit-led"; + reg = <0x08 0x04>; + offset = <0x08>; + mask = <0x04>; + label = "versatile:2"; + default-state = "off"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index 89a59b9c81f9..98fe37e8b17b 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -40,8 +40,8 @@ Optional properties for a client mutex node: defined in 'dt-bindings/gce/<chip>-gce.h'. Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h', -'dt-binding/gce/mt8183-gce.h', 'dt-binding/gce/mt8192-gce.h', -'dt-binding/gce/mt8195-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. +'dt-bindings/gce/mt8183-gce.h', 'dt-bindings/gce/mt8192-gce.h', +'dt-bindings/gce/mt8195-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as sub-system ids, thread priority, event ids. Example: diff --git a/Documentation/devicetree/bindings/media/i2c/ov5640.txt b/Documentation/devicetree/bindings/media/i2c/ov5640.txt deleted file mode 100644 index c97c2f2da12d..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/ov5640.txt +++ /dev/null @@ -1,92 +0,0 @@ -* Omnivision OV5640 MIPI CSI-2 / parallel sensor - -Required Properties: -- compatible: should be "ovti,ov5640" -- clocks: reference to the xclk input clock. -- clock-names: should be "xclk". -- DOVDD-supply: Digital I/O voltage supply, 1.8 volts -- AVDD-supply: Analog voltage supply, 2.8 volts -- DVDD-supply: Digital core voltage supply, 1.5 volts - -Optional Properties: -- reset-gpios: reference to the GPIO connected to the reset pin, if any. - This is an active low signal to the OV5640. -- powerdown-gpios: reference to the GPIO connected to the powerdown pin, - if any. This is an active high signal to the OV5640. -- rotation: as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt, - valid values are 0 (sensor mounted upright) and 180 (sensor - mounted upside down). - -The device node must contain one 'port' child node for its digital output -video port, in accordance with the video interface bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -OV5640 can be connected to a MIPI CSI-2 bus or a parallel bus endpoint. - -Endpoint node required properties for CSI-2 connection are: -- remote-endpoint: a phandle to the bus receiver's endpoint node. -- clock-lanes: should be set to <0> (clock lane on hardware lane 0) -- data-lanes: should be set to <1> or <1 2> (one or two CSI-2 lanes supported) - -Endpoint node required properties for parallel connection are: -- remote-endpoint: a phandle to the bus receiver's endpoint node. -- bus-width: shall be set to <8> for 8 bits parallel bus - or <10> for 10 bits parallel bus -- data-shift: shall be set to <2> for 8 bits parallel bus - (lines 9:2 are used) or <0> for 10 bits parallel bus -- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively. -- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively. -- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock - signal. - -Examples: - -&i2c1 { - ov5640: camera@3c { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - DOVDD-supply = <&vgen4_reg>; /* 1.8v */ - AVDD-supply = <&vgen3_reg>; /* 2.8v */ - DVDD-supply = <&vgen2_reg>; /* 1.5v */ - powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - rotation = <180>; - - port { - /* MIPI CSI-2 bus endpoint */ - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_from_ov5640>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; - }; -}; - -&i2c1 { - ov5640: camera@3c { - compatible = "ovti,ov5640"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; - clocks = <&clk_ext_camera>; - clock-names = "xclk"; - - port { - /* Parallel bus endpoint */ - ov5640_to_parallel: endpoint { - remote-endpoint = <¶llel_from_ov5640>; - bus-width = <8>; - data-shift = <2>; /* lines 9:2 are used */ - hsync-active = <0>; - vsync-active = <0>; - pclk-sample = <1>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml new file mode 100644 index 000000000000..540fd69ac39f --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov5640.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov5640.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OV5640 Image Sensor Device Tree Bindings + +maintainers: + - Steve Longerbeam <slongerbeam@gmail.com> + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + const: ovti,ov5640 + + reg: + maxItems: 1 + + clocks: + description: XCLK Input Clock + + clock-names: + const: xclk + + AVDD-supply: + description: Analog voltage supply, 2.8 volts + + DVDD-supply: + description: Digital core voltage supply, 1.5 volts + + DOVDD-supply: + description: Digital I/O voltage supply, 1.8 volts + + powerdown-gpios: + maxItems: 1 + description: > + Reference to the GPIO connected to the powerdown pin, if any. + + reset-gpios: + maxItems: 1 + description: > + Reference to the GPIO connected to the reset pin, if any. + + rotation: + enum: + - 0 + - 180 + + port: + description: Digital Output Port + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + const: 0 + + data-lanes: + minItems: 1 + maxItems: 2 + items: + enum: [1, 2] + + bus-width: + enum: [8, 10] + + data-shift: + enum: [0, 2] + +required: + - compatible + - reg + - clocks + - clock-names + - AVDD-supply + - DVDD-supply + - DOVDD-supply + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6qdl-clock.h> + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v */ + powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + rotation = <180>; + + port { + /* MIPI CSI-2 bus endpoint */ + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_from_ov5640>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + }; + + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x3c>; + clocks = <&clk_ext_camera>; + clock-names = "xclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v */ + + port { + /* Parallel bus endpoint */ + ov5640_to_parallel: endpoint { + remote-endpoint = <¶llel_from_ov5640>; + bus-width = <8>; + data-shift = <2>; /* lines 9:2 are used */ + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/ti,cal.yaml b/Documentation/devicetree/bindings/media/ti,cal.yaml index 65177cd69514..66c5d392fa75 100644 --- a/Documentation/devicetree/bindings/media/ti,cal.yaml +++ b/Documentation/devicetree/bindings/media/ti,cal.yaml @@ -154,7 +154,9 @@ examples: camera-sensor@3c { compatible = "ovti,ov5640"; reg = <0x3c>; - + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p5v>; clocks = <&clk_ov5640_fixed>; clock-names = "xclk"; diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt deleted file mode 100644 index dde6d837083a..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt +++ /dev/null @@ -1,29 +0,0 @@ -Freescale DDR memory controller - -Properties: - -- compatible : Should include "fsl,chip-memory-controller" where - chip is the processor (bsc9132, mpc8572 etc.), or - "fsl,qoriq-memory-controller". -- reg : Address and size of DDR controller registers -- interrupts : Error interrupt of DDR controller -- little-endian : Specifies little-endian access to registers - If omitted, big-endian will be used. - -Example 1: - - memory-controller@2000 { - compatible = "fsl,bsc9132-memory-controller"; - reg = <0x2000 0x1000>; - interrupts = <16 2 1 8>; - }; - - -Example 2: - - ddr1: memory-controller@8000 { - compatible = "fsl,qoriq-memory-controller-v4.7", - "fsl,qoriq-memory-controller"; - reg = <0x8000 0x1000>; - interrupts = <16 2 1 23>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml new file mode 100644 index 000000000000..af5147f9da72 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ddr.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ddr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale DDR memory controller + +maintainers: + - Borislav Petkov <bp@alien8.de> + - York Sun <york.sun@nxp.com> + +properties: + $nodename: + pattern: "^memory-controller@[0-9a-f]+$" + + compatible: + oneOf: + - items: + - enum: + - fsl,qoriq-memory-controller-v4.4 + - fsl,qoriq-memory-controller-v4.5 + - fsl,qoriq-memory-controller-v4.7 + - fsl,qoriq-memory-controller-v5.0 + - const: fsl,qoriq-memory-controller + - enum: + - fsl,bsc9132-memory-controller + - fsl,8540-memory-controller + - fsl,8541-memory-controller + - fsl,8544-memory-controller + - fsl,8548-memory-controller + - fsl,8555-memory-controller + - fsl,8568-memory-controller + - fsl,mpc8536-memory-controller + - fsl,mpc8540-memory-controller + - fsl,mpc8541-memory-controller + - fsl,mpc8544-memory-controller + - fsl,mpc8548-memory-controller + - fsl,mpc8555-memory-controller + - fsl,mpc8560-memory-controller + - fsl,mpc8568-memory-controller + - fsl,mpc8569-memory-controller + - fsl,mpc8572-memory-controller + - fsl,mpc8349-memory-controller + - fsl,p1020-memory-controller + - fsl,p1021-memory-controller + - fsl,p2020-memory-controller + - fsl,qoriq-memory-controller + + interrupts: + maxItems: 1 + + little-endian: + description: + Specifies little-endian access to registers. If omitted, big-endian will + be used. + type: boolean + + reg: + maxItems: 1 + +required: + - compatible + - interrupts + - reg + +additionalProperties: false + +examples: + - | + memory-controller@2000 { + compatible = "fsl,bsc9132-memory-controller"; + reg = <0x2000 0x1000>; + interrupts = <16 2 1 8>; + }; + + - | + memory-controller@8000 { + compatible = "fsl,qoriq-memory-controller-v4.7", + "fsl,qoriq-memory-controller"; + reg = <0x8000 0x1000>; + interrupts = <16 2 1 23>; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml new file mode 100644 index 000000000000..85e02854f083 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,mt7621-memc.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/mediatek,mt7621-memc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 SDRAM controller + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +properties: + compatible: + const: mediatek,mt7621-memc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + memory-controller@5000 { + compatible = "mediatek,mt7621-memc"; + reg = <0x5000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt deleted file mode 100644 index 936aa108eab4..000000000000 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ /dev/null @@ -1,157 +0,0 @@ -====================================================================== -Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller -====================================================================== - -The LPC bus is a means to bridge a host CPU to a number of low-bandwidth -peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The -primary use case of the Aspeed LPC controller is as a slave on the bus -(typically in a Baseboard Management Controller SoC), but under certain -conditions it can also take the role of bus master. - -The LPC controller is represented as a multi-function device to account for the -mix of functionality, which includes, but is not limited to: - -* An IPMI Block Transfer[2] Controller - -* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the - physical properties of some LPC pins, configuration of serial IRQs, and - APB-to-LPC bridging amonst other functions. - -* An LPC Host Interface Controller: Manages functions exposed to the host such - as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART - management and bus snoop configuration. - -* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom - hardware management protocols for handover between the host and baseboard - management controller. - -Additionally the state of the LPC controller influences the pinmux -configuration, therefore the host portion of the controller is exposed as a -syscon as a means to arbitrate access. - -[0] http://www.intel.com/design/chipsets/industry/25128901.pdf -[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4 -[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf -[3] https://en.wikipedia.org/wiki/Super_I/O - -Required properties -=================== - -- compatible: One of: - "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon" - "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon" - "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon" - -- reg: contains the physical address and length values of the Aspeed - LPC memory region. - -- #address-cells: <1> -- #size-cells: <1> -- ranges: Maps 0 to the physical address and length of the LPC memory - region - -Example: - -lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; - reg = <0x1e789000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - lpc_snoop: lpc-snoop@0 { - compatible = "aspeed,ast2600-lpc-snoop"; - reg = <0x0 0x80>; - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; - snoop-ports = <0x80>; - }; -}; - - -LPC Host Interface Controller -------------------- - -The LPC Host Interface Controller manages functions exposed to the host such as -LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART -management and bus snoop configuration. - -Required properties: - -- compatible: One of: - "aspeed,ast2400-lpc-ctrl"; - "aspeed,ast2500-lpc-ctrl"; - "aspeed,ast2600-lpc-ctrl"; - -- reg: contains offset/length values of the host interface controller - memory regions - -- clocks: contains a phandle to the syscon node describing the clocks. - There should then be one cell representing the clock to use - -Optional properties: - -- memory-region: A phandle to a reserved_memory region to be used for the LPC - to AHB mapping - -- flash: A phandle to the SPI flash controller containing the flash to - be exposed over the LPC to AHB mapping - -Example: - -lpc_ctrl: lpc-ctrl@80 { - compatible = "aspeed,ast2500-lpc-ctrl"; - reg = <0x80 0x80>; - clocks = <&syscon ASPEED_CLK_GATE_LCLK>; - memory-region = <&flash_memory>; - flash = <&spi>; -}; - -LPC Host Controller -------------------- - -The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour -between the host and the baseboard management controller. The registers exist -in the "host" portion of the Aspeed LPC controller, which must be the parent of -the LPC host controller node. - -Required properties: - -- compatible: One of: - "aspeed,ast2400-lhc"; - "aspeed,ast2500-lhc"; - "aspeed,ast2600-lhc"; - -- reg: contains offset/length values of the LHC memory regions. In the - AST2400 and AST2500 there are two regions. - -Example: - -lhc: lhc@a0 { - compatible = "aspeed,ast2500-lhc"; - reg = <0xa0 0x24 0xc8 0x8>; -}; - -LPC reset control ------------------ - -The UARTs present in the ASPEED SoC can have their resets tied to the reset -state of the LPC bus. Some systems may chose to modify this configuration. - -Required properties: - - - compatible: One of: - "aspeed,ast2600-lpc-reset"; - "aspeed,ast2500-lpc-reset"; - "aspeed,ast2400-lpc-reset"; - - - reg: offset and length of the IP in the LHC memory region - - #reset-controller indicates the number of reset cells expected - -Example: - -lpc_reset: reset-controller@98 { - compatible = "aspeed,ast2500-lpc-reset"; - reg = <0x98 0x4>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml new file mode 100644 index 000000000000..750996d9a175 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml @@ -0,0 +1,199 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# # Copyright (c) 2021 Aspeed Tehchnology Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed Low Pin Count (LPC) Bus Controller + +maintainers: + - Andrew Jeffery <andrew@aj.id.au> + - Chia-Wei Wang <chiawei_wang@aspeedtech.com> + +description: + The LPC bus is a means to bridge a host CPU to a number of low-bandwidth + peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The + primary use case of the Aspeed LPC controller is as a slave on the bus + (typically in a Baseboard Management Controller SoC), but under certain + conditions it can also take the role of bus master. + + The LPC controller is represented as a multi-function device to account for the + mix of functionality, which includes, but is not limited to + + * An IPMI Block Transfer[2] Controller + + * An LPC Host Interface Controller manages functions exposed to the host such + as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART + management and bus snoop configuration. + + * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom + hardware management protocols for handover between the host and baseboard + management controller. + + Additionally the state of the LPC controller influences the pinmux + configuration, therefore the host portion of the controller is exposed as a + syscon as a means to arbitrate access. + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-v2 + - aspeed,ast2500-lpc-v2 + - aspeed,ast2600-lpc-v2 + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^lpc-ctrl@[0-9a-f]+$": + type: object + additionalProperties: false + + description: | + The LPC Host Interface Controller manages functions exposed to the host such as + LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management + and bus snoop configuration. + + properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-ctrl + - aspeed,ast2500-lpc-ctrl + - aspeed,ast2600-lpc-ctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + memory-region: + maxItems: 1 + description: handle to memory reservation for the LPC to AHB mapping region + + flash: + $ref: /schemas/types.yaml#/definitions/phandle + description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping + + required: + - compatible + - clocks + + "^reset-controller@[0-9a-f]+$": + type: object + additionalProperties: false + + description: + The UARTs present in the ASPEED SoC can have their resets tied to the reset + state of the LPC bus. Some systems may chose to modify this configuration + + properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-reset + - aspeed,ast2500-lpc-reset + - aspeed,ast2600-lpc-reset + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + + required: + - compatible + - '#reset-cells' + + "^lpc-snoop@[0-9a-f]+$": + type: object + additionalProperties: false + + description: + The LPC snoop interface allows the BMC to listen on and record the data + bytes written by the Host to the targeted LPC I/O pots. + + properties: + compatible: + items: + - enum: + - aspeed,ast2400-lpc-snoop + - aspeed,ast2500-lpc-snoop + - aspeed,ast2600-lpc-snoop + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + snoop-ports: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: The LPC I/O ports to snoop + + required: + - compatible + - interrupts + - snoop-ports + + "^uart-routing@[0-9a-f]+$": + $ref: /schemas/soc/aspeed/uart-routing.yaml# + description: The UART routing control under LPC register space + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: + type: object + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/ast2600-clock.h> + + lpc: lpc@1e789000 { + compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + lpc_ctrl: lpc-ctrl@80 { + compatible = "aspeed,ast2600-lpc-ctrl"; + reg = <0x80 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + memory-region = <&flash_memory>; + flash = <&spi>; + }; + + lpc_reset: reset-controller@98 { + compatible = "aspeed,ast2600-lpc-reset"; + reg = <0x98 0x4>; + #reset-cells = <1>; + }; + + lpc_snoop: lpc-snoop@90 { + compatible = "aspeed,ast2600-lpc-snoop"; + reg = <0x90 0x8>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + snoop-ports = <0x80>; + }; + }; diff --git a/Documentation/devicetree/bindings/mips/ralink.txt b/Documentation/devicetree/bindings/mips/ralink.txt deleted file mode 100644 index 8cc0ab41578c..000000000000 --- a/Documentation/devicetree/bindings/mips/ralink.txt +++ /dev/null @@ -1,32 +0,0 @@ -Ralink MIPS SoC device tree bindings - -1. SoCs - -Each device tree must specify a compatible value for the Ralink SoC -it uses in the compatible property of the root node. The compatible -value must be one of the following values: - - ralink,rt2880-soc - ralink,rt3050-soc - ralink,rt3052-soc - ralink,rt3350-soc - ralink,rt3352-soc - ralink,rt3883-soc - ralink,rt5350-soc - ralink,mt7620a-soc - ralink,mt7620n-soc - ralink,mt7628a-soc - ralink,mt7688a-soc - -2. Boards - -GARDENA smart Gateway (MT7688) - -This board is based on the MediaTek MT7688 and equipped with 128 MiB -of DDR and 8 MiB of flash (SPI NOR) and additional 128MiB SPI NAND -storage. - ------------------------------- -Required root node properties: -- compatible = "gardena,smart-gateway-mt7688", "ralink,mt7688a-soc", - "ralink,mt7628a-soc"; diff --git a/Documentation/devicetree/bindings/mips/ralink.yaml b/Documentation/devicetree/bindings/mips/ralink.yaml new file mode 100644 index 000000000000..0588cee25ae9 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/ralink.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/ralink.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink SoC based Platforms Device Tree Bindings + +maintainers: + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + Boards with a Ralink SoC shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Boards with Ralink RT2880 SoC + items: + - enum: + - ralink,rt2880-eval-board + - const: ralink,rt2880-soc + + - description: Boards with Ralink RT3050 SoC + items: + - const: ralink,rt3050-soc + + - description: Boards with Ralink RT3052 SoC + items: + - enum: + - ralink,rt3052-eval-board + - const: ralink,rt3052-soc + + - description: Boards with Ralink RT3350 SoC + items: + - const: ralink,rt3350-soc + + - description: Boards with Ralink RT3352 SoC + items: + - const: ralink,rt3352-soc + + - description: Boards with Ralink RT3383 SoC + items: + - enum: + - ralink,rt3883-eval-board + - const: ralink,rt3383-soc + + - description: Boards with Ralink RT5350 SoC + items: + - const: ralink,rt5350-soc + + - description: Boards with Mediatek/Ralink MT7620A SoC + items: + - enum: + - ralink,mt7620a-eval-board + - const: ralink,mt7620a-soc + + - description: Boards with Mediatek/Ralink MT7620N SoC + items: + - const: ralink,mt7620n-soc + + - description: Boards with Mediatek/Ralink MT7628A SoC + items: + - enum: + - onion,omega2+ + - vocore,vocore2 + - const: ralink,mt7628a-soc + + - description: Boards with Mediatek/Ralink MT7688A SoC + items: + - enum: + - gardena,smart-gateway-mt7688 + - onion,omega2+ + - const: ralink,mt7628a-soc + + - description: Boards with Mediatek/Ralink MT7621 SoC + items: + - enum: + - gnubee,gb-pc1 + - gnubee,gb-pc2 + - const: mediatek,mt7621-soc + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 9eb4bb529ad5..407586bc366b 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -15,7 +15,7 @@ properties: oneOf: - const: allwinner,sun8i-a83t-emac - const: allwinner,sun8i-h3-emac - - const: allwinner,sun8i-r40-emac + - const: allwinner,sun8i-r40-gmac - const: allwinner,sun8i-v3s-emac - const: allwinner,sun50i-a64-emac - items: @@ -93,7 +93,7 @@ allOf: compatible: contains: enum: - - allwinner,sun8i-r40-emac + - allwinner,sun8i-r40-gmac then: properties: diff --git a/Documentation/devicetree/bindings/net/broadcom-bluetooth.yaml b/Documentation/devicetree/bindings/net/broadcom-bluetooth.yaml index fbdc2083bec4..5aac094fd217 100644 --- a/Documentation/devicetree/bindings/net/broadcom-bluetooth.yaml +++ b/Documentation/devicetree/bindings/net/broadcom-bluetooth.yaml @@ -50,16 +50,29 @@ properties: by interrupts and "host-wakeup" interrupt-names clocks: + minItems: 1 maxItems: 2 description: 1 or 2 clocks as defined in clock-names below, in that order clock-names: description: Names of the 1 to 2 supplied clocks - items: + oneOf: + - const: extclk + deprecated: true + description: Deprecated in favor of txco + - const: txco + description: > + external reference clock (not a standalone crystal) + - const: lpo - - const: extclk + description: > + external low power 32.768 kHz clock + + - items: + - const: txco + - const: lpo vbat-supply: description: phandle to regulator supply for VBAT diff --git a/Documentation/devicetree/bindings/net/marvell-bluetooth.txt b/Documentation/devicetree/bindings/net/marvell-bluetooth.txt deleted file mode 100644 index 0e2842296032..000000000000 --- a/Documentation/devicetree/bindings/net/marvell-bluetooth.txt +++ /dev/null @@ -1,25 +0,0 @@ -Marvell Bluetooth Chips ------------------------ - -This documents the binding structure and common properties for serial -attached Marvell Bluetooth devices. The following chips are included in -this binding: - -* Marvell 88W8897 Bluetooth devices - -Required properties: - - compatible: should be: - "mrvl,88w8897" - -Optional properties: -None so far - -Example: - -&serial0 { - compatible = "ns16550a"; - ... - bluetooth { - compatible = "mrvl,88w8897"; - }; -}; diff --git a/Documentation/devicetree/bindings/net/marvell-bluetooth.yaml b/Documentation/devicetree/bindings/net/marvell-bluetooth.yaml new file mode 100644 index 000000000000..309ef21a1e37 --- /dev/null +++ b/Documentation/devicetree/bindings/net/marvell-bluetooth.yaml @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/marvell-bluetooth.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Marvell Bluetooth chips + +description: | + This documents the binding structure and common properties for serial + attached Marvell Bluetooth devices. + +maintainers: + - Rob Herring <robh@kernel.org> + +properties: + compatible: + const: mrvl,88w8897 + +required: + - compatible + +additionalProperties: false + +examples: + - | + serial { + bluetooth { + compatible = "mrvl,88w8897"; + }; + }; diff --git a/Documentation/devicetree/bindings/net/nfc/marvell,nci.yaml b/Documentation/devicetree/bindings/net/nfc/marvell,nci.yaml new file mode 100644 index 000000000000..15a45db3899a --- /dev/null +++ b/Documentation/devicetree/bindings/net/nfc/marvell,nci.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/marvell,nci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell International Ltd. NCI NFC controller + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + +properties: + compatible: + enum: + - marvell,nfc-i2c + - marvell,nfc-spi + - marvell,nfc-uart + + hci-muxed: + type: boolean + description: | + Specifies that the chip is muxing NCI over HCI frames + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + reset-n-io: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + maxItems: 1 + description: | + Output GPIO pin used to reset the chip (active low) + + i2c-int-falling: + type: boolean + description: | + For I2C type of connection. Specifies that the chip read event shall be + trigged on falling edge. + + i2c-int-rising: + type: boolean + description: | + For I2C type of connection. Specifies that the chip read event shall be + trigged on rising edge. + + break-control: + type: boolean + description: | + For UART type of connection. Specifies that the chip needs specific break + management. + + flow-control: + type: boolean + description: | + For UART type of connection. Specifies that the chip is using RTS/CTS. + + spi-cpha: true + spi-cpol: true + spi-max-frequency: true + +required: + - compatible + +allOf: + - if: + properties: + compatible: + contains: + const: marvell,nfc-i2c + then: + properties: + break-control: false + flow-control: false + spi-cpha: false + spi-cpol: false + spi-max-frequency: false + required: + - reg + + - if: + properties: + compatible: + contains: + const: marvell,nfc-spi + then: + properties: + break-control: false + flow-control: false + i2c-int-falling: false + i2c-int-rising: false + required: + - reg + + - if: + properties: + compatible: + contains: + const: marvell,nfc-uart + then: + properties: + i2c-int-falling: false + i2c-int-rising: false + interrupts: false + spi-cpha: false + spi-cpol: false + spi-max-frequency: false + reg: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@8 { + compatible = "marvell,nfc-i2c"; + reg = <0x8>; + + interrupt-parent = <&gpio3>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + + i2c-int-rising; + + reset-n-io = <&gpio3 19 GPIO_ACTIVE_HIGH>; + }; + }; + + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + nfc@0 { + compatible = "marvell,nfc-spi"; + reg = <0>; + + spi-max-frequency = <3000000>; + spi-cpha; + spi-cpol; + + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + + reset-n-io = <&gpio3 19 GPIO_ACTIVE_HIGH>; + }; + }; + + - | + #include <dt-bindings/gpio/gpio.h> + + uart { + nfc { + compatible = "marvell,nfc-uart"; + + reset-n-io = <&gpio3 16 GPIO_ACTIVE_HIGH>; + + hci-muxed; + flow-control; + }; + }; diff --git a/Documentation/devicetree/bindings/net/nfc/nfcmrvl.txt b/Documentation/devicetree/bindings/net/nfc/nfcmrvl.txt deleted file mode 100644 index c9b35251bb20..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/nfcmrvl.txt +++ /dev/null @@ -1,84 +0,0 @@ -* Marvell International Ltd. NCI NFC Controller - -Required properties: -- compatible: Should be: - - "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices - - "marvell,nfc-i2c" for I2C devices - - "marvell,nfc-spi" for SPI devices - -Optional SoC specific properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- reset-n-io: Output GPIO pin used to reset the chip (active low). -- hci-muxed: Specifies that the chip is muxing NCI over HCI frames. - -Optional UART-based chip specific properties: -- flow-control: Specifies that the chip is using RTS/CTS. -- break-control: Specifies that the chip needs specific break management. - -Optional I2C-based chip specific properties: -- i2c-int-falling: Specifies that the chip read event shall be trigged on - falling edge. -- i2c-int-rising: Specifies that the chip read event shall be trigged on - rising edge. - -Example (for ARM-based BeagleBoard Black with 88W8887 on UART5): - -&uart5 { - - nfcmrvluart: nfcmrvluart@5 { - compatible = "marvell,nfc-uart"; - - reset-n-io = <&gpio3 16 0>; - - hci-muxed; - flow-control; - } -}; - - -Example (for ARM-based BeagleBoard Black with 88W8887 on I2C1): - -&i2c1 { - clock-frequency = <400000>; - - nfcmrvli2c0: i2c@1 { - compatible = "marvell,nfc-i2c"; - - reg = <0x8>; - - /* I2C INT configuration */ - interrupt-parent = <&gpio3>; - interrupts = <21 0>; - - /* I2C INT trigger configuration */ - i2c-int-rising; - - /* Reset IO */ - reset-n-io = <&gpio3 19 0>; - }; -}; - - -Example (for ARM-based BeagleBoard Black on SPI0): - -&spi0 { - - mrvlnfcspi0: spi@0 { - compatible = "marvell,nfc-spi"; - - reg = <0>; - - /* SPI Bus configuration */ - spi-max-frequency = <3000000>; - spi-cpha; - spi-cpol; - - /* SPI INT configuration */ - interrupt-parent = <&gpio1>; - interrupts = <17 0>; - - /* Reset IO */ - reset-n-io = <&gpio3 19 0>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml b/Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml new file mode 100644 index 000000000000..7465aea2e1c0 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/nxp,nci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Semiconductors NCI NFC controller + +maintainers: + - Charles Gorand <charles.gorand@effinnov.com> + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + +properties: + compatible: + oneOf: + - const: nxp,nxp-nci-i2c + - items: + - const: nxp,pn547 + - const: nxp,nxp-nci-i2c + + enable-gpios: + description: Output GPIO pin used for enabling/disabling the controller + + firmware-gpios: + description: Output GPIO pin used to enter firmware download mode + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - enable-gpios + - interrupts + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@29 { + compatible = "nxp,nxp-nci-i2c"; + + reg = <0x29>; + + interrupt-parent = <&gpio1>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/nfc/nxp,pn532.yaml b/Documentation/devicetree/bindings/net/nfc/nxp,pn532.yaml new file mode 100644 index 000000000000..d8ba5a18db98 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nfc/nxp,pn532.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/nxp,pn532.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Semiconductors PN532 NFC controller + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + +properties: + compatible: + oneOf: + - const: nxp,pn532 + - description: Deprecated bindings + enum: + - nxp,pn532-i2c + - nxp,pn533-i2c + deprecated: true + + interrupts: + description: Required if connected via I2C + maxItems: 1 + + reg: + description: Required if connected via I2C + maxItems: 1 + +required: + - compatible + +dependencies: + interrupts: [ 'reg' ] + +additionalProperties: false + +examples: + # PN532 on I2C bus + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@24 { + compatible = "nxp,pn532"; + + reg = <0x24>; + + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + # PN532 connected via UART + - | + serial@49042000 { + reg = <0x49042000 0x400>; + + nfc { + compatible = "nxp,pn532"; + }; + }; diff --git a/Documentation/devicetree/bindings/net/nfc/nxp,pn544.yaml b/Documentation/devicetree/bindings/net/nfc/nxp,pn544.yaml new file mode 100644 index 000000000000..d520414de463 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nfc/nxp,pn544.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/nxp,pn544.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Semiconductors PN544 NFC Controller + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + +properties: + compatible: + const: nxp,pn544-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + enable-gpios: + description: Output GPIO pin used for enabling/disabling the PN544 + maxItems: 1 + + firmware-gpios: + description: Output GPIO pin used to enter firmware download mode + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - enable-gpios + - firmware-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@28 { + compatible = "nxp,pn544-i2c"; + reg = <0x28>; + + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/nfc/nxp-nci.txt b/Documentation/devicetree/bindings/net/nfc/nxp-nci.txt deleted file mode 100644 index 285a37c2f189..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/nxp-nci.txt +++ /dev/null @@ -1,33 +0,0 @@ -* NXP Semiconductors NXP NCI NFC Controllers - -Required properties: -- compatible: Should be "nxp,nxp-nci-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- interrupts: GPIO interrupt to which the chip is connected -- enable-gpios: Output GPIO pin used for enabling/disabling the chip - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- firmware-gpios: Output GPIO pin used to enter firmware download mode - -Example (for ARM-based BeagleBone with NPC100 NFC controller on I2C2): - -&i2c2 { - - - npc100: npc100@29 { - - compatible = "nxp,nxp-nci-i2c"; - - reg = <0x29>; - clock-frequency = <100000>; - - interrupt-parent = <&gpio1>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; - firmware-gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/pn532.txt b/Documentation/devicetree/bindings/net/nfc/pn532.txt deleted file mode 100644 index a5507dc499bc..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/pn532.txt +++ /dev/null @@ -1,46 +0,0 @@ -* NXP Semiconductors PN532 NFC Controller - -Required properties: -- compatible: Should be - - "nxp,pn532" Place a node with this inside the devicetree node of the bus - where the NFC chip is connected to. - Currently the kernel has phy bindings for uart and i2c. - - "nxp,pn532-i2c" (DEPRECATED) only works for the i2c binding. - - "nxp,pn533-i2c" (DEPRECATED) only works for the i2c binding. - -Required properties if connected on i2c: -- clock-frequency: I²C work frequency. -- reg: for the I²C bus address. This is fixed at 0x24 for the PN532. -- interrupts: GPIO interrupt to which the chip is connected - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. - -Example (for ARM-based BeagleBone with PN532 on I2C2): - -&i2c2 { - - - pn532: nfc@24 { - - compatible = "nxp,pn532"; - - reg = <0x24>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; - - }; -}; - -Example (for PN532 connected via uart): - -uart4: serial@49042000 { - compatible = "ti,omap3-uart"; - - pn532: nfc { - compatible = "nxp,pn532"; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/pn544.txt b/Documentation/devicetree/bindings/net/nfc/pn544.txt deleted file mode 100644 index 2bd82562ce8e..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/pn544.txt +++ /dev/null @@ -1,33 +0,0 @@ -* NXP Semiconductors PN544 NFC Controller - -Required properties: -- compatible: Should be "nxp,pn544-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- interrupts: GPIO interrupt to which the chip is connected -- enable-gpios: Output GPIO pin used for enabling/disabling the PN544 -- firmware-gpios: Output GPIO pin used to enter firmware download mode - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. - -Example (for ARM-based BeagleBone with PN544 on I2C2): - -&i2c2 { - - - pn544: pn544@28 { - - compatible = "nxp,pn544-i2c"; - - reg = <0x28>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio1>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - firmware-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/st,st-nci.yaml b/Documentation/devicetree/bindings/net/nfc/st,st-nci.yaml new file mode 100644 index 000000000000..a6a1bc788d29 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nfc/st,st-nci.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/st,st-nci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics ST NCI NFC controller + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + +properties: + compatible: + enum: + - st,st21nfcb-i2c + - st,st21nfcb-spi + - st,st21nfcc-i2c + + reset-gpios: + description: Output GPIO pin used for resetting the controller + + ese-present: + type: boolean + description: | + Specifies that an ese is physically connected to the controller + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + spi-max-frequency: true + + uicc-present: + type: boolean + description: | + Specifies that the uicc swp signal can be physically connected to the + controller + +required: + - compatible + - interrupts + - reg + - reset-gpios + +if: + properties: + compatible: + contains: + enum: + - st,st21nfcb-i2c + - st,st21nfcc-i2c +then: + properties: + spi-max-frequency: false +else: + required: + - spi-max-frequency + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@8 { + compatible = "st,st21nfcb-i2c"; + reg = <0x08>; + + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + + ese-present; + uicc-present; + }; + }; + + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + nfc@0 { + compatible = "st,st21nfcb-spi"; + reg = <0>; + + spi-max-frequency = <4000000>; + + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + + ese-present; + uicc-present; + }; + }; diff --git a/Documentation/devicetree/bindings/net/nfc/st,st21nfca.yaml b/Documentation/devicetree/bindings/net/nfc/st,st21nfca.yaml new file mode 100644 index 000000000000..4356eacde8aa --- /dev/null +++ b/Documentation/devicetree/bindings/net/nfc/st,st21nfca.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/st,st21nfca.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics SAS ST21NFCA NFC controller + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + +properties: + compatible: + const: st,st21nfca-i2c + + enable-gpios: + description: Output GPIO pin used for enabling/disabling the controller + + ese-present: + type: boolean + description: | + Specifies that an ese is physically connected to the controller + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + uicc-present: + type: boolean + description: | + Specifies that the uicc swp signal can be physically connected to the + controller + +required: + - compatible + - enable-gpios + - interrupts + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@1 { + compatible = "st,st21nfca-i2c"; + reg = <0x1>; + + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + + ese-present; + uicc-present; + }; + }; diff --git a/Documentation/devicetree/bindings/net/nfc/st,st95hf.yaml b/Documentation/devicetree/bindings/net/nfc/st,st95hf.yaml new file mode 100644 index 000000000000..d3bca376039e --- /dev/null +++ b/Documentation/devicetree/bindings/net/nfc/st,st95hf.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/st,st95hf.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics ST95HF NFC controller + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + +properties: + compatible: + const: st,st95hf + + enable-gpio: + description: Output GPIO pin used for enabling/disabling the controller + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + st95hfvin-supply: + description: ST95HF transceiver's Vin regulator supply + + spi-max-frequency: true + +required: + - compatible + - enable-gpio + - interrupts + - reg + - spi-max-frequency + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + nfc@0{ + compatible = "st,st95hf"; + reg = <0>; + + spi-max-frequency = <1000000>; + enable-gpio = <&pio4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&pio0>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/nfc/st-nci-i2c.txt b/Documentation/devicetree/bindings/net/nfc/st-nci-i2c.txt deleted file mode 100644 index baa8f8133d19..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/st-nci-i2c.txt +++ /dev/null @@ -1,38 +0,0 @@ -* STMicroelectronics SAS. ST NCI NFC Controller - -Required properties: -- compatible: Should be "st,st21nfcb-i2c" or "st,st21nfcc-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- interrupts: GPIO interrupt to which the chip is connected -- reset-gpios: Output GPIO pin used to reset the ST21NFCB - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- ese-present: Specifies that an ese is physically connected to the nfc -controller. -- uicc-present: Specifies that the uicc swp signal can be physically -connected to the nfc controller. - -Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2): - -&i2c2 { - - - st21nfcb: st21nfcb@8 { - - compatible = "st,st21nfcb-i2c"; - - reg = <0x08>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - - reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - - ese-present; - uicc-present; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/st-nci-spi.txt b/Documentation/devicetree/bindings/net/nfc/st-nci-spi.txt deleted file mode 100644 index d33343330b94..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/st-nci-spi.txt +++ /dev/null @@ -1,36 +0,0 @@ -* STMicroelectronics SAS. ST NCI NFC Controller - -Required properties: -- compatible: Should be "st,st21nfcb-spi" -- spi-max-frequency: Maximum SPI frequency (<= 4000000). -- interrupts: GPIO interrupt to which the chip is connected -- reset-gpios: Output GPIO pin used to reset the ST21NFCB - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- ese-present: Specifies that an ese is physically connected to the nfc -controller. -- uicc-present: Specifies that the uicc swp signal can be physically -connected to the nfc controller. - -Example (for ARM-based BeagleBoard xM with ST21NFCB on SPI4): - -&mcspi4 { - - - st21nfcb: st21nfcb@0 { - - compatible = "st,st21nfcb-spi"; - - clock-frequency = <4000000>; - - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_EDGE_RISING>; - - reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - - ese-present; - uicc-present; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/st21nfca.txt b/Documentation/devicetree/bindings/net/nfc/st21nfca.txt deleted file mode 100644 index b8bd90f80e12..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/st21nfca.txt +++ /dev/null @@ -1,37 +0,0 @@ -* STMicroelectronics SAS. ST21NFCA NFC Controller - -Required properties: -- compatible: Should be "st,st21nfca-i2c". -- clock-frequency: I²C work frequency. -- reg: address on the bus -- enable-gpios: Output GPIO pin used for enabling/disabling the ST21NFCA - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- ese-present: Specifies that an ese is physically connected to the nfc -controller. -- uicc-present: Specifies that the uicc swp signal can be physically -connected to the nfc controller. - -Example (for ARM-based BeagleBoard xM with ST21NFCA on I2C2): - -&i2c2 { - - - st21nfca: st21nfca@1 { - - compatible = "st,st21nfca-i2c"; - - reg = <0x01>; - clock-frequency = <400000>; - - interrupt-parent = <&gpio5>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - - ese-present; - uicc-present; - }; -}; diff --git a/Documentation/devicetree/bindings/net/nfc/st95hf.txt b/Documentation/devicetree/bindings/net/nfc/st95hf.txt deleted file mode 100644 index 3f373a1e20ff..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/st95hf.txt +++ /dev/null @@ -1,45 +0,0 @@ -* STMicroelectronics : NFC Transceiver ST95HF - -ST NFC Transceiver is required to attach with SPI bus. -ST95HF node should be defined in DT as SPI slave device of SPI -master with which ST95HF transceiver is physically connected. -The properties defined below are required to be the part of DT -to include ST95HF transceiver into the platform. - -Required properties: -=================== -- reg: Address of SPI slave "ST95HF transceiver" on SPI master bus. - -- compatible: should be "st,st95hf" for ST95HF NFC transceiver - -- spi-max-frequency: Max. operating SPI frequency for ST95HF - transceiver. - -- enable-gpio: GPIO line to enable ST95HF transceiver. - -- interrupts : Standard way to define ST95HF transceiver's out - interrupt. - -Optional property: -================= -- st95hfvin-supply : This is an optional property. It contains a - phandle to ST95HF transceiver's regulator supply node in DT. - -Example: -======= -spi@9840000 { - reg = <0x9840000 0x110>; - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&pio0 4>; - - st95hf@0{ - reg = <0>; - compatible = "st,st95hf"; - spi-max-frequency = <1000000>; - enable-gpio = <&pio4 0>; - interrupt-parent = <&pio0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - }; - -}; diff --git a/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml b/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml new file mode 100644 index 000000000000..40da2ac98978 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nfc/ti,trf7970a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TRF7970A RFID/NFC/15693 Transceiver + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> + - Mark Greer <mgreer@animalcreek.com> + +properties: + compatible: + const: ti,trf7970a + + autosuspend-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Specify autosuspend delay in milliseconds. + + clock-frequency: + description: | + Set to specify that the input frequency to the trf7970a is 13560000Hz or + 27120000Hz + + en2-rf-quirk: + type: boolean + description: | + Specify that the trf7970a being used has the "EN2 RF" erratum + + interrupts: + maxItems: 1 + + irq-status-read-quirk: + type: boolean + description: | + Specify that the trf7970a being used has the "IRQ Status Read" erratum + + reg: + maxItems: 1 + + spi-max-frequency: true + + ti,enable-gpios: + minItems: 1 + maxItems: 2 + description: | + One or two GPIO entries used for 'EN' and 'EN2' pins on the TRF7970A. EN2 + is optional. + + vdd-io-supply: + description: | + Regulator specifying voltage for VDD-IO + + vin-supply: + description: | + Regulator for supply voltage to VIN pin + +required: + - compatible + - interrupts + - reg + - spi-max-frequency + - ti,enable-gpios + - vin-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + nfc@0 { + compatible = "ti,trf7970a"; + reg = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&trf7970a_default>; + spi-max-frequency = <2000000>; + interrupt-parent = <&gpio2>; + interrupts = <14 0>; + + ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>, + <&gpio2 5 GPIO_ACTIVE_HIGH>; + vin-supply = <&ldo3_reg>; + vdd-io-supply = <&ldo2_reg>; + autosuspend-delay = <30000>; + irq-status-read-quirk; + en2-rf-quirk; + clock-frequency = <27120000>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt deleted file mode 100644 index ba1934b950e5..000000000000 --- a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Texas Instruments TRF7970A RFID/NFC/15693 Transceiver - -Required properties: -- compatible: Should be "ti,trf7970a". -- spi-max-frequency: Maximum SPI frequency (<= 2000000). -- interrupts: A single interrupt specifier. -- ti,enable-gpios: One or two GPIO entries used for 'EN' and 'EN2' pins on the - TRF7970A. EN2 is optional. -- vin-supply: Regulator for supply voltage to VIN pin - -Optional SoC Specific Properties: -- pinctrl-names: Contains only one value - "default". -- pintctrl-0: Specifies the pin control groups used for this controller. -- autosuspend-delay: Specify autosuspend delay in milliseconds. -- irq-status-read-quirk: Specify that the trf7970a being used has the - "IRQ Status Read" erratum. -- en2-rf-quirk: Specify that the trf7970a being used has the "EN2 RF" - erratum. -- vdd-io-supply: Regulator specifying voltage for vdd-io -- clock-frequency: Set to specify that the input frequency to the trf7970a is 13560000Hz or 27120000Hz - -Example (for ARM-based BeagleBone with TRF7970A on SPI1): - -&spi1 { - - nfc@0 { - compatible = "ti,trf7970a"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&trf7970a_default>; - spi-max-frequency = <2000000>; - interrupt-parent = <&gpio2>; - interrupts = <14 0>; - ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>, - <&gpio2 5 GPIO_ACTIVE_HIGH>; - vin-supply = <&ldo3_reg>; - vdd-io-supply = <&ldo2_reg>; - autosuspend-delay = <30000>; - irq-status-read-quirk; - en2-rf-quirk; - clock-frequency = <27120000>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/qcom,ipa.yaml b/Documentation/devicetree/bindings/net/qcom,ipa.yaml index b8a0b392b24e..b86edf67ce62 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipa.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipa.yaml @@ -64,7 +64,8 @@ properties: - const: gsi iommus: - maxItems: 1 + minItems: 1 + maxItems: 2 clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml b/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml index 0634e69dd9a6..157d606bf9cb 100644 --- a/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml +++ b/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml @@ -34,6 +34,8 @@ properties: maxItems: 1 description: GPIO specifier, used to wakeup the host processor + max-speed: true + required: - compatible diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index c115c95ee584..282d7744f27f 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -50,7 +50,7 @@ properties: - allwinner,sun7i-a20-gmac - allwinner,sun8i-a83t-emac - allwinner,sun8i-h3-emac - - allwinner,sun8i-r40-emac + - allwinner,sun8i-r40-gmac - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac - loongson,ls2k-dwmac @@ -318,7 +318,7 @@ allOf: - allwinner,sun7i-a20-gmac - allwinner,sun8i-a83t-emac - allwinner,sun8i-h3-emac - - allwinner,sun8i-r40-emac + - allwinner,sun8i-r40-gmac - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac - ingenic,jz4775-mac @@ -366,7 +366,7 @@ allOf: - allwinner,sun7i-a20-gmac - allwinner,sun8i-a83t-emac - allwinner,sun8i-h3-emac - - allwinner,sun8i-r40-emac + - allwinner,sun8i-r40-gmac - allwinner,sun8i-v3s-emac - allwinner,sun50i-a64-emac - loongson,ls2k-dwmac diff --git a/Documentation/devicetree/bindings/net/ti,bluetooth.yaml b/Documentation/devicetree/bindings/net/ti,bluetooth.yaml new file mode 100644 index 000000000000..81616f9fb493 --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,bluetooth.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,bluetooth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments Bluetooth Chips + +maintainers: + - David Lechner <david@lechnology.com> + +description: | + This documents the binding structure and common properties for serial + attached TI Bluetooth devices. The following chips are included in this + binding: + + * TI CC256x Bluetooth devices + * TI WiLink 7/8 (wl12xx/wl18xx) Shared Transport BT/FM/GPS devices + + TI WiLink devices have a UART interface for providing Bluetooth, FM radio, + and GPS over what's called "shared transport". The shared transport is + standard BT HCI protocol with additional channels for the other functions. + + TI WiLink devices also have a separate WiFi interface as described in + wireless/ti,wlcore.yaml. + + This bindings follows the UART slave device binding in ../serial/serial.yaml. + +properties: + compatible: + enum: + - ti,cc2560 + - ti,wl1271-st + - ti,wl1273-st + - ti,wl1281-st + - ti,wl1283-st + - ti,wl1285-st + - ti,wl1801-st + - ti,wl1805-st + - ti,wl1807-st + - ti,wl1831-st + - ti,wl1835-st + - ti,wl1837-st + + enable-gpios: + maxItems: 1 + + vio-supply: + description: Vio input supply (1.8V) + + vbat-supply: + description: Vbat input supply (2.9-4.8V) + + clocks: + maxItems: 1 + + clock-names: + items: + - const: ext_clock + + max-speed: + default: 3000000 + + nvmem-cells: + maxItems: 1 + description: + Nvmem data cell that contains a 6 byte BD address with the most + significant byte first (big-endian). + + nvmem-cell-names: + items: + - const: bd-address + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + serial { + bluetooth { + compatible = "ti,wl1835-st"; + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + clocks = <&clk32k_wl18xx>; + clock-names = "ext_clock"; + nvmem-cells = <&bd_address>; + nvmem-cell-names = "bd-address"; + }; + }; diff --git a/Documentation/devicetree/bindings/net/ti-bluetooth.txt b/Documentation/devicetree/bindings/net/ti-bluetooth.txt deleted file mode 100644 index f48c17b38f58..000000000000 --- a/Documentation/devicetree/bindings/net/ti-bluetooth.txt +++ /dev/null @@ -1,60 +0,0 @@ -Texas Instruments Bluetooth Chips ---------------------------------- - -This documents the binding structure and common properties for serial -attached TI Bluetooth devices. The following chips are included in this -binding: - -* TI CC256x Bluetooth devices -* TI WiLink 7/8 (wl12xx/wl18xx) Shared Transport BT/FM/GPS devices - -TI WiLink devices have a UART interface for providing Bluetooth, FM radio, -and GPS over what's called "shared transport". The shared transport is -standard BT HCI protocol with additional channels for the other functions. - -TI WiLink devices also have a separate WiFi interface as described in -wireless/ti,wlcore.txt. - -This bindings follows the UART slave device binding in ../serial/serial.yaml. - -Required properties: - - compatible: should be one of the following: - "ti,cc2560" - "ti,wl1271-st" - "ti,wl1273-st" - "ti,wl1281-st" - "ti,wl1283-st" - "ti,wl1285-st" - "ti,wl1801-st" - "ti,wl1805-st" - "ti,wl1807-st" - "ti,wl1831-st" - "ti,wl1835-st" - "ti,wl1837-st" - -Optional properties: - - enable-gpios : GPIO signal controlling enabling of BT. Active high. - - vio-supply : Vio input supply (1.8V) - - vbat-supply : Vbat input supply (2.9-4.8V) - - clocks : Must contain an entry, for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. - - clock-names : Must include the following entry: - "ext_clock" (External clock provided to the TI combo chip). - - nvmem-cells: phandle to nvmem data cell that contains a 6 byte BD address - with the most significant byte first (big-endian). - - nvmem-cell-names: "bd-address" (required when nvmem-cells is specified) - -Example: - -&serial0 { - compatible = "ns16550a"; - ... - bluetooth { - compatible = "ti,wl1835-st"; - enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - clocks = <&clk32k_wl18xx>; - clock-names = "ext_clock"; - nvmem-cells = <&bd_address>; - nvmem-cell-names = "bd-address"; - }; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/esp,esp8089.txt b/Documentation/devicetree/bindings/net/wireless/esp,esp8089.txt deleted file mode 100644 index 6830c4786f8a..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/esp,esp8089.txt +++ /dev/null @@ -1,30 +0,0 @@ -Espressif ESP8089 wireless SDIO devices - -This node provides properties for controlling the ESP8089 wireless device. -The node is expected to be specified as a child node to the SDIO controller -that connects the device to the system. - -Required properties: - - - compatible : Should be "esp,esp8089". - -Optional properties: - - esp,crystal-26M-en: Integer value for the crystal_26M_en firmware parameter - -Example: - -&mmc1 { - #address-cells = <1>; - #size-cells = <0>; - - vmmc-supply = <®_dldo1>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - - esp8089: sdio_wifi@1 { - compatible = "esp,esp8089"; - reg = <1>; - esp,crystal-26M-en = <2>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/esp,esp8089.yaml b/Documentation/devicetree/bindings/net/wireless/esp,esp8089.yaml new file mode 100644 index 000000000000..284ef45add99 --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/esp,esp8089.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/esp,esp8089.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Espressif ESP8089 Device Tree Bindings + +maintainers: + - Hans de Goede <hdegoede@redhat.com> + +properties: + compatible: + const: esp,esp8089 + + reg: + maxItems: 1 + + esp,crystal-26M-en: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + Value for the crystal_26M_en firmware parameter + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + mmc { + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "esp,esp8089"; + reg = <1>; + esp,crystal-26M-en = <2>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wlcore,spi.txt b/Documentation/devicetree/bindings/net/wireless/ti,wlcore,spi.txt deleted file mode 100644 index cb5c9e1569ca..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/ti,wlcore,spi.txt +++ /dev/null @@ -1,57 +0,0 @@ -* Texas Instruments wl12xx/wl18xx wireless lan controller - -The wl12xx/wl18xx chips can be connected via SPI or via SDIO. This -document describes the binding for the SPI connected chip. - -Required properties: -- compatible : Should be one of the following: - * "ti,wl1271" - * "ti,wl1273" - * "ti,wl1281" - * "ti,wl1283" - * "ti,wl1801" - * "ti,wl1805" - * "ti,wl1807" - * "ti,wl1831" - * "ti,wl1835" - * "ti,wl1837" -- reg : Chip select address of device -- spi-max-frequency : Maximum SPI clocking speed of device in Hz -- interrupts : Should contain parameters for 1 interrupt line. -- vwlan-supply : Point the node of the regulator that powers/enable the - wl12xx/wl18xx chip - -Optional properties: -- ref-clock-frequency : Reference clock frequency (should be set for wl12xx) -- clock-xtal : boolean, clock is generated from XTAL - -- Please consult Documentation/devicetree/bindings/spi/spi-bus.txt - for optional SPI connection related properties, - -Examples: - -For wl12xx family: -&spi1 { - wlcore: wlcore@1 { - compatible = "ti,wl1271"; - reg = <1>; - spi-max-frequency = <48000000>; - interrupt-parent = <&gpio3>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; - vwlan-supply = <&vwlan_fixed>; - clock-xtal; - ref-clock-frequency = <38400000>; - }; -}; - -For wl18xx family: -&spi0 { - wlcore: wlcore@0 { - compatible = "ti,wl1835"; - reg = <0>; - spi-max-frequency = <48000000>; - interrupt-parent = <&gpio0>; - interrupts = <27 IRQ_TYPE_EDGE_RISING>; - vwlan-supply = <&vwlan_fixed>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt deleted file mode 100644 index 9306c4dadd46..000000000000 --- a/Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt +++ /dev/null @@ -1,45 +0,0 @@ -TI Wilink 6/7/8 (wl12xx/wl18xx) SDIO devices - -This node provides properties for controlling the wilink wireless device. The -node is expected to be specified as a child node to the SDIO controller that -connects the device to the system. - -Required properties: - - compatible: should be one of the following: - * "ti,wl1271" - * "ti,wl1273" - * "ti,wl1281" - * "ti,wl1283" - * "ti,wl1285" - * "ti,wl1801" - * "ti,wl1805" - * "ti,wl1807" - * "ti,wl1831" - * "ti,wl1835" - * "ti,wl1837" - - interrupts : specifies attributes for the out-of-band interrupt. - -Optional properties: - - ref-clock-frequency : ref clock frequency in Hz - - tcxo-clock-frequency : tcxo clock frequency in Hz - -Note: the *-clock-frequency properties assume internal clocks. In case of external -clock, new bindings (for parsing the clock nodes) have to be added. - -Example: - -&mmc3 { - vmmc-supply = <&wlan_en_reg>; - bus-width = <4>; - cap-power-off-card; - keep-power-in-suspend; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio0>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; - }; -}; diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml new file mode 100644 index 000000000000..8dd164d10290 --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/ti,wlcore.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments Wilink 6/7/8 (wl12xx/wl18xx) Wireless LAN Controller + +maintainers: + - Tony Lindgren <tony@atomide.com> + +description: + The wl12xx/wl18xx chips can be connected via SPI or via SDIO. + Note that the *-clock-frequency properties assume internal clocks. In case + of external clocks, new bindings (for parsing the clock nodes) have to be + added. + +properties: + compatible: + enum: + - ti,wl1271 + - ti,wl1273 + - ti,wl1281 + - ti,wl1283 + - ti,wl1285 + - ti,wl1801 + - ti,wl1805 + - ti,wl1807 + - ti,wl1831 + - ti,wl1835 + - ti,wl1837 + + reg: + maxItems: 1 + description: + This is required when connected via SPI, and optional when connected via + SDIO. + + spi-max-frequency: true + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + items: + - const: irq + - const: wakeup + + vwlan-supply: + description: + Points to the node of the regulator that powers/enable the wl12xx/wl18xx + chip. This is required when connected via SPI. + + + ref-clock-frequency: + description: Reference clock frequency. + + tcxo-clock-frequency: + description: TCXO clock frequency. + + clock-xtal: + $ref: /schemas/types.yaml#/definitions/flag + description: Indicates that the clock is generated from XTAL. + +required: + - compatible + - interrupts + +if: + properties: + compatible: + contains: + enum: + - ti,wl1271 + - ti,wl1273 + - ti,wl1281 + - ti,wl1283 +then: + required: + - ref-clock-frequency + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + // For wl12xx family: + spi1 { + #address-cells = <1>; + #size-cells = <0>; + + wlcore1: wlcore@1 { + compatible = "ti,wl1271"; + reg = <1>; + spi-max-frequency = <48000000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + vwlan-supply = <&vwlan_fixed>; + clock-xtal; + ref-clock-frequency = <38400000>; + }; + }; + + // For wl18xx family: + spi2 { + #address-cells = <1>; + #size-cells = <0>; + + wlcore2: wlcore@0 { + compatible = "ti,wl1835"; + reg = <0>; + spi-max-frequency = <48000000>; + interrupts = <27 IRQ_TYPE_EDGE_RISING>; + vwlan-supply = <&vwlan_fixed>; + }; + }; + + // SDIO example: + mmc3 { + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + + #address-cells = <1>; + #size-cells = <0>; + + wlcore3: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/numa.txt b/Documentation/devicetree/bindings/numa.txt index 21b35053ca5a..42f282c2f3cc 100644 --- a/Documentation/devicetree/bindings/numa.txt +++ b/Documentation/devicetree/bindings/numa.txt @@ -103,7 +103,51 @@ Example: }; ============================================================================== -4 - Example dts +4 - Empty memory nodes +============================================================================== + +Empty memory nodes, which no memory resides in, are allowed. There are no +device nodes for these empty memory nodes. However, the NUMA node IDs and +distance maps are still valid and memory may be added into them through +hotplug afterwards. + +Example: + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + numa-node-id = <0>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + numa-node-id = <1>; + }; + + /* Empty memory node 2 and 3 */ + distance-map { + compatible = "numa-distance-map-v1"; + distance-matrix = <0 0 10>, + <0 1 20>, + <0 2 40>, + <0 3 20>, + <1 0 20>, + <1 1 10>, + <1 2 20>, + <1 3 40>, + <2 0 40>, + <2 1 20>, + <2 2 10>, + <2 3 20>, + <3 0 20>, + <3 1 40>, + <3 2 20>, + <3 3 10>; + }; + +============================================================================== +5 - Example dts ============================================================================== Dual socket system consists of 2 boards connected through ccn bus and diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml new file mode 100644 index 000000000000..ef1d424ec299 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/apple,pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple PCIe host controller + +maintainers: + - Mark Kettenis <kettenis@openbsd.org> + +description: | + The Apple PCIe host controller is a PCIe host controller with + multiple root ports present in Apple ARM SoC platforms, including + various iPhone and iPad devices and the "Apple Silicon" Macs. + The controller incorporates Synopsys DesigWare PCIe logic to + implements its root ports. But the ATU found on most DesignWare + PCIe host bridges is absent. + + All root ports share a single ECAM space, but separate GPIOs are + used to take the PCI devices on those ports out of reset. Therefore + the standard "reset-gpios" and "max-link-speed" properties appear on + the child nodes that represent the PCI bridges that correspond to + the individual root ports. + + MSIs are handled by the PCIe controller and translated into regular + interrupts. A range of 32 MSIs is provided. These 32 MSIs can be + distributed over the root ports as the OS sees fit by programming + the PCIe controller's port registers. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - const: apple,t8103-pcie + - const: apple,pcie + + reg: + minItems: 3 + maxItems: 5 + + reg-names: + minItems: 3 + items: + - const: config + - const: rc + - const: port0 + - const: port1 + - const: port2 + + ranges: + minItems: 2 + maxItems: 2 + + interrupts: + description: + Interrupt specifiers, one for each root port. + minItems: 1 + maxItems: 3 + + msi-parent: true + + msi-ranges: + maxItems: 1 + + iommu-map: true + iommu-map-mask: true + +required: + - compatible + - reg + - reg-names + - bus-range + - interrupts + - msi-controller + - msi-parent + - msi-ranges + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/apple-aic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie0: pcie@690000000 { + compatible = "apple,t8103-pcie", "apple,pcie"; + device_type = "pci"; + + reg = <0x6 0x90000000 0x0 0x1000000>, + <0x6 0x80000000 0x0 0x100000>, + <0x6 0x81000000 0x0 0x4000>, + <0x6 0x82000000 0x0 0x4000>, + <0x6 0x83000000 0x0 0x4000>; + reg-names = "config", "rc", "port0", "port1", "port2"; + + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; + + iommu-map = <0x100 &dart0 1 1>, + <0x200 &dart1 1 1>, + <0x300 &dart2 1 1>; + iommu-map-mask = <0xff00>; + + bus-range = <0 3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; + + power-domains = <&ps_apcie>, <&ps_apcie_gp>, <&ps_pcie_ref>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 152 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 153 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 33 0>; + max-link-speed = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index b9589a0daa5c..1fe102743f82 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -88,6 +88,7 @@ required: allOf: - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index fb95c276a986..7b0776457178 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml index 295840cf612f..32a3b7665ff5 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml @@ -19,6 +19,7 @@ properties: - renesas,r8a774b1-pcie-ep # RZ/G2N - renesas,r8a774c0-pcie-ep # RZ/G2E - renesas,r8a774e1-pcie-ep # RZ/G2H + - renesas,r8a7795-pcie-ep # R-Car H3 - const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2 reg: diff --git a/Documentation/devicetree/bindings/reserved-memory/memory-region.yaml b/Documentation/devicetree/bindings/reserved-memory/memory-region.yaml new file mode 100644 index 000000000000..83dfe499a259 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/memory-region.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/memory-region.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Reserved Memory Region Device Tree Binding + +maintainers: + - devicetree-spec@vger.kernel.org + +description: | + Regions in the /reserved-memory node may be referenced by other device + nodes by adding a memory-region property to the device node. + +select: true + +properties: + memory-region: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: > + Phandle to a /reserved-memory child node assigned to the device. + + memory-region-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: > + A list of names, one for each corresponding entry in the + memory-region property + +additionalProperties: true + +examples: + - | + fb0: video@12300000 { + /* ... */ + reg = <0x12300000 0x1000>; + memory-region = <&display_reserved>; + }; + +... diff --git a/Documentation/devicetree/bindings/reserved-memory/ramoops.txt b/Documentation/devicetree/bindings/reserved-memory/ramoops.txt deleted file mode 100644 index b571ef6dab0f..000000000000 --- a/Documentation/devicetree/bindings/reserved-memory/ramoops.txt +++ /dev/null @@ -1,66 +0,0 @@ -Ramoops oops/panic logger -========================= - -ramoops provides persistent RAM storage for oops and panics, so they can be -recovered after a reboot. This is a child-node of "/reserved-memory", and -is named "ramoops" after the backend, rather than "pstore" which is the -subsystem. - -Parts of this storage may be set aside for other persistent log buffers, such -as kernel log messages, or for optional ECC error-correction data. The total -size of these optional buffers must fit in the reserved region. - -Any remaining space will be used for a circular buffer of oops and panic -records. These records have a configurable size, with a size of 0 indicating -that they should be disabled. - -At least one of "record-size", "console-size", "ftrace-size", or "pmsg-size" -must be set non-zero, but are otherwise optional as listed below. - - -Required properties: - -- compatible: must be "ramoops" - -- reg: region of memory that is preserved between reboots - - -Optional properties: - -- ecc-size: enables ECC support and specifies ECC buffer size in bytes - (defaults to 0: no ECC) - -- record-size: maximum size in bytes of each kmsg dump. - (defaults to 0: disabled) - -- console-size: size in bytes of log buffer reserved for kernel messages - (defaults to 0: disabled) - -- ftrace-size: size in bytes of log buffer reserved for function tracing and - profiling (defaults to 0: disabled) - -- pmsg-size: size in bytes of log buffer reserved for userspace messages - (defaults to 0: disabled) - -- mem-type: if present, sets the type of mapping is to be used to map the - reserved region. mem-type: 0 = write-combined (default), 1 = unbuffered, - 2 = cached. - -- unbuffered: deprecated, use mem_type instead. If present, and mem_type is - not specified, it is equivalent to mem_type = 1 and uses unbuffered mappings - to map the reserved region (defaults to buffered mappings mem_type = 0). If - both are specified -- "mem_type" overrides "unbuffered". - -- max-reason: if present, sets maximum type of kmsg dump reasons to store - (defaults to 2: log Oopses and Panics). This can be set to INT_MAX to - store all kmsg dumps. See include/linux/kmsg_dump.h KMSG_DUMP_* for other - kmsg dump reason values. Setting this to 0 (KMSG_DUMP_UNDEF), means the - reason filtering will be controlled by the printk.always_kmsg_dump boot - param: if unset, it will be KMSG_DUMP_OOPS, otherwise KMSG_DUMP_MAX. - -- no-dump-oops: deprecated, use max_reason instead. If present, and - max_reason is not specified, it is equivalent to max_reason = 1 - (KMSG_DUMP_PANIC). - -- flags: if present, pass ramoops behavioral flags (defaults to 0, - see include/linux/pstore_ram.h RAMOOPS_FLAG_* for flag values). diff --git a/Documentation/devicetree/bindings/reserved-memory/ramoops.yaml b/Documentation/devicetree/bindings/reserved-memory/ramoops.yaml new file mode 100644 index 000000000000..f4c351a69542 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/ramoops.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reserved-memory/ramoops.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Ramoops oops/panic logger + +description: | + ramoops provides persistent RAM storage for oops and panics, so they can be + recovered after a reboot. This is a child-node of "/reserved-memory", and + is named "ramoops" after the backend, rather than "pstore" which is the + subsystem. + + Parts of this storage may be set aside for other persistent log buffers, such + as kernel log messages, or for optional ECC error-correction data. The total + size of these optional buffers must fit in the reserved region. + + Any remaining space will be used for a circular buffer of oops and panic + records. These records have a configurable size, with a size of 0 indicating + that they should be disabled. + + At least one of "record-size", "console-size", "ftrace-size", or "pmsg-size" + must be set non-zero, but are otherwise optional as listed below. + +maintainers: + - Kees Cook <keescook@chromium.org> + +allOf: + - $ref: "reserved-memory.yaml" + +properties: + compatible: + const: ramoops + + reg: + description: region of memory that is preserved between reboots + + ecc-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: enables ECC support and specifies ECC buffer size in bytes + default: 0 # no ECC + + record-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: maximum size in bytes of each kmsg dump + default: 0 + + console-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: size in bytes of log buffer reserved for kernel messages + default: 0 + + ftrace-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: size in bytes of log buffer reserved for function tracing and profiling + default: 0 + + pmsg-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: size in bytes of log buffer reserved for userspace messages + default: 0 + + mem-type: + $ref: /schemas/types.yaml#/definitions/uint32 + description: if present, sets the type of mapping is to be used to map the reserved region. + default: 0 + oneOf: + - const: 0 + description: write-combined + - const: 1 + description: unbuffered + - const: 2 + description: cached + + max-reason: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 2 # log oopses and panics + maximum: 0x7fffffff + description: | + If present, sets maximum type of kmsg dump reasons to store. + This can be set to INT_MAX to store all kmsg dumps. + See include/linux/kmsg_dump.h KMSG_DUMP_* for other kmsg dump reason values. + Setting this to 0 (KMSG_DUMP_UNDEF), means the reason filtering will be + controlled by the printk.always_kmsg_dump boot param. + If unset, it will be 2 (KMSG_DUMP_OOPS), otherwise 5 (KMSG_DUMP_MAX). + + flags: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + description: | + If present, pass ramoops behavioral flags + (see include/linux/pstore_ram.h RAMOOPS_FLAG_* for flag values). + + no-dump-oops: + deprecated: true + type: boolean + description: | + Use max_reason instead. If present, and max_reason is not specified, + it is equivalent to max_reason = 1 (KMSG_DUMP_PANIC). + + unbuffered: + deprecated: true + type: boolean + description: | + Use mem_type instead. If present, and mem_type is not specified, + it is equivalent to mem_type = 1 and uses unbuffered mappings to map + the reserved region (defaults to buffered mappings mem_type = 0). + If both are specified -- "mem_type" overrides "unbuffered". + +unevaluatedProperties: false + +required: + - compatible + - reg + +anyOf: + - required: [record-size] + - required: [console-size] + - required: [ftrace-size] + - required: [pmsg-size] + +examples: + - | + / { + compatible = "foo"; + model = "foo"; + #address-cells = <1>; + #size-cells = <1>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@bfdf0000 { + compatible = "ramoops"; + reg = <0xbfdf0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt index 39b5f4c5a511..1810701a8509 100644 --- a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt +++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt @@ -1,171 +1 @@ -*** Reserved memory regions *** - -Reserved memory is specified as a node under the /reserved-memory node. -The operating system shall exclude reserved memory from normal usage -one can create child nodes describing particular reserved (excluded from -normal use) memory regions. Such memory regions are usually designed for -the special usage by various device drivers. - -Parameters for each memory region can be encoded into the device tree -with the following nodes: - -/reserved-memory node ---------------------- -#address-cells, #size-cells (required) - standard definition - - Should use the same values as the root node -ranges (required) - standard definition - - Should be empty - -/reserved-memory/ child nodes ------------------------------ -Each child of the reserved-memory node specifies one or more regions of -reserved memory. Each child node may either use a 'reg' property to -specify a specific range of reserved memory, or a 'size' property with -optional constraints to request a dynamically allocated block of memory. - -Following the generic-names recommended practice, node names should -reflect the purpose of the node (ie. "framebuffer" or "dma-pool"). Unit -address (@<address>) should be appended to the name if the node is a -static allocation. - -Properties: -Requires either a) or b) below. -a) static allocation - reg (required) - standard definition -b) dynamic allocation - size (required) - length based on parent's #size-cells - - Size in bytes of memory to reserve. - alignment (optional) - length based on parent's #size-cells - - Address boundary for alignment of allocation. - alloc-ranges (optional) - prop-encoded-array (address, length pairs). - - Specifies regions of memory that are - acceptable to allocate from. - -If both reg and size are present, then the reg property takes precedence -and size is ignored. - -Additional properties: -compatible (optional) - standard definition - - may contain the following strings: - - shared-dma-pool: This indicates a region of memory meant to be - used as a shared pool of DMA buffers for a set of devices. It can - be used by an operating system to instantiate the necessary pool - management subsystem if necessary. - - restricted-dma-pool: This indicates a region of memory meant to be - used as a pool of restricted DMA buffers for a set of devices. The - memory region would be the only region accessible to those devices. - When using this, the no-map and reusable properties must not be set, - so the operating system can create a virtual mapping that will be used - for synchronization. The main purpose for restricted DMA is to - mitigate the lack of DMA access control on systems without an IOMMU, - which could result in the DMA accessing the system memory at - unexpected times and/or unexpected addresses, possibly leading to data - leakage or corruption. The feature on its own provides a basic level - of protection against the DMA overwriting buffer contents at - unexpected times. However, to protect against general data leakage and - system memory corruption, the system needs to provide way to lock down - the memory access, e.g., MPU. Note that since coherent allocation - needs remapping, one must set up another device coherent pool by - shared-dma-pool and use dma_alloc_from_dev_coherent instead for atomic - coherent allocation. - - vendor specific string in the form <vendor>,[<device>-]<usage> -no-map (optional) - empty property - - Indicates the operating system must not create a virtual mapping - of the region as part of its standard mapping of system memory, - nor permit speculative access to it under any circumstances other - than under the control of the device driver using the region. -reusable (optional) - empty property - - The operating system can use the memory in this region with the - limitation that the device driver(s) owning the region need to be - able to reclaim it back. Typically that means that the operating - system can use that region to store volatile or cached data that - can be otherwise regenerated or migrated elsewhere. - -A node must not carry both the no-map and the reusable property as these are -logically contradictory. - -Linux implementation note: -- If a "linux,cma-default" property is present, then Linux will use the - region for the default pool of the contiguous memory allocator. - -- If a "linux,dma-default" property is present, then Linux will use the - region for the default pool of the consistent DMA allocator. - -Device node references to reserved memory ------------------------------------------ -Regions in the /reserved-memory node may be referenced by other device -nodes by adding a memory-region property to the device node. - -memory-region (optional) - phandle, specifier pairs to children of /reserved-memory -memory-region-names (optional) - a list of names, one for each corresponding - entry in the memory-region property - -Example -------- -This example defines 4 contiguous regions for Linux kernel: -one default of all device drivers (named linux,cma@72000000 and 64MiB in size), -one dedicated to the framebuffer device (named framebuffer@78000000, 8MiB), -one for multimedia processing (named multimedia-memory@77000000, 64MiB), and -one for restricted dma pool (named restricted_dma_reserved@0x50000000, 64MiB). - -/ { - #address-cells = <1>; - #size-cells = <1>; - - memory { - reg = <0x40000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x4000000>; - alignment = <0x2000>; - linux,cma-default; - }; - - display_reserved: framebuffer@78000000 { - reg = <0x78000000 0x800000>; - }; - - multimedia_reserved: multimedia@77000000 { - compatible = "acme,multimedia-memory"; - reg = <0x77000000 0x4000000>; - }; - - restricted_dma_reserved: restricted_dma_reserved { - compatible = "restricted-dma-pool"; - reg = <0x50000000 0x4000000>; - }; - }; - - /* ... */ - - fb0: video@12300000 { - memory-region = <&display_reserved>; - /* ... */ - }; - - scaler: scaler@12500000 { - memory-region = <&multimedia_reserved>; - /* ... */ - }; - - codec: codec@12600000 { - memory-region = <&multimedia_reserved>; - /* ... */ - }; - - pcie_device: pcie_device@0,0 { - reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 - 0x83010000 0x0 0x00100000 0x0 0x00100000>; - memory-region = <&restricted_dma_reserved>; - /* ... */ - }; -}; +This file has been moved to reserved-memory.yaml. diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml new file mode 100644 index 000000000000..7a0744052ff6 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/reserved-memory.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: /reserved-memory Child Node Common Device Tree Bindings + +maintainers: + - devicetree-spec@vger.kernel.org + +description: > + Reserved memory is specified as a node under the /reserved-memory node. The + operating system shall exclude reserved memory from normal usage one can + create child nodes describing particular reserved (excluded from normal use) + memory regions. Such memory regions are usually designed for the special + usage by various device drivers. + + Each child of the reserved-memory node specifies one or more regions + of reserved memory. Each child node may either use a 'reg' property to + specify a specific range of reserved memory, or a 'size' property with + optional constraints to request a dynamically allocated block of + memory. + + Following the generic-names recommended practice, node names should + reflect the purpose of the node (ie. "framebuffer" or "dma-pool"). + Unit address (@<address>) should be appended to the name if the node + is a static allocation. + +properties: + reg: true + + size: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + description: > + Length based on parent's \#size-cells. Size in bytes of memory to + reserve. + + alignment: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + description: > + Length based on parent's \#size-cells. Address boundary for + alignment of allocation. + + alloc-ranges: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: > + Address and Length pairs. Specifies regions of memory that are + acceptable to allocate from. + + no-map: + type: boolean + description: > + Indicates the operating system must not create a virtual mapping + of the region as part of its standard mapping of system memory, + nor permit speculative access to it under any circumstances other + than under the control of the device driver using the region. + + reusable: + type: boolean + description: > + The operating system can use the memory in this region with the + limitation that the device driver(s) owning the region need to be + able to reclaim it back. Typically that means that the operating + system can use that region to store volatile or cached data that + can be otherwise regenerated or migrated elsewhere. + +allOf: + - if: + required: + - no-map + + then: + not: + required: + - reusable + + - if: + required: + - reusable + + then: + not: + required: + - no-map + +oneOf: + - required: + - reg + + - required: + - size + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/reserved-memory/shared-dma-pool.yaml b/Documentation/devicetree/bindings/reserved-memory/shared-dma-pool.yaml new file mode 100644 index 000000000000..a4bf757d6881 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/shared-dma-pool.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/shared-dma-pool.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: /reserved-memory DMA pool node bindings + +maintainers: + - devicetree-spec@vger.kernel.org + +allOf: + - $ref: "reserved-memory.yaml" + +properties: + compatible: + oneOf: + - const: shared-dma-pool + description: > + This indicates a region of memory meant to be used as a shared + pool of DMA buffers for a set of devices. It can be used by an + operating system to instantiate the necessary pool management + subsystem if necessary. + + - const: restricted-dma-pool + description: > + This indicates a region of memory meant to be used as a pool + of restricted DMA buffers for a set of devices. The memory + region would be the only region accessible to those devices. + When using this, the no-map and reusable properties must not + be set, so the operating system can create a virtual mapping + that will be used for synchronization. The main purpose for + restricted DMA is to mitigate the lack of DMA access control + on systems without an IOMMU, which could result in the DMA + accessing the system memory at unexpected times and/or + unexpected addresses, possibly leading to data leakage or + corruption. The feature on its own provides a basic level of + protection against the DMA overwriting buffer contents at + unexpected times. However, to protect against general data + leakage and system memory corruption, the system needs to + provide way to lock down the memory access, e.g., MPU. Note + that since coherent allocation needs remapping, one must set + up another device coherent pool by shared-dma-pool and use + dma_alloc_from_dev_coherent instead for atomic coherent + allocation. + + linux,cma-default: + type: boolean + description: > + If this property is present, then Linux will use the region for + the default pool of the contiguous memory allocator. + + linux,dma-default: + type: boolean + description: > + If this property is present, then Linux will use the region for + the default pool of the consistent DMA allocator. + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x4000000>; + alignment = <0x2000>; + linux,cma-default; + }; + + display_reserved: framebuffer@78000000 { + reg = <0x78000000 0x800000>; + }; + + restricted_dma_reserved: restricted-dma-pool@50000000 { + compatible = "restricted-dma-pool"; + reg = <0x50000000 0x4000000>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index e534f6a7cfa1..aa5fb64d57eb 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -31,9 +31,7 @@ properties: - sifive,bullet0 - sifive,e5 - sifive,e7 - - sifive,e51 - sifive,e71 - - sifive,u54-mc - sifive,u74-mc - sifive,u54 - sifive,u74 @@ -41,6 +39,12 @@ properties: - sifive,u7 - canaan,k210 - const: riscv + - items: + - enum: + - sifive,e51 + - sifive,u54-mc + - const: sifive,rocket0 + - const: riscv - const: riscv # Simulator only description: Identifies that the hart uses the RISC-V instruction set diff --git a/Documentation/devicetree/bindings/rng/omap_rng.txt b/Documentation/devicetree/bindings/rng/omap_rng.txt deleted file mode 100644 index ea434ce50f36..000000000000 --- a/Documentation/devicetree/bindings/rng/omap_rng.txt +++ /dev/null @@ -1,38 +0,0 @@ -OMAP SoC and Inside-Secure HWRNG Module - -Required properties: - -- compatible : Should contain entries for this and backward compatible - RNG versions: - - "ti,omap2-rng" for OMAP2. - - "ti,omap4-rng" for OMAP4, OMAP5 and AM33XX. - - "inside-secure,safexcel-eip76" for SoCs with EIP76 IP block - Note that these two versions are incompatible. -- ti,hwmods: Name of the hwmod associated with the RNG module -- reg : Offset and length of the register set for the module -- interrupts : the interrupt number for the RNG module. - Used for "ti,omap4-rng" and "inside-secure,safexcel-eip76" -- clocks: the trng clock source. Only mandatory for the - "inside-secure,safexcel-eip76" compatible, the second clock is - needed for the Armada 7K/8K SoCs -- clock-names: mandatory if there is a second clock, in this case the - name must be "core" for the first clock and "reg" for the second - one - - -Example: -/* AM335x */ -rng: rng@48310000 { - compatible = "ti,omap4-rng"; - ti,hwmods = "rng"; - reg = <0x48310000 0x2000>; - interrupts = <111>; -}; - -/* SafeXcel IP-76 */ -trng: rng@f2760000 { - compatible = "inside-secure,safexcel-eip76"; - reg = <0xf2760000 0x7d>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cpm_syscon0 1 25>; -}; diff --git a/Documentation/devicetree/bindings/rng/omap_rng.yaml b/Documentation/devicetree/bindings/rng/omap_rng.yaml new file mode 100644 index 000000000000..010188cdbec8 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/omap_rng.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/omap_rng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OMAP SoC and Inside-Secure HWRNG Module + +maintainers: + - Jayesh Choudhary <j-choudhary@ti.com> + +properties: + compatible: + enum: + - ti,omap2-rng + - ti,omap4-rng + - inside-secure,safexcel-eip76 + + ti,hwmods: + const: rng + deprecated: true + description: Name of the hwmod associated with the RNG module + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: EIP150 gatable clock + - description: Main gatable clock + + clock-names: + minItems: 1 + items: + - const: core + - const: reg + + +allOf: + - if: + properties: + compatible: + contains: + enum: + - ti,omap4-rng + - inside-secure,safexcel-eip76 + + then: + required: + - interrupts + + - if: + properties: + compatible: + contains: + enum: + - inside-secure,safexcel-eip76 + + then: + required: + - clocks + + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + /* AM335x */ + rng: rng@48310000 { + compatible = "ti,omap4-rng"; + ti,hwmods = "rng"; + reg = <0x48310000 0x2000>; + interrupts = <111>; + }; + - | + /* SafeXcel IP-76 */ + trng: rng@f2760000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0xf2760000 0x7d>; + interrupts = <0 59 4>; + clocks = <&cpm_syscon0 1 25>; + }; + +... diff --git a/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml new file mode 100644 index 000000000000..6876407124dc --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# # Copyright (c) 2018 Google LLC +# # Copyright (c) 2021 Aspeed Technology Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Aspeed UART Routing Controller + +maintainers: + - Oskar Senft <osk@google.com> + - Chia-Wei Wang <chiawei_wang@aspeedtech.com> + +description: + The Aspeed UART routing control allow to dynamically route the inputs for + the built-in UARTS and physical serial I/O ports. + + This allows, for example, to connect the output of UART to another UART. + This can be used to enable Host <-> BMC communication via UARTs, e.g. to + allow access to the Host's serial console. + + This driver is for the BMC side. The sysfs files allow the BMC userspace + which owns the system configuration policy, to configure how UARTs and + physical serial I/O ports are routed. + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-uart-routing + - aspeed,ast2500-uart-routing + - aspeed,ast2600-uart-routing + reg: + maxItems: 1 + +required: + - compatible + +additionalProperties: false + +examples: + - | + lpc: lpc@1e789000 { + compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + uart_routing: uart-routing@98 { + compatible = "aspeed,ast2600-uart-routing"; + reg = <0x98 0x8>; + }; + }; diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 3eda5049d183..939cf2418445 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -60,7 +60,7 @@ properties: type: boolean patternProperties: - "^([a-z]*-)?sram(-section)?@[a-f0-9]+$": + "^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$": type: object description: Each child of the sram node specifies a region of reserved memory. diff --git a/Documentation/devicetree/bindings/submitting-patches.rst b/Documentation/devicetree/bindings/submitting-patches.rst index 8087780f1685..36a17b250ccc 100644 --- a/Documentation/devicetree/bindings/submitting-patches.rst +++ b/Documentation/devicetree/bindings/submitting-patches.rst @@ -63,6 +63,9 @@ I. For patch submitters string that is matched by the driver (as in the "nvidia,tegra20-pcie" example above). + 9) Bindings are actively used by multiple projects other than the Linux + Kernel, extra care and consideration may need to be taken when making changes + to existing bindings. II. For kernel maintainers ========================== diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml index b9ca8ef4f2be..95ac1c18334d 100644 --- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml @@ -20,6 +20,8 @@ properties: compatible: enum: - samsung,exynos7-ufs + - samsung,exynosautov9-ufs + - samsung,exynosautov9-ufs-vh reg: items: @@ -54,6 +56,14 @@ properties: phy-names: const: ufs-phy + samsung,sysreg: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: Should be phandle/offset pair. The phandle to the syscon node + which indicates the FSYSx sysreg interface and the offset of + the control register for UFS io coherency setting. + + dma-coherent: true + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/usb/udc-xilinx.txt b/Documentation/devicetree/bindings/usb/udc-xilinx.txt deleted file mode 100644 index 47b4e397a08d..000000000000 --- a/Documentation/devicetree/bindings/usb/udc-xilinx.txt +++ /dev/null @@ -1,18 +0,0 @@ -Xilinx USB2 device controller - -Required properties: -- compatible : Should be "xlnx,usb2-device-4.00.a" -- reg : Physical base address and size of the USB2 - device registers map. -- interrupts : Should contain single irq line of USB2 device - controller -- xlnx,has-builtin-dma : if DMA is included - -Example: - axi-usb2-device@42e00000 { - compatible = "xlnx,usb2-device-4.00.a"; - interrupts = <0x0 0x39 0x1>; - reg = <0x42e00000 0x10000>; - xlnx,has-builtin-dma; - }; - diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml new file mode 100644 index 000000000000..04c123c7252a --- /dev/null +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/xlnx,usb2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx udc controller + +maintainers: + - Manish Narani <manish.narani@xilinx.com> + +properties: + compatible: + const: xlnx,usb2-device-4.00.a + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + xlnx,has-builtin-dma: + description: + If present, hardware has dma capability. + type: boolean + + clocks: + minItems: 1 + + clock-names: + const: s_axi_aclk + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + axi-usb2-device@42e00000 { + compatible = "xlnx,usb2-device-4.00.a"; + interrupts = <0x0 0x39 0x1>; + reg = <0xee000000 0xc00>; + xlnx,has-builtin-dma; + }; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 0aa9e7676fcf..a826ac73feec 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1104,6 +1104,8 @@ patternProperties: description: Spansion Inc. "^sparkfun,.*": description: SparkFun Electronics + "^spinalhdl,.*": + description: SpinalHDL "^sprd,.*": description: Spreadtrum Communications Inc. "^sst,.*": diff --git a/Documentation/devicetree/bindings/w1/w1-gpio.txt b/Documentation/devicetree/bindings/w1/w1-gpio.txt deleted file mode 100644 index 3d6554eac240..000000000000 --- a/Documentation/devicetree/bindings/w1/w1-gpio.txt +++ /dev/null @@ -1,27 +0,0 @@ -w1-gpio devicetree bindings - -Required properties: - - - compatible: "w1-gpio" - - gpios: one or two GPIO specs: - - the first one is used as data I/O pin - - the second one is optional. If specified, it is used as - enable pin for an external pin pullup. - -Optional properties: - - - linux,open-drain: if specified, the data pin is considered in - open-drain mode. - -Also refer to the generic w1.txt document. - -Examples: - - onewire { - compatible = "w1-gpio"; - gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; - - battery { - // ... - }; - }; diff --git a/Documentation/devicetree/bindings/w1/w1-gpio.yaml b/Documentation/devicetree/bindings/w1/w1-gpio.yaml new file mode 100644 index 000000000000..8eef2380161b --- /dev/null +++ b/Documentation/devicetree/bindings/w1/w1-gpio.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/w1/w1-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bitbanged GPIO 1-Wire Bus Device Tree Bindings + +maintainers: + - Daniel Mack <zonque@gmail.com> + +properties: + compatible: + const: w1-gpio + + gpios: + minItems: 1 + items: + - description: Data I/O pin + - description: Enable pin for an external pull-up resistor + + linux,open-drain: + type: boolean + description: > + If specified, the data pin is considered in open-drain mode. + +required: + - compatible + - gpios + +additionalProperties: + type: object + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + onewire { + compatible = "w1-gpio"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + }; + +... diff --git a/Documentation/devicetree/bindings/writing-bindings.rst b/Documentation/devicetree/bindings/writing-bindings.rst index f7dfb98c156e..18d9e0689d49 100644 --- a/Documentation/devicetree/bindings/writing-bindings.rst +++ b/Documentation/devicetree/bindings/writing-bindings.rst @@ -44,7 +44,7 @@ Properties of prior implementations. DO add new compatibles in case there are new features or bugs. -- DO use a vendor prefix on device specific property names. Consider if +- DO use a vendor prefix on device-specific property names. Consider if properties could be common among devices of the same class. Check other existing bindings for similar devices. diff --git a/Documentation/devicetree/bindings/writing-schema.rst b/Documentation/devicetree/bindings/writing-schema.rst index 23d6579aea2c..ea21c72aeb37 100644 --- a/Documentation/devicetree/bindings/writing-schema.rst +++ b/Documentation/devicetree/bindings/writing-schema.rst @@ -4,7 +4,7 @@ Writing Devicetree Bindings in json-schema ========================================== Devicetree bindings are written using json-schema vocabulary. Schema files are -written in a JSON compatible subset of YAML. YAML is used instead of JSON as it +written in a JSON-compatible subset of YAML. YAML is used instead of JSON as it is considered more human readable and has some advantages such as allowing comments (Prefixed with '#'). @@ -22,16 +22,16 @@ $id URI typically containing the binding's filename and path. For DT schema, it must begin with "http://devicetree.org/schemas/". The URL is used in constructing references to other files specified in schema "$ref" properties. A $ref value - with a leading '/' will have the hostname prepended. A $ref value a relative - path or filename only will be prepended with the hostname and path components - of the current schema file's '$id' value. A URL is used even for local files, - but there may not actually be files present at those locations. + with a leading '/' will have the hostname prepended. A $ref value with only a + relative path or filename will be prepended with the hostname and path + components of the current schema file's '$id' value. A URL is used even for + local files, but there may not actually be files present at those locations. $schema Indicates the meta-schema the schema file adheres to. title - A one line description on the contents of the binding schema. + A one-line description on the contents of the binding schema. maintainers A DT specific property. Contains a list of email address(es) @@ -45,8 +45,8 @@ description select Optional. A json-schema used to match nodes for applying the - schema. By default without 'select', nodes are matched against their possible - compatible string values or node name. Most bindings should not need select. + schema. By default, without 'select', nodes are matched against their possible + compatible-string values or node name. Most bindings should not need select. allOf Optional. A list of other schemas to include. This is used to @@ -56,7 +56,8 @@ allOf properties A set of sub-schema defining all the DT properties for the binding. The exact schema syntax depends on whether properties are known, - common properties (e.g. 'interrupts') or are binding/vendor specific properties. + common properties (e.g. 'interrupts') or are binding/vendor-specific + properties. A property can also define a child DT node with child properties defined under it. @@ -81,23 +82,23 @@ Property Schema The 'properties' section of the schema contains all the DT properties for a binding. Each property contains a set of constraints using json-schema -vocabulary for that property. The properties schemas are what is used for +vocabulary for that property. The properties schemas are what are used for validation of DT files. -For common properties, only additional constraints not covered by the common +For common properties, only additional constraints not covered by the common, binding schema need to be defined such as how many values are valid or what possible values are valid. -Vendor specific properties will typically need more detailed schema. With the +Vendor-specific properties will typically need more detailed schema. With the exception of boolean properties, they should have a reference to a type in schemas/types.yaml. A "description" property is always required. -The Devicetree schemas don't exactly match the YAML encoded DT data produced by +The Devicetree schemas don't exactly match the YAML-encoded DT data produced by dtc. They are simplified to make them more compact and avoid a bunch of boilerplate. The tools process the schema files to produce the final schema for validation. There are currently 2 transformations the tools perform. -The default for arrays in json-schema is they are variable sized and allow more +The default for arrays in json-schema is they are variable-sized and allow more entries than explicitly defined. This can be restricted by defining 'minItems', 'maxItems', and 'additionalItems'. However, for DeviceTree Schemas, a fixed size is desired in most cases, so these properties are added based on the diff --git a/Documentation/w1/masters/w1-gpio.rst b/Documentation/w1/masters/w1-gpio.rst index 18fdb7366372..15236605503b 100644 --- a/Documentation/w1/masters/w1-gpio.rst +++ b/Documentation/w1/masters/w1-gpio.rst @@ -11,7 +11,7 @@ Description GPIO 1-wire bus master driver. The driver uses the GPIO API to control the wire and the GPIO pin can be specified using GPIO machine descriptor tables. It is also possible to define the master using device tree, see -Documentation/devicetree/bindings/w1/w1-gpio.txt +Documentation/devicetree/bindings/w1/w1-gpio.yaml Example (mach-at91) diff --git a/MAINTAINERS b/MAINTAINERS index dede1aa3320d..a941b85a20c9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1412,7 +1412,7 @@ F: Documentation/devicetree/bindings/auxdisplay/arm,versatile-lcd.yaml F: Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml F: Documentation/devicetree/bindings/i2c/i2c-versatile.txt F: Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt -F: Documentation/devicetree/bindings/mtd/arm-versatile.txt +F: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml F: arch/arm/boot/dts/arm-realview-* F: arch/arm/boot/dts/integrator* F: arch/arm/boot/dts/versatile* @@ -1723,6 +1723,7 @@ T: git https://github.com/AsahiLinux/linux.git F: Documentation/devicetree/bindings/arm/apple.yaml F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml +F: Documentation/devicetree/bindings/pci/apple,pcie.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml F: arch/arm64/boot/dts/apple/ F: drivers/irqchip/irq-apple-aic.c @@ -1751,7 +1752,7 @@ R: Joel Stanley <joel@jms.id.au> L: linux-i2c@vger.kernel.org L: openbmc@lists.ozlabs.org (moderated for non-subscribers) S: Maintained -F: Documentation/devicetree/bindings/i2c/i2c-aspeed.txt +F: Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml F: Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2400-i2c-ic.txt F: drivers/i2c/busses/i2c-aspeed.c F: drivers/irqchip/irq-aspeed-i2c-ic.c @@ -1878,10 +1879,10 @@ M: Linus Walleij <linus.walleij@linaro.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://github.com/ulli-kroll/linux.git -F: Documentation/devicetree/bindings/arm/gemini.txt +F: Documentation/devicetree/bindings/arm/gemini.yaml F: Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt -F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt +F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.yaml F: arch/arm/boot/dts/gemini* F: arch/arm/mach-gemini/ F: drivers/crypto/gemini/ @@ -3779,7 +3780,7 @@ L: bcm-kernel-feedback-list@broadcom.com L: netdev@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/net/brcm,bcmgenet.txt -F: Documentation/devicetree/bindings/net/brcm,unimac-mdio.txt +F: Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml F: drivers/net/ethernet/broadcom/genet/ F: drivers/net/ethernet/broadcom/unimac.h F: drivers/net/mdio/mdio-bcm-unimac.c @@ -9562,7 +9563,7 @@ F: include/linux/soc/ixp4xx/qmgr.h INTEL IXP4XX RANDOM NUMBER GENERATOR SUPPORT M: Deepak Saxena <dsaxena@plexity.net> S: Maintained -F: Documentation/devicetree/bindings/display/intel,ixp46x-rng.yaml +F: Documentation/devicetree/bindings/rng/intel,ixp46x-rng.yaml F: drivers/char/hw_random/ixp4xx-rng.c INTEL KEEM BAY DRM DRIVER @@ -13634,6 +13635,7 @@ NXP-NCI NFC DRIVER R: Charles Gorand <charles.gorand@effinnov.com> L: linux-nfc@lists.01.org (subscribers-only) S: Supported +F: Documentation/devicetree/bindings/net/nfc/nxp,nci.yaml F: drivers/nfc/nxp-nci NXP i.MX 8QXP/8QM JPEG V4L2 DRIVER @@ -13641,7 +13643,7 @@ M: Mirela Rabulea <mirela.rabulea@nxp.com> R: NXP Linux Team <linux-imx@nxp.com> L: linux-media@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/media/imx8-jpeg.yaml +F: Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml F: drivers/media/platform/imx-jpeg NZXT-KRAKEN2 HARDWARE MONITORING DRIVER @@ -15267,7 +15269,7 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git for-next/pstore F: Documentation/admin-guide/ramoops.rst F: Documentation/admin-guide/pstore-blk.rst -F: Documentation/devicetree/bindings/reserved-memory/ramoops.txt +F: Documentation/devicetree/bindings/reserved-memory/ramoops.yaml F: drivers/acpi/apei/erst.c F: drivers/firmware/efi/efi-pstore.c F: fs/pstore/ @@ -18632,7 +18634,7 @@ M: Santosh Shilimkar <ssantosh@kernel.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml -F: Documentation/devicetree/bindings/arm/keystone/ti,sci.txt +F: Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml F: Documentation/devicetree/bindings/clock/ti,sci-clk.yaml F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml @@ -18902,7 +18904,7 @@ M: Mark Greer <mgreer@animalcreek.com> L: linux-wireless@vger.kernel.org L: linux-nfc@lists.01.org (subscribers-only) S: Supported -F: Documentation/devicetree/bindings/net/nfc/trf7970a.txt +F: Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml F: drivers/nfc/trf7970a.c TI TSC2046 ADC DRIVER @@ -1400,17 +1400,17 @@ endif ifneq ($(dtstree),) -%.dtb: include/config/kernel.release scripts_dtc - $(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@ +%.dtb: dt_binding_check include/config/kernel.release scripts_dtc + $(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@ $(dtstree)/$*.dt.yaml -%.dtbo: include/config/kernel.release scripts_dtc - $(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@ +%.dtbo: dt_binding_check include/config/kernel.release scripts_dtc + $(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@ $(dtstree)/$*.dt.yaml PHONY += dtbs dtbs_install dtbs_check dtbs: include/config/kernel.release scripts_dtc $(Q)$(MAKE) $(build)=$(dtstree) -ifneq ($(filter dtbs_check, $(MAKECMDGOALS)),) +ifneq ($(filter dtbs_check %.dtb %.dtbo, $(MAKECMDGOALS)),) export CHECK_DTBS=y dtbs: dt_binding_check endif diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts index 9ce8d81250aa..b4c4ca7e1842 100644 --- a/arch/arm/boot/dts/omap3-gta04a5.dts +++ b/arch/arm/boot/dts/omap3-gta04a5.dts @@ -79,7 +79,7 @@ /* * for WL183x module see - * Documentation/devicetree/bindings/net/wireless/ti,wlcore.txt + * Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml */ &wifi_pwrseq { diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index 28311dd0fee6..02839d8b6202 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -84,33 +84,15 @@ void __init arm_dt_init_cpu_maps(void) return; for_each_of_cpu_node(cpu) { - const __be32 *cell; - int prop_bytes; - u32 hwid; + u32 hwid = of_get_cpu_hwid(cpu, 0); pr_debug(" * %pOF...\n", cpu); - /* - * A device tree containing CPU nodes with missing "reg" - * properties is considered invalid to build the - * cpu_logical_map. - */ - cell = of_get_property(cpu, "reg", &prop_bytes); - if (!cell || prop_bytes < sizeof(*cell)) { - pr_debug(" * %pOF missing reg property\n", cpu); - of_node_put(cpu); - return; - } /* * Bits n:24 must be set to 0 in the DT since the reg property * defines the MPIDR[23:0]. */ - do { - hwid = be32_to_cpu(*cell++); - prop_bytes -= sizeof(*cell); - } while (!hwid && prop_bytes > 0); - - if (prop_bytes || (hwid & ~MPIDR_HWID_BITMASK)) { + if (hwid & ~MPIDR_HWID_BITMASK) { of_node_put(cpu); return; } diff --git a/arch/arm/mach-bcm/bcm63xx_pmb.c b/arch/arm/mach-bcm/bcm63xx_pmb.c index 0e5a05bac3ea..003f1472ab45 100644 --- a/arch/arm/mach-bcm/bcm63xx_pmb.c +++ b/arch/arm/mach-bcm/bcm63xx_pmb.c @@ -91,10 +91,10 @@ static int bcm63xx_pmb_get_resources(struct device_node *dn, struct of_phandle_args args; int ret; - ret = of_property_read_u32(dn, "reg", cpu); - if (ret) { + *cpu = of_get_cpu_hwid(dn, 0); + if (*cpu == ~0U) { pr_err("CPU is missing a reg node\n"); - return ret; + return -ENODEV; } ret = of_parse_phandle_with_args(dn, "resets", "#reset-cells", diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 44369b99a57e..27df5c1e6baa 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -466,33 +466,6 @@ void __init smp_prepare_boot_cpu(void) kasan_init_hw_tags(); } -static u64 __init of_get_cpu_mpidr(struct device_node *dn) -{ - const __be32 *cell; - u64 hwid; - - /* - * A cpu node with missing "reg" property is - * considered invalid to build a cpu_logical_map - * entry. - */ - cell = of_get_property(dn, "reg", NULL); - if (!cell) { - pr_err("%pOF: missing reg property\n", dn); - return INVALID_HWID; - } - - hwid = of_read_number(cell, of_n_addr_cells(dn)); - /* - * Non affinity bits must be set to 0 in the DT - */ - if (hwid & ~MPIDR_HWID_BITMASK) { - pr_err("%pOF: invalid reg property\n", dn); - return INVALID_HWID; - } - return hwid; -} - /* * Duplicate MPIDRs are a recipe for disaster. Scan all initialized * entries and check for duplicates. If any is found just ignore the @@ -656,9 +629,9 @@ static void __init of_parse_and_init_cpus(void) struct device_node *dn; for_each_of_cpu_node(dn) { - u64 hwid = of_get_cpu_mpidr(dn); + u64 hwid = of_get_cpu_hwid(dn, 0); - if (hwid == INVALID_HWID) + if (hwid & ~MPIDR_HWID_BITMASK) goto next; if (is_mpidr_duplicate(cpu_count, hwid)) { diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp.c index e2993539af8e..6bb38bc2f39b 100644 --- a/arch/csky/kernel/smp.c +++ b/arch/csky/kernel/smp.c @@ -180,15 +180,13 @@ void __init setup_smp_ipi(void) void __init setup_smp(void) { struct device_node *node = NULL; - int cpu; + unsigned int cpu; for_each_of_cpu_node(node) { if (!of_device_is_available(node)) continue; - if (of_property_read_u32(node, "reg", &cpu)) - continue; - + cpu = of_get_cpu_hwid(node, 0); if (cpu >= NR_CPUS) continue; diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c index 415e209732a3..da21e22bf4da 100644 --- a/arch/openrisc/kernel/smp.c +++ b/arch/openrisc/kernel/smp.c @@ -65,11 +65,7 @@ void __init smp_init_cpus(void) u32 cpu_id; for_each_of_cpu_node(cpu) { - if (of_property_read_u32(cpu, "reg", &cpu_id)) { - pr_warn("%s missing reg property", cpu->full_name); - continue; - } - + cpu_id = of_get_cpu_hwid(cpu, 0); if (cpu_id < NR_CPUS) set_cpu_possible(cpu_id, true); } diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index f7440f4eca2e..c23ee842c4c3 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -1313,18 +1313,13 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle) int cpu_to_core_id(int cpu) { struct device_node *np; - const __be32 *reg; int id = -1; np = of_get_cpu_node(cpu, NULL); if (!np) goto out; - reg = of_get_property(np, "reg", NULL); - if (!reg) - goto out; - - id = be32_to_cpup(reg); + id = of_get_cpu_hwid(np, 0); out: of_node_put(np); return id; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 6d59e6906fdd..f13b2c9ea912 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -22,7 +22,8 @@ int riscv_of_processor_hartid(struct device_node *node) return -ENODEV; } - if (of_property_read_u32(node, "reg", &hart)) { + hart = of_get_cpu_hwid(node, 0); + if (hart == ~0U) { pr_warn("Found CPU without hart ID\n"); return -ENODEV; } diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c index 921d76fc3358..f7f3e618e85b 100644 --- a/arch/sh/boards/of-generic.c +++ b/arch/sh/boards/of-generic.c @@ -62,9 +62,8 @@ static void sh_of_smp_probe(void) init_cpu_possible(cpumask_of(0)); for_each_of_cpu_node(np) { - const __be32 *cell = of_get_property(np, "reg", NULL); - u64 id = -1; - if (cell) id = of_read_number(cell, of_n_addr_cells(np)); + u64 id = of_get_cpu_hwid(np, 0); + if (id < NR_CPUS) { if (!method) of_property_read_string(np, "enable-method", &method); diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 78b2311b3b8b..5cd51f25f446 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -134,12 +134,11 @@ static void __init dtb_cpu_setup(void) { struct device_node *dn; u32 apic_id, version; - int ret; version = GET_APIC_VERSION(apic_read(APIC_LVR)); for_each_of_cpu_node(dn) { - ret = of_property_read_u32(dn, "reg", &apic_id); - if (ret < 0) { + apic_id = of_get_cpu_hwid(dn, 0); + if (apic_id == ~0U) { pr_warn("%pOF: missing local APIC ID\n", dn); continue; } diff --git a/drivers/of/base.c b/drivers/of/base.c index 0ac17256258d..61de453b885c 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -287,6 +287,28 @@ const void *of_get_property(const struct device_node *np, const char *name, } EXPORT_SYMBOL(of_get_property); +/** + * of_get_cpu_hwid - Get the hardware ID from a CPU device node + * + * @cpun: CPU number(logical index) for which device node is required + * @thread: The local thread number to get the hardware ID for. + * + * Return: The hardware ID for the CPU node or ~0ULL if not found. + */ +u64 of_get_cpu_hwid(struct device_node *cpun, unsigned int thread) +{ + const __be32 *cell; + int ac, len; + + ac = of_n_addr_cells(cpun); + cell = of_get_property(cpun, "reg", &len); + if (!cell || !ac || ((sizeof(*cell) * ac * (thread + 1)) > len)) + return ~0ULL; + + cell += ac * thread; + return of_read_number(cell, ac); +} + /* * arch_match_cpu_phys_id - Match the given logical CPU and physical id * diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index 4546572af24b..bdca35284ceb 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -562,39 +562,35 @@ static int __init __reserved_mem_check_root(unsigned long node) } /* - * __fdt_scan_reserved_mem() - scan a single FDT node for reserved memory + * fdt_scan_reserved_mem() - scan a single FDT node for reserved memory */ -static int __init __fdt_scan_reserved_mem(unsigned long node, const char *uname, - int depth, void *data) +static int __init fdt_scan_reserved_mem(void) { - static int found; - int err; - - if (!found && depth == 1 && strcmp(uname, "reserved-memory") == 0) { - if (__reserved_mem_check_root(node) != 0) { - pr_err("Reserved memory: unsupported node format, ignoring\n"); - /* break scan */ - return 1; - } - found = 1; - /* scan next node */ - return 0; - } else if (!found) { - /* scan next node */ - return 0; - } else if (found && depth < 2) { - /* scanning of /reserved-memory has been finished */ - return 1; + int node, child; + const void *fdt = initial_boot_params; + + node = fdt_path_offset(fdt, "/reserved-memory"); + if (node < 0) + return -ENODEV; + + if (__reserved_mem_check_root(node) != 0) { + pr_err("Reserved memory: unsupported node format, ignoring\n"); + return -EINVAL; } - if (!of_fdt_device_is_available(initial_boot_params, node)) - return 0; + fdt_for_each_subnode(child, fdt, node) { + const char *uname; + int err; - err = __reserved_mem_reserve_reg(node, uname); - if (err == -ENOENT && of_get_flat_dt_prop(node, "size", NULL)) - fdt_reserved_mem_save_node(node, uname, 0, 0); + if (!of_fdt_device_is_available(fdt, child)) + continue; - /* scan next node */ + uname = fdt_get_name(fdt, child, NULL); + + err = __reserved_mem_reserve_reg(child, uname); + if (err == -ENOENT && of_get_flat_dt_prop(child, "size", NULL)) + fdt_reserved_mem_save_node(child, uname, 0, 0); + } return 0; } @@ -645,7 +641,7 @@ void __init early_init_fdt_scan_reserved_mem(void) early_init_dt_reserve_memory_arch(base, size, false); } - of_scan_flat_dt(__fdt_scan_reserved_mem, NULL); + fdt_scan_reserved_mem(); fdt_init_reserved_mem(); fdt_reserve_elfcorehdr(); } diff --git a/drivers/of/kobj.c b/drivers/of/kobj.c index 6675b5e56960..7d3853a5a09a 100644 --- a/drivers/of/kobj.c +++ b/drivers/of/kobj.c @@ -5,13 +5,13 @@ #include "of_private.h" /* true when node is initialized */ -static int of_node_is_initialized(struct device_node *node) +static int of_node_is_initialized(const struct device_node *node) { return node && node->kobj.state_initialized; } /* true when node is attached (i.e. present on sysfs) */ -int of_node_is_attached(struct device_node *node) +int of_node_is_attached(const struct device_node *node) { return node && node->kobj.state_in_sysfs; } diff --git a/drivers/of/of_numa.c b/drivers/of/of_numa.c index fe6b13608e51..5949829a1b00 100644 --- a/drivers/of/of_numa.c +++ b/drivers/of/of_numa.c @@ -111,6 +111,8 @@ static int __init of_numa_parse_distance_map_v1(struct device_node *map) return -EINVAL; } + node_set(nodea, numa_nodes_parsed); + numa_set_distance(nodea, nodeb, distance); /* Set default distance of node B->A same as A->B */ diff --git a/drivers/of/of_private.h b/drivers/of/of_private.h index 631489f7f8c0..9324483397f6 100644 --- a/drivers/of/of_private.h +++ b/drivers/of/of_private.h @@ -60,7 +60,7 @@ static inline int of_property_notify(int action, struct device_node *np, #endif /* CONFIG_OF_DYNAMIC */ #if defined(CONFIG_OF_KOBJ) -int of_node_is_attached(struct device_node *node); +int of_node_is_attached(const struct device_node *node); int __of_add_property_sysfs(struct device_node *np, struct property *pp); void __of_remove_property_sysfs(struct device_node *np, struct property *prop); void __of_update_property_sysfs(struct device_node *np, struct property *newprop, @@ -127,19 +127,11 @@ struct device_node *__of_find_node_by_full_path(struct device_node *node, extern const void *__of_get_property(const struct device_node *np, const char *name, int *lenp); extern int __of_add_property(struct device_node *np, struct property *prop); -extern int __of_add_property_sysfs(struct device_node *np, - struct property *prop); extern int __of_remove_property(struct device_node *np, struct property *prop); -extern void __of_remove_property_sysfs(struct device_node *np, - struct property *prop); extern int __of_update_property(struct device_node *np, struct property *newprop, struct property **oldprop); -extern void __of_update_property_sysfs(struct device_node *np, - struct property *newprop, struct property *oldprop); -extern int __of_attach_node_sysfs(struct device_node *np); extern void __of_detach_node(struct device_node *np); -extern void __of_detach_node_sysfs(struct device_node *np); extern void __of_sysfs_remove_bin_file(struct device_node *np, struct property *prop); diff --git a/drivers/of/unittest-data/Makefile b/drivers/of/unittest-data/Makefile index a5d2d9254b2c..fbded24c608c 100644 --- a/drivers/of/unittest-data/Makefile +++ b/drivers/of/unittest-data/Makefile @@ -37,7 +37,9 @@ DTC_FLAGS_overlay_base += -@ DTC_FLAGS_testcases += -@ # suppress warnings about intentional errors -DTC_FLAGS_testcases += -Wno-interrupts_property +DTC_FLAGS_testcases += -Wno-interrupts_property \ + -Wno-node_name_vs_property_name \ + -Wno-interrupt_map # Apply overlays statically with fdtoverlay. This is a build time test that # the overlays can be applied successfully by fdtoverlay. This does not @@ -82,6 +84,10 @@ apply_static_overlay_1 := overlay_0.dtbo \ apply_static_overlay_2 := overlay.dtbo +DTC_FLAGS_static_base_1 += -Wno-interrupts_property \ + -Wno-node_name_vs_property_name \ + -Wno-interrupt_map + static_test_1-dtbs := static_base_1.dtb $(apply_static_overlay_1) static_test_2-dtbs := static_base_2.dtb $(apply_static_overlay_2) diff --git a/drivers/of/unittest-data/tests-interrupts.dtsi b/drivers/of/unittest-data/tests-interrupts.dtsi index 9b60a549f502..ecc74dbcc373 100644 --- a/drivers/of/unittest-data/tests-interrupts.dtsi +++ b/drivers/of/unittest-data/tests-interrupts.dtsi @@ -31,6 +31,21 @@ test_intmap1: intmap1 { #interrupt-cells = <2>; + /* + * #address-cells is required + * + * The property is not provided in this node to + * test that the code will properly handle + * this case for legacy .dts files. + * + * Not having #address-cells will result in a + * warning from dtc starting with + * version v1.6.1-19-g0a3a9d3449c8 + * The warning is suppressed by adding + * -Wno-interrupt_map to the Makefile for all + * .dts files this include this .dtsi + #address-cells = <1>; + */ interrupt-map = <0x5000 1 2 &test_intc0 15>; }; @@ -46,6 +61,10 @@ interrupts-extended0 { reg = <0x5000 0x100>; + /* + * Do not remove &test_intmap1 from this + * property - see comment in node intmap1 + */ interrupts-extended = <&test_intc0 1>, <&test_intc1 2 3 4>, <&test_intc2 5 6>, diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c index 8c056972a6dd..481ba8682ebf 100644 --- a/drivers/of/unittest.c +++ b/drivers/of/unittest.c @@ -1129,6 +1129,12 @@ static void __init of_unittest_parse_interrupts_extended(void) passed &= (args.args[1] == 14); break; case 6: + /* + * Tests child node that is missing property + * #address-cells. See the comments in + * drivers/of/unittest-data/tests-interrupts.dtsi + * nodes intmap1 and interrupts-extended0 + */ passed &= !rc; passed &= (args.args_count == 1); passed &= (args.args[0] == 15); @@ -1688,19 +1694,19 @@ static void __init of_unittest_overlay_gpio(void) */ EXPECT_BEGIN(KERN_INFO, - "GPIO line <<int>> (line-B-input) hogged as input\n"); + "gpio-<<int>> (line-B-input): hogged as input\n"); EXPECT_BEGIN(KERN_INFO, - "GPIO line <<int>> (line-A-input) hogged as input\n"); + "gpio-<<int>> (line-A-input): hogged as input\n"); ret = platform_driver_register(&unittest_gpio_driver); if (unittest(ret == 0, "could not register unittest gpio driver\n")) return; EXPECT_END(KERN_INFO, - "GPIO line <<int>> (line-A-input) hogged as input\n"); + "gpio-<<int>> (line-A-input): hogged as input\n"); EXPECT_END(KERN_INFO, - "GPIO line <<int>> (line-B-input) hogged as input\n"); + "gpio-<<int>> (line-B-input): hogged as input\n"); unittest(probe_pass_count + 2 == unittest_gpio_probe_pass_count, "unittest_gpio_probe() failed or not called\n"); @@ -1727,7 +1733,7 @@ static void __init of_unittest_overlay_gpio(void) chip_request_count = unittest_gpio_chip_request_count; EXPECT_BEGIN(KERN_INFO, - "GPIO line <<int>> (line-D-input) hogged as input\n"); + "gpio-<<int>> (line-D-input): hogged as input\n"); /* overlay_gpio_03 contains gpio node and child gpio hog node */ @@ -1735,7 +1741,7 @@ static void __init of_unittest_overlay_gpio(void) "Adding overlay 'overlay_gpio_03' failed\n"); EXPECT_END(KERN_INFO, - "GPIO line <<int>> (line-D-input) hogged as input\n"); + "gpio-<<int>> (line-D-input): hogged as input\n"); unittest(probe_pass_count + 1 == unittest_gpio_probe_pass_count, "unittest_gpio_probe() failed or not called\n"); @@ -1774,7 +1780,7 @@ static void __init of_unittest_overlay_gpio(void) */ EXPECT_BEGIN(KERN_INFO, - "GPIO line <<int>> (line-C-input) hogged as input\n"); + "gpio-<<int>> (line-C-input): hogged as input\n"); /* overlay_gpio_04b contains child gpio hog node */ @@ -1782,7 +1788,7 @@ static void __init of_unittest_overlay_gpio(void) "Adding overlay 'overlay_gpio_04b' failed\n"); EXPECT_END(KERN_INFO, - "GPIO line <<int>> (line-C-input) hogged as input\n"); + "gpio-<<int>> (line-C-input): hogged as input\n"); unittest(chip_request_count + 1 == unittest_gpio_chip_request_count, "unittest_gpio_chip_request() called %d times (expected 1 time)\n", @@ -3094,6 +3100,8 @@ static __init void of_unittest_overlay_high_level(void) if (!strcmp(np->full_name, base_child->full_name)) { unittest(0, "illegal node name in overlay_base %pOFn", np); + of_node_put(np); + of_node_put(base_child); return; } } diff --git a/include/linux/of.h b/include/linux/of.h index 6f1c41f109bb..ff143a027abc 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -185,7 +185,7 @@ static inline bool of_node_is_root(const struct device_node *node) return node && (node->parent == NULL); } -static inline int of_node_check_flag(struct device_node *n, unsigned long flag) +static inline int of_node_check_flag(const struct device_node *n, unsigned long flag) { return test_bit(flag, &n->_flags); } @@ -353,6 +353,7 @@ extern struct device_node *of_get_cpu_node(int cpu, unsigned int *thread); extern struct device_node *of_get_next_cpu_node(struct device_node *prev); extern struct device_node *of_get_cpu_state_node(struct device_node *cpu_node, int index); +extern u64 of_get_cpu_hwid(struct device_node *cpun, unsigned int thread); #define for_each_property_of_node(dn, pp) \ for (pp = dn->properties; pp != NULL; pp = pp->next) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 54582673fc1a..56d50eb0cd80 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -310,7 +310,6 @@ DTC_FLAGS += -Wno-interrupt_provider # Disable noisy checks by default ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),) DTC_FLAGS += -Wno-unit_address_vs_reg \ - -Wno-unit_address_format \ -Wno-avoid_unnecessary_addr_size \ -Wno-alias_paths \ -Wno-graph_child_address \ diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c index 17cb6890d45a..781ba1129a8e 100644 --- a/scripts/dtc/checks.c +++ b/scripts/dtc/checks.c @@ -143,6 +143,14 @@ static void check_nodes_props(struct check *c, struct dt_info *dti, struct node check_nodes_props(c, dti, child); } +static bool is_multiple_of(int multiple, int divisor) +{ + if (divisor == 0) + return multiple == 0; + else + return (multiple % divisor) == 0; +} + static bool run_check(struct check *c, struct dt_info *dti) { struct node *dt = dti->dt; @@ -297,19 +305,20 @@ ERROR(duplicate_property_names, check_duplicate_property_names, NULL); #define LOWERCASE "abcdefghijklmnopqrstuvwxyz" #define UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ" #define DIGITS "0123456789" -#define PROPNODECHARS LOWERCASE UPPERCASE DIGITS ",._+*#?-" +#define NODECHARS LOWERCASE UPPERCASE DIGITS ",._+-@" +#define PROPCHARS LOWERCASE UPPERCASE DIGITS ",._+*#?-" #define PROPNODECHARSSTRICT LOWERCASE UPPERCASE DIGITS ",-" static void check_node_name_chars(struct check *c, struct dt_info *dti, struct node *node) { - int n = strspn(node->name, c->data); + size_t n = strspn(node->name, c->data); if (n < strlen(node->name)) FAIL(c, dti, node, "Bad character '%c' in node name", node->name[n]); } -ERROR(node_name_chars, check_node_name_chars, PROPNODECHARS "@"); +ERROR(node_name_chars, check_node_name_chars, NODECHARS); static void check_node_name_chars_strict(struct check *c, struct dt_info *dti, struct node *node) @@ -330,6 +339,20 @@ static void check_node_name_format(struct check *c, struct dt_info *dti, } ERROR(node_name_format, check_node_name_format, NULL, &node_name_chars); +static void check_node_name_vs_property_name(struct check *c, + struct dt_info *dti, + struct node *node) +{ + if (!node->parent) + return; + + if (get_property(node->parent, node->name)) { + FAIL(c, dti, node, "node name and property name conflict"); + } +} +WARNING(node_name_vs_property_name, check_node_name_vs_property_name, + NULL, &node_name_chars); + static void check_unit_address_vs_reg(struct check *c, struct dt_info *dti, struct node *node) { @@ -363,14 +386,14 @@ static void check_property_name_chars(struct check *c, struct dt_info *dti, struct property *prop; for_each_property(node, prop) { - int n = strspn(prop->name, c->data); + size_t n = strspn(prop->name, c->data); if (n < strlen(prop->name)) FAIL_PROP(c, dti, node, prop, "Bad character '%c' in property name", prop->name[n]); } } -ERROR(property_name_chars, check_property_name_chars, PROPNODECHARS); +ERROR(property_name_chars, check_property_name_chars, PROPCHARS); static void check_property_name_chars_strict(struct check *c, struct dt_info *dti, @@ -380,7 +403,7 @@ static void check_property_name_chars_strict(struct check *c, for_each_property(node, prop) { const char *name = prop->name; - int n = strspn(name, c->data); + size_t n = strspn(name, c->data); if (n == strlen(prop->name)) continue; @@ -497,7 +520,7 @@ static cell_t check_phandle_prop(struct check *c, struct dt_info *dti, phandle = propval_cell(prop); - if ((phandle == 0) || (phandle == -1)) { + if (!phandle_is_valid(phandle)) { FAIL_PROP(c, dti, node, prop, "bad value (0x%x) in %s property", phandle, prop->name); return 0; @@ -556,7 +579,7 @@ static void check_name_properties(struct check *c, struct dt_info *dti, if (!prop) return; /* No name property, that's fine */ - if ((prop->val.len != node->basenamelen+1) + if ((prop->val.len != node->basenamelen + 1U) || (memcmp(prop->val.val, node->name, node->basenamelen) != 0)) { FAIL(c, dti, node, "\"name\" property is incorrect (\"%s\" instead" " of base node name)", prop->val.val); @@ -657,7 +680,6 @@ ERROR(omit_unused_nodes, fixup_omit_unused_nodes, NULL, &phandle_references, &pa */ WARNING_IF_NOT_CELL(address_cells_is_cell, "#address-cells"); WARNING_IF_NOT_CELL(size_cells_is_cell, "#size-cells"); -WARNING_IF_NOT_CELL(interrupt_cells_is_cell, "#interrupt-cells"); WARNING_IF_NOT_STRING(device_type_is_string, "device_type"); WARNING_IF_NOT_STRING(model_is_string, "model"); @@ -672,8 +694,7 @@ static void check_names_is_string_list(struct check *c, struct dt_info *dti, struct property *prop; for_each_property(node, prop) { - const char *s = strrchr(prop->name, '-'); - if (!s || !streq(s, "-names")) + if (!strends(prop->name, "-names")) continue; c->data = prop->name; @@ -753,7 +774,7 @@ static void check_reg_format(struct check *c, struct dt_info *dti, size_cells = node_size_cells(node->parent); entrylen = (addr_cells + size_cells) * sizeof(cell_t); - if (!entrylen || (prop->val.len % entrylen) != 0) + if (!is_multiple_of(prop->val.len, entrylen)) FAIL_PROP(c, dti, node, prop, "property has invalid length (%d bytes) " "(#address-cells == %d, #size-cells == %d)", prop->val.len, addr_cells, size_cells); @@ -794,7 +815,7 @@ static void check_ranges_format(struct check *c, struct dt_info *dti, "#size-cells (%d) differs from %s (%d)", ranges, c_size_cells, node->parent->fullpath, p_size_cells); - } else if ((prop->val.len % entrylen) != 0) { + } else if (!is_multiple_of(prop->val.len, entrylen)) { FAIL_PROP(c, dti, node, prop, "\"%s\" property has invalid length (%d bytes) " "(parent #address-cells == %d, child #address-cells == %d, " "#size-cells == %d)", ranges, prop->val.len, @@ -871,7 +892,7 @@ static void check_pci_device_bus_num(struct check *c, struct dt_info *dti, struc } else { cells = (cell_t *)prop->val.val; min_bus = fdt32_to_cpu(cells[0]); - max_bus = fdt32_to_cpu(cells[0]); + max_bus = fdt32_to_cpu(cells[1]); } if ((bus_num < min_bus) || (bus_num > max_bus)) FAIL_PROP(c, dti, node, prop, "PCI bus number %d out of range, expected (%d - %d)", @@ -1367,9 +1388,9 @@ static void check_property_phandle_args(struct check *c, const struct provider *provider) { struct node *root = dti->dt; - int cell, cellsize = 0; + unsigned int cell, cellsize = 0; - if (prop->val.len % sizeof(cell_t)) { + if (!is_multiple_of(prop->val.len, sizeof(cell_t))) { FAIL_PROP(c, dti, node, prop, "property size (%d) is invalid, expected multiple of %zu", prop->val.len, sizeof(cell_t)); @@ -1379,14 +1400,14 @@ static void check_property_phandle_args(struct check *c, for (cell = 0; cell < prop->val.len / sizeof(cell_t); cell += cellsize + 1) { struct node *provider_node; struct property *cellprop; - int phandle; + cell_t phandle; phandle = propval_cell_n(prop, cell); /* * Some bindings use a cell value 0 or -1 to skip over optional * entries when each index position has a specific definition. */ - if (phandle == 0 || phandle == -1) { + if (!phandle_is_valid(phandle)) { /* Give up if this is an overlay with external references */ if (dti->dtsflags & DTSF_PLUGIN) break; @@ -1452,7 +1473,8 @@ static void check_provider_cells_property(struct check *c, } #define WARNING_PROPERTY_PHANDLE_CELLS(nm, propname, cells_name, ...) \ static struct provider nm##_provider = { (propname), (cells_name), __VA_ARGS__ }; \ - WARNING(nm##_property, check_provider_cells_property, &nm##_provider, &phandle_references); + WARNING_IF_NOT_CELL(nm##_is_cell, cells_name); \ + WARNING(nm##_property, check_provider_cells_property, &nm##_provider, &nm##_is_cell, &phandle_references); WARNING_PROPERTY_PHANDLE_CELLS(clocks, "clocks", "#clock-cells"); WARNING_PROPERTY_PHANDLE_CELLS(cooling_device, "cooling-device", "#cooling-cells"); @@ -1473,24 +1495,17 @@ WARNING_PROPERTY_PHANDLE_CELLS(thermal_sensors, "thermal-sensors", "#thermal-sen static bool prop_is_gpio(struct property *prop) { - char *str; - /* * *-gpios and *-gpio can appear in property names, * so skip over any false matches (only one known ATM) */ - if (strstr(prop->name, "nr-gpio")) + if (strends(prop->name, ",nr-gpios")) return false; - str = strrchr(prop->name, '-'); - if (str) - str++; - else - str = prop->name; - if (!(streq(str, "gpios") || streq(str, "gpio"))) - return false; - - return true; + return strends(prop->name, "-gpios") || + streq(prop->name, "gpios") || + strends(prop->name, "-gpio") || + streq(prop->name, "gpio"); } static void check_gpios_property(struct check *c, @@ -1525,13 +1540,10 @@ static void check_deprecated_gpio_property(struct check *c, struct property *prop; for_each_property(node, prop) { - char *str; - if (!prop_is_gpio(prop)) continue; - str = strstr(prop->name, "gpio"); - if (!streq(str, "gpio")) + if (!strends(prop->name, "gpio")) continue; FAIL_PROP(c, dti, node, prop, @@ -1561,21 +1573,106 @@ static void check_interrupt_provider(struct check *c, struct node *node) { struct property *prop; + bool irq_provider = node_is_interrupt_provider(node); - if (!node_is_interrupt_provider(node)) + prop = get_property(node, "#interrupt-cells"); + if (irq_provider && !prop) { + FAIL(c, dti, node, + "Missing '#interrupt-cells' in interrupt provider"); return; + } - prop = get_property(node, "#interrupt-cells"); - if (!prop) + if (!irq_provider && prop) { FAIL(c, dti, node, - "Missing #interrupt-cells in interrupt provider"); + "'#interrupt-cells' found, but node is not an interrupt provider"); + return; + } +} +WARNING(interrupt_provider, check_interrupt_provider, NULL, &interrupts_extended_is_cell); - prop = get_property(node, "#address-cells"); - if (!prop) +static void check_interrupt_map(struct check *c, + struct dt_info *dti, + struct node *node) +{ + struct node *root = dti->dt; + struct property *prop, *irq_map_prop; + size_t cellsize, cell, map_cells; + + irq_map_prop = get_property(node, "interrupt-map"); + if (!irq_map_prop) + return; + + if (node->addr_cells < 0) { FAIL(c, dti, node, - "Missing #address-cells in interrupt provider"); + "Missing '#address-cells' in interrupt-map provider"); + return; + } + cellsize = node_addr_cells(node); + cellsize += propval_cell(get_property(node, "#interrupt-cells")); + + prop = get_property(node, "interrupt-map-mask"); + if (prop && (prop->val.len != (cellsize * sizeof(cell_t)))) + FAIL_PROP(c, dti, node, prop, + "property size (%d) is invalid, expected %zu", + prop->val.len, cellsize * sizeof(cell_t)); + + if (!is_multiple_of(irq_map_prop->val.len, sizeof(cell_t))) { + FAIL_PROP(c, dti, node, irq_map_prop, + "property size (%d) is invalid, expected multiple of %zu", + irq_map_prop->val.len, sizeof(cell_t)); + return; + } + + map_cells = irq_map_prop->val.len / sizeof(cell_t); + for (cell = 0; cell < map_cells; ) { + struct node *provider_node; + struct property *cellprop; + int phandle; + size_t parent_cellsize; + + if ((cell + cellsize) >= map_cells) { + FAIL_PROP(c, dti, node, irq_map_prop, + "property size (%d) too small, expected > %zu", + irq_map_prop->val.len, (cell + cellsize) * sizeof(cell_t)); + break; + } + cell += cellsize; + + phandle = propval_cell_n(irq_map_prop, cell); + if (!phandle_is_valid(phandle)) { + /* Give up if this is an overlay with external references */ + if (!(dti->dtsflags & DTSF_PLUGIN)) + FAIL_PROP(c, dti, node, irq_map_prop, + "Cell %zu is not a phandle(%d)", + cell, phandle); + break; + } + + provider_node = get_node_by_phandle(root, phandle); + if (!provider_node) { + FAIL_PROP(c, dti, node, irq_map_prop, + "Could not get phandle(%d) node for (cell %zu)", + phandle, cell); + break; + } + + cellprop = get_property(provider_node, "#interrupt-cells"); + if (cellprop) { + parent_cellsize = propval_cell(cellprop); + } else { + FAIL(c, dti, node, "Missing property '#interrupt-cells' in node %s or bad phandle (referred from interrupt-map[%zu])", + provider_node->fullpath, cell); + break; + } + + cellprop = get_property(provider_node, "#address-cells"); + if (cellprop) + parent_cellsize += propval_cell(cellprop); + + cell += 1 + parent_cellsize; + } } -WARNING(interrupt_provider, check_interrupt_provider, NULL); +WARNING(interrupt_map, check_interrupt_map, NULL, &phandle_references, &addr_size_cells, &interrupt_provider); static void check_interrupts_property(struct check *c, struct dt_info *dti, @@ -1584,13 +1681,13 @@ static void check_interrupts_property(struct check *c, struct node *root = dti->dt; struct node *irq_node = NULL, *parent = node; struct property *irq_prop, *prop = NULL; - int irq_cells, phandle; + cell_t irq_cells, phandle; irq_prop = get_property(node, "interrupts"); if (!irq_prop) return; - if (irq_prop->val.len % sizeof(cell_t)) + if (!is_multiple_of(irq_prop->val.len, sizeof(cell_t))) FAIL_PROP(c, dti, node, irq_prop, "size (%d) is invalid, expected multiple of %zu", irq_prop->val.len, sizeof(cell_t)); @@ -1603,7 +1700,7 @@ static void check_interrupts_property(struct check *c, prop = get_property(parent, "interrupt-parent"); if (prop) { phandle = propval_cell(prop); - if ((phandle == 0) || (phandle == -1)) { + if (!phandle_is_valid(phandle)) { /* Give up if this is an overlay with * external references */ if (dti->dtsflags & DTSF_PLUGIN) @@ -1639,7 +1736,7 @@ static void check_interrupts_property(struct check *c, } irq_cells = propval_cell(prop); - if (irq_prop->val.len % (irq_cells * sizeof(cell_t))) { + if (!is_multiple_of(irq_prop->val.len, irq_cells * sizeof(cell_t))) { FAIL_PROP(c, dti, node, prop, "size is (%d), expected multiple of %d", irq_prop->val.len, (int)(irq_cells * sizeof(cell_t))); @@ -1750,7 +1847,7 @@ WARNING(graph_port, check_graph_port, NULL, &graph_nodes); static struct node *get_remote_endpoint(struct check *c, struct dt_info *dti, struct node *endpoint) { - int phandle; + cell_t phandle; struct node *node; struct property *prop; @@ -1760,7 +1857,7 @@ static struct node *get_remote_endpoint(struct check *c, struct dt_info *dti, phandle = propval_cell(prop); /* Give up if this is an overlay with external references */ - if (phandle == 0 || phandle == -1) + if (!phandle_is_valid(phandle)) return NULL; node = get_node_by_phandle(dti->dt, phandle); @@ -1796,7 +1893,7 @@ WARNING(graph_endpoint, check_graph_endpoint, NULL, &graph_nodes); static struct check *check_table[] = { &duplicate_node_names, &duplicate_property_names, &node_name_chars, &node_name_format, &property_name_chars, - &name_is_string, &name_properties, + &name_is_string, &name_properties, &node_name_vs_property_name, &duplicate_label, @@ -1804,7 +1901,7 @@ static struct check *check_table[] = { &phandle_references, &path_references, &omit_unused_nodes, - &address_cells_is_cell, &size_cells_is_cell, &interrupt_cells_is_cell, + &address_cells_is_cell, &size_cells_is_cell, &device_type_is_string, &model_is_string, &status_is_string, &label_is_string, @@ -1839,26 +1936,43 @@ static struct check *check_table[] = { &chosen_node_is_root, &chosen_node_bootargs, &chosen_node_stdout_path, &clocks_property, + &clocks_is_cell, &cooling_device_property, + &cooling_device_is_cell, &dmas_property, + &dmas_is_cell, &hwlocks_property, + &hwlocks_is_cell, &interrupts_extended_property, + &interrupts_extended_is_cell, &io_channels_property, + &io_channels_is_cell, &iommus_property, + &iommus_is_cell, &mboxes_property, + &mboxes_is_cell, &msi_parent_property, + &msi_parent_is_cell, &mux_controls_property, + &mux_controls_is_cell, &phys_property, + &phys_is_cell, &power_domains_property, + &power_domains_is_cell, &pwms_property, + &pwms_is_cell, &resets_property, + &resets_is_cell, &sound_dai_property, + &sound_dai_is_cell, &thermal_sensors_property, + &thermal_sensors_is_cell, &deprecated_gpio_property, &gpios_property, &interrupts_property, &interrupt_provider, + &interrupt_map, &alias_paths, @@ -1882,7 +1996,7 @@ static void enable_warning_error(struct check *c, bool warn, bool error) static void disable_warning_error(struct check *c, bool warn, bool error) { - int i; + unsigned int i; /* Lowering level, also lower it for things this is the prereq * for */ @@ -1903,7 +2017,7 @@ static void disable_warning_error(struct check *c, bool warn, bool error) void parse_checks_option(bool warn, bool error, const char *arg) { - int i; + unsigned int i; const char *name = arg; bool enable = true; @@ -1930,7 +2044,7 @@ void parse_checks_option(bool warn, bool error, const char *arg) void process_checks(bool force, struct dt_info *dti) { - int i; + unsigned int i; int error = 0; for (i = 0; i < ARRAY_SIZE(check_table); i++) { diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l index b3b7270300de..5568b4ae84cf 100644 --- a/scripts/dtc/dtc-lexer.l +++ b/scripts/dtc/dtc-lexer.l @@ -57,7 +57,7 @@ static void PRINTF(1, 2) lexical_error(const char *fmt, ...); push_input_file(name); } -<*>^"#"(line)?[ \t]+[0-9]+[ \t]+{STRING}([ \t]+[0-9]+)? { +<*>^"#"(line)?[ \t]+[0-9]+[ \t]+{STRING}([ \t]+[0-9]+)* { char *line, *fnstart, *fnend; struct data fn; /* skip text before line # */ diff --git a/scripts/dtc/dtc.c b/scripts/dtc/dtc.c index 838c5df96c00..bc786c543b7e 100644 --- a/scripts/dtc/dtc.c +++ b/scripts/dtc/dtc.c @@ -12,7 +12,7 @@ * Command line options */ int quiet; /* Level of quietness */ -int reservenum; /* Number of memory reservation slots */ +unsigned int reservenum;/* Number of memory reservation slots */ int minsize; /* Minimum blob size */ int padsize; /* Additional padding to blob */ int alignsize; /* Additional padding to blob accroding to the alignsize */ @@ -197,7 +197,7 @@ int main(int argc, char *argv[]) depname = optarg; break; case 'R': - reservenum = strtol(optarg, NULL, 0); + reservenum = strtoul(optarg, NULL, 0); break; case 'S': minsize = strtol(optarg, NULL, 0); @@ -359,8 +359,6 @@ int main(int argc, char *argv[]) #endif } else if (streq(outform, "dtb")) { dt_to_blob(outf, dti, outversion); - } else if (streq(outform, "dtbo")) { - dt_to_blob(outf, dti, outversion); } else if (streq(outform, "asm")) { dt_to_asm(outf, dti, outversion); } else if (streq(outform, "null")) { diff --git a/scripts/dtc/dtc.h b/scripts/dtc/dtc.h index d3e82fb8e3db..0a1f54991026 100644 --- a/scripts/dtc/dtc.h +++ b/scripts/dtc/dtc.h @@ -35,7 +35,7 @@ * Command line options */ extern int quiet; /* Level of quietness */ -extern int reservenum; /* Number of memory reservation slots */ +extern unsigned int reservenum; /* Number of memory reservation slots */ extern int minsize; /* Minimum blob size */ extern int padsize; /* Additional padding to blob */ extern int alignsize; /* Additional padding to blob accroding to the alignsize */ @@ -51,6 +51,11 @@ extern int annotate; /* annotate .dts with input source location */ typedef uint32_t cell_t; +static inline bool phandle_is_valid(cell_t phandle) +{ + return phandle != 0 && phandle != ~0U; +} + static inline uint16_t dtb_ld16(const void *p) { const uint8_t *bp = (const uint8_t *)p; @@ -86,6 +91,16 @@ static inline uint64_t dtb_ld64(const void *p) #define streq(a, b) (strcmp((a), (b)) == 0) #define strstarts(s, prefix) (strncmp((s), (prefix), strlen(prefix)) == 0) #define strprefixeq(a, n, b) (strlen(b) == (n) && (memcmp(a, b, n) == 0)) +static inline bool strends(const char *str, const char *suffix) +{ + unsigned int len, suffix_len; + + len = strlen(str); + suffix_len = strlen(suffix); + if (len < suffix_len) + return false; + return streq(str + len - suffix_len, suffix); +} #define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) @@ -101,6 +116,12 @@ enum markertype { TYPE_UINT64, TYPE_STRING, }; + +static inline bool is_type_marker(enum markertype type) +{ + return type >= TYPE_UINT8; +} + extern const char *markername(enum markertype markertype); struct marker { @@ -125,7 +146,22 @@ struct data { for_each_marker(m) \ if ((m)->type == (t)) -size_t type_marker_length(struct marker *m); +static inline struct marker *next_type_marker(struct marker *m) +{ + for_each_marker(m) + if (is_type_marker(m->type)) + break; + return m; +} + +static inline size_t type_marker_length(struct marker *m) +{ + struct marker *next = next_type_marker(m->next); + + if (next) + return next->offset - m->offset; + return 0; +} void data_free(struct data d); diff --git a/scripts/dtc/flattree.c b/scripts/dtc/flattree.c index 4659afbfcbab..95e43d32c3e6 100644 --- a/scripts/dtc/flattree.c +++ b/scripts/dtc/flattree.c @@ -124,7 +124,8 @@ static void asm_emit_cell(void *e, cell_t val) { FILE *f = e; - fprintf(f, "\t.byte 0x%02x; .byte 0x%02x; .byte 0x%02x; .byte 0x%02x\n", + fprintf(f, "\t.byte\t0x%02x\n" "\t.byte\t0x%02x\n" + "\t.byte\t0x%02x\n" "\t.byte\t0x%02x\n", (val >> 24) & 0xff, (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff); } @@ -134,9 +135,9 @@ static void asm_emit_string(void *e, const char *str, int len) FILE *f = e; if (len != 0) - fprintf(f, "\t.string\t\"%.*s\"\n", len, str); + fprintf(f, "\t.asciz\t\"%.*s\"\n", len, str); else - fprintf(f, "\t.string\t\"%s\"\n", str); + fprintf(f, "\t.asciz\t\"%s\"\n", str); } static void asm_emit_align(void *e, int a) @@ -295,7 +296,7 @@ static struct data flatten_reserve_list(struct reserve_info *reservelist, { struct reserve_info *re; struct data d = empty_data; - int j; + unsigned int j; for (re = reservelist; re; re = re->next) { d = data_append_re(d, re->address, re->size); @@ -438,7 +439,7 @@ static void dump_stringtable_asm(FILE *f, struct data strbuf) while (p < (strbuf.val + strbuf.len)) { len = strlen(p); - fprintf(f, "\t.string \"%s\"\n", p); + fprintf(f, "\t.asciz \"%s\"\n", p); p += len+1; } } diff --git a/scripts/dtc/libfdt/fdt.c b/scripts/dtc/libfdt/fdt.c index 3e893073da05..9fe7cf4b747d 100644 --- a/scripts/dtc/libfdt/fdt.c +++ b/scripts/dtc/libfdt/fdt.c @@ -90,6 +90,10 @@ int fdt_check_header(const void *fdt) { size_t hdrsize; + /* The device tree must be at an 8-byte aligned address */ + if ((uintptr_t)fdt & 7) + return -FDT_ERR_ALIGNMENT; + if (fdt_magic(fdt) != FDT_MAGIC) return -FDT_ERR_BADMAGIC; if (!can_assume(LATEST)) { diff --git a/scripts/dtc/libfdt/fdt_rw.c b/scripts/dtc/libfdt/fdt_rw.c index f13458d165d4..3621d3651d3f 100644 --- a/scripts/dtc/libfdt/fdt_rw.c +++ b/scripts/dtc/libfdt/fdt_rw.c @@ -349,7 +349,10 @@ int fdt_add_subnode_namelen(void *fdt, int parentoffset, return offset; /* Try to place the new node after the parent's properties */ - fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */ + tag = fdt_next_tag(fdt, parentoffset, &nextoffset); + /* the fdt_subnode_offset_namelen() should ensure this never hits */ + if (!can_assume(LIBFDT_FLAWLESS) && (tag != FDT_BEGIN_NODE)) + return -FDT_ERR_INTERNAL; do { offset = nextoffset; tag = fdt_next_tag(fdt, offset, &nextoffset); @@ -391,7 +394,9 @@ int fdt_del_node(void *fdt, int nodeoffset) } static void fdt_packblocks_(const char *old, char *new, - int mem_rsv_size, int struct_size) + int mem_rsv_size, + int struct_size, + int strings_size) { int mem_rsv_off, struct_off, strings_off; @@ -406,8 +411,7 @@ static void fdt_packblocks_(const char *old, char *new, fdt_set_off_dt_struct(new, struct_off); fdt_set_size_dt_struct(new, struct_size); - memmove(new + strings_off, old + fdt_off_dt_strings(old), - fdt_size_dt_strings(old)); + memmove(new + strings_off, old + fdt_off_dt_strings(old), strings_size); fdt_set_off_dt_strings(new, strings_off); fdt_set_size_dt_strings(new, fdt_size_dt_strings(old)); } @@ -467,7 +471,8 @@ int fdt_open_into(const void *fdt, void *buf, int bufsize) return -FDT_ERR_NOSPACE; } - fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size); + fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size, + fdt_size_dt_strings(fdt)); memmove(buf, tmp, newsize); fdt_set_magic(buf, FDT_MAGIC); @@ -487,7 +492,8 @@ int fdt_pack(void *fdt) mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) * sizeof(struct fdt_reserve_entry); - fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt)); + fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt), + fdt_size_dt_strings(fdt)); fdt_set_totalsize(fdt, fdt_data_size_(fdt)); return 0; diff --git a/scripts/dtc/libfdt/fdt_strerror.c b/scripts/dtc/libfdt/fdt_strerror.c index b4356931b06d..d852b77e81e7 100644 --- a/scripts/dtc/libfdt/fdt_strerror.c +++ b/scripts/dtc/libfdt/fdt_strerror.c @@ -39,6 +39,7 @@ static struct fdt_errtabent fdt_errtable[] = { FDT_ERRTABENT(FDT_ERR_BADOVERLAY), FDT_ERRTABENT(FDT_ERR_NOPHANDLES), FDT_ERRTABENT(FDT_ERR_BADFLAGS), + FDT_ERRTABENT(FDT_ERR_ALIGNMENT), }; #define FDT_ERRTABSIZE ((int)(sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))) diff --git a/scripts/dtc/libfdt/libfdt.h b/scripts/dtc/libfdt/libfdt.h index c42807a7663e..ce31e844856a 100644 --- a/scripts/dtc/libfdt/libfdt.h +++ b/scripts/dtc/libfdt/libfdt.h @@ -131,6 +131,13 @@ uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); * to work even with unaligned pointers on platforms (such as ARMv5) that don't * like unaligned loads and stores. */ +static inline uint16_t fdt16_ld(const fdt16_t *p) +{ + const uint8_t *bp = (const uint8_t *)p; + + return ((uint16_t)bp[0] << 8) | bp[1]; +} + static inline uint32_t fdt32_ld(const fdt32_t *p) { const uint8_t *bp = (const uint8_t *)p; diff --git a/scripts/dtc/livetree.c b/scripts/dtc/livetree.c index 7eacd0248641..cc612370ec61 100644 --- a/scripts/dtc/livetree.c +++ b/scripts/dtc/livetree.c @@ -526,7 +526,7 @@ struct node *get_node_by_path(struct node *tree, const char *path) p = strchr(path, '/'); for_each_child(tree, child) { - if (p && strprefixeq(path, p - path, child->name)) + if (p && strprefixeq(path, (size_t)(p - path), child->name)) return get_node_by_path(child, p+1); else if (!p && streq(path, child->name)) return child; @@ -559,7 +559,7 @@ struct node *get_node_by_phandle(struct node *tree, cell_t phandle) { struct node *child, *node; - if ((phandle == 0) || (phandle == -1)) { + if (!phandle_is_valid(phandle)) { assert(generate_fixups); return NULL; } @@ -594,7 +594,7 @@ cell_t get_node_phandle(struct node *root, struct node *node) static cell_t phandle = 1; /* FIXME: ick, static local */ struct data d = empty_data; - if ((node->phandle != 0) && (node->phandle != -1)) + if (phandle_is_valid(node->phandle)) return node->phandle; while (get_node_by_phandle(root, phandle)) diff --git a/scripts/dtc/treesource.c b/scripts/dtc/treesource.c index 061ba8c9c5e8..33fedee82d58 100644 --- a/scripts/dtc/treesource.c +++ b/scripts/dtc/treesource.c @@ -124,27 +124,6 @@ static void write_propval_int(FILE *f, const char *p, size_t len, size_t width) } } -static bool has_data_type_information(struct marker *m) -{ - return m->type >= TYPE_UINT8; -} - -static struct marker *next_type_marker(struct marker *m) -{ - while (m && !has_data_type_information(m)) - m = m->next; - return m; -} - -size_t type_marker_length(struct marker *m) -{ - struct marker *next = next_type_marker(m->next); - - if (next) - return next->offset - m->offset; - return 0; -} - static const char *delim_start[] = { [TYPE_UINT8] = "[", [TYPE_UINT16] = "/bits/ 16 <", @@ -229,26 +208,39 @@ static void write_propval(FILE *f, struct property *prop) size_t chunk_len = (m->next ? m->next->offset : len) - m->offset; size_t data_len = type_marker_length(m) ? : len - m->offset; const char *p = &prop->val.val[m->offset]; + struct marker *m_phandle; - if (has_data_type_information(m)) { + if (is_type_marker(m->type)) { emit_type = m->type; fprintf(f, " %s", delim_start[emit_type]); } else if (m->type == LABEL) fprintf(f, " %s:", m->ref); - else if (m->offset) - fputc(' ', f); - if (emit_type == TYPE_NONE) { - assert(chunk_len == 0); + if (emit_type == TYPE_NONE || chunk_len == 0) continue; - } switch(emit_type) { case TYPE_UINT16: write_propval_int(f, p, chunk_len, 2); break; case TYPE_UINT32: - write_propval_int(f, p, chunk_len, 4); + m_phandle = prop->val.markers; + for_each_marker_of_type(m_phandle, REF_PHANDLE) + if (m->offset == m_phandle->offset) + break; + + if (m_phandle) { + if (m_phandle->ref[0] == '/') + fprintf(f, "&{%s}", m_phandle->ref); + else + fprintf(f, "&%s", m_phandle->ref); + if (chunk_len > 4) { + fputc(' ', f); + write_propval_int(f, p + 4, chunk_len - 4, 4); + } + } else { + write_propval_int(f, p, chunk_len, 4); + } break; case TYPE_UINT64: write_propval_int(f, p, chunk_len, 8); diff --git a/scripts/dtc/util.h b/scripts/dtc/util.h index a771b4654c76..c45b2c295aa5 100644 --- a/scripts/dtc/util.h +++ b/scripts/dtc/util.h @@ -13,10 +13,10 @@ */ #ifdef __GNUC__ -#ifdef __clang__ -#define PRINTF(i, j) __attribute__((format (printf, i, j))) -#else +#if __GNUC__ >= 5 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4) #define PRINTF(i, j) __attribute__((format (gnu_printf, i, j))) +#else +#define PRINTF(i, j) __attribute__((format (printf, i, j))) #endif #define NORETURN __attribute__((noreturn)) #else diff --git a/scripts/dtc/version_gen.h b/scripts/dtc/version_gen.h index 73a7839603f1..785cc4c57326 100644 --- a/scripts/dtc/version_gen.h +++ b/scripts/dtc/version_gen.h @@ -1 +1 @@ -#define DTC_VERSION "DTC 1.6.0-g183df9e9" +#define DTC_VERSION "DTC 1.6.1-g0a3a9d34" diff --git a/scripts/dtc/yamltree.c b/scripts/dtc/yamltree.c index e63d32fe142a..55908c829c98 100644 --- a/scripts/dtc/yamltree.c +++ b/scripts/dtc/yamltree.c @@ -29,11 +29,12 @@ char *yaml_error_name[] = { (emitter)->problem, __func__, __LINE__); \ }) -static void yaml_propval_int(yaml_emitter_t *emitter, struct marker *markers, char *data, unsigned int len, int width) +static void yaml_propval_int(yaml_emitter_t *emitter, struct marker *markers, + char *data, unsigned int seq_offset, unsigned int len, int width) { yaml_event_t event; void *tag; - unsigned int off, start_offset = markers->offset; + unsigned int off; switch(width) { case 1: tag = "!u8"; break; @@ -66,7 +67,7 @@ static void yaml_propval_int(yaml_emitter_t *emitter, struct marker *markers, ch m = markers; is_phandle = false; for_each_marker_of_type(m, REF_PHANDLE) { - if (m->offset == (start_offset + off)) { + if (m->offset == (seq_offset + off)) { is_phandle = true; break; } @@ -114,6 +115,7 @@ static void yaml_propval(yaml_emitter_t *emitter, struct property *prop) yaml_event_t event; unsigned int len = prop->val.len; struct marker *m = prop->val.markers; + struct marker *markers = prop->val.markers; /* Emit the property name */ yaml_scalar_event_initialize(&event, NULL, @@ -151,19 +153,19 @@ static void yaml_propval(yaml_emitter_t *emitter, struct property *prop) switch(m->type) { case TYPE_UINT16: - yaml_propval_int(emitter, m, data, chunk_len, 2); + yaml_propval_int(emitter, markers, data, m->offset, chunk_len, 2); break; case TYPE_UINT32: - yaml_propval_int(emitter, m, data, chunk_len, 4); + yaml_propval_int(emitter, markers, data, m->offset, chunk_len, 4); break; case TYPE_UINT64: - yaml_propval_int(emitter, m, data, chunk_len, 8); + yaml_propval_int(emitter, markers, data, m->offset, chunk_len, 8); break; case TYPE_STRING: yaml_propval_string(emitter, data, chunk_len); break; default: - yaml_propval_int(emitter, m, data, chunk_len, 1); + yaml_propval_int(emitter, markers, data, m->offset, chunk_len, 1); break; } } |