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| author | Vinay Belgaumkar <vinay.belgaumkar@intel.com> | 2023-11-17 16:14:49 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:45:08 -0500 |
| commit | 975e4a3795d4f1373be538177525c0b714e0e65e (patch) | |
| tree | 3c90febd24b445e133e8d6d4cdd465b1ceebea4c /drivers/gpu/drm/xe/regs | |
| parent | f1cb5f647e8959a1034941d85b311d7485a7095f (diff) | |
| download | lwn-975e4a3795d4f1373be538177525c0b714e0e65e.tar.gz lwn-975e4a3795d4f1373be538177525c0b714e0e65e.zip | |
drm/xe: Manually setup C6 when skip_guc_pc is set
Skip the init/start/stop GuC PC functions and toggle C6 using
register writes instead. Also request max possible frequency
as dynamic freq management is disabled.
v2: Fix compile warning
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 18b13224480d..d318ec0efd7d 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -272,7 +272,11 @@ #define RPSWCTL_ENABLE REG_FIELD_PREP(RPSWCTL_MASK, 2) #define RPSWCTL_DISABLE REG_FIELD_PREP(RPSWCTL_MASK, 0) #define RC_CONTROL XE_REG(0xa090) +#define RC_CTL_HW_ENABLE REG_BIT(31) +#define RC_CTL_TO_MODE REG_BIT(28) +#define RC_CTL_RC6_ENABLE REG_BIT(18) #define RC_STATE XE_REG(0xa094) +#define RC_IDLE_HYSTERSIS XE_REG(0xa0ac) #define PMINTRMSK XE_REG(0xa168) #define PMINTR_DISABLE_REDIRECT_TO_GUC REG_BIT(31) |