diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2024-07-08 16:40:03 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2024-07-08 16:40:15 +0200 |
| commit | 2d61b9303cec948fb619d18c6d5808ae7767e58b (patch) | |
| tree | 83f2e8102862950cd19073070a477333074970da | |
| parent | 462eeb978db8071722a3a546039943d42a297114 (diff) | |
| parent | 968178e35e78e566f75dbb7fbfc4dd1436ce8309 (diff) | |
| download | lwn-2d61b9303cec948fb619d18c6d5808ae7767e58b.tar.gz lwn-2d61b9303cec948fb619d18c6d5808ae7767e58b.zip | |
Merge tag 'qcom-arm64-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm64 DeviceTree updates for v6.11
This introduces 11 new boards, namely:
* ASUS Vivobook S 15
* Lenovo Smart Tab M10 DTS
* Motorola Moto E 2015 LTE (surnia)
* Motorola Moto G 2015 (osprey)
* Motorola Moto G4 Play (harpia)
* Qualcomm AIM300 AIoT development board
* Qualcomm SM8650 Hardware Development Kit (HDK)
* SHIFTphone 8
* Samsung Galaxy Z Fold5
* Schneider HMIBSC board DTS
* TP-Link Archer AX55 v1
Of particular interest here is the Asus Vivobook, the first supported X1
Elite consumer laptop.
For IPQ6018 an SDHCI controller is added and on IPQ9574 an MDIO bus is
described.
The improvements to MSM8916-based devices continues, with sound and
mdoem support added to Acer Iconia Talk S and GPLUS FL8005A, the latter
also gaining BMS support. Samsung Galaxy devices gains PMIC and charger
definitions, NFC support and MUIC. Accelerometer and magnetometer
support is added to the Samsung Galaxy Grand Prime devices.
On MSM8976 definitions for IOMMU, the display subsystem, wifi subsystem,
and Adreno GPU are added.
On MSM8996 UFS core clock frequencies are specified, FastRPC nodes are
added for the audio DSP, glink-edges are described where available, the
display subsystem reset is added.
Venus is introduced on MSM8998 and the "No MSA Ready" quirk is added to
allow ath10k to come up.
GPU support is added to QCM2290 and enabled on the RB1 development
board.
The I2C controller used for communicating with the LT9611UXC HDMI
bridge is temporarily replaced with i2c-gpio while issues with the
builtin controller is diagnosed. The same is done for RB2, on the
QRB4210 platform.
On RB2 TCPM max current draw is corrected and the vreg_l9a regulator is
marked as always on to match expectations.
On the QDU1000 platform, USB is added, secure QFPROM is introduced to
allow LLCC to access OTP data. USB is enabled on the two IDP boards.
SA8775p gains PCIe endpoint definitions, LLCCC support, IMEM and PIL
info regions. Nodes are marked as dma-coherent as needed, a dedicated
carveout for shared memory bridge allocations is introduced.
The SA8775P ride device is split in the two versions r2 and r3.
The SC7180 Trogdor clamshell/detachable fragments are refactored for
convenience, and pwmleds are disabled where unused.
On SC7280 the APR nodes for interfacing with the audio services in audio
DSP firmware are introduced. The Qualcomm SMMU TBUs are described, to
enable improved debug support. QoS clocks are added to interconnects, as
needed in order to operate the QoS settings on some buses.
SuperSpeed in park is disabled for the primary DWC3 instance to address
host controller issues under load.
The PM8008 (camera PMIC) is introduced in Fairphone 5, regulators are
named for better output, and firmware name for IPA is adjusted to the
preferred file format.
The HDMI bridge on Rb3gen2 is described, rtc, gpi-dma and qup nodes are
enabled.
The Type-C port manager found in PM7250b is enabled, for targets not
using pmic-glink firmware for Type-C management.
SC8180X gets a number of smaller corrections, and some cleanups -
related to both functional issues and DeviceTree validation.
The PSHOLD node is marked reserved, after reports that this causes
issues during shutdown. Description of the USB signals are updated to
match the signal path. The PM8008 camera PMIC is added to Lenovo
ThinkPad X13s.
The PM660 PMIC is extended with charger and rradc definitions, and the
SDM670 gains a SMEM region definition.
On SDM845 the Qualcomm SMMU TBU nodes are described, to enable improved
debug output during faults etc. The UFS PHY is associated with its GDSC,
and the DisplayPort controller is wired up to the QMP PHY.
The Lenovo Yoga C630 Embedded Controller is introduced, adding battery
and Type-C port management and altmode support. The C630 also gains WiFI
calibration variant information, to cause selection of the right data.
The missing IPA firmware path is corrected.
For the SDX75 platform, AOSS, IPCC, SDHCI, TCSR, modem SMP2P, I2C and
SPI nodes are introduced. SD-card support is added to the IDP board.
CPUfreq support is introduced for the SM4450 platform.
Missing reset is added to the SDHC controller of SM6115. The UFS PHY
is associated with its GDSC, so is the PHY on SM6350.
On Fairphone 4, the camera pmic (PM8008) is introduced, regulators are
named for more informative debug output, and USB role switching is
enabled.
On the Fairphone 3, vibrator support is added and enabled.
On SM8250, the USB signal paths are properly described in the OF graph,
the UFS PHY gains its required power-domains description.
Thanks to the introduction of PCI power sequence support, the QRB5165
RB5 WiFi chip can now be powered up, so this is added.
Touchscreen interrupt flags are corrected accross a number of Sony
Xperia devices, to remove the unexpected traces from downstream.
On SM8450 an OPP-table is introduced for the PCIe controllers, to
specify the bandwidth and performance state requirements for the
different genrations and link widths. For this the PCIe controllers also
gains interconnect path definitions. The LLCC register layout is
corrected, and the UFS PHY is associated with its GDSC.
On the SM8550 development boards speaker port mapping is added. WiFi
support is finally enabled on the QRD board.
The new AIM300 development platform/board is introduced.
For SM8650 video and camera clock controller are introduced. SCM node
gains details necessary to trigger USB ramdump (download mode) upon a
system crash.
WiFi support and speaker port mapping is added to the QRD and the newly
introduced HDK. On the MTP the USB Type-C connector is describe to be
routed to the PHY.
In addition to the base HDK, a Display Card overlay is also introduced.
For X1 Elite bwmon, fastrpc and GPU support, tsens, and the missing PCIe
6a instance are added. Thermal zones are described. Pmic-glink is
introduced for both CRD and QCP devices, and remaining PMICs are
described. Audio support is also added to the QCP.
An explicit, larger, chunk of CMA memory is added to the various
devices, in order to compensate for the lack of IOMMU for PCIe.
Across a wide range of platforms, the thermal zone polling delays are
removed as supplies are interrupt driven anyways. Also thermal related
is the introduction of GPU thermal throttling, across many SoCs.
The old SMSM implementation is finally transitioned to using the
mailbox-based description and implementation for invoking interrupts on
remote processors. As such interrupt-triggering is converted to use this
mechanism on related platforms.
The usb-role-switch property is removed for all USB instances hard coded
to either host or peripheral across a range of boards.
* tag 'qcom-arm64-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (279 commits)
dt-bindings: arm: qcom: Document samsung,ms013g
arm64: dts: qcom: Add device tree for ASUS Vivobook S 15
dt-bindings: arm: qcom: Add ASUS Vivobook S 15
arm64: dts: qcom: qrb4210-rb2: Correct max current draw for VBUS
arm64: dts: qcom: msm8998: add venus node
arm64: dts: qcom: sa8775p-ride-r3: add new board file
arm64: dts: qcom: move common parts for sa8775p-ride variants into a .dtsi
dt-bindings: arm: qcom: add sa8775p-ride Rev 3
arm64: dts: qcom: sm8550-qrd: add port mapping to speakers
arm64: dts: qcom: sm8550-mtp: add port mapping to speakers
arm64: dts: qcom: sm8550-hdk: add port mapping to speakers
arm64: dts: qcom: sm8650-qrd: add port mapping to speakers
arm64: dts: qcom: sm8650-mtp: add port mapping to speakers
arm64: dts: qcom: sm8650-hdk: add port mapping to speakers
arm64: dts: qcom: sm7225-fairphone-fp4: Name the regulators
arm64: dts: qcom: pm8916: correct thermal zone name
arm64: dts: qcom: x1e80100: Add gpu support
arm64: dts: qcom: x1e80100: Fix USB HS PHY 0.8V supply
arm64: dts: qcom: qcs6490-rb3gen2: enable hdmi bridge
arm64: dts: qcom: sm6115: add resets for sdhc_1
...
Link: https://lore.kernel.org/r/20240706173140.18887-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
193 files changed, 19692 insertions, 2578 deletions
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index ae885414b181..1c8643eeb2d1 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -42,6 +42,7 @@ description: | msm8996 msm8998 qcs404 + qcs8550 qcm2290 qcm6490 qdu1000 @@ -96,6 +97,7 @@ properties: - items: - enum: - qcom,apq8016-sbc + - schneider,apq8016-hmibsc - const: qcom,apq8016 - items: @@ -104,6 +106,7 @@ properties: - huawei,sturgeon - lg,lenok - samsung,matisse-wifi + - samsung,milletwifi - const: qcom,apq8026 - items: @@ -138,6 +141,7 @@ properties: - microsoft,makepeace - microsoft,moneypenny - motorola,falcon + - samsung,ms013g - samsung,s3ve3g - const: qcom,msm8226 @@ -175,6 +179,7 @@ properties: - items: - enum: - lge,hammerhead + - samsung,hlte - sony,xperia-amami - sony,xperia-honami - const: qcom,msm8974 @@ -182,8 +187,10 @@ properties: - items: - enum: - fairphone,fp2 + - htc,m8 - oneplus,bacon - samsung,klte + - sony,xperia-aries - sony,xperia-castor - sony,xperia-leo - const: qcom,msm8974pro @@ -205,6 +212,9 @@ properties: - huawei,g7 - longcheer,l8910 - longcheer,l8150 + - motorola,harpia + - motorola,osprey + - motorola,surnia - qcom,msm8916-mtp - samsung,a3u-eur - samsung,a5u-eur @@ -316,6 +326,7 @@ properties: - items: - enum: - qcom,ipq5018-rdp432-c2 + - tplink,archer-ax55-v1 - const: qcom,ipq5018 - items: @@ -366,6 +377,7 @@ properties: - fairphone,fp5 - qcom,qcm6490-idp - qcom,qcs6490-rb3gen2 + - shift,otter - const: qcom,qcm6490 - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform @@ -802,6 +814,7 @@ properties: - items: - enum: + - lenovo,tbx605f - motorola,ali - const: qcom,sdm450 @@ -883,6 +896,7 @@ properties: - items: - enum: - qcom,sa8775p-ride + - qcom,sa8775p-ride-r3 - const: qcom,sa8775p - items: @@ -1004,17 +1018,27 @@ properties: - qcom,sm8550-hdk - qcom,sm8550-mtp - qcom,sm8550-qrd + - samsung,q5q - sony,pdx234 - const: qcom,sm8550 - items: - enum: + - qcom,qcs8550-aim300-aiot + - const: qcom,qcs8550-aim300 + - const: qcom,qcs8550 + - const: qcom,sm8550 + + - items: + - enum: + - qcom,sm8650-hdk - qcom,sm8650-mtp - qcom,sm8650-qrd - const: qcom,sm8650 - items: - enum: + - asus,vivobook-s15 - qcom,x1e80100-crd - qcom,x1e80100-qcp - const: qcom,x1e80100 diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml new file mode 100644 index 000000000000..734880805c1b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on QCM2290 + +maintainers: + - Konrad Dybcio <konradybcio@kernel.org> + +description: | + Qualcomm graphics clock control module provides the clocks, resets and power + domains on Qualcomm SoCs. + + See also:: + include/dt-bindings/clock/qcom,qcm2290-gpucc.h + +properties: + compatible: + const: qcom,qcm2290-gpucc + + reg: + maxItems: 1 + + clocks: + items: + - description: AHB interface clock, + - description: SoC CXO clock + - description: GPLL0 main branch source + - description: GPLL0 div branch source + + power-domains: + description: + A phandle and PM domain specifier for the CX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required CX performance point. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-qcm2290.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@5990000 { + compatible = "qcom,qcm2290-gpucc"; + reg = <0x0 0x05990000 0x0 0x9000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmpd QCM2290_VDDCX>; + required-opps = <&rpmpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index fa0e5b6b02b8..f58edfc10f4c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -8,15 +8,17 @@ title: Qualcomm Camera Clock & Reset Controller on SM8450 maintainers: - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> + - Jagadeesh Kona <quic_jkona@quicinc.com> description: | Qualcomm camera clock control module provides the clocks, resets and power domains on SM8450. - See also:: + See also: + include/dt-bindings/clock/qcom,sc8280xp-camcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h - include/dt-bindings/clock/qcom,sc8280xp-camcc.h + include/dt-bindings/clock/qcom,sm8650-camcc.h include/dt-bindings/clock/qcom,x1e80100-camcc.h allOf: @@ -28,6 +30,7 @@ properties: - qcom,sc8280xp-camcc - qcom,sm8450-camcc - qcom,sm8550-camcc + - qcom,sm8650-camcc - qcom,x1e80100-camcc clocks: diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index bad8f019a8d3..8ce5972a65d5 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -8,18 +8,22 @@ title: Qualcomm Video Clock & Reset Controller on SM8450 maintainers: - Taniya Das <quic_tdas@quicinc.com> + - Jagadeesh Kona <quic_jkona@quicinc.com> description: | Qualcomm video clock control module provides the clocks, resets and power domains on SM8450. - See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h + See also: + include/dt-bindings/clock/qcom,sm8450-videocc.h + include/dt-bindings/clock/qcom,sm8650-videocc.h properties: compatible: enum: - qcom,sm8450-videocc - qcom,sm8550-videocc + - qcom,sm8650-videocc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index 8025a852bc9c..faef3d6e0a94 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -22,6 +22,7 @@ properties: - qcom,msm8974-imem - qcom,qcs404-imem - qcom,qdu1000-imem + - qcom,sa8775p-imem - qcom,sc7180-imem - qcom,sc7280-imem - qcom,sdm630-imem diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 1cacadd6a8dc..87ec6772b2d4 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1262,6 +1262,8 @@ patternProperties: description: Smart Battery System "^schindler,.*": description: Schindler + "^schneider,.*": + description: Schneider Electric "^seagate,.*": description: Seagate Technology PLC "^seeed,.*": diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f63abb43e9fe..e0babd642fa8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -5,11 +5,13 @@ apq8016-sbc-usb-host-dtbs := apq8016-sbc.dtb apq8016-sbc-usb-host.dtbo dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-usb-host.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3-camera-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8016-schneider-hmibsc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb @@ -31,6 +33,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-gplus-fl8005a.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-harpia.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-osprey.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-motorola-surnia.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb @@ -93,9 +98,11 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb @@ -106,6 +113,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb @@ -175,6 +183,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc8180x-primus.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm450-lenovo-tbx605f.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm450-motorola-ali.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb @@ -241,8 +250,15 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-samsung-q5q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb + +sm8650-hdk-display-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-qcp.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts b/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts new file mode 100644 index 000000000000..75c6137e5a11 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/apq8016-schneider-hmibsc.dts @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Ltd. + */ + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/pinctrl/qcom,pmic-mpp.h> +#include <dt-bindings/sound/apq8016-lpass.h> + +/ { + model = "Schneider Electric HMIBSC Board"; + compatible = "schneider,apq8016-hmibsc", "qcom,apq8016"; + + aliases { + i2c1 = &blsp_i2c6; + i2c3 = &blsp_i2c4; + i2c4 = &blsp_i2c3; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart1; + serial1 = &blsp_uart2; + spi0 = &blsp_spi5; + usid0 = &pm8916_0; + }; + + chosen { + stdout-path = "serial0"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-0 = <&msm_key_volp_n_default>; + pinctrl-names = "default"; + + button { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pm8916_mpps_leds>; + pinctrl-names = "default"; + + led-1 { + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_YELLOW>; + gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led-2 { + function = LED_FUNCTION_BLUETOOTH; + color = <LED_COLOR_ID_BLUE>; + gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; + + memory@80000000 { + reg = <0 0x80000000 0 0x40000000>; + }; + + reserved-memory { + ramoops@bff00000 { + compatible = "ramoops"; + reg = <0x0 0xbff00000 0x0 0x100000>; + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x20000>; + ecc-size = <16>; + }; + }; + + usb-hub { + compatible = "smsc,usb3503"; + reset-gpios = <&pm8916_gpios 1 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c3 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; +}; + +&blsp_i2c4 { + status = "okay"; + + adv_bridge: bridge@39 { + compatible = "adi,adv7533"; + reg = <0x39>; + interrupts-extended = <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + + adi,dsi-lanes = <4>; + clocks = <&rpmcc RPM_SMD_BB_CLK2>; + clock-names = "cec"; + pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; + + avdd-supply = <&pm8916_l6>; + a2vdd-supply = <&pm8916_l6>; + dvdd-supply = <&pm8916_l6>; + pvdd-supply = <&pm8916_l6>; + v1p2-supply = <&pm8916_l6>; + v3p3-supply = <&pm8916_l17>; + + pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; + pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; + pinctrl-names = "default","sleep"; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7533_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7533_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&blsp_i2c6 { + status = "okay"; + + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +&blsp_spi5 { + cs-gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <500000>; + }; +}; + +&blsp_uart1 { + label = "UART0"; + status = "okay"; +}; + +&blsp_uart2 { + label = "UART1"; + status = "okay"; +}; + +&lpass { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&adv7533_in>; +}; + +&pm8916_codec { + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + status = "okay"; +}; + +&pm8916_gpios { + gpio-line-names = + "USB_HUB_RESET_N_PM", + "USB_SW_SEL_PM", + "NC", + "NC"; + + usb_hub_reset_pm: usb-hub-reset-pm-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + input-disable; + output-high; + }; + + usb_hub_reset_pm_device: usb-hub-reset-pm-device-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + input-disable; + output-low; + }; + + usb_sw_sel_pm: usb-sw-sel-pm-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <PM8916_GPIO_VPH>; + input-disable; + output-high; + }; + + usb_sw_sel_pm_device: usb-sw-sel-pm-device-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <PM8916_GPIO_VPH>; + input-disable; + output-low; + }; +}; + +&pm8916_mpps { + gpio-line-names = + "NC", + "WLAN_LED_CTRL", + "BT_LED_CTRL", + "NC"; + + pm8916_mpps_leds: pm8916-mpps-state { + pins = "mpp2", "mpp3"; + function = "digital"; + output-low; + }; +}; + +&pm8916_resin { + linux,code = <KEY_POWER>; + status = "okay"; +}; + +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sound { + pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>; + pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>; + pinctrl-names = "default", "sleep"; + model = "HMIBSC"; + audio-routing = + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; + status = "okay"; + + quaternary-dai-link { + link-name = "ADV7533"; + cpu { + sound-dai = <&lpass MI2S_QUATERNARY>; + }; + codec { + sound-dai = <&adv_bridge 0>; + }; + }; + + primary-dai-link { + link-name = "WCD"; + cpu { + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>; + }; + }; + + tertiary-dai-link { + link-name = "WCD-Capture"; + cpu { + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>; + }; + }; +}; + +&tlmm { + pinctrl-0 = <&uart1_mux0_rs232_high &uart1_mux1_rs232_low>; + pinctrl-names = "default"; + + adv7533_int_active: adv533-int-active-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + adv7533_int_suspend: adv7533-int-suspend-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + adv7533_switch_active: adv7533-switch-active-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + adv7533_switch_suspend: adv7533-switch-suspend-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + msm_key_volp_n_default: msm-key-volp-n-default-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + /* + * UART1 being the debug console supports various modes of + * operation (RS-232/485/422) controlled via GPIOs configured + * mux as follows: + * + * gpio100 gpio99 UART mode + * 0 0 loopback + * 0 1 RS-232 + * 1 0 RS-485 + * 1 1 RS-422 + * + * The default mode configured here is RS-232 mode. + */ + uart1_mux0_rs232_high: uart1-mux0-rs232-state { + bootph-all; + pins = "gpio99"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + + uart1_mux1_rs232_low: uart1-mux1-rs232-state { + bootph-all; + pins = "gpio100"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; + pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; + pinctrl-names = "default", "device"; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&wcnss { + firmware-name = "qcom/apq8016/wcnss.mbn"; + status = "okay"; +}; + +&wcnss_ctrl { + firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + +&wcnss_mem { + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in msm8916.dtsi */ + +/* + * 2mA drive strength is not enough when connecting multiple + * I2C devices with different pull up resistors. + */ +&blsp_i2c4_default { + drive-strength = <16>; +}; + +&blsp_i2c6_default { + drive-strength = <16>; +}; + +&blsp_uart1_default { + bootph-all; +}; + +/* Enable CoreSight */ +&cti0 { status = "okay"; }; +&cti1 { status = "okay"; }; +&cti12 { status = "okay"; }; +&cti13 { status = "okay"; }; +&cti14 { status = "okay"; }; +&cti15 { status = "okay"; }; +&debug0 { status = "okay"; }; +&debug1 { status = "okay"; }; +&debug2 { status = "okay"; }; +&debug3 { status = "okay"; }; +&etf { status = "okay"; }; +&etm0 { status = "okay"; }; +&etm1 { status = "okay"; }; +&etm2 { status = "okay"; }; +&etm3 { status = "okay"; }; +&etr { status = "okay"; }; +&funnel0 { status = "okay"; }; +&funnel1 { status = "okay"; }; +&replicator { status = "okay"; }; +&stm { status = "okay"; }; +&tpiu { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts new file mode 100644 index 000000000000..5bb021cb29cd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +#include "ipq5018.dtsi" + +/ { + model = "TP-Link Archer AX55 v1"; + compatible = "tplink,archer-ax55-v1", "qcom,ipq5018"; + + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WAN_ONLINE; + gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WLAN_2GHZ; + gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_POWER; + gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + color = <LED_COLOR_ID_ORANGE>; + function = LED_FUNCTION_WAN; + gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_USB; + gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; + }; + + led-6 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WLAN_5GHZ; + gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>; + }; + }; + + buttons { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + button-reset { + debounce-interval = <60>; + gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = <KEY_RESTART>; + }; + + button-wps { + debounce-interval = <60>; + gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + }; + }; +}; + +&blsp1_uart1 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + button_pins: button-pins-state { + pins = "gpio25", "gpio31"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + led_pins: led-pins-state { + pins = "gpio10", "gpio11", "gpio13", "gpio18", "gpio22", + "gpio38", "gpio39"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + uart_pins: uart-pins-state { + pins = "gpio20", "gpio21"; + function = "blsp0_uart0"; + drive-strength = <8>; + bias-disable; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 32b178b639f0..7e6e2c121979 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -179,7 +179,6 @@ <0>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; }; tcsr_mutex: hwlock@1905000 { diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 770d9c2fb456..573656587c0d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -208,7 +208,6 @@ reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; clocks = <&xo_board>, <&sleep_clk>, <0>, diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 17ab6c475958..b3b98f050cfd 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -396,7 +396,7 @@ }; }; - gcc: gcc@1800000 { + gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq6018"; reg = <0x0 0x01800000 0x0 0x80000>; clocks = <&xo>, <&sleep_clk>; @@ -457,6 +457,25 @@ }; }; + sdhc: mmc@7804000 { + compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x07804000 0x0 0x1000>, + <0x0 0x07805000 0x0 0x1000>; + reg-names = "hc", "cqhci"; + + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC1_BCR>; + max-frequency = <192000000>; + status = "disabled"; + }; + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x07884000 0x0 0x2b000>; @@ -923,7 +942,6 @@ thermal-zones { nss-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 4>; trips { @@ -937,7 +955,6 @@ nss-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 5>; trips { @@ -951,7 +968,6 @@ wcss-phya0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 7>; trips { @@ -979,7 +995,6 @@ cpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 13>; trips { @@ -1009,7 +1024,6 @@ lpass-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 14>; trips { @@ -1023,7 +1037,6 @@ ddrss-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 15>; trips { diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 5d42de829e75..92682d3c9478 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -363,7 +363,7 @@ }; }; - gcc: gcc@1800000 { + gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq8074"; reg = <0x01800000 0x80000>; clocks = <&xo>, @@ -982,7 +982,6 @@ thermal-zones { nss-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 4>; @@ -997,7 +996,6 @@ nss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 5>; @@ -1012,7 +1010,6 @@ nss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 6>; @@ -1027,7 +1024,6 @@ wcss-phya0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 7>; @@ -1042,7 +1038,6 @@ wcss-phya1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 8>; @@ -1057,7 +1052,6 @@ cpu0_thermal: cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 9>; @@ -1072,7 +1066,6 @@ cpu1_thermal: cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 10>; @@ -1087,7 +1080,6 @@ cpu2_thermal: cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 11>; @@ -1102,7 +1094,6 @@ cpu3_thermal: cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 12>; @@ -1117,7 +1108,6 @@ cluster_thermal: cluster-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 13>; @@ -1132,7 +1122,6 @@ wcss-phyb0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 14>; @@ -1147,7 +1136,6 @@ wcss-phyb1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 15>; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 7f2e5cbf3bbb..04ba09a9156c 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -232,6 +232,16 @@ clock-names = "core"; }; + mdio: mdio@90000 { + compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio"; + reg = <0x00090000 0x64>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_MDIO_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + }; + qfprom: efuse@a4000 { compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x5a1>; @@ -305,7 +315,6 @@ <0>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; }; tcsr_mutex: hwlock@1905000 { @@ -749,8 +758,6 @@ thermal-zones { nss-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 3>; trips { @@ -763,8 +770,6 @@ }; ubi-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 4>; trips { @@ -777,8 +782,6 @@ }; ubi-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 5>; trips { @@ -791,8 +794,6 @@ }; ubi-2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 6>; trips { @@ -805,8 +806,6 @@ }; ubi-3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 7>; trips { @@ -819,8 +818,6 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 8>; trips { @@ -833,8 +830,6 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 9>; trips { @@ -847,8 +842,6 @@ }; cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 10>; trips { @@ -877,8 +870,6 @@ }; cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 11>; trips { @@ -907,8 +898,6 @@ }; cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 12>; trips { @@ -937,8 +926,6 @@ }; cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 13>; trips { @@ -967,8 +954,6 @@ }; wcss-phyb-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 14>; trips { @@ -981,8 +966,6 @@ }; top-glue-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens 15>; trips { diff --git a/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts b/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts index 366914be7d53..fba68bf8bf79 100644 --- a/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts +++ b/arch/arm64/boot/dts/qcom/msm8216-samsung-fortuna3g.dts @@ -9,3 +9,17 @@ compatible = "samsung,fortuna3g", "qcom,msm8916"; chassis-type = "handset"; }; + +&battery { + charge-term-current-microamp = <200000>; + constant-charge-current-max-microamp = <1000000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + +&st_accel { + status = "okay"; +}; + +&st_magn { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index b32c7a97394d..b4ce14a79370 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "msm8916-pm8916.dtsi" +#include "msm8916-modem-qdsp6.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -135,6 +136,17 @@ status = "okay"; }; +&mpss_mem { + reg = <0x0 0x86800000 0x0 0x4500000>; +}; + +&pm8916_codec { + qcom,micbias-lvl = <2800>; + qcom,mbhc-vthreshold-low = <150 237 450 500 590>; + qcom,mbhc-vthreshold-high = <150 237 450 500 590>; + qcom,hphl-jack-type-normally-open; +}; + &pm8916_resin { linux,code = <KEY_VOLUMEDOWN>; status = "okay"; @@ -170,6 +182,20 @@ status = "okay"; }; +&sound { + model = "acer-a1-724"; + audio-routing = + "DMIC1", "MIC BIAS External1", + "DMIC1", "Digital Mic1", + "AMIC2", "MIC BIAS Internal2", + "DMIC2", "MIC BIAS External1", + "DMIC2", "Digital Mic2"; + + pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default &pri_mi2s_mclk_default &cdc_dmic_default>; + pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep &pri_mi2s_mclk_sleep &cdc_dmic_sleep>; + pinctrl-names = "default", "sleep"; +}; + &usb { extcon = <&usb_id>, <&usb_id>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index b748d140b52e..f7be7e371820 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "msm8916-pm8916.dtsi" +#include "msm8916-modem-qdsp6.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> @@ -23,6 +24,28 @@ stdout-path = "serial0"; }; + battery: battery { + compatible = "simple-battery"; + device-chemistry = "lithium-ion-polymer"; + voltage-min-design-microvolt = <3700000>; + voltage-max-design-microvolt = <4200000>; + energy-full-design-microwatt-hours = <13690000>; + charge-full-design-microamp-hours = <3700000>; + + ocv-capacity-celsius = <25>; + ocv-capacity-table-0 = + <4186000 100>, <4126000 95>, <4078000 90>, + <4036000 85>, <3997000 80>, <3962000 75>, + <3932000 70>, <3904000 65>, <3874000 60>, + <3839000 55>, <3809000 50>, <3792000 45>, + <3780000 40>, <3772000 35>, <3764000 30>, + <3752000 25>, <3731000 20>, <3704000 16>, + <3677000 13>, <3670000 11>, <3668000 10>, + <3666000 9>, <3662000 8>, <3658000 7>, <3648000 6>, + <3624000 5>, <3580000 4>, <3518000 3>, <3434000 2>, + <3310000 1>, <3000000 0>; + }; + flash-led-controller { /* Actually qcom,leds-gpio-flash */ compatible = "sgmicro,sgm3140"; @@ -111,6 +134,22 @@ status = "okay"; }; +&mpss_mem { + reg = <0x0 0x86800000 0x0 0x5000000>; +}; + +&pm8916_bms { + monitored-battery = <&battery>; + status = "okay"; +}; + +&pm8916_codec { + qcom,micbias-lvl = <2800>; + qcom,mbhc-vthreshold-low = <150 180 237 450 500>; + qcom,mbhc-vthreshold-high = <150 180 237 450 500>; + qcom,hphl-jack-type-normally-open; +}; + &pm8916_resin { linux,code = <KEY_VOLUMEDOWN>; status = "okay"; @@ -141,6 +180,14 @@ status = "okay"; }; +&sound { + model = "msm8916-1mic"; + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; +}; + &usb { extcon = <&usb_id>, <&usb_id>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi new file mode 100644 index 000000000000..6a27d0ecd2ad --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-motorola-common.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8916-pm8916.dtsi" +#include "msm8916-modem-qdsp6.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + aliases { + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart1; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + volume-up-button { + label = "Volume Up"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + }; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-1 = <&usb_id_sleep>; + pinctrl-names = "default", "sleep"; + }; +}; + +&blsp_i2c2 { + status = "okay"; + + touchscreen: touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + vio-supply = <&pm8916_l6>; + + syna,startup-delay-ms = <100>; + + rmi4-f01@1 { + reg = <1>; + syna,nosleep-mode = <1>; /* Allow sleeping */ + }; + + rmi4-f11@11 { + reg = <11>; + syna,sensor-type = <1>; /* Touchscreen */ + }; + }; +}; + +&blsp_uart1 { + status = "okay"; +}; + +&mpss_mem { + reg = <0x0 0x86800000 0x0 0x5500000>; +}; + +&pm8916_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pm8916_rpm_regulators { + pm8916_l16: l16 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&pm8916_vib { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&venus { + status = "okay"; +}; + +&venus_mem { + status = "okay"; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + +&wcnss_mem { + status = "okay"; +}; + +/* CTS/RTX are not used */ +&blsp_uart1_default { + pins = "gpio0", "gpio1"; +}; +&blsp_uart1_sleep { + pins = "gpio0", "gpio1"; +}; + +&tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + usb_id_sleep: usb-id-sleep-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-motorola-harpia.dts b/arch/arm64/boot/dts/qcom/msm8916-motorola-harpia.dts new file mode 100644 index 000000000000..8380451ebbf6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-motorola-harpia.dts @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-motorola-common.dtsi" + +/ { + model = "Motorola Moto G4 Play"; + compatible = "motorola,harpia", "qcom,msm8916"; + chassis-type = "handset"; +}; + +&blsp_i2c1 { + status = "okay"; + + battery@36 { + compatible = "maxim,max17050"; + reg = <0x36>; + + interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&battery_alert_default>; + pinctrl-names = "default"; + + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <600>; + maxim,cold-temp = <(-200)>; + maxim,dead-volt = <3200>; + maxim,over-volt = <4500>; + }; + + /* charger@6b */ +}; + +&blsp_i2c4 { + status = "okay"; + + accelerometer@19 { + compatible = "bosch,bma253"; + reg = <0x19>; + + interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_RISING>, + <&tlmm 119 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + }; + + /* proximity@49 */ +}; + +&pm8916_codec { + qcom,micbias-lvl = <2800>; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + qcom,micbias1-ext-cap; +}; + +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; +}; + +&sound { + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; + + pinctrl-0 = <&cdc_pdm_default &headset_switch_supply_en + &headset_switch_in>; + pinctrl-1 = <&cdc_pdm_sleep &headset_switch_supply_en + &headset_switch_in>; + pinctrl-names = "default", "sleep"; +}; + +&touchscreen { + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&pm8916_l16>; + + pinctrl-0 = <&ts_int_default>; + pinctrl-names = "default"; +}; + +&tlmm { + accel_int_default: accel-int-default-state { + pins = "gpio115", "gpio119"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + battery_alert_default: battery-alert-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + headset_switch_in: headset-switch-in-state { + pins = "gpio112"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + headset_switch_supply_en: headset-switch-supply-en-state { + pins = "gpio111"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio118"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-motorola-osprey.dts b/arch/arm64/boot/dts/qcom/msm8916-motorola-osprey.dts new file mode 100644 index 000000000000..ec5589fc69bd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-motorola-osprey.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-motorola-common.dtsi" + +/ { + model = "Motorola Moto G 2015"; + compatible = "motorola,osprey", "qcom,msm8916"; + chassis-type = "handset"; + + reg_touch_vdda: regulator-touch-vdda { + compatible = "regulator-fixed"; + regulator-name = "touch_vdda"; + gpio = <&tlmm 114 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&touch_vdda_default>; + pinctrl-names = "default"; + startup-delay-us = <300>; + vin-supply = <&pm8916_l16>; + }; +}; + +&blsp_i2c1 { + status = "okay"; + + battery@36 { + compatible = "maxim,max17050"; + reg = <0x36>; + + interrupts-extended = <&tlmm 49 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&battery_alert_default>; + pinctrl-names = "default"; + + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <600>; + maxim,cold-temp = <(-200)>; + maxim,dead-volt = <3200>; + maxim,over-volt = <4500>; + + }; +}; + +&blsp_i2c6 { + /* magnetometer@c */ +}; + +&pm8916_codec { + qcom,micbias1-ext-cap; + qcom,micbias2-ext-cap; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; +}; + +&sound { + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC3", "MIC BIAS External1"; +}; + +&touchscreen { + interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <®_touch_vdda>; + + pinctrl-0 = <&ts_int_default>; + pinctrl-names = "default"; +}; + +&tlmm { + battery_alert_default: battery-alert-default-state { + pins = "gpio49"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touch_vdda_default: touch-vdda-default-state { + pins = "gpio114"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-motorola-surnia.dts b/arch/arm64/boot/dts/qcom/msm8916-motorola-surnia.dts new file mode 100644 index 000000000000..eecf78ba45bb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-motorola-surnia.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-motorola-common.dtsi" + +/ { + model = "Motorola Moto E 2015 LTE"; + compatible = "motorola,surnia", "qcom,msm8916"; + chassis-type = "handset"; +}; + +&blsp_i2c4 { + status = "okay"; + + battery@36 { + compatible = "maxim,max17050"; + reg = <0x36>; + + interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&battery_alert_default>; + pinctrl-names = "default"; + + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <600>; + maxim,cold-temp = <(-200)>; + maxim,dead-volt = <3200>; + maxim,over-volt = <4500>; + + }; +}; + +&pm8916_codec { + qcom,micbias1-ext-cap; + qcom,micbias2-ext-cap; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; +}; + +&sound { + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC3", "MIC BIAS External1"; +}; + +&touchscreen { + interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&pm8916_l16>; + + pinctrl-0 = <&ts_int_default>; + pinctrl-names = "default"; +}; + +&tlmm { + battery_alert_default: battery-alert-default-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 4bbbee80b5e4..e6355e5e2177 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -28,6 +28,12 @@ }; }; + battery: battery { + compatible = "simple-battery"; + precharge-current-microamp = <450000>; + precharge-upper-limit-microvolt = <3500000>; + }; + clk_pwm: pwm { compatible = "clk-pwm"; #pwm-cells = <2>; @@ -245,7 +251,7 @@ &blsp_i2c4 { status = "okay"; - battery@35 { + fuel-gauge@35 { compatible = "richtek,rt5033-battery"; reg = <0x35>; interrupt-parent = <&tlmm>; @@ -253,6 +259,44 @@ pinctrl-names = "default"; pinctrl-0 = <&fg_alert_default>; + + power-supplies = <&charger>; + }; +}; + +&blsp_i2c6 { + status = "okay"; + + pmic@34 { + compatible = "richtek,rt5033"; + reg = <0x34>; + + interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&pmic_int_default>; + pinctrl-names = "default"; + + regulators { + rt5033_reg_safe_ldo: SAFE_LDO { + regulator-min-microvolt = <4900000>; + regulator-max-microvolt = <4900000>; + regulator-always-on; + }; + + /* + * Needed for camera, but not used yet. + * Define empty nodes to allow disabling the unused + * regulators. + */ + LDO {}; + BUCK {}; + }; + + charger: charger { + compatible = "richtek,rt5033-charger"; + monitored-battery = <&battery>; + richtek,usb-connector = <&usb_con>; + }; }; }; @@ -476,6 +520,13 @@ bias-disable; }; + pmic_int_default: pmic-int-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + sdc2_cd_default: sdc2-cd-default-state { pins = "gpio38"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index 3b934f5eba47..906d31f1ea21 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -55,6 +55,12 @@ "0", "0", "1"; }; +&battery { + charge-term-current-microamp = <150000>; + constant-charge-current-max-microamp = <1000000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + &blsp_i2c5 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts index 391befa22bb4..fe39be7a742b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts @@ -29,6 +29,12 @@ "0", "0", "1"; }; +&battery { + charge-term-current-microamp = <200000>; + constant-charge-current-max-microamp = <1500000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + &blsp_i2c5 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts index fad2535255f7..800cb1038da0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts @@ -23,6 +23,12 @@ chassis-type = "handset"; }; +&battery { + charge-term-current-microamp = <200000>; + constant-charge-current-max-microamp = <1500000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + &blsp_i2c5 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e7.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-e7.dts index b412b61ca258..ec1debd2e245 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e7.dts @@ -23,6 +23,13 @@ chassis-type = "handset"; }; +&battery { + charge-term-current-microamp = <200000>; + constant-charge-current-max-microamp = <1500000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + + &pm8916_l17 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index 5e933fb8b363..81b3e0760154 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> / { aliases { @@ -26,6 +27,12 @@ }; }; + battery: battery { + compatible = "simple-battery"; + precharge-current-microamp = <450000>; + precharge-upper-limit-microvolt = <3500000>; + }; + clk_pwm_backlight: backlight { compatible = "pwm-backlight"; pwms = <&clk_pwm 0 100000>; @@ -78,6 +85,35 @@ max-microvolt = <3300000>; }; + i2c_nfc: i2c-nfc { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&nfc_i2c_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + s3fwrn5_nfc: nfc@27 { + compatible = "samsung,s3fwrn5-i2c"; + reg = <0x27>; + + interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_RISING>; + + en-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>; + + clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; + + pinctrl-0 = <&nfc_default>, <&nfc_clk_req>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + reg_motor_vdd: regulator-motor-vdd { compatible = "regulator-fixed"; regulator-name = "motor_vdd"; @@ -114,6 +150,82 @@ interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>; pinctrl-0 = <&muic_int_default>; pinctrl-names = "default"; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; + }; +}; + +&blsp_i2c2 { + /* Available sensors vary depending on model variant */ + status = "okay"; + + bosch_accel: accelerometer@10 { + compatible = "bosch,bmc150_accel"; + reg = <0x10>; + interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l5>; + vddio-supply = <&pm8916_l5>; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + + status = "disabled"; + }; + + bosch_magn: magnetometer@12 { + compatible = "bosch,bmc150_magn"; + reg = <0x12>; + + vdd-supply = <&pm8916_l5>; + vddio-supply = <&pm8916_l5>; + + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + + status = "disabled"; + }; + + st_accel: accelerometer@1d { + compatible = "st,lsm303c-accel"; + reg = <0x1d>; + interrupts-extended = <&tlmm 115 IRQ_TYPE_LEVEL_HIGH>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + + st,drdy-int-pin = <1>; + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "-1"; + + status = "disabled"; + }; + + st_magn: magnetometer@1e { + compatible = "st,lsm303c-magn"; + reg = <0x1e>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; + + mount-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "-1"; + + status = "disabled"; }; }; @@ -128,6 +240,8 @@ pinctrl-0 = <&fg_alert_default>; pinctrl-names = "default"; + + power-supplies = <&charger>; }; }; @@ -151,6 +265,42 @@ }; }; +&blsp_i2c6 { + status = "okay"; + + pmic@34 { + compatible = "richtek,rt5033"; + reg = <0x34>; + + interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&pmic_int_default>; + pinctrl-names = "default"; + + regulators { + rt5033_reg_safe_ldo: SAFE_LDO { + regulator-min-microvolt = <4900000>; + regulator-max-microvolt = <4900000>; + regulator-always-on; + }; + + /* + * Needed for camera, but not used yet. + * Define empty nodes to allow disabling the unused + * regulators. + */ + LDO {}; + BUCK {}; + }; + + charger: charger { + compatible = "richtek,rt5033-charger"; + monitored-battery = <&battery>; + richtek,usb-connector = <&usb_con>; + }; + }; +}; + &blsp_uart2 { status = "okay"; }; @@ -223,6 +373,13 @@ }; &tlmm { + accel_int_default: accel-int-default-state { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + backlight_en_default: backlight-en-default-state { pins = "gpio98"; function = "gpio"; @@ -263,6 +420,36 @@ bias-disable; }; + nfc_default: nfc-default-state { + irq-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + nfc-pins { + pins = "gpio20", "gpio49"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + nfc_i2c_default: nfc-i2c-default-state { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pmic_int_default: pmic-int-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + sdc2_cd_default: sdc2-cd-default-state { pins = "gpio38"; function = "gpio"; @@ -284,3 +471,13 @@ bias-disable; }; }; + +&pm8916_gpios { + nfc_clk_req: nfc-clk-req-state { + pins = "gpio2"; + function = "func1"; + power-source = <PM8916_GPIO_L2>; + bias-disable; + input-enable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts index 9d65fa58ba92..677e4e286ac0 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gprimeltecan.dts @@ -21,6 +21,76 @@ }; }; +&battery { + charge-term-current-microamp = <200000>; + constant-charge-current-max-microamp = <1000000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + +&bosch_accel { + status = "okay"; +}; + +&bosch_magn { + status = "okay"; +}; + +&blsp_i2c6 { + /* pmic@34 is on i2c_nfc instead */ + /delete-node/ pmic@34; + + nfc@27 { + compatible = "samsung,s3fwrn5-i2c"; + reg = <0x27>; + + interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_RISING>; + + en-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>; + + clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>; + + pinctrl-0 = <&nfc_default>, <&nfc_clk_req>; + pinctrl-names = "default"; + }; +}; + +&i2c_nfc { + /* nfc@27 is on &blsp_i2c6 */ + + pmic@34 { + compatible = "richtek,rt5033"; + reg = <0x34>; + + interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&pmic_int_default>; + pinctrl-names = "default"; + + regulators { + rt5033_reg_safe_ldo: SAFE_LDO { + regulator-min-microvolt = <4900000>; + regulator-max-microvolt = <4900000>; + regulator-always-on; + }; + + /* + * Needed for camera, but not used yet. + * Define empty nodes to allow disabling the unused + * regulators. + */ + LDO {}; + BUCK {}; + }; + + charger: charger { + compatible = "richtek,rt5033-charger"; + monitored-battery = <&battery>; + richtek,usb-connector = <&usb_con>; + }; + }; +}; + &mpss_mem { /* Firmware for gprimeltecan needs more space */ reg = <0x0 0x86800000 0x0 0x5400000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts index 5882b3a593b8..135df1739dbd 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts @@ -41,6 +41,12 @@ }; }; +&battery { + charge-term-current-microamp = <150000>; + constant-charge-current-max-microamp = <1000000>; + constant-charge-voltage-max-microvolt = <4400000>; +}; + ®_motor_vdd { gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts index a66ce4b13547..582bfcb09684 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandprimelte.dts @@ -10,6 +10,20 @@ chassis-type = "handset"; }; +&battery { + charge-term-current-microamp = <200000>; + constant-charge-current-max-microamp = <1000000>; + constant-charge-voltage-max-microvolt = <4350000>; +}; + +&bosch_accel { + status = "okay"; +}; + +&bosch_magn { + status = "okay"; +}; + &mpss_mem { /* Firmware for grandprimelte needs more space */ reg = <0x0 0x86800000 0x0 0x5400000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi index b438fa81886c..e7f265e3c2ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi @@ -15,6 +15,12 @@ interrupts-extended = <&tlmm 12 IRQ_TYPE_EDGE_FALLING>; pinctrl-0 = <&muic_int_default>; pinctrl-names = "default"; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; @@ -26,3 +32,15 @@ &clk_pwm_backlight { status = "disabled"; }; + +&s3fwrn5_nfc { + status = "okay"; +}; + +&st_accel { + compatible = "st,lis2hh12"; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts index ebaa13c6b016..1981bb71f6a9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa.dts @@ -10,6 +10,12 @@ chassis-type = "handset"; }; +&battery { + charge-term-current-microamp = <150000>; + constant-charge-current-max-microamp = <700000>; + constant-charge-voltage-max-microvolt = <4400000>; +}; + &mpss_mem { /* Firmware for rossa needs more space */ reg = <0x0 0x86800000 0x0 0x5800000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index cedff4166bfb..7383bcc603ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -308,7 +308,7 @@ smd-edge { interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 0>; + mboxes = <&apcs 0>; qcom,smd-edge = <15>; rpm_requests: rpm-requests { @@ -360,7 +360,7 @@ interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 14>; + mboxes = <&apcs 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; @@ -385,7 +385,7 @@ interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 18>; + mboxes = <&apcs 18>; qcom,local-pid = <0>; qcom,remote-pid = <4>; @@ -410,8 +410,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-3 = <&apcs 8 19>; + mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>; apps_smsm: apps@0 { reg = <0>; @@ -1978,7 +1977,7 @@ interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; qcom,smd-edge = <0>; - qcom,ipc = <&apcs 8 12>; + mboxes = <&apcs 12>; qcom,remote-pid = <1>; label = "hexagon"; @@ -2459,7 +2458,7 @@ smd-edge { interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 17>; + mboxes = <&apcs 17>; qcom,smd-edge = <6>; qcom,remote-pid = <4>; @@ -2626,7 +2625,6 @@ thermal-zones { cpu0-1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 5>; @@ -2656,7 +2654,6 @@ cpu2-3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 4>; @@ -2686,7 +2683,6 @@ gpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 2>; @@ -2713,7 +2709,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 1>; @@ -2728,7 +2723,6 @@ modem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 0>; diff --git a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts index 0c599e71a464..91acdb160227 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts @@ -33,6 +33,15 @@ }; }; + battery: battery { + compatible = "simple-battery"; + charge-term-current-microamp = <150000>; + constant-charge-current-max-microamp = <1500000>; + constant-charge-voltage-max-microvolt = <4300000>; + precharge-current-microamp = <450000>; + precharge-upper-limit-microvolt = <3500000>; + }; + gpio-hall-sensor { compatible = "gpio-keys"; @@ -82,7 +91,7 @@ #address-cells = <1>; #size-cells = <0>; - battery@35 { + fuel-gauge@35 { compatible = "richtek,rt5033-battery"; reg = <0x35>; @@ -91,6 +100,8 @@ pinctrl-0 = <&fg_alert_default>; pinctrl-names = "default"; + + power-supplies = <&charger>; }; }; @@ -325,6 +336,42 @@ }; }; +&blsp_i2c6 { + status = "okay"; + + pmic@34 { + compatible = "richtek,rt5033"; + reg = <0x34>; + + interrupts-extended = <&tlmm 62 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&pmic_int_default>; + pinctrl-names = "default"; + + regulators { + rt5033_reg_safe_ldo: SAFE_LDO { + regulator-min-microvolt = <4900000>; + regulator-max-microvolt = <4900000>; + regulator-always-on; + }; + + /* + * Needed for camera, but not used yet. + * Define empty nodes to allow disabling the unused + * regulators. + */ + LDO {}; + BUCK {}; + }; + + charger: charger { + compatible = "richtek,rt5033-charger"; + monitored-battery = <&battery>; + richtek,usb-connector = <&usb_con>; + }; + }; +}; + &blsp_uart2 { status = "okay"; }; @@ -510,6 +557,13 @@ bias-disable; }; + pmic_int_default: pmic-int-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + reg_tsp_en_default: reg-tsp-en-default-state { pins = "gpio73"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index dd45975682b2..46d9480cd464 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -248,7 +248,7 @@ smd-edge { interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs1_mbox 8 0>; + mboxes = <&apcs1_mbox 0>; qcom,smd-edge = <15>; rpm_requests: rpm-requests { @@ -443,8 +443,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,ipc-1 = <&apcs1_mbox 8 13>; - qcom,ipc-3 = <&apcs1_mbox 8 19>; + mboxes = <0>, <&apcs1_mbox 13>, <0>, <&apcs1_mbox 19>; apps_smsm: apps@0 { reg = <0>; @@ -2067,7 +2066,7 @@ smd-edge { interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs1_mbox 8 17>; + mboxes = <&apcs1_mbox 17>; qcom,smd-edge = <6>; qcom,remote-pid = <4>; @@ -2299,7 +2298,6 @@ thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 5>; @@ -2330,7 +2328,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 6>; @@ -2361,7 +2358,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 7>; @@ -2392,7 +2388,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 8>; @@ -2423,7 +2418,6 @@ cpu4567-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 9>; @@ -2454,7 +2448,6 @@ gpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 3>; @@ -2482,7 +2475,6 @@ modem1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 0>; @@ -2497,7 +2489,6 @@ modem2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 2>; @@ -2512,7 +2503,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 1>; diff --git a/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts b/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts index 711d84dad9d7..2edf804eb7c9 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts @@ -301,5 +301,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts index a5957e79b818..336b916729e4 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts @@ -321,5 +321,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts index 6b9245cd8b0c..bdf1bfc79c56 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts @@ -326,5 +326,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts index 9ac4f507e321..fccb9c4360ca 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts @@ -322,5 +322,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts index b0588f30f8f1..d46325e79917 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts @@ -357,5 +357,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 5d818fe057dd..a4bfb624fb8a 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -195,7 +195,7 @@ smd-edge { interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 0>; + mboxes = <&apcs 0>; qcom,smd-edge = <15>; rpm_requests: rpm-requests { @@ -361,7 +361,7 @@ interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 14>; + mboxes = <&apcs 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; @@ -386,7 +386,7 @@ interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 18>; + mboxes = <&apcs 18>; qcom,local-pid = <0>; qcom,remote-pid = <4>; @@ -411,8 +411,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-3 = <&apcs 8 19>; + mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>; apps_smsm: apps@0 { reg = <0>; @@ -1267,7 +1266,7 @@ interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; qcom,smd-edge = <0>; - qcom,ipc = <&apcs 8 12>; + mboxes = <&apcs 12>; qcom,remote-pid = <1>; label = "modem"; @@ -1748,7 +1747,7 @@ smd-edge { interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 17>; + mboxes = <&apcs 17>; qcom,smd-edge = <6>; qcom,remote-pid = <4>; @@ -1968,8 +1967,9 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens0 9>; + trips { cpu0_alert: trip-point0 { temperature = <80000>; @@ -1991,8 +1991,9 @@ }; cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens0 10>; + trips { cpu1_alert: trip-point0 { temperature = <80000>; @@ -2014,8 +2015,9 @@ }; cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens0 11>; + trips { cpu2_alert: trip-point0 { temperature = <80000>; @@ -2037,8 +2039,9 @@ }; cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens0 12>; + trips { cpu3_alert: trip-point0 { temperature = <80000>; @@ -2060,7 +2063,6 @@ }; cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; trips { cpu4_alert: trip-point0 { @@ -2083,7 +2085,6 @@ }; cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; trips { cpu5_alert: trip-point0 { @@ -2106,7 +2107,6 @@ }; cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; trips { cpu6_alert: trip-point0 { @@ -2129,7 +2129,6 @@ }; cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; trips { cpu7_alert: trip-point0 { @@ -2153,7 +2152,6 @@ gpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 15>; trips { diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi index 668e05185c21..fa36b62156bb 100644 --- a/arch/arm64/boot/dts/qcom/msm8956.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi @@ -8,8 +8,8 @@ #include "msm8976.dtsi" -&pmu { - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; +&pmu_a72 { + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0x30) | IRQ_TYPE_LEVEL_HIGH)>; }; &tsens { diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index d2bb1ada361a..d62dcb76fa48 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -222,11 +222,17 @@ reg = <0x0 0x80000000 0x0 0x0>; }; - pmu: pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + pmu-a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + pmu_a72: pmu-a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -237,7 +243,7 @@ smd-edge { interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 0>; + mboxes = <&apcs 0>; qcom,smd-edge = <15>; rpm_requests: rpm-requests { @@ -361,7 +367,7 @@ smp2p-hexagon { compatible = "qcom,smp2p"; interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 10>; + mboxes = <&apcs 10>; qcom,local-pid = <0>; qcom,remote-pid = <2>; @@ -384,7 +390,7 @@ smp2p-modem { compatible = "qcom,smp2p"; interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 14>; + mboxes = <&apcs 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; @@ -407,7 +413,7 @@ smp2p-wcnss { compatible = "qcom,smp2p"; interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 18>; + mboxes = <&apcs 18>; qcom,local-pid = <0>; qcom,remote-pid = <4>; @@ -433,9 +439,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-2 = <&apcs 8 9>; - qcom,ipc-3 = <&apcs 8 19>; + mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; apps_smsm: apps@0 { reg = <0>; @@ -771,6 +775,36 @@ drive-strength = <2>; bias-disable; }; + + wcss_wlan_default: wcss-wlan-default-state { + wcss-wlan2-pins { + pins = "gpio40"; + function = "wcss_wlan2"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan1-pins { + pins = "gpio41"; + function = "wcss_wlan1"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan0-pins { + pins = "gpio42"; + function = "wcss_wlan0"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan-pins { + pins = "gpio43", "gpio44"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; + }; }; gcc: clock-controller@1800000 { @@ -785,10 +819,10 @@ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, - <0>, - <0>, - <0>, - <0>; + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>; clock-names = "xo", "xo_a", "dsi0pll", @@ -808,6 +842,430 @@ reg = <0x01937000 0x30000>; }; + mdss: display-subsystem@1a00000 { + compatible = "qcom,mdss"; + + reg = <0x01a00000 0x1000>, + <0x01ab0000 0x3000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&gcc MDSS_GDSC>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "vsync", + "core"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@1a01000 { + compatible = "qcom,msm8976-mdp5", "qcom,mdp5"; + reg = <0x01a01000 0x89000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDP_TBU_CLK>, + <&gcc GCC_MDP_RT_TBU_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync", + "tbu", + "tbu_rt"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + iommus = <&apps_iommu 22>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_mdp5_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + mdss_mdp5_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-177780000 { + opp-hz = /bits/ 64 <177780000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-360000000 { + opp-hz = /bits/ 64 <360000000>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@1a94000 { + compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x01a94000 0x300>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + assigned-clocks = <&gcc GCC_MDSS_BYTE0_CLK_SRC>, + <&gcc GCC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + phys = <&mdss_dsi0_phy>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp5_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-161250000 { + opp-hz = /bits/ 64 <161250000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi1: dsi@1a96000 { + compatible = "qcom,msm8976-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x01a96000 0x300>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_BYTE1_CLK>, + <&gcc GCC_MDSS_PCLK1_CLK>, + <&gcc GCC_MDSS_ESC1_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core"; + + assigned-clocks = <&gcc GCC_MDSS_BYTE1_CLK_SRC>, + <&gcc GCC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + phys = <&mdss_dsi1_phy>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&gcc MDSS_GDSC>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&mdss_mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@1a94a00 { + compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; + reg = <0x01a94a00 0xd4>, + <0x01a94400 0x280>, + <0x01a94b80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1_phy: phy@1a96a00 { + compatible = "qcom,dsi-phy-28nm-hpm-fam-b"; + reg = <0x01a96a00 0xd4>, + <0x01a96400 0x280>, + <0x01a96b80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + adreno_gpu: gpu@1c00000 { + compatible = "qcom,adreno-510.0", "qcom,adreno"; + + reg = <0x01c00000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "kgsl_3d0_irq"; + + clocks = <&gcc GCC_GFX3D_OXILI_CLK>, + <&gcc GCC_GFX3D_OXILI_AHB_CLK>, + <&gcc GCC_GFX3D_OXILI_GMEM_CLK>, + <&gcc GCC_GFX3D_BIMC_CLK>, + <&gcc GCC_GFX3D_OXILI_TIMER_CLK>, + <&gcc GCC_GFX3D_OXILI_AON_CLK>; + clock-names = "core", + "iface", + "mem", + "mem_iface", + "rbbmtimer", + "alwayson"; + + power-domains = <&gcc OXILI_GX_GDSC>; + + iommus = <&gpu_iommu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-supported-hw = <0xff>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmpd_opp_svs>; + opp-supported-hw = <0xff>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmpd_opp_nom>; + opp-supported-hw = <0xff>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmpd_opp_nom_plus>; + opp-supported-hw = <0xff>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmpd_opp_turbo>; + opp-supported-hw = <0xff>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmpd_opp_turbo>; + opp-supported-hw = <0xff>; + }; + }; + }; + + apps_iommu: iommu@1ee0000 { + compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; + reg = <0x01ee0000 0x3000>; + ranges = <0 0x01e20000 0x20000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + + qcom,iommu-secure-id = <17>; + + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + + /* VFE */ + iommu-ctx@15000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x15000 0x1000>; + qcom,ctx-asid = <20>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* VENUS NS */ + iommu-ctx@16000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x16000 0x1000>; + qcom,ctx-asid = <21>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* MDP0 */ + iommu-ctx@17000 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x17000 0x1000>; + qcom,ctx-asid = <22>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpu_iommu: iommu@1f08000 { + compatible = "qcom,msm8976-iommu", "qcom,msm-iommu-v2"; + ranges = <0 0x01f08000 0x8000>; + + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX3D_TCU_CLK>; + clock-names = "iface", "bus"; + + power-domains = <&gcc OXILI_CX_GDSC>; + + qcom,iommu-secure-id = <18>; + + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + + /* gfx3d user */ + iommu-ctx@0 { + compatible = "qcom,msm-iommu-v2-ns"; + reg = <0x0 0x1000>; + qcom,ctx-asid = <0>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* gfx3d secure */ + iommu-ctx@1000 { + compatible = "qcom,msm-iommu-v2-sec"; + reg = <0x1000 0x1000>; + qcom,ctx-asid = <2>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* gfx3d priv */ + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v2-sec"; + reg = <0x2000 0x1000>; + qcom,ctx-asid = <1>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x1000>, @@ -1034,6 +1492,81 @@ status = "disabled"; }; + wcnss: remoteproc@a204000 { + compatible = "qcom,pronto-v3-pil", "qcom,pronto"; + reg = <0x0a204000 0x2000>, + <0x0a202000 0x1000>, + <0x0a21b000 0x3000>; + reg-names = "ccu", + "dxe", + "pmu"; + + memory-region = <&wcnss_fw_mem>; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + power-domains = <&rpmpd MSM8976_VDDCX>, + <&rpmpd MSM8976_VDDMX>; + power-domain-names = "cx", "mx"; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + pinctrl-0 = <&wcss_wlan_default>; + pinctrl-names = "default"; + + status = "disabled"; + + wcnss_iris: iris { + /* Separate chip, compatible is board-specific */ + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss_ctrl: wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&wcnss>; + + wcnss_bt: bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, + <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; @@ -1124,7 +1657,6 @@ thermal-zones { aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 0>; @@ -1139,7 +1671,6 @@ modem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 1>; trips { @@ -1153,7 +1684,6 @@ qdsp-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 2>; trips { @@ -1167,7 +1697,6 @@ cam-isp-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 3>; trips { @@ -1181,7 +1710,7 @@ cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 4>; trips { @@ -1205,7 +1734,7 @@ cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 5>; trips { @@ -1229,7 +1758,7 @@ cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 6>; trips { @@ -1253,7 +1782,7 @@ cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 7>; trips { @@ -1277,7 +1806,7 @@ big-l2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 8>; trips { @@ -1301,7 +1830,7 @@ cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 9>; trips { @@ -1325,7 +1854,7 @@ gpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; + thermal-sensors = <&tsens 10>; trips { diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 695e541832ad..917fa246857d 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -183,7 +183,7 @@ smd-edge { interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 0>; + mboxes = <&apcs 0>; qcom,smd-edge = <15>; qcom,remote-pid = <6>; @@ -300,7 +300,7 @@ interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 10>; + mboxes = <&apcs 10>; qcom,local-pid = <0>; qcom,remote-pid = <2>; @@ -325,7 +325,7 @@ interrupt-parent = <&intc>; interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 14>; + mboxes = <&apcs 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; @@ -1093,10 +1093,10 @@ timer: timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 2 0xff08>, - <GIC_PPI 3 0xff08>, - <GIC_PPI 4 0xff08>, - <GIC_PPI 1 0xff08>; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; vph_pwr: vph-pwr-regulator { diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 5ab583be9e0a..0386636a29f0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -405,7 +405,6 @@ &hsusb_phy1 { status = "okay"; - extcon = <&typec>; vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 8d2cb6f41095..2b20cedfe26c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -982,6 +982,8 @@ <&mmcc MDSS_MDP_CLK>; clock-names = "iface", "core"; + resets = <&mmcc MDSS_BCR>; + #address-cells = <1>; #size-cells = <1>; ranges; @@ -2077,24 +2079,20 @@ power-domains = <&gcc UFS_GDSC>; clock-names = - "core_clk_src", "core_clk", "bus_clk", "bus_aggr_clk", "iface_clk", - "core_clk_unipro_src", "core_clk_unipro", "core_clk_ice", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk"; clocks = - <&gcc UFS_AXI_CLK_SRC>, <&gcc GCC_UFS_AXI_CLK>, <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, <&gcc GCC_AGGRE2_UFS_AXI_CLK>, <&gcc GCC_UFS_AHB_CLK>, - <&gcc UFS_ICE_CORE_CLK_SRC>, <&gcc GCC_UFS_UNIPRO_CORE_CLK>, <&gcc GCC_UFS_ICE_CORE_CLK>, <&rpmcc RPM_SMD_LN_BB_CLK>, @@ -2105,10 +2103,8 @@ <0 0>, <0 0>, <0 0>, - <0 0>, - <150000000 300000000>, <75000000 150000000>, - <0 0>, + <150000000 300000000>, <0 0>, <0 0>, <0 0>; @@ -2483,6 +2479,13 @@ status = "disabled"; + glink-edge { + interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; + label = "dsps"; + qcom,remote-pid = <3>; + mboxes = <&apcs_glb 27>; + }; + smd-edge { interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; @@ -2552,6 +2555,13 @@ memory-region = <&mdata_mem>; }; + glink-edge { + interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 15>; + }; + smd-edge { interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; @@ -3497,6 +3507,14 @@ status = "disabled"; + glink-edge { + interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 9>; + }; + + smd-edge { interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; @@ -3553,6 +3571,63 @@ }; }; }; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,smd-channels = "fastrpcsmd-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&lpass_q6_smmu 5>; + }; + + cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&lpass_q6_smmu 6>; + }; + + cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&lpass_q6_smmu 7>; + }; + + cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&lpass_q6_smmu 8>; + }; + + cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + iommus = <&lpass_q6_smmu 9>; + }; + + cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + iommus = <&lpass_q6_smmu 10>; + }; + + cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&lpass_q6_smmu 11>; + }; + + cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&lpass_q6_smmu 12>; + }; + }; }; }; @@ -3654,7 +3729,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -3675,7 +3749,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -3696,7 +3769,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -3717,7 +3789,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -3738,7 +3809,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; @@ -3760,7 +3830,6 @@ gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 7>; @@ -3782,7 +3851,6 @@ m4m-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -3797,7 +3865,6 @@ l3-or-venus-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -3812,7 +3879,6 @@ cluster0-l2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -3827,7 +3893,6 @@ cluster1-l2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -3842,7 +3907,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -3857,7 +3921,6 @@ q6-dsp-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -3872,7 +3935,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -3887,7 +3949,6 @@ modemtx-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index d795b2bbe133..99f811a57ac5 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -488,7 +488,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -509,7 +508,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -530,7 +528,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -551,7 +548,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -572,7 +568,6 @@ cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -593,7 +588,6 @@ cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -614,7 +608,6 @@ cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -635,7 +628,6 @@ cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -656,7 +648,6 @@ gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -671,7 +662,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 13>; @@ -686,7 +676,6 @@ clust0-mhm-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -701,7 +690,6 @@ clust1-mhm-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -716,7 +704,6 @@ cluster1-l2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 11>; @@ -731,7 +718,6 @@ modem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -746,7 +732,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -761,7 +746,6 @@ wlan-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -776,7 +760,6 @@ q6-dsp-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; @@ -791,7 +774,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 5>; @@ -806,7 +788,6 @@ multimedia-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; @@ -1590,7 +1571,6 @@ * SoC VDDMX RPM Power Domain in the Adreno driver. */ power-domains = <&gpucc GPU_GX_GDSC>; - status = "disabled"; }; gpucc: clock-controller@5065000 { @@ -3020,6 +3000,54 @@ }; }; + venus: video-codec@cc00000 { + compatible = "qcom,msm8998-venus"; + reg = <0x0cc00000 0xff000>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&mmcc VIDEO_TOP_GDSC>; + clocks = <&mmcc VIDEO_CORE_CLK>, + <&mmcc VIDEO_AHB_CLK>, + <&mmcc VIDEO_AXI_CLK>, + <&mmcc VIDEO_MAXI_CLK>; + clock-names = "core", "iface", "bus", "mbus"; + iommus = <&mmss_smmu 0x400>, + <&mmss_smmu 0x401>, + <&mmss_smmu 0x40a>, + <&mmss_smmu 0x407>, + <&mmss_smmu 0x40e>, + <&mmss_smmu 0x40f>, + <&mmss_smmu 0x408>, + <&mmss_smmu 0x409>, + <&mmss_smmu 0x40b>, + <&mmss_smmu 0x40c>, + <&mmss_smmu 0x40d>, + <&mmss_smmu 0x410>, + <&mmss_smmu 0x421>, + <&mmss_smmu 0x428>, + <&mmss_smmu 0x429>, + <&mmss_smmu 0x42b>, + <&mmss_smmu 0x42c>, + <&mmss_smmu 0x42d>, + <&mmss_smmu 0x411>, + <&mmss_smmu 0x431>; + memory-region = <&venus_mem>; + status = "disabled"; + + video-decoder { + compatible = "venus-decoder"; + clocks = <&mmcc VIDEO_SUBCORE0_CLK>; + clock-names = "core"; + power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>; + }; + + video-encoder { + compatible = "venus-encoder"; + clocks = <&mmcc VIDEO_SUBCORE1_CLK>; + clock-names = "core"; + power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>; + }; + }; + mmss_smmu: iommu@cd00000 { compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; reg = <0x0cd00000 0x40000>; @@ -3195,6 +3223,7 @@ iommus = <&anoc2_smmu 0x1900>, <&anoc2_smmu 0x1901>; qcom,snoc-host-cap-8bit-quirk; + qcom,no-msa-ready-indicator; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi index 99369a0cdb61..d0db28336fa9 100644 --- a/arch/arm64/boot/dts/qcom/pm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm6125-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm6125_temp>; diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 6de6ed562d97..b4f4d700800d 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -13,7 +13,7 @@ thermal-zones { pm6150_thermal: pm6150-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm6150_temp>; trips { diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 0fce45276e5c..334f976f1154 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -10,9 +10,6 @@ / { thermal-zones { pm6150l-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm6150l_temp>; trips { diff --git a/arch/arm64/boot/dts/qcom/pm6350.dtsi b/arch/arm64/boot/dts/qcom/pm6350.dtsi index 3a2a841e83f1..a20ee2457101 100644 --- a/arch/arm64/boot/dts/qcom/pm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6350.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm6350-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm6350_temp>; diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index 98dc04962fe3..156b2ddff0dc 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -13,7 +13,6 @@ thermal-zones { pm660-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&pm660_temp>; @@ -74,6 +73,23 @@ }; }; + pm660_charger: charger@1000 { + compatible = "qcom,pm660-charger"; + reg = <0x1000>; + + interrupts = <0x0 0x13 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "usb-plugin", "bat-ov", "wdog-bark", "usbin-icl-change"; + + io-channels = <&pm660_rradc 3>, + <&pm660_rradc 4>; + io-channel-names = "usbin_i", "usbin_v"; + + status = "disabled"; + }; + pm660_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; @@ -181,6 +197,14 @@ }; }; + pm660_rradc: adc@4500 { + compatible = "qcom,pm660-rradc"; + reg = <0x4500>; + #io-channel-cells = <1>; + + status = "disabled"; + }; + pm660_gpios: gpio@c000 { compatible = "qcom,pm660-gpio", "qcom,spmi-gpio"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index 6fdbf507c262..0094e0ef058b 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -13,7 +13,6 @@ thermal-zones { pm660l-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&pm660l_temp>; diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index 3bf7cf5d1700..0761e6b5fd8d 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -11,7 +11,6 @@ thermal-zones { pm7250b-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm7250b_temp>; @@ -45,6 +44,52 @@ #address-cells = <1>; #size-cells = <0>; + pm7250b_vbus: usb-vbus-regulator@1100 { + compatible = "qcom,pm7250b-vbus-reg", "qcom,pm8150b-vbus-reg"; + reg = <0x1100>; + status = "disabled"; + }; + + pm7250b_typec: typec@1500 { + compatible = "qcom,pm7250b-typec", "qcom,pm8150b-typec"; + reg = <0x1500>, + <0x1700>; + interrupts = <PM7250B_SID 0x15 0x00 IRQ_TYPE_EDGE_RISING>, + <PM7250B_SID 0x15 0x01 IRQ_TYPE_EDGE_BOTH>, + <PM7250B_SID 0x15 0x02 IRQ_TYPE_EDGE_RISING>, + <PM7250B_SID 0x15 0x03 IRQ_TYPE_EDGE_BOTH>, + <PM7250B_SID 0x15 0x04 IRQ_TYPE_EDGE_RISING>, + <PM7250B_SID 0x15 0x05 IRQ_TYPE_EDGE_RISING>, + <PM7250B_SID 0x15 0x06 IRQ_TYPE_EDGE_BOTH>, + <PM7250B_SID 0x15 0x07 IRQ_TYPE_EDGE_RISING>, + <PM7250B_SID 0x17 0x00 IRQ_TYPE_EDGE_RISING>, + <PM7250B_SID 0x17 0x01 IRQ_TYPE_EDGE_RISING>, + <PM7250B_SID 0x17 0x02 IRQ_TYPE_EDGE_RISING>, + <PM7250B_SID 0x17 0x03 IRQ_TYPE_EDGE_RISING>, + <PM7250B_SID 0x17 0x04 IRQ_TYPE_EDGE_RISING>, + <PM7250B_SID 0x17 0x05 IRQ_TYPE_EDGE_RISING>, + <PM7250B_SID 0x17 0x06 IRQ_TYPE_EDGE_RISING>, + <PM7250B_SID 0x17 0x07 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "or-rid-detect-change", + "vpd-detect", + "cc-state-change", + "vconn-oc", + "vbus-change", + "attach-detach", + "legacy-cable-detect", + "try-snk-src-detect", + "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded", + "fr-swap"; + vdd-vbus-supply = <&pm7250b_vbus>; + status = "disabled"; + }; + pm7250b_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; diff --git a/arch/arm64/boot/dts/qcom/pm7325.dtsi b/arch/arm64/boot/dts/qcom/pm7325.dtsi index d1c5476af5ee..6e29468505b2 100644 --- a/arch/arm64/boot/dts/qcom/pm7325.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7325.dtsi @@ -35,7 +35,7 @@ &thermal_zones { pm7325_thermal: pm7325-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm7325_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/pm7550ba.dtsi b/arch/arm64/boot/dts/qcom/pm7550ba.dtsi index 8b00ece987d1..853a1d83a7f0 100644 --- a/arch/arm64/boot/dts/qcom/pm7550ba.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7550ba.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm7550ba-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm7550ba_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pm8010.dtsi b/arch/arm64/boot/dts/qcom/pm8010.dtsi index 0ea641e12209..ef330194946b 100644 --- a/arch/arm64/boot/dts/qcom/pm8010.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8010.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm8010-m-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8010_m_temp_alarm>; @@ -31,7 +30,6 @@ pm8010-n-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8010_n_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 3ba3ba5d8fce..a74a7ff660d2 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -13,7 +13,6 @@ thermal-zones { pm8150-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8150_temp>; diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index 1aee3270ce7b..3f7b0b6a1d10 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -12,7 +12,6 @@ thermal-zones { pm8150b-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8150b_temp>; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index ac08a09c64c2..3911d6d0d2e2 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -12,7 +12,6 @@ thermal-zones { pm8150l-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8150l_temp>; diff --git a/arch/arm64/boot/dts/qcom/pm8350.dtsi b/arch/arm64/boot/dts/qcom/pm8350.dtsi index 9ed9ba23e81e..cb55b23688d6 100644 --- a/arch/arm64/boot/dts/qcom/pm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350.dtsi @@ -10,7 +10,7 @@ thermal-zones { pm8350_thermal: pm8350-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm8350_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/pm8350b.dtsi b/arch/arm64/boot/dts/qcom/pm8350b.dtsi index 05c105898892..cf82f8a64a9b 100644 --- a/arch/arm64/boot/dts/qcom/pm8350b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350b.dtsi @@ -10,7 +10,7 @@ thermal-zones { pm8350b_thermal: pm8350b-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm8350b_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/pm8350c.dtsi b/arch/arm64/boot/dts/qcom/pm8350c.dtsi index aa74e21fe0dc..1a24e6439e36 100644 --- a/arch/arm64/boot/dts/qcom/pm8350c.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350c.dtsi @@ -48,7 +48,7 @@ thermal-zones { pm8350c_thermal: pm8350c-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm8350c_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/pm8450.dtsi b/arch/arm64/boot/dts/qcom/pm8450.dtsi index ae5bce3cf46e..decb8809fd36 100644 --- a/arch/arm64/boot/dts/qcom/pm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8450.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm8450-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8450_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qcom/pm8550.dtsi index 797a18c249a4..896bcacb6490 100644 --- a/arch/arm64/boot/dts/qcom/pm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm8550-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pm8550b.dtsi b/arch/arm64/boot/dts/qcom/pm8550b.dtsi index 72609f31c890..74d23b8970f4 100644 --- a/arch/arm64/boot/dts/qcom/pm8550b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550b.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm8550b-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550b_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi index 4dc1f03ab2c7..9d4734eabf5a 100644 --- a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm8550ve-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550ve_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi index 97b1c18aa7d8..6426b431616b 100644 --- a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi @@ -10,7 +10,6 @@ thermal-zones { pm8550vs-c-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550vs_c_temp_alarm>; @@ -31,7 +30,6 @@ pm8550vs-d-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550vs_d_temp_alarm>; @@ -52,7 +50,6 @@ pm8550vs-e-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550vs_e_temp_alarm>; @@ -73,7 +70,6 @@ pm8550vs-g-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pm8550vs_g_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 4b2e8fb47d2d..f8e4829ff7f7 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -4,8 +4,37 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/spmi/spmi.h> -&spmi_bus { +/ { + thermal-zones { + pm8916-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8916_temp>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; +&spmi_bus { pm8916_0: pmic@0 { compatible = "qcom,pm8916", "qcom,spmi-pmic"; reg = <0x0 SPMI_USID>; diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi index 1067e141be6c..64258505f9ba 100644 --- a/arch/arm64/boot/dts/qcom/pm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi @@ -9,9 +9,6 @@ / { thermal-zones { pm8953-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8953_temp>; trips { diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index d44a95caf04a..353e4a6bd088 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -8,7 +8,6 @@ thermal-zones { pm8994-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&pm8994_temp>; diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 3f82715392c6..3ecb330590e5 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -11,7 +11,6 @@ thermal-zones { pm8998-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&pm8998_temp>; diff --git a/arch/arm64/boot/dts/qcom/pmi632.dtsi b/arch/arm64/boot/dts/qcom/pmi632.dtsi index 94d53b1cf6c8..8c899d148e46 100644 --- a/arch/arm64/boot/dts/qcom/pmi632.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi632.dtsi @@ -11,7 +11,6 @@ thermal-zones { pmi632-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmi632_temp>; @@ -200,5 +199,11 @@ status = "disabled"; }; + + pmi632_vib: vibrator@5700 { + compatible = "qcom,pmi632-vib"; + reg = <0x5700>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi index 1029f3b1bb9a..b4822cb17a37 100644 --- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi @@ -84,6 +84,14 @@ #address-cells = <1>; #size-cells = <0>; + pmi8950_pwm: pwm@b000 { + compatible = "qcom,pmi8950-pwm"; + reg = <0xb000 0x100>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pmi8950_wled: leds@d800 { compatible = "qcom,pmi8950-wled"; reg = <0xd800>, <0xd900>; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi index dbd4b91dfe06..5084de66fc46 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi @@ -12,7 +12,6 @@ thermal-zones { pmm8155au-1-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmm8155au_1_temp>; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi index 1cee20ac2c9c..555e4a456ef1 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi @@ -11,7 +11,6 @@ thermal-zones { pmm8155au-2-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmm8155au_2_temp>; diff --git a/arch/arm64/boot/dts/qcom/pmr735a.dtsi b/arch/arm64/boot/dts/qcom/pmr735a.dtsi index febda50779f9..f8efd8e5e68f 100644 --- a/arch/arm64/boot/dts/qcom/pmr735a.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735a.dtsi @@ -36,7 +36,7 @@ thermal-zones { pmr735a_thermal: pmr735a-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pmr735a_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/pmr735b.dtsi b/arch/arm64/boot/dts/qcom/pmr735b.dtsi index f7473e247322..09affc05b397 100644 --- a/arch/arm64/boot/dts/qcom/pmr735b.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735b.dtsi @@ -10,7 +10,7 @@ thermal-zones { pmr735b_thermal: pmr735b-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pmr735b_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi b/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi index 37daaefe3431..f9f1793d310e 100644 --- a/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735d_a.dtsi @@ -10,7 +10,6 @@ thermal-zones { pmr735d-k-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmr735d_k_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi b/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi index 3b470f6ac46f..d91fbd3bff10 100644 --- a/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735d_b.dtsi @@ -10,7 +10,6 @@ thermal-zones { pmr735d-l-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmr735d_l_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 461ad97032f7..3f9100c7eff4 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -12,7 +12,6 @@ thermal-zones { pms405-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&pms405_temp>; diff --git a/arch/arm64/boot/dts/qcom/pmx75.dtsi b/arch/arm64/boot/dts/qcom/pmx75.dtsi index 373e45f63dff..2e61b7849c92 100644 --- a/arch/arm64/boot/dts/qcom/pmx75.dtsi +++ b/arch/arm64/boot/dts/qcom/pmx75.dtsi @@ -10,7 +10,6 @@ thermal-zones { pmx75-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmx75_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 106110a9f551..8f3be4c75db3 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/clock/qcom,dispcc-qcm2290.h> #include <dt-bindings/clock/qcom,gcc-qcm2290.h> +#include <dt-bindings/clock/qcom,qcm2290-gpucc.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/firmware/qcom,scm.h> @@ -758,6 +759,11 @@ reg = <0x25b 0x1>; bits = <1 4>; }; + + gpu_speed_bin: gpu-speed-bin@2006 { + reg = <0x2006 0x2>; + bits = <5 8>; + }; }; pmu@1b8e300 { @@ -1425,6 +1431,154 @@ }; }; + gpu: gpu@5900000 { + compatible = "qcom,adreno-07000200", "qcom,adreno"; + reg = <0x0 0x05900000 0x0 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_BIMC_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>; + clock-names = "core", + "iface", + "mem_iface", + "alt_mem_iface", + "gmu", + "xo"; + + interconnects = <&bimc MASTER_GFX3D RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; + interconnect-names = "gfx-mem"; + + iommus = <&adreno_smmu 0 1>, + <&adreno_smmu 2 0>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&rpmpd QCM2290_VDDCX>; + qcom,gmu = <&gmu_wrapper>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + #cooling-cells = <2>; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: Scale RPM_SMD_BIMC_GPU_CLK w/ turbo freqs */ + opp-1123200000 { + opp-hz = /bits/ 64 <1123200000>; + required-opps = <&rpmpd_opp_turbo_plus>; + opp-peak-kBps = <6881000>; + opp-supported-hw = <0x3>; + turbo-mode; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + required-opps = <&rpmpd_opp_turbo>; + opp-peak-kBps = <6881000>; + opp-supported-hw = <0x3>; + turbo-mode; + }; + + opp-921600000 { + opp-hz = /bits/ 64 <921600000>; + required-opps = <&rpmpd_opp_nom_plus>; + opp-peak-kBps = <6881000>; + opp-supported-hw = <0x3>; + }; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + required-opps = <&rpmpd_opp_nom>; + opp-peak-kBps = <6881000>; + opp-supported-hw = <0x7>; + }; + + opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + required-opps = <&rpmpd_opp_svs_plus>; + opp-peak-kBps = <3879000>; + opp-supported-hw = <0xf>; + }; + + opp-537600000 { + opp-hz = /bits/ 64 <537600000>; + required-opps = <&rpmpd_opp_svs>; + opp-peak-kBps = <2929000>; + opp-supported-hw = <0xf>; + }; + + opp-355200000 { + opp-hz = /bits/ 64 <355200000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-peak-kBps = <1720000>; + opp-supported-hw = <0xf>; + }; + }; + }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0 0x0596a000 0x0 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + }; + + gpucc: clock-controller@5990000 { + compatible = "qcom,qcm2290-gpucc"; + reg = <0x0 0x05990000 0x0 0x9000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmpd QCM2290_VDDCX>; + required-opps = <&rpmpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@59a0000 { + compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x059a0000 0x0 0x10000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "mem", + "hlos", + "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + + #global-interrupts = <1>; + #iommu-cells = <2>; + }; + mdss: display-subsystem@5e00000 { compatible = "qcom,qcm2290-mdss"; reg = <0x0 0x05e00000 0x0 0x1000>; @@ -1924,9 +2078,6 @@ thermal-zones { mapss-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; trips { @@ -1951,9 +2102,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 1>; trips { @@ -1978,9 +2126,6 @@ }; wlan-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 2>; trips { @@ -2005,9 +2150,6 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 3>; trips { @@ -2032,9 +2174,6 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 4>; trips { @@ -2059,9 +2198,6 @@ }; mdm0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 5>; trips { @@ -2086,9 +2222,6 @@ }; mdm1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 6>; trips { @@ -2113,9 +2246,6 @@ }; gpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 7>; trips { @@ -2140,9 +2270,6 @@ }; hm-center-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; trips { @@ -2167,9 +2294,6 @@ }; camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; trips { diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index f3432701945f..8ab30c01712e 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -167,7 +167,7 @@ thermal-zones { camera-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 2>; trips { @@ -181,7 +181,7 @@ chg-skin-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm 0>; trips { @@ -195,7 +195,7 @@ conn-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm 1>; trips { @@ -207,9 +207,28 @@ }; }; + pm8008-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pm8008>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + quiet-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 1>; trips { @@ -223,7 +242,7 @@ rear-cam-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 4>; trips { @@ -237,7 +256,7 @@ sdm-skin-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 3>; trips { @@ -251,7 +270,7 @@ xo-thermal { polling-delay-passive = <0>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 0>; trips { @@ -271,46 +290,54 @@ qcom,pmic-id = "b"; vreg_s1b: smps1 { + regulator-name = "vreg_s1b"; regulator-min-microvolt = <1840000>; regulator-max-microvolt = <2040000>; }; vreg_s7b: smps7 { + regulator-name = "vreg_s7b"; regulator-min-microvolt = <535000>; regulator-max-microvolt = <1120000>; }; vreg_s8b: smps8 { + regulator-name = "vreg_s8b"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>; }; vreg_l1b: ldo1 { + regulator-name = "vreg_l1b"; regulator-min-microvolt = <825000>; regulator-max-microvolt = <925000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l2b: ldo2 { + regulator-name = "vreg_l2b"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; regulator-min-microvolt = <312000>; regulator-max-microvolt = <910000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l6b: ldo6 { + regulator-name = "vreg_l6b"; regulator-min-microvolt = <1140000>; regulator-max-microvolt = <1260000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l7b: ldo7 { + regulator-name = "vreg_l7b"; /* Constrained for UFS VCC, at least until UFS driver scales voltage */ regulator-min-microvolt = <2952000>; regulator-max-microvolt = <2952000>; @@ -318,66 +345,77 @@ }; vreg_l8b: ldo8 { + regulator-name = "vreg_l8b"; regulator-min-microvolt = <870000>; regulator-max-microvolt = <970000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l9b: ldo9 { + regulator-name = "vreg_l9b"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l11b: ldo11 { + regulator-name = "vreg_l11b"; regulator-min-microvolt = <1504000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l12b: ldo12 { + regulator-name = "vreg_l12b"; regulator-min-microvolt = <751000>; regulator-max-microvolt = <824000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l13b: ldo13 { + regulator-name = "vreg_l13b"; regulator-min-microvolt = <530000>; regulator-max-microvolt = <824000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l14b: ldo14 { + regulator-name = "vreg_l14b"; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l15b: ldo15 { + regulator-name = "vreg_l15b"; regulator-min-microvolt = <765000>; regulator-max-microvolt = <1020000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l16b: ldo16 { + regulator-name = "vreg_l16b"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l17b: ldo17 { + regulator-name = "vreg_l17b"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1900000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l18b: ldo18 { + regulator-name = "vreg_l18b"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l19b: ldo19 { + regulator-name = "vreg_l19b"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; @@ -389,60 +427,70 @@ qcom,pmic-id = "c"; vreg_s1c: smps1 { + regulator-name = "vreg_s1c"; regulator-min-microvolt = <2190000>; regulator-max-microvolt = <2210000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_s9c: smps9 { + regulator-name = "vreg_s9c"; regulator-min-microvolt = <1010000>; regulator-max-microvolt = <1170000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1950000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3400000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l5c: ldo5 { + regulator-name = "vreg_l5c"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; @@ -451,36 +499,42 @@ }; vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l10c: ldo10 { + regulator-name = "vreg_l10c"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1050000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l11c: ldo11 { + regulator-name = "vreg_l11c"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l12c: ldo12 { + regulator-name = "vreg_l12c"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l13c: ldo13 { + regulator-name = "vreg_l13c"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_bob: bob { + regulator-name = "vreg_bob"; regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3960000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; @@ -522,7 +576,76 @@ &i2c1 { status = "okay"; - /* PM8008 PMIC @ 8 and 9 */ + pm8008: pmic@8 { + compatible = "qcom,pm8008"; + reg = <0x8>; + + interrupts-extended = <&tlmm 25 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&pm8350c_gpios 3 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply = <&vreg_s8b>; + vdd-l3-l4-supply = <&vreg_bob>; + vdd-l5-supply = <&vreg_bob>; + vdd-l6-supply = <&vreg_s1b>; + vdd-l7-supply = <&vreg_bob>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_int_default>, <&pm8008_reset_n_default>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells = <2>; + + #thermal-sensor-cells = <0>; + + regulators { + vreg_l1p: ldo1 { + regulator-name = "vreg_l1p"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l2p: ldo2 { + regulator-name = "vreg_l2p"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1152000>; + }; + + vreg_l3p: ldo3 { + regulator-name = "vreg_l3p"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + }; + + vreg_l4p: ldo4 { + regulator-name = "vreg_l4p"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + vreg_l5p: ldo5 { + regulator-name = "vreg_l5p"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2900000>; + }; + + vreg_l6p: ldo6 { + regulator-name = "vreg_l6p"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l7p: ldo7 { + regulator-name = "vreg_l7p"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + /* Pixelworks @ 26 */ /* FSA4480 USB audio switch @ 42 */ /* AW86927FCR haptics @ 5a */ @@ -551,7 +674,7 @@ &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/qcm6490/fairphone5/ipa_fws.mdt"; + firmware-name = "qcom/qcm6490/fairphone5/ipa_fws.mbn"; status = "okay"; }; @@ -653,6 +776,14 @@ }; }; +&pm8350c_gpios { + pm8008_reset_n_default: pm8008-reset-n-default-state { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-down; + }; +}; + &pmk8350_rtc { status = "okay"; }; @@ -810,6 +941,13 @@ bias-pull-up; }; + pm8008_int_default: pm8008-int-default-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { pins = "gpio28"; function = "gpio"; @@ -864,7 +1002,6 @@ }; &uart5 { - compatible = "qcom,geni-debug-uart"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 47ca2d000341..a0668f767e4b 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -658,7 +658,6 @@ }; &uart5 { - compatible = "qcom,geni-debug-uart"; status = "okay"; }; @@ -667,6 +666,7 @@ }; &usb_1_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts new file mode 100644 index 000000000000..4667e47a74bc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -0,0 +1,961 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Luca Weiss <luca.weiss@fairphone.com> + * Copyright (c) 2024, Caleb Connolly <caleb@postmarketos.org> + */ + +/dts-v1/; + +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sc7280.dtsi" +#include "pm7250b.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ + +/delete-node/ &rmtfs_mem; + +/ { + model = "SHIFT SHIFTphone 8"; + compatible = "shift,otter", "qcom,qcm6490"; + chassis-type = "handset"; + + aliases { + serial0 = &uart5; + serial1 = &uart7; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + framebuffer0: framebuffer@a000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0xe1000000 0x0 (2400 * 1080 * 4)>; + width = <1080>; + height = <2400>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_down_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + }; + }; + + pmic-glink { + compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; + }; + + reserved-memory { + cont_splash_mem: cont-splash@e1000000 { + reg = <0x0 0xe1000000 0x0 0x2300000>; + no-map; + }; + + cdsp_mem: cdsp@88f00000 { + reg = <0x0 0x88f00000 0x0 0x1e00000>; + no-map; + }; + + rmtfs_mem: rmtfs@f8500000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xf8500000 0x0 0x600000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>, <QCOM_SCM_VMID_NAV>; + }; + }; + + thermal-zones { + camera-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + chg-skin-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm7250b_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rear-cam-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 4>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-skin-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vreg_s1b: smps1 { + regulator-name = "vreg_s1b"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7b: smps7 { + regulator-name = "vreg_s7b"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b: smps8 { + regulator-name = "vreg_s8b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>; + }; + + vreg_l1b: ldo1 { + regulator-name = "vreg_l1b"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b: ldo2 { + regulator-name = "vreg_l2b"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <910000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b: ldo6 { + regulator-name = "vreg_l6b"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b: ldo7 { + regulator-name = "vreg_l7b"; + /* Constrained for UFS VCC, at least until UFS driver scales voltage */ + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b: ldo8 { + regulator-name = "vreg_l8b"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b: ldo9 { + regulator-name = "vreg_l9b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b: ldo11 { + regulator-name = "vreg_l11b"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b: ldo12 { + regulator-name = "vreg_l12b"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b: ldo13 { + regulator-name = "vreg_l13b"; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b: ldo14 { + regulator-name = "vreg_l14b"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b: ldo15 { + regulator-name = "vreg_l15b"; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16b: ldo16 { + regulator-name = "vreg_l16b"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b: ldo17 { + regulator-name = "vreg_l17b"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18b: ldo18 { + regulator-name = "vreg_l18b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l19b: ldo19 { + regulator-name = "vreg_l19b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s1c: smps1 { + regulator-name = "vreg_s1c"; + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s9c: smps9 { + regulator-name = "vreg_s9c"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5c: ldo5 { + regulator-name = "vreg_l5c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10c: ldo10 { + regulator-name = "vreg_l10c"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11c: ldo11 { + regulator-name = "vreg_l11c"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12c: ldo12 { + regulator-name = "vreg_l12c"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13c: ldo13 { + regulator-name = "vreg_l13c"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + }; + }; +}; + +&gcc { + protected-clocks = <GCC_CFG_NOC_LPASS_CLK>, + <GCC_EDP_CLKREF_EN>, + <GCC_MSS_CFG_AHB_CLK>, + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, + <GCC_MSS_OFFLINE_AXI_CLK>, + <GCC_MSS_Q6SS_BOOT_CLK_SRC>, + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <GCC_MSS_SNOC_AXI_CLK>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>, + <GCC_SEC_CTRL_CLK_SRC>, + <GCC_WPSS_AHB_BDG_MST_CLK>, + <GCC_WPSS_AHB_CLK>, + <GCC_WPSS_RSCP_CLK>; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcm6490/SHIFT/otter/a660_zap.mbn"; +}; + +&i2c1 { + status = "okay"; + + /* PM8008 PMIC @ 8 and 9 */ + /* rtc6226 FM receiver @ 64 */ + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + vcc-supply = <&vreg_bob>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + /* tas2563 audio codec @ 4d */ +}; + +&i2c9 { + status = "okay"; + + /* TMS(?) NFC @ 28 */ + /* Ti drv2624 haptics @ 5a */ +}; + +&i2c13 { + status = "okay"; + + /* focaltech FT3658U @ 38 */ +}; + +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/qcm6490/SHIFT/otter/ipa_fws.mbn"; + status = "okay"; +}; + +&pm7250b_adc { + channel@4d { + reg = <ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "charger_skin_therm"; + }; + + channel@4f { + reg = <ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "conn_therm"; + }; +}; + +&pm7250b_adc_tm { + status = "okay"; + + charger-skin-therm@0 { + reg = <0>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + conn-therm@1 { + reg = <1>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm7325_gpios { + volume_down_default: volume-down-default-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + cam-flash-therm@2 { + reg = <2>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + sdm-skin-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + wide-rfc-therm@4 { + reg = <4>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pmk8350_vadc { + status = "okay"; + + channel@44 { + reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pmk8350_xo_therm"; + }; + + channel@144 { + reg = <PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_quiet_therm"; + }; + + channel@145 { + reg = <PM7325_ADC7_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_cam_flash_therm"; + }; + + channel@146 { + reg = <PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_sdm_skin_therm"; + }; + + channel@147 { + reg = <PM7325_ADC7_AMUX_THM4_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_wide_rfc_therm"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&qup_spi13_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi13_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_uart5_rx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart5_tx { + drive-strength = <2>; + bias-disable; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcm6490/SHIFT/otter/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcm6490/SHIFT/otter/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/qcm6490/SHIFT/otter/modem.mbn"; + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/qcm6490/SHIFT/otter/wpss.mbn"; + status = "okay"; +}; + +&sdc2_clk { + drive-strength = <16>; + bias-disable; +}; + +&sdc2_cmd { + drive-strength = <10>; + bias-pull-up; +}; + +&sdc2_data { + drive-strength = <10>; + bias-pull-up; +}; + +&sdhc_2 { + vmmc-supply = <&vreg_l9c>; + vqmmc-supply = <&vreg_l6c>; + + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; + + status = "okay"; +}; + +&tlmm { + /* + * 48-52: protected by XPU, not sure why. + */ + gpio-reserved-ranges = <48 4>; + + bluetooth_enable_default: bluetooth-enable-default-state { + pins = "gpio85"; + function = "gpio"; + output-low; + bias-disable; + }; + + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio86"; + function = "gpio"; + bias-pull-down; + }; +}; + +&uart5 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&uart7 { + /delete-property/interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>; + pinctrl-names = "default", "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6750-bt"; + + pinctrl-0 = <&bluetooth_enable_default>, <&sw_ctrl_default>; + pinctrl-names = "default"; + + enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&vreg_l19b>; + vddaon-supply = <&vreg_s7b>; + vddbtcxmx-supply = <&vreg_s7b>; + vddrfacmn-supply = <&vreg_s7b>; + vddrfa0p8-supply = <&vreg_s7b>; + vddrfa1p7-supply = <&vreg_s1b>; + vddrfa1p2-supply = <&vreg_s8b>; + vddrfa2p2-supply = <&vreg_s1c>; + vddasd-supply = <&vreg_l11c>; + + max-speed = <3200000>; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b>; + vcc-max-microamp = <800000>; + /* + * Technically l9b enables an eLDO (supplied by s1b) which then powers + * VCCQ2 of the UFS. + */ + vccq-supply = <&vreg_l9b>; + vccq-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c>; + vdda-pll-supply = <&vreg_l6b>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l10c>; + vdda18-supply = <&vreg_l1c>; + vdda33-supply = <&vreg_l2b>; + + qcom,hs-crossover-voltage-microvolt = <28000>; + qcom,hs-output-impedance-micro-ohms = <2600000>; + qcom,hs-rise-fall-time-bp = <5430>; + qcom,hs-disconnect-bp = <1743>; + qcom,hs-amplitude-bp = <2430>; + + qcom,pre-emphasis-amplitude-bp = <20000>; + qcom,pre-emphasis-duration-bp = <20000>; + + qcom,squelch-detector-bp = <(-2090)>; + + orientation-switch; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l6b>; + vdda-pll-supply = <&vreg_l1b>; + + status = "okay"; +}; + +&wifi { + qcom,ath11k-calibration-variant = "SHIFTphone_8"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ac451f378056..c291bbed6073 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1324,7 +1324,7 @@ }; apcs_hfpll: clock-controller@b016000 { - compatible = "qcom,hfpll"; + compatible = "qcom,qcs404-hfpll"; reg = <0x0b016000 0x30>; #clock-cells = <0>; clock-output-names = "apcs_hfpll"; @@ -1531,10 +1531,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 2 0xff08>, - <GIC_PPI 3 0xff08>, - <GIC_PPI 4 0xff08>, - <GIC_PPI 1 0xff08>; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; smp2p-adsp { @@ -1600,7 +1600,6 @@ thermal-zones { aoss-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 0>; @@ -1615,7 +1614,6 @@ q6-hvx-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 1>; @@ -1630,7 +1628,6 @@ lpass-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 2>; @@ -1645,7 +1642,6 @@ wlan-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 3>; @@ -1660,7 +1656,6 @@ cluster-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 4>; @@ -1694,7 +1689,6 @@ cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 5>; @@ -1728,7 +1722,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 6>; @@ -1762,7 +1755,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 7>; @@ -1796,7 +1788,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 8>; @@ -1830,7 +1821,6 @@ gpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 9>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index a085ff5b5fb2..0d45662b8028 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -52,6 +52,25 @@ }; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + lt9611_1v2: lt9611-vdd12-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + reserved-memory { xbl_mem: xbl@80700000 { reg = <0x0 0x80700000 0x0 0x100000>; @@ -530,6 +549,54 @@ <GCC_WPSS_RSCP_CLK>; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 24 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <&vreg_l11c_2p8>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + &i2c1 { status = "okay"; @@ -587,6 +654,21 @@ remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; +&mdss_dsi { + vdda-supply = <&vreg_l6b_1p2>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi_phy { + vdds-supply = <&vreg_l10c_0p88>; + status = "okay"; +}; + &mdss_edp { status = "okay"; }; @@ -602,10 +684,18 @@ status = "okay"; }; +&pmk8350_rtc { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/qcs6490/adsp.mbn"; status = "okay"; @@ -632,7 +722,6 @@ }; &uart5 { - compatible = "qcom,geni-debug-uart"; status = "okay"; }; @@ -711,3 +800,23 @@ function = "gpio"; bias-disable; }; + +&pm7250b_gpios { + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio2"; + function = "normal"; + + output-high; + input-disable; + power-source = <0>; + }; +}; + +&tlmm { + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio24"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts new file mode 100644 index 000000000000..2e2e46f214c7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include "qcs8550-aim300.dtsi" +#include "pm8010.dtsi" +#include "pmr735d_a.dtsi" +#include "pmr735d_b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS8550 AIM300 AIOT"; + compatible = "qcom,qcs8550-aim300-aiot", "qcom,qcs8550-aim300", "qcom,qcs8550", + "qcom,sm8550"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + debounce-interval = <15>; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&redriver_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + }; + + regulators-3 { + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + }; + + regulators-4 { + vdd-s4-supply = <&vph_pwr>; + }; + + regulators-5 { + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + }; +}; + +&i2c_hub_2 { + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + vcc-supply = <&vreg_bob1>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; + + typec-retimer@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l15b_1p8>; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_ss_in: endpoint { + data-lanes = <3 2 1 0>; + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; +}; + +&mdss_dsi0 { + status = "okay"; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + pinctrl-0 = <&dsi_active>, <&te_default>; + pinctrl-1 = <&dsi_suspend>, <&te_default>; + pinctrl-names = "default", "sleep"; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + vddio-supply = <&vreg_l12b_1p8>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs8550/adsp.mbn", + "qcom/qcs8550/adsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs8550/cdsp.mbn", + "qcom/qcs8550/cdsp_dtb.mbn"; + status = "okay"; +}; + +&swr1 { + status = "okay"; +}; + +&swr2 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <32 8>; + + dsi_active: dsi-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + dsi_suspend: dsi-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + te_default: te-default-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&uart7 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + status = "okay"; +}; + +&usb_dp_qmpphy { + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_ss_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi new file mode 100644 index 000000000000..f6960e2d466a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "qcs8550.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s4g_1p25>; + vdd-l12-supply = <&vreg_s6g_1p86>; + vdd-l15-supply = <&vreg_s6g_1p86>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + vreg_l3c_0p9: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4g_1p25>; + + vreg_s4e_0p95: smps4 { + regulator-name = "vreg_s4e_0p95"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5e_1p08: smps5 { + regulator-name = "vreg_s5e_1p08"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name = "vreg_l1e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + vreg_s4f_0p5: smps4 { + regulator-name = "vreg_s4f_0p5"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name = "vreg_l1f_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name = "vreg_l2f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f_0p88: ldo3 { + regulator-name = "vreg_l3f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-supply = <&vreg_s4g_1p25>; + + vreg_s1g_1p25: smps1 { + regulator-name = "vreg_s1g_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2g_0p85: smps2 { + regulator-name = "vreg_s2g_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1036000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s3g_0p8: smps3 { + regulator-name = "vreg_s3g_0p8"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s4g_1p25: smps4 { + regulator-name = "vreg_s4g_1p25"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1408000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5g_0p85: smps5 { + regulator-name = "vreg_s5g_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s6g_1p86: smps6 { + regulator-name = "vreg_s6g_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1272000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2g_1p2: ldo2 { + regulator-name = "vreg_l2g_1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3e_1p2>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1e_0p88>; +}; + +&pcie0 { + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; +}; + +&pcie1 { + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l1e_0p88>; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1g_1p2>; + vccq-max-microamp = <1200000>; + vdd-hba-supply = <&vreg_l3g_1p2>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_hsphy { + phys = <&pm8550b_eusb2_repeater>; + + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3f_0p88>; +}; + +&xo_board { + clock-frequency = <76800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs8550.dtsi b/arch/arm64/boot/dts/qcom/qcs8550.dtsi new file mode 100644 index 000000000000..07b314834d88 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sm8550.dtsi" + +/delete-node/ &reserved_memory; + +/ { + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + + /* These are 3 types of reserved memory regions here: + * 1. Firmware related regions which aren't shared with kernel. + * The device tree source in kernel doesn't need to have node to + * indicate the firmware related reserved information. Bootloader + * conveys the information by updating devicetree at runtime. + * This will be described as: UEFI saves the physical address of + * the UEFI System Table to dts file's chosen node. Kernel read this + * table and add reserved memory regions to efi config table. Current + * reserved memory region may have reserved region which was not yet + * used, release note of the firmware have such kind of information. + * 2. Firmware related memory regions which are shared with Kernel + * The device tree source in the kernel needs to include nodes + * that indicate fimware-related shared information. A label name + * is suggested because this type of shared information needs to + * be referenced by specific drivers for handling purposes. + * Unlike previous platforms, QCS8550 boots using EFI and describes + * most reserved regions in the ESRT memory map. As a result, reserved + * memory regions which aren't relevant to the kernel(like the hypervisor + ( region) don't need to be described in DT. + * 3. Remoteproc regions. + * Remoteproc regions will be reserved and then assigned to + * subsystem firmware later. + * Here is a reserved memory map for this platform: + * 0x80000000 +-------------------+ + * | | + * | Firmware Related | + * | | + * 0x8a800000 +-------------------+ + * | | + * | Remoteproc Region | + * | | + * 0xa7000000 +-------------------+ + * | | + * | Kernel Available | + * | | + * 0xd4d00000 +-------------------+ + * | | + * | Firmware Related | + * | | + * 0x100000000 +-------------------+ + */ + + aop_image_mem: aop-image-region@81c00000 { + reg = <0x0 0x81c00000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-region@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: aop-config-region@81c80000 { + no-map; + reg = <0x0 0x81c80000 0x0 0x20000>; + }; + + smem_mem: smem-region@81d00000 { + compatible = "qcom,smem"; + reg = <0x0 0x81d00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi-region@81f00000 { + reg = <0x0 0x81f00000 0x0 0x20000>; + no-map; + }; + + mpss_mem: mpss-region@8a800000 { + reg = <0x0 0x8a800000 0x0 0x10800000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { + reg = <0x0 0x9b000000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@9b080000 { + reg = <0x0 0x9b080000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@9b090000 { + reg = <0x0 0x9b090000 0x0 0xa000>; + no-map; + }; + + gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { + reg = <0x0 0x9b09a000 0x0 0x2000>; + no-map; + }; + + spss_region_mem: spss-region@9b100000 { + reg = <0x0 0x9b100000 0x0 0x180000>; + no-map; + }; + + spu_secure_shared_memory_mem: spu-secure-shared-memory-region@9b280000 { + reg = <0x0 0x9b280000 0x0 0x80000>; + no-map; + }; + + camera_mem: camera-region@9b300000 { + reg = <0x0 0x9b300000 0x0 0x800000>; + no-map; + }; + + video_mem: video-region@9bb00000 { + reg = <0x0 0x9bb00000 0x0 0x700000>; + no-map; + }; + + cvp_mem: cvp-region@9c200000 { + reg = <0x0 0x9c200000 0x0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp-region@9c900000 { + reg = <0x0 0x9c900000 0x0 0x2000000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { + reg = <0x0 0x9e900000 0x0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { + reg = <0x0 0x9e980000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi-region@9ea00000 { + reg = <0x0 0x9ea00000 0x0 0x4080000>; + no-map; + }; + + mpss_dsm_mem: mpss_dsm_region@d4d00000 { + reg = <0x0 0xd4d00000 0x0 0x3300000>; + no-map; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts index 5a25cdec969e..e65305f8136c 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -500,3 +500,26 @@ &uart7 { status = "okay"; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l8a_0p91>; + vdda18-supply = <&vreg_l14a_1p8>; + vdda33-supply = <&vreg_l2a_2p3>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l8a_0p91>; + vdda-pll-supply = <&vreg_l3a_1p2>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index f2a5e2e40461..31329cbe0976 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -6,6 +6,8 @@ #include <dt-bindings/clock/qcom,qdu1000-gcc.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> @@ -913,6 +915,126 @@ }; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,qdu1000-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0x0 0x088e3000 0x0 0x120>; + #phy-cells = <0>; + + clocks =<&gcc GCC_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_1_qmpphy: phy@88e5000 { + compatible = "qcom,qdu1000-qmp-usb3-uni-phy"; + reg = <0x0 0x088e5000 0x0 0x2000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB2_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + reset-names = "phy", + "phy_phy"; + + #clock-cells = <0>; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,qdu1000-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 8 IRQ_TYPE_EDGE_BOTH>, + <&pdc 9 IRQ_TYPE_EDGE_BOTH>, + <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&system_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; + + interconnect-names = "usb-ddr", + "apps-usb"; + + status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&apps_smmu 0xc0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, + <&usb_1_qmpphy>; + phy-names = "usb2-phy", + "usb3-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,qdu1000-pdc", "qcom,pdc"; reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; @@ -1464,6 +1586,21 @@ reg-names = "llcc0_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + + nvmem-cells = <&multi_chan_ddr>; + nvmem-cell-names = "multi-chan-ddr"; + }; + + sec_qfprom: efuse@221c8000 { + compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom"; + reg = <0 0x221c8000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + multi_chan_ddr: multi-chan-ddr@12b { + reg = <0x12b 0x1>; + bits = <0 2>; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index bb5191422660..e19790464a11 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -59,6 +59,17 @@ }; }; + i2c2_gpio: i2c { + compatible = "i2c-gpio"; + + sda-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + scl-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + leds { compatible = "gpio-leds"; @@ -199,7 +210,15 @@ status = "okay"; }; -&i2c2 { +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/qcm2290/a702_zap.mbn"; + }; +}; + +&i2c2_gpio { clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 2c39bb1b97db..1888d99d398b 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -60,6 +60,17 @@ }; }; + i2c2_gpio: i2c { + compatible = "i2c-gpio"; + + sda-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + scl-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + leds { compatible = "gpio-leds"; @@ -190,7 +201,7 @@ }; }; -&i2c2 { +&i2c2_gpio { clock-frequency = <400000>; status = "okay"; @@ -294,7 +305,7 @@ &pmi632_vbus { regulator-min-microamp = <500000>; - regulator-max-microamp = <3000000>; + regulator-max-microamp = <1000000>; status = "okay"; }; @@ -403,6 +414,8 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-allow-set-load; + regulator-always-on; + regulator-boot-on; }; vreg_l10a_1p8: l10 { diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index cd0db4f31d4a..ccff6cd73fdf 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -108,10 +108,69 @@ regulator-always-on; }; + qca6390-pmu { + compatible = "qcom,qca6390-pmu"; + + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_state>, <&wlan_en_state>; + + vddaon-supply = <&vreg_s6a_0p95>; + vddpmu-supply = <&vreg_s2f_0p95>; + vddrfa0p95-supply = <&vreg_s2f_0p95>; + vddrfa1p3-supply = <&vreg_s8c_1p3>; + vddrfa1p9-supply = <&vreg_s5a_1p9>; + vddpcie1p3-supply = <&vreg_s8c_1p3>; + vddpcie1p9-supply = <&vreg_s5a_1p9>; + vddio-supply = <&vreg_s4a_1p8>; + + wlan-enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; + thermal-zones { conn-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150b_adc_tm 0>; trips { @@ -124,8 +183,6 @@ }; pm8150l-pcb-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150l_adc_tm 1>; trips { @@ -138,8 +195,6 @@ }; skin-msm-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150l_adc_tm 0>; trips { @@ -152,8 +207,6 @@ }; wifi-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150_adc_tm 1>; trips { @@ -166,8 +219,6 @@ }; xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150_adc_tm 0>; trips { @@ -734,6 +785,23 @@ vdda-pll-supply = <&vreg_l9a_1p2>; }; +&pcieport0 { + wifi@0 { + compatible = "pci17cb,1101"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie1 { status = "okay"; }; @@ -1303,6 +1371,14 @@ function = "gpio"; bias-pull-up; }; + + wlan_en_state: wlan-default-state { + pins = "gpio20"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-pull-up; + }; }; &uart6 { @@ -1311,17 +1387,12 @@ bluetooth { compatible = "qcom,qca6390-bt"; - pinctrl-names = "default"; - pinctrl-0 = <&bt_en_state>; - - enable-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; - - vddio-supply = <&vreg_s4a_1p8>; - vddpmu-supply = <&vreg_s2f_0p95>; - vddaon-supply = <&vreg_s6a_0p95>; - vddrfa0p9-supply = <&vreg_s2f_0p95>; - vddrfa1p3-supply = <&vreg_s8c_1p3>; - vddrfa1p9-supply = <&vreg_s5a_1p9>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; @@ -1356,8 +1427,8 @@ usb-role-switch; }; -&usb_1_role_switch_out { - remote-endpoint = <&pm8150b_role_switch_in>; +&usb_1_dwc3_hs_out { + remote-endpoint = <&pm8150b_hs_in>; }; &usb_1_hsphy { @@ -1373,7 +1444,6 @@ vdda-phy-supply = <&vreg_l9a_1p2>; vdda-pll-supply = <&vreg_l18a_0p92>; - orientation-switch; }; &usb_1_qmpphy_out { @@ -1465,8 +1535,8 @@ port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { - remote-endpoint = <&usb_1_role_switch_out>; + pm8150b_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs_out>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts index 2a862c83309e..1c781d9e24cf 100644 --- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -467,3 +467,26 @@ &uart7 { status = "okay"; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l8a_0p91>; + vdda18-supply = <&vreg_l14a_1p8>; + vdda33-supply = <&vreg_l2a_2p3>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l8a_0p91>; + vdda-pll-supply = <&vreg_l3a_1p2>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index eaa43f022a65..1369c3d43f86 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -10,7 +10,7 @@ thermal-zones { pmm8654au_0_thermal: pm8775-0-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pmm8654au_0_temp_alarm>; trips { @@ -30,7 +30,7 @@ pmm8654au_1_thermal: pm8775-1-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pmm8654au_1_temp_alarm>; trips { @@ -50,7 +50,7 @@ pmm8654au_2_thermal: pm8775-2-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pmm8654au_2_temp_alarm>; trips { @@ -70,7 +70,7 @@ pmm8654au_3_thermal: pm8775-3-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pmm8654au_3_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts new file mode 100644 index 000000000000..ae065ae92478 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include "sa8775p-ride.dtsi" + +/ { + model = "Qualcomm SA8775P Ride Rev3"; + compatible = "qcom,sa8775p-ride-r3", "qcom,sa8775p"; +}; + +ðernet0 { + phy-mode = "2500base-x"; +}; + +ðernet1 { + phy-mode = "2500base-x"; +}; + +&mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy0: phy@8 { + compatible = "ethernet-phy-id31c3.1c33"; + reg = <0x8>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + + sgmii_phy1: phy@0 { + compatible = "ethernet-phy-id31c3.1c33"; + reg = <0x0>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 26ad05bd3b3f..2e87fd760dbd 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -5,835 +5,43 @@ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/regulator/qcom,rpmh-regulator.h> - -#include "sa8775p.dtsi" -#include "sa8775p-pmics.dtsi" +#include "sa8775p-ride.dtsi" / { model = "Qualcomm SA8775P Ride"; compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; - - aliases { - ethernet0 = ðernet0; - ethernet1 = ðernet1; - i2c11 = &i2c11; - i2c18 = &i2c18; - serial0 = &uart10; - serial1 = &uart12; - serial2 = &uart17; - spi16 = &spi16; - ufshc1 = &ufs_mem_hc; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&apps_rsc { - regulators-0 { - compatible = "qcom,pmm8654au-rpmh-regulators"; - qcom,pmic-id = "a"; - - vreg_s4a: smps4 { - regulator-name = "vreg_s4a"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1816000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_s5a: smps5 { - regulator-name = "vreg_s5a"; - regulator-min-microvolt = <1850000>; - regulator-max-microvolt = <1996000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_s9a: smps9 { - regulator-name = "vreg_s9a"; - regulator-min-microvolt = <535000>; - regulator-max-microvolt = <1120000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l4a: ldo4 { - regulator-name = "vreg_l4a"; - regulator-min-microvolt = <788000>; - regulator-max-microvolt = <1050000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l5a: ldo5 { - regulator-name = "vreg_l5a"; - regulator-min-microvolt = <870000>; - regulator-max-microvolt = <950000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l6a: ldo6 { - regulator-name = "vreg_l6a"; - regulator-min-microvolt = <870000>; - regulator-max-microvolt = <970000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l7a: ldo7 { - regulator-name = "vreg_l7a"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <950000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l8a: ldo8 { - regulator-name = "vreg_l8a"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l9a: ldo9 { - regulator-name = "vreg_l9a"; - regulator-min-microvolt = <2970000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - }; - - regulators-1 { - compatible = "qcom,pmm8654au-rpmh-regulators"; - qcom,pmic-id = "c"; - - vreg_l1c: ldo1 { - regulator-name = "vreg_l1c"; - regulator-min-microvolt = <1140000>; - regulator-max-microvolt = <1260000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l2c: ldo2 { - regulator-name = "vreg_l2c"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l3c: ldo3 { - regulator-name = "vreg_l3c"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l4c: ldo4 { - regulator-name = "vreg_l4c"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - /* - * FIXME: This should have regulator-allow-set-load but - * we're getting an over-current fault from the PMIC - * when switching to LPM. - */ - }; - - vreg_l5c: ldo5 { - regulator-name = "vreg_l5c"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l6c: ldo6 { - regulator-name = "vreg_l6c"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l7c: ldo7 { - regulator-name = "vreg_l7c"; - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l8c: ldo8 { - regulator-name = "vreg_l8c"; - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l9c: ldo9 { - regulator-name = "vreg_l9c"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2700000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - }; - - regulators-2 { - compatible = "qcom,pmm8654au-rpmh-regulators"; - qcom,pmic-id = "e"; - - vreg_s4e: smps4 { - regulator-name = "vreg_s4e"; - regulator-min-microvolt = <970000>; - regulator-max-microvolt = <1520000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_s7e: smps7 { - regulator-name = "vreg_s7e"; - regulator-min-microvolt = <1010000>; - regulator-max-microvolt = <1170000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_s9e: smps9 { - regulator-name = "vreg_s9e"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <570000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l6e: ldo6 { - regulator-name = "vreg_l6e"; - regulator-min-microvolt = <1280000>; - regulator-max-microvolt = <1450000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - - vreg_l8e: ldo8 { - regulator-name = "vreg_l8e"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1950000>; - regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; - regulator-allow-set-load; - regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM - RPMH_REGULATOR_MODE_HPM>; - }; - }; }; ðernet0 { phy-mode = "sgmii"; - phy-handle = <&sgmii_phy0>; - - pinctrl-0 = <ðernet0_default>; - pinctrl-names = "default"; - - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - snps,ps-speed = <1000>; - - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - sgmii_phy0: phy@8 { - compatible = "ethernet-phy-id0141.0dd4"; - reg = <0x8>; - device_type = "ethernet-phy"; - interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; - reset-assert-us = <11000>; - reset-deassert-us = <70000>; - }; - - sgmii_phy1: phy@a { - compatible = "ethernet-phy-id0141.0dd4"; - reg = <0xa>; - device_type = "ethernet-phy"; - interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <11000>; - reset-deassert-us = <70000>; - }; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xc>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <4>; - snps,tx-sched-sp; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - }; }; ðernet1 { phy-mode = "sgmii"; - phy-handle = <&sgmii_phy1>; - - snps,mtl-rx-config = <&mtl_rx_setup1>; - snps,mtl-tx-config = <&mtl_tx_setup1>; - snps,ps-speed = <1000>; - - status = "okay"; - - mtl_rx_setup1: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xc>; - }; - }; - - mtl_tx_setup1: tx-queues-config { - snps,tx-queues-to-use = <4>; - snps,tx-sched-sp; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - }; -}; - -&i2c11 { - clock-frequency = <400000>; - pinctrl-0 = <&qup_i2c11_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c18 { - clock-frequency = <400000>; - pinctrl-0 = <&qup_i2c18_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pmm8654au_0_gpios { - gpio-line-names = "DS_EN", - "POFF_COMPLETE", - "UFS0_VER_ID", - "FAST_POFF", - "DBU1_PON_DONE", - "AOSS_SLEEP", - "CAM_DES0_EN", - "CAM_DES1_EN", - "CAM_DES2_EN", - "CAM_DES3_EN", - "UEFI", - "ANALOG_PON_OPT"; -}; - -&pmm8654au_0_pon_resin { - linux,code = <KEY_VOLUMEDOWN>; - status = "okay"; -}; - -&pmm8654au_1_gpios { - gpio-line-names = "PMIC_C_ID0", - "PMIC_C_ID1", - "UFS1_VER_ID", - "IPA_PWR", - "", - "WLAN_DBU4_EN", - "WLAN_EN", - "BT_EN", - "USB2_PWR_EN", - "USB2_FAULT"; - - usb2_en_state: usb2-en-state { - pins = "gpio9"; - function = "normal"; - output-high; - power-source = <0>; - }; -}; - -&pmm8654au_2_gpios { - gpio-line-names = "PMIC_E_ID0", - "PMIC_E_ID1", - "USB0_PWR_EN", - "USB0_FAULT", - "SENSOR_IRQ_1", - "SENSOR_IRQ_2", - "SENSOR_RST", - "SGMIIO0_RST", - "SGMIIO1_RST", - "USB1_PWR_ENABLE", - "USB1_FAULT", - "VMON_SPX8"; - - usb0_en_state: usb0-en-state { - pins = "gpio3"; - function = "normal"; - output-high; - power-source = <0>; - }; - - usb1_en_state: usb1-en-state { - pins = "gpio10"; - function = "normal"; - output-high; - power-source = <0>; - }; -}; - -&pmm8654au_3_gpios { - gpio-line-names = "PMIC_G_ID0", - "PMIC_G_ID1", - "GNSS_RST", - "GNSS_EN", - "GNSS_BOOT_MODE"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&qupv3_id_2 { - status = "okay"; -}; - -&serdes0 { - phy-supply = <&vreg_l5a>; - status = "okay"; -}; - -&serdes1 { - phy-supply = <&vreg_l5a>; - status = "okay"; -}; - -&sleep_clk { - clock-frequency = <32764>; -}; - -&spi16 { - pinctrl-0 = <&qup_spi16_default>; - pinctrl-names = "default"; - status = "okay"; }; -&tlmm { - ethernet0_default: ethernet0-default-state { - ethernet0_mdc: ethernet0-mdc-pins { - pins = "gpio8"; - function = "emac0_mdc"; - drive-strength = <16>; - bias-pull-up; - }; - - ethernet0_mdio: ethernet0-mdio-pins { - pins = "gpio9"; - function = "emac0_mdio"; - drive-strength = <16>; - bias-pull-up; - }; - }; - - qup_uart10_default: qup-uart10-state { - pins = "gpio46", "gpio47"; - function = "qup1_se3"; - }; - - qup_spi16_default: qup-spi16-state { - pins = "gpio86", "gpio87", "gpio88", "gpio89"; - function = "qup2_se2"; - drive-strength = <6>; - bias-disable; - }; - - qup_i2c11_default: qup-i2c11-state { - pins = "gpio48", "gpio49"; - function = "qup1_se4"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c18_default: qup-i2c18-state { - pins = "gpio95", "gpio96"; - function = "qup2_se4"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_uart12_default: qup-uart12-state { - qup_uart12_cts: qup-uart12-cts-pins { - pins = "gpio52"; - function = "qup1_se5"; - bias-disable; - }; - - qup_uart12_rts: qup-uart12-rts-pins { - pins = "gpio53"; - function = "qup1_se5"; - bias-pull-down; - }; - - qup_uart12_tx: qup-uart12-tx-pins { - pins = "gpio54"; - function = "qup1_se5"; - bias-pull-up; - }; - - qup_uart12_rx: qup-uart12-rx-pins { - pins = "gpio55"; - function = "qup1_se5"; - bias-pull-down; - }; - }; - - qup_uart17_default: qup-uart17-state { - qup_uart17_cts: qup-uart17-cts-pins { - pins = "gpio91"; - function = "qup2_se3"; - bias-disable; - }; - - qup_uart17_rts: qup0-uart17-rts-pins { - pins = "gpio92"; - function = "qup2_se3"; - bias-pull-down; - }; - - qup_uart17_tx: qup0-uart17-tx-pins { - pins = "gpio93"; - function = "qup2_se3"; - bias-pull-up; - }; - - qup_uart17_rx: qup0-uart17-rx-pins { - pins = "gpio94"; - function = "qup2_se3"; - bias-pull-down; - }; - }; +&mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; - pcie0_default_state: pcie0-default-state { - perst-pins { - pins = "gpio2"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq-pins { - pins = "gpio1"; - function = "pcie0_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; - - wake-pins { - pins = "gpio0"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; + sgmii_phy0: phy@8 { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0x8>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; }; - pcie1_default_state: pcie1-default-state { - perst-pins { - pins = "gpio4"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq-pins { - pins = "gpio3"; - function = "pcie1_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; - - wake-pins { - pins = "gpio5"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; + sgmii_phy1: phy@a { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0xa>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; }; }; - -&pcie0 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; - - status = "okay"; -}; - -&pcie1 { - perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; - - status = "okay"; -}; - -&pcie0_phy { - vdda-phy-supply = <&vreg_l5a>; - vdda-pll-supply = <&vreg_l1c>; - - status = "okay"; -}; - -&pcie1_phy { - vdda-phy-supply = <&vreg_l5a>; - vdda-pll-supply = <&vreg_l1c>; - - status = "okay"; -}; - -&uart10 { - compatible = "qcom,geni-debug-uart"; - pinctrl-0 = <&qup_uart10_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart12 { - pinctrl-0 = <&qup_uart12_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart17 { - pinctrl-0 = <&qup_uart17_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&ufs_mem_hc { - reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; - vcc-supply = <&vreg_l8a>; - vcc-max-microamp = <1100000>; - vccq-supply = <&vreg_l4c>; - vccq-max-microamp = <1200000>; - - status = "okay"; -}; - -&ufs_mem_phy { - vdda-phy-supply = <&vreg_l4a>; - vdda-pll-supply = <&vreg_l1c>; - - status = "okay"; -}; - -&usb_0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_en_state>; - - status = "okay"; -}; - -&usb_0_dwc3 { - dr_mode = "peripheral"; -}; - -&usb_0_hsphy { - vdda-pll-supply = <&vreg_l7a>; - vdda18-supply = <&vreg_l6c>; - vdda33-supply = <&vreg_l9a>; - - status = "okay"; -}; - -&usb_0_qmpphy { - vdda-phy-supply = <&vreg_l1c>; - vdda-pll-supply = <&vreg_l7a>; - - status = "okay"; -}; - -&usb_1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_en_state>; - - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_hsphy { - vdda-pll-supply = <&vreg_l7a>; - vdda18-supply = <&vreg_l6c>; - vdda33-supply = <&vreg_l9a>; - - status = "okay"; -}; - -&usb_1_qmpphy { - vdda-phy-supply = <&vreg_l1c>; - vdda-pll-supply = <&vreg_l7a>; - - status = "okay"; -}; - -&usb_2 { - pinctrl-names = "default"; - pinctrl-0 = <&usb2_en_state>; - - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - vdda-pll-supply = <&vreg_l7a>; - vdda18-supply = <&vreg_l6c>; - vdda33-supply = <&vreg_l9a>; - - status = "okay"; -}; - -&xo_board_clk { - clock-frequency = <38400000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi new file mode 100644 index 000000000000..2a6170623ea9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -0,0 +1,814 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "sa8775p.dtsi" +#include "sa8775p-pmics.dtsi" + +/ { + aliases { + ethernet0 = ðernet0; + ethernet1 = ðernet1; + i2c11 = &i2c11; + i2c18 = &i2c18; + serial0 = &uart10; + serial1 = &uart12; + serial2 = &uart17; + spi16 = &spi16; + ufshc1 = &ufs_mem_hc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1816000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5a: smps5 { + regulator-name = "vreg_s5a"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1996000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s9a: smps9 { + regulator-name = "vreg_s9a"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + /* + * FIXME: This should have regulator-allow-set-load but + * we're getting an over-current fault from the PMIC + * when switching to LPM. + */ + }; + + vreg_l5c: ldo5 { + regulator-name = "vreg_l5c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "e"; + + vreg_s4e: smps4 { + regulator-name = "vreg_s4e"; + regulator-min-microvolt = <970000>; + regulator-max-microvolt = <1520000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s7e: smps7 { + regulator-name = "vreg_s7e"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s9e: smps9 { + regulator-name = "vreg_s9e"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6e: ldo6 { + regulator-name = "vreg_l6e"; + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8e: ldo8 { + regulator-name = "vreg_l8e"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +ðernet0 { + phy-handle = <&sgmii_phy0>; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,ps-speed = <1000>; + + status = "okay"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +ðernet1 { + phy-handle = <&sgmii_phy1>; + + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,ps-speed = <1000>; + + status = "okay"; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +&i2c11 { + clock-frequency = <400000>; + pinctrl-0 = <&qup_i2c11_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c18 { + clock-frequency = <400000>; + pinctrl-0 = <&qup_i2c18_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pmm8654au_0_gpios { + gpio-line-names = "DS_EN", + "POFF_COMPLETE", + "UFS0_VER_ID", + "FAST_POFF", + "DBU1_PON_DONE", + "AOSS_SLEEP", + "CAM_DES0_EN", + "CAM_DES1_EN", + "CAM_DES2_EN", + "CAM_DES3_EN", + "UEFI", + "ANALOG_PON_OPT"; +}; + +&pmm8654au_0_pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pmm8654au_1_gpios { + gpio-line-names = "PMIC_C_ID0", + "PMIC_C_ID1", + "UFS1_VER_ID", + "IPA_PWR", + "", + "WLAN_DBU4_EN", + "WLAN_EN", + "BT_EN", + "USB2_PWR_EN", + "USB2_FAULT"; + + usb2_en_state: usb2-en-state { + pins = "gpio9"; + function = "normal"; + output-high; + power-source = <0>; + }; +}; + +&pmm8654au_2_gpios { + gpio-line-names = "PMIC_E_ID0", + "PMIC_E_ID1", + "USB0_PWR_EN", + "USB0_FAULT", + "SENSOR_IRQ_1", + "SENSOR_IRQ_2", + "SENSOR_RST", + "SGMIIO0_RST", + "SGMIIO1_RST", + "USB1_PWR_ENABLE", + "USB1_FAULT", + "VMON_SPX8"; + + usb0_en_state: usb0-en-state { + pins = "gpio3"; + function = "normal"; + output-high; + power-source = <0>; + }; + + usb1_en_state: usb1-en-state { + pins = "gpio10"; + function = "normal"; + output-high; + power-source = <0>; + }; +}; + +&pmm8654au_3_gpios { + gpio-line-names = "PMIC_G_ID0", + "PMIC_G_ID1", + "GNSS_RST", + "GNSS_EN", + "GNSS_BOOT_MODE"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&serdes0 { + phy-supply = <&vreg_l5a>; + status = "okay"; +}; + +&serdes1 { + phy-supply = <&vreg_l5a>; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&spi16 { + pinctrl-0 = <&qup_spi16_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio8"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio9"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qup_uart10_default: qup-uart10-state { + pins = "gpio46", "gpio47"; + function = "qup1_se3"; + }; + + qup_spi16_default: qup-spi16-state { + pins = "gpio86", "gpio87", "gpio88", "gpio89"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_i2c11_default: qup-i2c11-state { + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c18_default: qup-i2c18-state { + pins = "gpio95", "gpio96"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart12_default: qup-uart12-state { + qup_uart12_cts: qup-uart12-cts-pins { + pins = "gpio52"; + function = "qup1_se5"; + bias-disable; + }; + + qup_uart12_rts: qup-uart12-rts-pins { + pins = "gpio53"; + function = "qup1_se5"; + bias-pull-down; + }; + + qup_uart12_tx: qup-uart12-tx-pins { + pins = "gpio54"; + function = "qup1_se5"; + bias-pull-up; + }; + + qup_uart12_rx: qup-uart12-rx-pins { + pins = "gpio55"; + function = "qup1_se5"; + bias-pull-down; + }; + }; + + qup_uart17_default: qup-uart17-state { + qup_uart17_cts: qup-uart17-cts-pins { + pins = "gpio91"; + function = "qup2_se3"; + bias-disable; + }; + + qup_uart17_rts: qup0-uart17-rts-pins { + pins = "gpio92"; + function = "qup2_se3"; + bias-pull-down; + }; + + qup_uart17_tx: qup0-uart17-tx-pins { + pins = "gpio93"; + function = "qup2_se3"; + bias-pull-up; + }; + + qup_uart17_rx: qup0-uart17-rx-pins { + pins = "gpio94"; + function = "qup2_se3"; + bias-pull-down; + }; + }; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins = "gpio4"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio3"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&pcie0 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&uart10 { + compatible = "qcom,geni-debug-uart"; + pinctrl-0 = <&qup_uart10_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart12 { + pinctrl-0 = <&qup_uart12_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart17 { + pinctrl-0 = <&qup_uart17_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l8a>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l4c>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&usb_0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_en_state>; + + status = "okay"; +}; + +&usb_0_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_0_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l7a>; + + status = "okay"; +}; + +&usb_1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_en_state>; + + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l7a>; + + status = "okay"; +}; + +&usb_2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_en_state>; + + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 31de73594839..23f1b2e5e624 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -205,9 +205,23 @@ }; }; + dummy-sink { + compatible = "arm,coresight-dummy-sink"; + + in-ports { + port { + eud_in: endpoint { + remote-endpoint = + <&swao_rep_out1>; + }; + }; + }; + }; + firmware { scm { compatible = "qcom,scm-sa8775p", "qcom,scm"; + memory-region = <&tz_ffi_mem>; }; }; @@ -418,6 +432,12 @@ no-map; }; + tz_ffi_mem: tz-ffi@91c00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x91c00000 0x0 0x1400000>; + no-map; + }; + lpass_machine_learning_mem: lpass-machine-learning@93b00000 { reg = <0x0 0x93b00000 0x0 0xf00000>; no-map; @@ -1644,6 +1664,919 @@ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + stm: stm@4002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x4002000 0x0 0x1000>, + <0x0 0x16280000 0x0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = + <&funnel0_in7>; + }; + }; + }; + }; + + tpdm@4003000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4003000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + qdss_tpdm0_out: endpoint { + remote-endpoint = + <&qdss_tpda_in0>; + }; + }; + }; + }; + + tpda@4004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x4004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + qdss_tpda_out: endpoint { + remote-endpoint = + <&funnel0_in6>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + qdss_tpda_in0: endpoint { + remote-endpoint = + <&qdss_tpdm0_out>; + }; + }; + + port@1 { + reg = <1>; + qdss_tpda_in1: endpoint { + remote-endpoint = + <&qdss_tpdm1_out>; + }; + }; + }; + }; + + tpdm@400f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x400f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + qdss_tpdm1_out: endpoint { + remote-endpoint = + <&qdss_tpda_in1>; + }; + }; + }; + }; + + funnel@4041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4041000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&qdss_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + funnel0_in6: endpoint { + remote-endpoint = + <&qdss_tpda_out>; + }; + }; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = + <&stm_out>; + }; + }; + }; + }; + + funnel@4042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4042000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = + <&qdss_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + funnel1_in4: endpoint { + remote-endpoint = + <&apss_funnel1_out>; + }; + }; + }; + }; + + funnel@4045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4045000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + qdss_funnel_out: endpoint { + remote-endpoint = + <&aoss_funnel_in7>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + qdss_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + qdss_funnel_in1: endpoint { + remote-endpoint = + <&funnel1_out>; + }; + }; + }; + }; + + funnel@4b04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4b04000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + aoss_funnel_out: endpoint { + remote-endpoint = + <&etf0_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + aoss_funnel_in6: endpoint { + remote-endpoint = + <&aoss_tpda_out>; + }; + }; + + port@7 { + reg = <7>; + aoss_funnel_in7: endpoint { + remote-endpoint = + <&qdss_funnel_out>; + }; + }; + }; + }; + + tmc_etf: tmc@4b05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x4b05000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf0_out: endpoint { + remote-endpoint = + <&swao_rep_in>; + }; + }; + }; + + in-ports { + port { + etf0_in: endpoint { + remote-endpoint = + <&aoss_funnel_out>; + }; + }; + }; + }; + + replicator@4b06000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x4b06000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + swao_rep_out1: endpoint { + remote-endpoint = + <&eud_in>; + }; + }; + }; + + in-ports { + port { + swao_rep_in: endpoint { + remote-endpoint = + <&etf0_out>; + }; + }; + }; + }; + + tpda@4b08000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x4b08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + aoss_tpda_out: endpoint { + remote-endpoint = + <&aoss_funnel_in6>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aoss_tpda_in0: endpoint { + remote-endpoint = + <&aoss_tpdm0_out>; + }; + }; + + port@1 { + reg = <1>; + aoss_tpda_in1: endpoint { + remote-endpoint = + <&aoss_tpdm1_out>; + }; + }; + + port@2 { + reg = <2>; + aoss_tpda_in2: endpoint { + remote-endpoint = + <&aoss_tpdm2_out>; + }; + }; + + port@3 { + reg = <3>; + aoss_tpda_in3: endpoint { + remote-endpoint = + <&aoss_tpdm3_out>; + }; + }; + + port@4 { + reg = <4>; + aoss_tpda_in4: endpoint { + remote-endpoint = + <&aoss_tpdm4_out>; + }; + }; + }; + }; + + tpdm@4b09000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm0_out: endpoint { + remote-endpoint = + <&aoss_tpda_in0>; + }; + }; + }; + }; + + tpdm@4b0a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b0a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm1_out: endpoint { + remote-endpoint = + <&aoss_tpda_in1>; + }; + }; + }; + }; + + tpdm@4b0b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm2_out: endpoint { + remote-endpoint = + <&aoss_tpda_in2>; + }; + }; + }; + }; + + tpdm@4b0c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm3_out: endpoint { + remote-endpoint = + <&aoss_tpda_in3>; + }; + }; + }; + }; + + tpdm@4b0d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x4b0d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + aoss_tpdm4_out: endpoint { + remote-endpoint = + <&aoss_tpda_in4>; + }; + }; + }; + }; + + aoss_cti: cti@4b13000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x4b13000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + etm@6040000 { + compatible = "arm,primecell"; + reg = <0x0 0x6040000 0x0 0x1000>; + cpu = <&CPU0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel0_in0>; + }; + }; + }; + }; + + etm@6140000 { + compatible = "arm,primecell"; + reg = <0x0 0x6140000 0x0 0x1000>; + cpu = <&CPU1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel0_in1>; + }; + }; + }; + }; + + etm@6240000 { + compatible = "arm,primecell"; + reg = <0x0 0x6240000 0x0 0x1000>; + cpu = <&CPU2>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel0_in2>; + }; + }; + }; + }; + + etm@6340000 { + compatible = "arm,primecell"; + reg = <0x0 0x6340000 0x0 0x1000>; + cpu = <&CPU3>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel0_in3>; + }; + }; + }; + }; + + etm@6440000 { + compatible = "arm,primecell"; + reg = <0x0 0x6440000 0x0 0x1000>; + cpu = <&CPU4>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&apss_funnel0_in4>; + }; + }; + }; + }; + + etm@6540000 { + compatible = "arm,primecell"; + reg = <0x0 0x6540000 0x0 0x1000>; + cpu = <&CPU5>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&apss_funnel0_in5>; + }; + }; + }; + }; + + etm@6640000 { + compatible = "arm,primecell"; + reg = <0x0 0x6640000 0x0 0x1000>; + cpu = <&CPU6>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&apss_funnel0_in6>; + }; + }; + }; + }; + + etm@6740000 { + compatible = "arm,primecell"; + reg = <0x0 0x6740000 0x0 0x1000>; + cpu = <&CPU7>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&apss_funnel0_in7>; + }; + }; + }; + }; + + funnel@6800000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x6800000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel0_out: endpoint { + remote-endpoint = + <&apss_funnel1_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel0_in0: endpoint { + remote-endpoint = + <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel0_in1: endpoint { + remote-endpoint = + <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel0_in2: endpoint { + remote-endpoint = + <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel0_in3: endpoint { + remote-endpoint = + <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel0_in4: endpoint { + remote-endpoint = + <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel0_in5: endpoint { + remote-endpoint = + <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel0_in6: endpoint { + remote-endpoint = + <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel0_in7: endpoint { + remote-endpoint = + <&etm7_out>; + }; + }; + }; + }; + + funnel@6810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x6810000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel1_out: endpoint { + remote-endpoint = + <&funnel1_in4>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel1_in0: endpoint { + remote-endpoint = + <&apss_funnel0_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel1_in3: endpoint { + remote-endpoint = + <&apss_tpda_out>; + }; + }; + }; + }; + + tpdm@6860000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x6860000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm3_out: endpoint { + remote-endpoint = + <&apss_tpda_in3>; + }; + }; + }; + }; + + tpdm@6861000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x6861000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm4_out: endpoint { + remote-endpoint = + <&apss_tpda_in4>; + }; + }; + }; + }; + + tpda@6863000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x6863000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_tpda_out: endpoint { + remote-endpoint = + <&apss_funnel1_in3>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_tpda_in0: endpoint { + remote-endpoint = + <&apss_tpdm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_tpda_in1: endpoint { + remote-endpoint = + <&apss_tpdm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_tpda_in2: endpoint { + remote-endpoint = + <&apss_tpdm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_tpda_in3: endpoint { + remote-endpoint = + <&apss_tpdm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_tpda_in4: endpoint { + remote-endpoint = + <&apss_tpdm4_out>; + }; + }; + }; + }; + + tpdm@68a0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x68a0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm0_out: endpoint { + remote-endpoint = + <&apss_tpda_in0>; + }; + }; + }; + }; + + tpdm@68b0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x68b0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm1_out: endpoint { + remote-endpoint = + <&apss_tpda_in1>; + }; + }; + }; + }; + + tpdm@68c0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x68c0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + apss_tpdm2_out: endpoint { + remote-endpoint = + <&apss_tpda_in2>; + }; + }; + }; + }; + usb_0_hsphy: phy@88e4000 { compatible = "qcom,sa8775p-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; @@ -1959,6 +2892,25 @@ status = "disabled"; }; + llcc: system-cache-controller@9200000 { + compatible = "qcom,sa8775p-llcc"; + reg = <0x0 0x09200000 0x0 0x80000>, + <0x0 0x09300000 0x0 0x80000>, + <0x0 0x09400000 0x0 0x80000>, + <0x0 0x09500000 0x0 0x80000>, + <0x0 0x09600000 0x0 0x80000>, + <0x0 0x09700000 0x0 0x80000>, + <0x0 0x09a00000 0x0 0x80000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc4_base", + "llcc5_base", + "llcc_broadcast_base"; + interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, @@ -2099,6 +3051,20 @@ wakeup-parent = <&pdc>; }; + sram: sram@146d8000 { + compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; + reg = <0x0 0x146d8000 0x0 0x1000>; + ranges = <0x0 0x0 0x146d8000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; @@ -2504,6 +3470,7 @@ phy-names = "serdes"; iommus = <&apps_smmu 0x140 0xf>; + dma-coherent; snps,tso; snps,pbl = <32>; @@ -2538,6 +3505,7 @@ phy-names = "serdes"; iommus = <&apps_smmu 0x120 0xf>; + dma-coherent; snps,tso; snps,pbl = <32>; @@ -2550,9 +3518,6 @@ thermal-zones { aoss-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; trips { @@ -2572,7 +3537,6 @@ cpu-0-0-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; @@ -2593,7 +3557,6 @@ cpu-0-1-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; @@ -2614,7 +3577,6 @@ cpu-0-2-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; @@ -2635,7 +3597,6 @@ cpu-0-3-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; @@ -2656,7 +3617,6 @@ gpuss-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; @@ -2677,7 +3637,6 @@ gpuss-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; @@ -2698,7 +3657,6 @@ gpuss-2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; @@ -2718,9 +3676,6 @@ }; audio-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; trips { @@ -2739,9 +3694,6 @@ }; camss-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; trips { @@ -2760,9 +3712,6 @@ }; pcie-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 10>; trips { @@ -2781,9 +3730,6 @@ }; cpuss-0-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 11>; trips { @@ -2802,9 +3748,6 @@ }; aoss-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 0>; trips { @@ -2824,7 +3767,6 @@ cpu-0-0-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; @@ -2845,7 +3787,6 @@ cpu-0-1-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; @@ -2866,7 +3807,6 @@ cpu-0-2-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 3>; @@ -2887,7 +3827,6 @@ cpu-0-3-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 4>; @@ -2908,7 +3847,6 @@ gpuss-3-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 5>; @@ -2929,7 +3867,6 @@ gpuss-4-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 6>; @@ -2950,7 +3887,6 @@ gpuss-5-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens1 7>; @@ -2970,9 +3906,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; trips { @@ -2991,9 +3924,6 @@ }; camss-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; trips { @@ -3012,9 +3942,6 @@ }; pcie-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; trips { @@ -3033,9 +3960,6 @@ }; cpuss-0-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 11>; trips { @@ -3054,9 +3978,6 @@ }; aoss-2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens2 0>; trips { @@ -3076,7 +3997,6 @@ cpu-1-0-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 1>; @@ -3097,7 +4017,6 @@ cpu-1-1-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 2>; @@ -3118,7 +4037,6 @@ cpu-1-2-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 3>; @@ -3139,7 +4057,6 @@ cpu-1-3-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 4>; @@ -3160,7 +4077,6 @@ nsp-0-0-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 5>; @@ -3181,7 +4097,6 @@ nsp-0-1-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 6>; @@ -3202,7 +4117,6 @@ nsp-0-2-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 7>; @@ -3223,7 +4137,6 @@ nsp-1-0-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 8>; @@ -3244,7 +4157,6 @@ nsp-1-1-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 9>; @@ -3265,7 +4177,6 @@ nsp-1-2-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens2 10>; @@ -3285,9 +4196,6 @@ }; ddrss-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens2 11>; trips { @@ -3306,9 +4214,6 @@ }; cpuss-1-0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens2 12>; trips { @@ -3327,9 +4232,6 @@ }; aoss-3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens3 0>; trips { @@ -3349,7 +4251,6 @@ cpu-1-0-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 1>; @@ -3370,7 +4271,6 @@ cpu-1-1-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 2>; @@ -3391,7 +4291,6 @@ cpu-1-2-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 3>; @@ -3412,7 +4311,6 @@ cpu-1-3-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 4>; @@ -3433,7 +4331,6 @@ nsp-0-0-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 5>; @@ -3454,7 +4351,6 @@ nsp-0-1-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 6>; @@ -3475,7 +4371,6 @@ nsp-0-2-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 7>; @@ -3496,7 +4391,6 @@ nsp-1-0-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 8>; @@ -3517,7 +4411,6 @@ nsp-1-1-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 9>; @@ -3538,7 +4431,6 @@ nsp-1-2-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; thermal-sensors = <&tsens3 10>; @@ -3558,9 +4450,6 @@ }; ddrss-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens3 11>; trips { @@ -3579,9 +4468,6 @@ }; cpuss-1-1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens3 12>; trips { @@ -3605,7 +4491,7 @@ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; pcie0: pcie@1c00000 { @@ -3689,6 +4575,53 @@ }; }; + pcie0_ep: pcie-ep@1c00000 { + compatible = "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40200000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>, + <0x0 0x40005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus = <&pcie_smmu 0x0000 0x7f>; + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_0_GDSC>; + phys = <&pcie0_phy>; + phy-names = "pciephy"; + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ + num-lanes = <2>; + + status = "disabled"; + }; + pcie0_phy: phy@1c04000 { compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; reg = <0x0 0x1c04000 0x0 0x2000>; @@ -3799,6 +4732,53 @@ }; }; + pcie1_ep: pcie-ep@1c10000 { + compatible = "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60200000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>, + <0x0 0x60005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus = <&pcie_smmu 0x80 0x7f>; + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_1_GDSC>; + phys = <&pcie1_phy>; + phy-names = "pciephy"; + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ + num-lanes = <4>; + + status = "disabled"; + }; + pcie1_phy: phy@1c14000 { compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; reg = <0x0 0x1c14000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi new file mode 100644 index 000000000000..d91533b80e76 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-clamshell.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Trogdor dts fragment for clamshells + * + * Copyright 2024 Google LLC. + */ + +/* This file must be included after sc7180-trogdor.dtsi to modify cros_ec */ +#include <arm/cros-ec-keyboard.dtsi> diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 7765c8f64905..3c124bbe2f4c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -7,6 +7,7 @@ #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" +#include "sc7180-trogdor-detachable.dtsi" /* Deleted nodes from sc7180-trogdor.dtsi */ @@ -25,7 +26,6 @@ thermal-zones { skin_temp_thermal: skin-temp-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&pm6150_adc_tm 1>; sustainable-power = <965>; @@ -80,10 +80,6 @@ }; &cros_ec { - keyboard-controller { - compatible = "google,cros-ec-keyb-switches"; - }; - cros_ec_proximity: proximity { compatible = "google,cros-ec-mkbp-proximity"; label = "proximity-wifi"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi new file mode 100644 index 000000000000..7c5d8a57ef7f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-detachable.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Trogdor dts fragment for detachables + * + * Copyright 2024 Google LLC. + */ + +/* This file must be included after sc7180-trogdor.dtsi to modify cros_ec */ +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index 2ba3bbf3b9ad..b2df22faafe8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -5,9 +5,8 @@ * Copyright 2021 Google LLC. */ -/* This file must be included after sc7180-trogdor.dtsi */ - #include "sc7180-trogdor-rt5682i-sku.dtsi" +#include "sc7180-trogdor-detachable.dtsi" / { /* BOARD-SPECIFIC TOP LEVEL NODES */ @@ -45,7 +44,6 @@ thermal-zones { skin_temp_thermal: skin-temp-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&pm6150_adc_tm 1>; sustainable-power = <965>; @@ -135,12 +133,6 @@ ap_ts_pen_1v8: &i2c4 { status = "okay"; }; -&cros_ec { - keyboard-controller { - compatible = "google,cros-ec-keyb-switches"; - }; -}; - &panel { compatible = "samsung,atna33xc20"; enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts index d6db7d83adcf..655bea928e52 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts @@ -9,7 +9,7 @@ #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" -#include <arm/cros-ec-keyboard.dtsi> +#include "sc7180-trogdor-clamshell.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" #include "sc7180-trogdor-rt5682s-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts index 919bfaea6189..340cb119d0a0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts @@ -12,6 +12,6 @@ compatible = "google,lazor-rev1-sku2", "google,lazor-rev2-sku2", "qcom,sc7180"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts index eb20157f6af9..d45e60e3eb9e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts @@ -17,6 +17,6 @@ status = "okay"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-kb.dts index 45d34718a1bc..e906ce877b8c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-kb.dts @@ -18,6 +18,6 @@ compatible = "google,lazor-sku2", "qcom,sc7180"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-lte.dts index 79028d0dd1b0..4b9ee15b09f6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r10-lte.dts @@ -22,6 +22,6 @@ status = "okay"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts index 3459b81c5628..a960553f3994 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts @@ -21,6 +21,6 @@ "qcom,sc7180"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts index ff8f47da109d..82bd9ed7e21a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts @@ -25,6 +25,6 @@ status = "okay"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts index faf527972977..6278c1715d3f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts @@ -18,6 +18,6 @@ compatible = "google,lazor-rev9-sku2", "qcom,sc7180"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts index d737fd0637fb..0ec1697ae2c9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts @@ -22,6 +22,6 @@ status = "okay"; }; -&keyboard_backlight { +&pwmleds { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index e9f213d27711..c3fd6760de7a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -5,8 +5,7 @@ * Copyright 2020 Google LLC. */ -/* This file must be included after sc7180-trogdor.dtsi */ -#include <arm/cros-ec-keyboard.dtsi> +#include "sc7180-trogdor-clamshell.dtsi" &ap_sar_sensor { semtech,cs0-ground; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi index 8823edbb4d6e..cc2c5610a279 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi @@ -5,8 +5,7 @@ * Copyright 2021 Google LLC. */ -/* This file must be included after sc7180-trogdor.dtsi */ -#include <arm/cros-ec-keyboard.dtsi> +#include "sc7180-trogdor-clamshell.dtsi" &ap_sar_sensor { compatible = "semtech,sx9324"; @@ -83,6 +82,8 @@ gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; }; +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + &en_pp3300_dx_edp { pins = "gpio67"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 067813f5f437..ac8d4589e3fb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -6,17 +6,13 @@ */ #include "sc7180-trogdor.dtsi" -/* Must come after sc7180-trogdor.dtsi to modify cros_ec */ -#include <arm/cros-ec-keyboard.dtsi> +#include "sc7180-trogdor-clamshell.dtsi" #include "sc7180-trogdor-rt5682i-sku.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" / { thermal-zones { 5v-choke-thermal { - polling-delay-passive = <0>; - polling-delay = <250>; - thermal-sensors = <&pm6150_adc_tm 1>; trips { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi index 5f06842c683b..00229b1515e6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -9,9 +9,7 @@ #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-rt5682i-sku.dtsi" - -/* This board only has 1 USB Type-C port. */ -/delete-node/ &usb_c1; +#include "sc7180-trogdor-detachable.dtsi" / { ppvar_lcd: ppvar-lcd-regulator { @@ -47,12 +45,6 @@ status = "okay"; }; -&cros_ec { - keyboard-controller { - compatible = "google,cros-ec-keyb-switches"; - }; -}; - &gpio_keys { status = "okay"; }; @@ -136,6 +128,11 @@ pp3300_disp_on: &pp3300_dx_edp { gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; }; +/* This board only has 1 USB Type-C port. */ +&usb_c1 { + status = "disabled"; +}; + /* PINCTRL - modifications to sc7180-trogdor.dtsi */ /* diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index c9667751a990..d393a2712ce6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -8,8 +8,7 @@ /dts-v1/; #include "sc7180-trogdor.dtsi" -/* Must come after sc7180-trogdor.dtsi to modify cros_ec */ -#include <arm/cros-ec-keyboard.dtsi> +#include "sc7180-trogdor-clamshell.dtsi" #include "sc7180-trogdor-rt5682i-sku.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 305ad127246e..af89d80426ab 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -8,6 +8,7 @@ /dts-v1/; #include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-detachable.dtsi" / { avdd_lcd: avdd-lcd-regulator { @@ -50,7 +51,6 @@ thermal-zones { skin_temp_thermal: skin-temp-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&pm6150_adc_tm 1>; sustainable-power = <574>; @@ -104,10 +104,6 @@ base_detection: cbas { compatible = "google,cros-cbas"; }; - - keyboard-controller { - compatible = "google,cros-ec-keyb-switches"; - }; }; &i2c4 { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 8513be297120..74ab321d3333 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -21,9 +21,6 @@ / { thermal-zones { charger_thermal: charger-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm6150_adc_tm 0>; trips { @@ -359,10 +356,11 @@ #sound-dai-cells = <0>; }; - pwmleds { + pwmleds: pwmleds { compatible = "pwm-leds"; + status = "disabled"; + keyboard_backlight: led-0 { - status = "disabled"; label = "cros_ec::kbd_backlight"; function = LED_FUNCTION_KBD_BACKLIGHT; pwms = <&cros_ec_pwm 0>; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 4774a859bd7e..b5ebf8980325 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1582,8 +1582,7 @@ }; ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sc7180-qmp-ufs-phy", - "qcom,sm7150-qmp-ufs-phy"; + compatible = "qcom,sc7180-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, @@ -3067,6 +3066,7 @@ iommus = <&apps_smmu 0x540 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,parkmode-disable-ss-quirk; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; @@ -4036,7 +4036,6 @@ thermal-zones { cpu0_thermal: cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; sustainable-power = <1052>; @@ -4085,7 +4084,6 @@ cpu1_thermal: cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; sustainable-power = <1052>; @@ -4134,7 +4132,6 @@ cpu2_thermal: cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; sustainable-power = <1052>; @@ -4183,7 +4180,6 @@ cpu3_thermal: cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; sustainable-power = <1052>; @@ -4232,7 +4228,6 @@ cpu4_thermal: cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; sustainable-power = <1052>; @@ -4281,7 +4276,6 @@ cpu5_thermal: cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; sustainable-power = <1052>; @@ -4330,7 +4324,6 @@ cpu6_thermal: cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 9>; sustainable-power = <1425>; @@ -4371,7 +4364,6 @@ cpu7_thermal: cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 10>; sustainable-power = <1425>; @@ -4412,7 +4404,6 @@ cpu8_thermal: cpu8-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 11>; sustainable-power = <1425>; @@ -4453,7 +4444,6 @@ cpu9_thermal: cpu9-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 12>; sustainable-power = <1425>; @@ -4494,7 +4484,6 @@ aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 0>; @@ -4515,7 +4504,6 @@ cpuss0-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; @@ -4535,7 +4523,6 @@ cpuss1-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 8>; @@ -4555,7 +4542,6 @@ gpuss0-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 13>; @@ -4583,7 +4569,6 @@ gpuss1-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 14>; @@ -4611,7 +4596,6 @@ aoss1-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 0>; @@ -4632,7 +4616,6 @@ cwlan-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; @@ -4653,7 +4636,6 @@ audio-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; @@ -4674,7 +4656,6 @@ ddr-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 3>; @@ -4695,7 +4676,6 @@ q6-hvx-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 4>; @@ -4716,7 +4696,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 5>; @@ -4737,7 +4716,6 @@ mdm-core-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 6>; @@ -4758,7 +4736,6 @@ mdm-dsp-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 7>; @@ -4779,7 +4756,6 @@ npu-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 8>; @@ -4800,7 +4776,6 @@ video-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens1 9>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index a0059527d9e4..7370aa0dbf0e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -495,7 +495,6 @@ }; &uart5 { - compatible = "qcom,geni-debug-uart"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index f9b96bd2477e..7d1d5bbbbbd9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -427,7 +427,6 @@ }; uart_dbg: &uart5 { - compatible = "qcom,geni-debug-uart"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index fc9ec367e3a5..06d0e59e7125 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -24,6 +24,7 @@ #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/reset/qcom,sdm845-aoss.h> #include <dt-bindings/reset/qcom,sdm845-pdc.h> +#include <dt-bindings/soc/qcom,apr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/sound/qcom,lpass.h> #include <dt-bindings/thermal/thermal.h> @@ -1440,12 +1441,12 @@ }; uart5: serial@994000 { - compatible = "qcom,geni-uart"; + compatible = "qcom,geni-debug-uart"; reg = <0 0x00994000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; pinctrl-names = "default"; - pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; + pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; @@ -2129,6 +2130,8 @@ reg = <0 0x016e0000 0 0x1c080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { @@ -2136,6 +2139,7 @@ compatible = "qcom,sc7280-aggre2-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&rpmhcc RPMH_IPA_CLK>; }; mmss_noc: interconnect@1740000 { @@ -2989,6 +2993,18 @@ dma-coherent; }; + gfx_0_tbu: tbu@3dd9000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x3dd9000 0x0 0x1000>; + qcom,stream-id-range = <&adreno_smmu 0x0 0x400>; + }; + + gfx_1_tbu: tbu@3ddd000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x3ddd000 0x0 0x1000>; + qcom,stream-id-range = <&adreno_smmu 0x400 0x400>; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sc7280-mpss-pas"; reg = <0 0x04080000 0 0x10000>; @@ -3762,6 +3778,75 @@ label = "lpass"; qcom,remote-pid = <2>; + apr { + compatible = "qcom,apr-v2"; + qcom,glink-channels = "apr_audio_svc"; + qcom,domain = <APR_DOMAIN_ADSP>; + #address-cells = <1>; + #size-cells = <0>; + + service@3 { + reg = <APR_SVC_ADSP_CORE>; + compatible = "qcom,q6core"; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = <APR_SVC_AFE>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + + q6afecc: clock-controller { + compatible = "qcom,q6afe-clocks"; + #clock-cells = <2>; + }; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = <APR_SVC_ASM>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + iommus = <&apps_smmu 0x1801 0x0>; + + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; + }; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = <APR_SVC_ADM>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6routing: routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; + fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; @@ -4150,6 +4235,7 @@ iommus = <&apps_smmu 0xe0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,parkmode-disable-ss-quirk; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; @@ -5407,16 +5493,6 @@ function = "qup04"; }; - qup_uart5_cts: qup-uart5-cts-state { - pins = "gpio20"; - function = "qup05"; - }; - - qup_uart5_rts: qup-uart5-rts-state { - pins = "gpio21"; - function = "qup05"; - }; - qup_uart5_tx: qup-uart5-tx-state { pins = "gpio22"; function = "qup05"; @@ -5802,6 +5878,83 @@ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; }; + anoc_1_tbu: tbu@151dd000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151dd000 0x0 0x1000>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; + qcom,stream-id-range = <&apps_smmu 0x0 0x400>; + }; + + anoc_2_tbu: tbu@151e1000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151e1000 0x0 0x1000>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; + qcom,stream-id-range = <&apps_smmu 0x400 0x400>; + }; + + mnoc_hf_0_tbu: tbu@151e5000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151e5000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x800 0x400>; + }; + + mnoc_hf_1_tbu: tbu@151e9000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151e9000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; + qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; + }; + + compute_dsp_1_tbu: tbu@151ed000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151ed000 0x0 0x1000>; + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; + }; + + compute_dsp_0_tbu: tbu@151f1000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151f1000 0x0 0x1000>; + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; + }; + + adsp_tbu: tbu@151f5000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151f5000 0x0 0x1000>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; + }; + + anoc_1_pcie_tbu: tbu@151f9000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151f9000 0x0 0x1000>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; + qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; + }; + + mnoc_sf_0_tbu: tbu@151fd000 { + compatible = "qcom,sc7280-tbu"; + reg = <0x0 0x151fd000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x2000 0x400>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0 0x17a00000 0 0x10000>, /* GICD */ @@ -5991,10 +6144,12 @@ }; }; + sound: sound { + }; + thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; @@ -6038,7 +6193,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; @@ -6082,7 +6236,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; @@ -6126,7 +6279,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; @@ -6170,7 +6322,6 @@ cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; @@ -6214,7 +6365,6 @@ cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 8>; @@ -6258,7 +6408,6 @@ cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 9>; @@ -6302,7 +6451,6 @@ cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 10>; @@ -6346,7 +6494,6 @@ cpu8-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 11>; @@ -6390,7 +6537,6 @@ cpu9-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 12>; @@ -6434,7 +6580,6 @@ cpu10-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 13>; @@ -6478,7 +6623,6 @@ cpu11-thermal { polling-delay-passive = <250>; - polling-delay = <0>; thermal-sensors = <&tsens0 14>; @@ -6522,7 +6666,6 @@ aoss0-thermal { polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 0>; @@ -6543,7 +6686,6 @@ aoss1-thermal { polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 0>; @@ -6564,7 +6706,6 @@ cpuss0-thermal { polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; @@ -6584,7 +6725,6 @@ cpuss1-thermal { polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; @@ -6604,7 +6744,6 @@ gpuss0-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; @@ -6632,7 +6771,6 @@ gpuss1-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; @@ -6659,9 +6797,6 @@ }; nspss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 3>; trips { @@ -6680,9 +6815,6 @@ }; nspss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 4>; trips { @@ -6701,9 +6833,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 5>; trips { @@ -6722,9 +6851,6 @@ }; ddr-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 6>; trips { @@ -6743,9 +6869,6 @@ }; mdmss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 7>; trips { @@ -6764,9 +6887,6 @@ }; mdmss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; trips { @@ -6785,9 +6905,6 @@ }; mdmss2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; trips { @@ -6806,9 +6923,6 @@ }; mdmss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; trips { @@ -6827,9 +6941,6 @@ }; camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 11>; trips { diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 6af99116c715..5b226577f9d8 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -68,7 +68,7 @@ reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_prim_role_switch>; + remote-endpoint = <&usb_prim_dwc3_hs>; }; }; @@ -103,7 +103,7 @@ reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_sec_role_switch>; + remote-endpoint = <&usb_sec_dwc3_hs>; }; }; @@ -582,6 +582,10 @@ dr_mode = "host"; }; +&usb_prim_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_prim_qmpphy_dp_in { remote-endpoint = <&mdss_dp0_out>; }; @@ -590,8 +594,8 @@ remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_prim_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; +&usb_sec_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; }; &usb_sec_hsphy { @@ -619,10 +623,6 @@ remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_sec_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &usb_sec { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi index ddc84282f142..1c6f12fafe1d 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi @@ -13,7 +13,6 @@ thermal-zones { pmc8180-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmc8180_temp>; @@ -40,7 +39,6 @@ pmc8180c-thermal { polling-delay-passive = <100>; - polling-delay = <0>; thermal-sensors = <&pmc8180c_temp>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index bfee60c93ccc..65d923497a05 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -71,7 +71,7 @@ reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_prim_role_switch>; + remote-endpoint = <&usb_prim_dwc3_hs>; }; }; @@ -106,7 +106,7 @@ reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_sec_role_switch>; + remote-endpoint = <&usb_sec_dwc3_hs>; }; }; @@ -648,6 +648,10 @@ dr_mode = "host"; }; +&usb_prim_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_prim_qmpphy_dp_in { remote-endpoint = <&mdss_dp0_out>; }; @@ -656,10 +660,6 @@ remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_prim_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; -}; - &usb_sec_hsphy { vdda-pll-supply = <&vreg_l5e_0p88>; vdda18-supply = <&vreg_l12a_1p8>; @@ -685,10 +685,6 @@ remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_sec_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &usb_sec { status = "okay"; }; @@ -697,6 +693,10 @@ dr_mode = "host"; }; +&usb_sec_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &wifi { memory-region = <&wlan_mem>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 067712310560..6e707d993aeb 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sc8180x.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/thermal/thermal.h> @@ -1890,7 +1891,7 @@ power-domains = <&gcc PCIE_3_GDSC>; interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, - <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>; interconnect-names = "pcie-mem", "cpu-pcie"; phys = <&pcie3_phy>; @@ -2012,7 +2013,7 @@ power-domains = <&gcc PCIE_1_GDSC>; interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, - <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; phys = <&pcie1_phy>; @@ -2134,7 +2135,7 @@ power-domains = <&gcc PCIE_2_GDSC>; interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, - <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>; interconnect-names = "pcie-mem", "cpu-pcie"; phys = <&pcie2_phy>; @@ -2245,18 +2246,13 @@ resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; + power-domains = <&gcc UFS_PHY_GDSC>; + #phy-cells = <0>; status = "disabled"; }; - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sc8180x-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -2511,28 +2507,25 @@ status = "disabled"; }; - usb_prim_qmpphy: phy@88e9000 { + usb_prim_qmpphy: phy@88e8000 { compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; - reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x38>, - <0 0x088ea000 0 0x40>; - reg-names = "reg-base", "dp_com"; + reg = <0 0x088e8000 0 0x3000>; + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; clock-names = "aux", - "ref_clk_src", "ref", - "com_aux"; + "com_aux", + "usb3_pipe"; + resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; reset-names = "phy", "common"; #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #phy-cells = <1>; status = "disabled"; @@ -2546,59 +2539,40 @@ usb_prim_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_prim_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_prim_dwc3_ss>; + }; + }; + port@2 { reg = <2>; usb_prim_qmpphy_dp_in: endpoint {}; }; }; - - usb_prim_ssphy: usb3-phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x218>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_prim_phy_pipe_clk_src"; - }; - - usb_prim_dpphy: dp-phy@88ea200 { - reg = <0 0x088ea200 0 0x200>, - <0 0x088ea400 0 0x200>, - <0 0x088eaa00 0 0x200>, - <0 0x088ea600 0 0x200>, - <0 0x088ea800 0 0x200>; - #clock-cells = <1>; - #phy-cells = <0>; - }; }; usb_sec_qmpphy: phy@88ee000 { compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; - reg = <0 0x088ee000 0 0x18c>, - <0 0x088ed000 0 0x10>, - <0 0x088ef000 0 0x40>; - reg-names = "reg-base", "dp_com"; + reg = <0 0x088ed000 0 0x3000>; + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB3_SEC_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "aux", - "ref_clk_src", "ref", - "com_aux"; + "com_aux", + "usb3_pipe"; resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, <&gcc GCC_USB3_PHY_SEC_BCR>; reset-names = "phy", "common"; #clock-cells = <1>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #phy-cells = <1>; status = "disabled"; @@ -2612,46 +2586,32 @@ usb_sec_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_sec_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_sec_dwc3_ss>; + }; + }; + port@2 { reg = <2>; usb_sec_qmpphy_dp_in: endpoint {}; }; }; - - usb_sec_ssphy: usb3-phy@88e9200 { - reg = <0 0x088ee200 0 0x200>, - <0 0x088ee400 0 0x200>, - <0 0x088eec00 0 0x218>, - <0 0x088ee600 0 0x200>, - <0 0x088ee800 0 0x200>, - <0 0x088eea00 0 0x100>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_sec_phy_pipe_clk_src"; - }; - - usb_sec_dpphy: dp-phy@88ef200 { - reg = <0 0x088ef200 0 0x200>, - <0 0x088ef400 0 0x200>, - <0 0x088efa00 0 0x200>, - <0 0x088ef600 0 0x200>, - <0 0x088ef800 0 0x200>; - #clock-cells = <1>; - #phy-cells = <0>; - clock-output-names = "qmp_dptx1_phy_pll_link_clk", - "qmp_dptx1_phy_pll_vco_div_clk"; - }; }; system-cache-controller@9200000 { compatible = "qcom,sc8180x-llcc"; - reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, - <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, - <0 0x09600000 0 0x50000>; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, + <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, + <0 0x09600000 0 0x58000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", - "llcc3_base", "llcc_broadcast_base"; + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; @@ -2711,11 +2671,26 @@ iommus = <&apps_smmu 0x140 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; + phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_prim_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_prim_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_prim_dwc3_ss: endpoint { + remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>; + }; }; }; }; @@ -2768,11 +2743,26 @@ iommus = <&apps_smmu 0x160 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; + phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_sec_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_sec_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_sec_dwc3_ss: endpoint { + remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3086,9 +3076,10 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; - assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; + assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - phys = <&usb_prim_dpphy>; + phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>; phy-names = "dp"; #sound-dai-cells = <0>; @@ -3163,9 +3154,10 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; - assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; + assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; - phys = <&usb_sec_dpphy>; + phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>; phy-names = "dp"; #sound-dai-cells = <0>; @@ -3308,21 +3300,27 @@ compatible = "qcom,sc8180x-dispcc"; reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, - <&sleep_clk>, - <&usb_prim_dpphy 0>, - <&usb_prim_dpphy 1>, - <&usb_sec_dpphy 0>, - <&usb_sec_dpphy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&edp_phy 0>, - <&edp_phy 1>; + <&edp_phy 1>, + <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names = "bi_tcxo", - "sleep_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", "dp_phy_pll_vco_div_clk", - "dptx1_phy_pll_link_clk", - "dptx1_phy_pll_vco_div_clk", "edp_phy_pll_link_clk", - "edp_phy_pll_vco_div_clk"; + "edp_phy_pll_vco_div_clk", + "dptx1_phy_pll_link_clk", + "dptx1_phy_pll_vco_div_clk"; power-domains = <&rpmhpd SC8180X_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; @@ -3368,7 +3366,6 @@ mboxes = <&apss_shared 0>; #clock-cells = <0>; - #power-domain-cells = <1>; }; sram@c3f0000 { @@ -3771,7 +3768,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -3786,7 +3782,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -3801,7 +3796,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -3816,7 +3810,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -3831,7 +3824,6 @@ cpu4-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -3846,7 +3838,6 @@ cpu5-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -3861,7 +3852,6 @@ cpu6-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -3876,7 +3866,6 @@ cpu7-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -3891,7 +3880,6 @@ cpu4-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 11>; @@ -3906,7 +3894,6 @@ cpu5-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -3921,7 +3908,6 @@ cpu6-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 13>; @@ -3936,7 +3922,6 @@ cpu7-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 14>; @@ -3951,7 +3936,6 @@ aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 0>; @@ -3966,7 +3950,6 @@ cluster0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -3981,7 +3964,6 @@ cluster1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -3996,7 +3978,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 15>; @@ -4009,16 +3990,27 @@ trips { gpu_top_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; aoss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 0>; @@ -4033,7 +4025,6 @@ wlan-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -4048,7 +4039,6 @@ video-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -4063,7 +4053,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -4078,7 +4067,6 @@ q6-hvx-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; @@ -4093,7 +4081,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 5>; @@ -4108,7 +4095,6 @@ compute-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; @@ -4123,7 +4109,6 @@ mdm-dsp-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 7>; @@ -4138,7 +4123,6 @@ npu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 8>; @@ -4153,7 +4137,6 @@ gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 11>; @@ -4166,10 +4149,22 @@ trips { gpu_bottom_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 41215567b3ae..a2627ab4db9a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -56,7 +56,7 @@ reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_0_role_switch>; + remote-endpoint = <&usb_0_dwc3_hs>; }; }; @@ -91,7 +91,7 @@ reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_1_role_switch>; + remote-endpoint = <&usb_1_dwc3_hs>; }; }; @@ -675,6 +675,10 @@ dr_mode = "host"; }; +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_0_hsphy { vdda-pll-supply = <&vreg_l9d>; vdda18-supply = <&vreg_l1c>; @@ -700,10 +704,6 @@ remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_0_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; -}; - &usb_1 { status = "okay"; }; @@ -712,6 +712,10 @@ dr_mode = "host"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &usb_1_hsphy { vdda-pll-supply = <&vreg_l4b>; vdda18-supply = <&vreg_l1c>; @@ -737,10 +741,6 @@ remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_1_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &xo_board_clk { clock-frequency = <38400000>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index e937732abede..40da95b202da 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -117,7 +117,7 @@ reg = <0>; pmic_glink_con0_hs: endpoint { - remote-endpoint = <&usb_0_role_switch>; + remote-endpoint = <&usb_0_dwc3_hs>; }; }; @@ -152,7 +152,7 @@ reg = <0>; pmic_glink_con1_hs: endpoint { - remote-endpoint = <&usb_1_role_switch>; + remote-endpoint = <&usb_1_dwc3_hs>; }; }; @@ -297,9 +297,30 @@ }; thermal-zones { + pm8008-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8008>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + skin-temp-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8280_adc_tm 5>; trips { @@ -670,6 +691,85 @@ }; }; +&i2c11 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c11_default>; + + status = "okay"; + + pm8008: pmic@c { + compatible = "qcom,pm8008"; + reg = <0xc>; + + interrupts-extended = <&tlmm 41 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 42 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply = <&vreg_s11b>; + vdd-l3-l4-supply = <&vreg_bob>; + vdd-l5-supply = <&vreg_bob>; + vdd-l6-supply = <&vreg_bob>; + vdd-l7-supply = <&vreg_bob>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_default>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells = <2>; + + #thermal-sensor-cells = <0>; + + regulators { + vreg_l1q: ldo1 { + regulator-name = "vreg_l1q"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l2q: ldo2 { + regulator-name = "vreg_l2q"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l3q: ldo3 { + regulator-name = "vreg_l3q"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vreg_l4q: ldo4 { + regulator-name = "vreg_l4q"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vreg_l5q: ldo5 { + regulator-name = "vreg_l5q"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l6q: ldo6 { + regulator-name = "vreg_l6q"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l7q: ldo7 { + regulator-name = "vreg_l7q"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; + }; +}; + &i2c21 { clock-frequency = <400000>; @@ -1131,6 +1231,10 @@ dr_mode = "host"; }; +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_0_hsphy { vdda-pll-supply = <&vreg_l9d>; vdda18-supply = <&vreg_l1c>; @@ -1156,10 +1260,6 @@ remote-endpoint = <&pmic_glink_con0_ss>; }; -&usb_0_role_switch { - remote-endpoint = <&pmic_glink_con0_hs>; -}; - &usb_1 { status = "okay"; }; @@ -1168,6 +1268,10 @@ dr_mode = "host"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &usb_1_hsphy { vdda-pll-supply = <&vreg_l4b>; vdda18-supply = <&vreg_l1c>; @@ -1193,10 +1297,6 @@ remote-endpoint = <&pmic_glink_con1_ss>; }; -&usb_1_role_switch { - remote-endpoint = <&pmic_glink_con1_hs>; -}; - &usb_2 { status = "okay"; }; @@ -1355,6 +1455,13 @@ bias-disable; }; + i2c11_default: i2c11-default-state { + pins = "gpio18", "gpio19"; + function = "qup11"; + drive-strength = <16>; + bias-disable; + }; + i2c21_default: i2c21-default-state { pins = "gpio81", "gpio82"; function = "qup21"; @@ -1458,6 +1565,22 @@ }; }; + pm8008_default: pm8008-default-state { + int-pins { + pins = "gpio41"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + reset-n-pins { + pins = "gpio42"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + spkr_1_sd_n_default: spkr-1-sd-n-default-state { perst-n-pins { pins = "gpio178"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index 945de77911de..1e3babf2e40d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -14,7 +14,7 @@ thermal-zones { pm8280_1_thermal: pm8280-1-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm8280_1_temp_alarm>; trips { @@ -34,7 +34,7 @@ pm8280_2_thermal: pm8280-2-thermal { polling-delay-passive = <100>; - polling-delay = <0>; + thermal-sensors = <&pm8280_2_temp_alarm>; trips { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0549ba1fbeea..80a57aa22839 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3222,6 +3222,14 @@ usb_0_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_0_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_0_dwc3_ss>; + }; + }; + port@2 { reg = <2>; @@ -3275,6 +3283,14 @@ usb_1_qmpphy_out: endpoint {}; }; + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + port@2 { reg = <2>; @@ -3560,8 +3576,23 @@ phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_0_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_0_dwc3_ss: endpoint { + remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3622,8 +3653,23 @@ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_1_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; }; }; }; @@ -4623,6 +4669,8 @@ restart@c264000 { compatible = "qcom,pshold"; reg = <0 0x0c264000 0 0x4>; + /* TZ seems to block access */ + status = "reserved"; }; tsens1: thermal-sensor@c265000 { @@ -5831,7 +5879,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -5846,7 +5893,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -5861,7 +5907,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -5876,7 +5921,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -5891,7 +5935,6 @@ cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -5906,7 +5949,6 @@ cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -5921,7 +5963,6 @@ cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -5936,7 +5977,6 @@ cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -5951,7 +5991,6 @@ cluster0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -5965,13 +6004,25 @@ }; gpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; + polling-delay-passive = <250>; thermal-sensors = <&tsens2 2>; + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - gpu-crit { + gpu_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5981,7 +6032,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 15>; diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 702ab49bbc59..60412281ab27 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -96,6 +96,18 @@ vin-supply = <&vph_pwr>; }; + + /* + * this is also used for APC1 CPU power, touching it resets the board + */ + vreg_l10a_1p8: vreg-l10a-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_l10a_1p8"; + regulator-min-microvolt = <1804000>; + regulator-max-microvolt = <1896000>; + regulator-always-on; + regulator-boot-on; + }; }; &adsp_pil { @@ -220,6 +232,7 @@ status = "okay"; vdd-supply = <&vreg_l1b_0p925>; + vdda-pll-supply = <&vreg_l10a_1p8>; vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; }; @@ -227,6 +240,7 @@ status = "okay"; vdd-supply = <&vreg_l1b_0p925>; + vdda-pll-supply = <&vreg_l10a_1p8>; vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; }; @@ -464,5 +478,6 @@ &usb3_qmpphy { vdda-phy-supply = <&vreg_l1b_0p925>; + vdda-pll-supply = <&vreg_l10a_1p8>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm450-lenovo-tbx605f.dts b/arch/arm64/boot/dts/qcom/sdm450-lenovo-tbx605f.dts new file mode 100644 index 000000000000..175befc02b22 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm450-lenovo-tbx605f.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Neil Armstrong <neil.armstrong@linaro.org> + */ +/dts-v1/; + +#include "sdm450.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" + +/ { + model = "Lenovo Smart Tab M10"; + compatible = "lenovo,tbx605f", "qcom,sdm450"; + chassis-type = "tablet"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@90001000 { + compatible = "simple-framebuffer"; + reg = <0 0x90001000 0 (1200 * 1920 * 3)>; + + width = <1200>; + height = <1920>; + stride = <(1200 * 3)>; + format = "r8g8b8"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + reserved-memory { + other_ext_region@0 { + no-map; + reg = <0x00 0x84500000 0x00 0x2300000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + key-volume-up { + label = "volume_up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5506"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + vcc-supply = <&pm8953_l10>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1200>; + touchscreen-size-y = <1920>; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s1: s1 { + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <1156000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2050000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_off>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <135 4>; + + ts_int_active: ts-int-active-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_reset_active: ts-reset-active-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <0x08>; + bias-pull-up; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; + +&wcnss { + vddpx-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660b"; + + vddxo-supply = <&pm8953_l7>; + vddrfa-supply = <&pm8953_l19>; + vddpa-supply = <&pm8953_l9>; + vdddig-supply = <&pm8953_l5>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts b/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts index e27f3c5d5bba..a288d52fb6d7 100644 --- a/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts +++ b/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts @@ -248,5 +248,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index f5921b80ef94..94057ebf767f 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2422,7 +2422,6 @@ thermal-zones { aoss-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 0>; @@ -2437,7 +2436,6 @@ cpuss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 1>; @@ -2452,7 +2450,6 @@ cpuss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 2>; @@ -2467,7 +2464,6 @@ cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 3>; @@ -2488,7 +2484,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 4>; @@ -2509,7 +2504,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 5>; @@ -2530,7 +2524,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 6>; @@ -2557,7 +2550,6 @@ pwr-cluster-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 7>; @@ -2578,7 +2570,6 @@ gpu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens 8>; @@ -2591,20 +2582,32 @@ trips { gpu_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; }; timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 1 0xf08>, - <GIC_PPI 2 0xf08>, - <GIC_PPI 3 0xf08>, - <GIC_PPI 0 0xf08>; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index e2708c74e95a..2c1172aa97e4 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -143,6 +143,10 @@ status = "okay"; }; +&pmi632_vib { + status = "okay"; +}; + &sdhc_1 { status = "okay"; vmmc-supply = <&pm8953_l8>; diff --git a/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts b/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts index c82d6e628d2c..2f55db0c8ce3 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts @@ -287,5 +287,6 @@ }; &usb3_dwc3 { + /delete-property/ usb-role-switch; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 80e81c4233b3..187c6698835d 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -509,6 +509,18 @@ no-map; }; + smem@86000000 { + compatible = "qcom,smem"; + reg = <0 0x86000000 0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + tz_mem: tz@86200000 { + reg = <0 0x86200000 0 0x2d00000>; + no-map; + }; + camera_mem: camera-mem@8ab00000 { reg = <0 0x8ab00000 0 0x500000>; no-map; @@ -1139,6 +1151,12 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0 0x01f40000 0 0x20000>; + #hwlock-cells = <1>; + }; + tlmm: pinctrl@3400000 { compatible = "qcom,sdm670-tlmm"; reg = <0 0x03400000 0 0xc00000>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 76bfa786612c..2391f842c903 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -51,9 +51,6 @@ thermal-zones { xo_thermal: xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8998_adc_tm 1>; trips { @@ -66,9 +63,6 @@ }; msm_thermal: msm-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8998_adc_tm 2>; trips { @@ -81,9 +75,6 @@ }; pa_thermal: pa-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8998_adc_tm 3>; trips { @@ -96,9 +87,6 @@ }; quiet_thermal: quiet-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&pm8998_adc_tm 4>; trips { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 10de2bd46ffc..23b101bb3842 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -15,6 +15,7 @@ #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/firmware/qcom,scm.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sdm845.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -2666,6 +2667,8 @@ "ref_aux", "qref"; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -4028,6 +4031,35 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint { + remote-endpoint = <&dp_out>; + }; + }; + }; }; usb_2_qmpphy: phy@88eb000 { @@ -4108,6 +4140,26 @@ snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; + }; }; }; @@ -4598,7 +4650,9 @@ port@1 { reg = <1>; - dp_out: endpoint { }; + dp_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; }; }; @@ -5105,6 +5159,78 @@ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; }; + anoc_1_tbu: tbu@150c5000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150c5000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x0 0x400>; + }; + + anoc_2_tbu: tbu@150c9000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150c9000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x400 0x400>; + }; + + mnoc_hf_0_tbu: tbu@150cd000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150cd000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x800 0x400>; + }; + + mnoc_hf_1_tbu: tbu@150d1000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150d1000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY + &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; + qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; + }; + + mnoc_sf_0_tbu: tbu@150d5000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150d5000 0x0 0x1000>; + interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY + &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; + }; + + compute_dsp_tbu: tbu@150d9000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150d9000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; + }; + + adsp_tbu: tbu@150dd000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150dd000 0x0 0x1000>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; + }; + + anoc_1_pcie_tbu: tbu@150e1000 { + compatible = "qcom,sdm845-tbu"; + reg = <0x0 0x150e1000 0x0 0x1000>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>; + qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; + }; + lpasscc: clock-controller@17014000 { compatible = "qcom,sdm845-lpasscc"; reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; @@ -5358,7 +5484,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -5385,7 +5510,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -5412,7 +5536,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -5439,7 +5562,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -5466,7 +5588,6 @@ cpu4-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -5493,7 +5614,6 @@ cpu5-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -5520,7 +5640,6 @@ cpu6-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -5547,7 +5666,6 @@ cpu7-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -5574,7 +5692,6 @@ aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 0>; @@ -5589,7 +5706,6 @@ cluster0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -5609,7 +5725,6 @@ cluster1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -5629,7 +5744,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 11>; @@ -5642,16 +5756,27 @@ trips { gpu_top_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -5664,16 +5789,27 @@ trips { gpu_bottom_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; aoss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 0>; @@ -5688,7 +5824,6 @@ q6-modem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -5703,7 +5838,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -5718,7 +5852,6 @@ wlan-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -5733,7 +5866,6 @@ q6-hvx-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; @@ -5748,7 +5880,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 5>; @@ -5763,7 +5894,6 @@ video-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; @@ -5778,7 +5908,6 @@ modem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 7>; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 47dc42f6e936..f18050848cd8 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -370,6 +370,66 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; + + embedded-controller@70 { + compatible = "lenovo,yoga-c630-ec"; + reg = <0x70>; + + interrupts-extended = <&tlmm 20 IRQ_TYPE_LEVEL_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&ec_int_state>; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ucsi0_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + ucsi0_ss_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + ucsi0_sbu: endpoint { + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "host"; + + /* + * connected to the onboard USB hub, orientation is + * handled by the controller + */ + }; + }; }; &i2c3 { @@ -494,6 +554,7 @@ &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sdm850/LENOVO/81JL/ipa_fws.elf"; status = "okay"; }; @@ -694,6 +755,13 @@ bias-disable; }; + + ec_int_state: ec-int-state { + pins = "gpio20"; + function = "gpio"; + + bias-disable; + }; }; &uart6 { @@ -741,6 +809,10 @@ dr_mode = "host"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&ucsi0_hs_in>; +}; + &usb_1_hsphy { status = "okay"; @@ -761,6 +833,10 @@ vdda-pll-supply = <&vdda_usb1_ss_core>; }; +&usb_1_qmpphy_out { + remote-endpoint = <&ucsi0_ss_in>; +}; + &usb_2 { status = "okay"; }; @@ -834,6 +910,7 @@ vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; qcom,snoc-host-cap-8bit-quirk; + qcom,ath10k-calibration-variant = "Lenovo_C630"; }; &crypto { diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts index f76e72fb2072..fde16308c7e2 100644 --- a/arch/arm64/boot/dts/qcom/sdx75-idp.dts +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -41,6 +41,29 @@ vin-supply = <&vph_ext>; }; + + reg_2v952_vcc: regulator-2v952-vcc { + compatible = "regulator-gpio"; + regulator-name = "2v952_vcc"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3600000>; + enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; + states = <1650000 0>, <3600000 1>; + startup-delay-us = <5000>; + enable-active-high; + regulator-boot-on; + + vin-supply = <&vph_ext>; + }; + + reg_2v95_vdd: regulator-2v95-vdd { + compatible = "regulator-fixed"; + regulator-name = "2v95_vdd"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + vin-supply = <®_2v952_vcc>; + }; }; &apps_rsc { @@ -259,8 +282,30 @@ status = "okay"; }; +&sdhc { + cd-gpios = <&tlmm 103 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_2v95_vdd>; + vqmmc-supply = <®_2v952_vcc>; + bus-width = <4>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc1_default &sd_cd>; + pinctrl-1 = <&sdc1_sleep &sd_cd>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <110 6>; + + sd_cd: sd-cd-state { + pins = "gpio103"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart1 { diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index da1704061d58..9b93f6501d55 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -8,9 +8,12 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sdx75-gcc.h> +#include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,sdx75.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -405,7 +408,42 @@ }; }; - smem: qcom,smem { + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smem: smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; hwlocks = <&tcsr_mutex 3>; @@ -441,6 +479,37 @@ #power-domain-cells = <1>; }; + ipcc: mailbox@408000 { + compatible = "qcom,sdx75-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + gpi_dma: dma-controller@900000 { + compatible = "qcom,sdx75-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00900000 0x0 0x60000>; + #dma-cells = <3>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <12>; + dma-channel-mask = <0x7f>; + iommus = <&apps_smmu 0xf6 0x0>; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x2000>; @@ -457,6 +526,52 @@ ranges; status = "disabled"; + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00980000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 0 QCOM_GPI_I2C>, + <&gpi_dma 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00980000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 0 QCOM_GPI_SPI>, + <&gpi_dma 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + uart1: serial@984000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x00984000 0x0 0x4000>; @@ -475,6 +590,229 @@ "sleep"; status = "disabled"; }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00988000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 2 QCOM_GPI_I2C>, + <&gpi_dma 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00988000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 2 QCOM_GPI_SPI>, + <&gpi_dma 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0098c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 3 QCOM_GPI_I2C>, + <&gpi_dma 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0098c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 3 QCOM_GPI_SPI>, + <&gpi_dma 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart4: serial@990000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00990000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_uart4_default>, <&qup_uart4_cts_rts>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00994000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 5 QCOM_GPI_I2C>, + <&gpi_dma 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00998000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 6 QCOM_GPI_I2C>, + <&gpi_dma 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00998000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 6 QCOM_GPI_SPI>, + <&gpi_dma 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c7: i2c@99c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0099c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 7 QCOM_GPI_I2C>, + <&gpi_dma 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi7: spi@99c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0099c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; + pinctrl-names = "default"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma 0 7 QCOM_GPI_SPI>, + <&gpi_dma 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + status = "disabled"; + }; }; usb_hsphy: phy@ff4000 { @@ -538,6 +876,59 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1fc0000 { + compatible = "qcom,sdx75-tcsr", "syscon"; + reg = <0x0 0x01fc0000 0x0 0x30000>; + }; + + sdhc: mmc@8804000 { + compatible = "qcom,sdx75-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + iommus = <&apps_smmu 0x00a0 0x0>; + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SDCC_1>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + bus-width = <4>; + dma-coherent; + + /* Forbid SDR104/SDR50 - broken hw! */ + sdhci-caps-mask = <0x3 0>; + + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + usb: usb@a6f8800 { compatible = "qcom,sdx75-dwc3", "qcom,dwc3"; reg = <0x0 0x0a6f8800 0x0 0x400>; @@ -627,6 +1018,17 @@ interrupt-controller; }; + aoss_qmp: power-controller@c310000 { + compatible = "qcom,sdx75-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c310000 0 0x1000>; + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + spmi_bus: spmi@c400000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c400000 0x0 0x3000>, @@ -661,6 +1063,145 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio8", "gpio9"; + function = "qup_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio14", "gpio15"; + function = "qup_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio52", "gpio53"; + function = "qup_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio110", "gpio111"; + function = "qup_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio112", "gpio113"; + function = "qup_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio116", "gpio117"; + function = "qup_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio11"; + function = "qup_se0"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio8", "gpio9", "gpio10"; + function = "qup_se0"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio17"; + function = "qup_se2"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio14", "gpio15", "gpio16"; + function = "qup_se2"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio55"; + function = "qup_se3"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio52", "gpio53", "gpio54"; + function = "qup_se3"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio115"; + function = "qup_se6"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio112", "gpio113", "gpio114"; + function = "qup_se6"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi7_cs: qup-spi7-cs-state { + pins = "gpio119"; + function = "qup_se7"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_spi7_data_clk: qup-spi7-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio116", "gpio117", "gpio118"; + function = "qup_se7"; + drive-strength = <6>; + bias-pull-down; + }; + + qup_uart4_cts_rts: qup-uart4-cts-rts-state { + /* CTS, RTS */ + pins = "gpio52", "gpio53"; + function = "qup_se3"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart4_default: qup-uart4-default-state { + /* TX, RX */ + pins = "gpio54", "gpio55"; + function = "qup_se3"; + drive-strength = <2>; + bias-pull-up; + }; + qupv3_se1_2uart_active: qupv3-se1-2uart-active-state { tx-pins { pins = "gpio12"; @@ -683,6 +1224,46 @@ drive-strength = <2>; bias-pull-down; }; + + sdc1_default: sdc1-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc1_sleep: sdc1-sleep-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; apps_smmu: iommu@15000000 { diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts index 2c7a12983dae..9153a5a55ed9 100644 --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -240,6 +240,7 @@ }; &usb_dwc3 { + /delete-property/ usb-role-switch; maximum-speed = "high-speed"; dr_mode = "peripheral"; diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index 603c962661cc..9c9919e78fbd 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -29,6 +29,14 @@ clock-frequency = <32000>; #clock-cells = <0>; }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-mult = <1>; + clock-div = <2>; + }; }; cpus { @@ -39,10 +47,12 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_0: l2-cache { @@ -63,10 +73,12 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_100>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_100: l2-cache { @@ -81,10 +93,12 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_200>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_200: l2-cache { @@ -99,10 +113,12 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_300>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_300: l2-cache { @@ -117,10 +133,12 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_400>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_400: l2-cache { @@ -135,10 +153,12 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_500>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_500: l2-cache { @@ -153,10 +173,12 @@ device_type = "cpu"; compatible = "arm,cortex-a78"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_600>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_600: l2-cache { @@ -171,10 +193,12 @@ device_type = "cpu"; compatible = "arm,cortex-a78"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_700>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_700: l2-cache { @@ -268,9 +292,14 @@ reg = <0x0 0xa0000000 0x0 0x0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; psci { @@ -526,6 +555,19 @@ }; }; + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sm4450-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x17d91000 0 0x1000>, + <0 0x17d92000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; }; timer { diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 98eb072fa912..4a30024aa48f 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -234,6 +234,7 @@ }; &usb_dwc3 { + /delete-property/ usb-role-switch; maximum-speed = "high-speed"; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index aca0a87092e4..ac5f071a8db3 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1088,6 +1088,8 @@ <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface", "core", "xo", "ice"; + resets = <&gcc GCC_SDCC1_BCR>; + power-domains = <&rpmpd SM6115_VDDCX>; operating-points-v2 = <&sdhc1_opp_table>; interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG @@ -1230,6 +1232,8 @@ "ref_aux", "qref"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -3011,8 +3015,6 @@ thermal-zones { mapss-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 0>; trips { @@ -3031,8 +3033,6 @@ }; cdsp-hvx-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; trips { @@ -3051,8 +3051,6 @@ }; wlan-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; trips { @@ -3071,8 +3069,6 @@ }; camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; trips { @@ -3091,8 +3087,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; trips { @@ -3111,8 +3105,6 @@ }; modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; trips { @@ -3131,8 +3123,6 @@ }; cpu4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; trips { @@ -3157,8 +3147,6 @@ }; cpu5-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; trips { @@ -3183,8 +3171,6 @@ }; cpu6-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 8>; trips { @@ -3209,8 +3195,6 @@ }; cpu7-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 9>; trips { @@ -3235,8 +3219,6 @@ }; cpu45-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 10>; trips { @@ -3261,8 +3243,6 @@ }; cpu67-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 11>; trips { @@ -3287,8 +3267,6 @@ }; cpu0123-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 12>; trips { @@ -3313,8 +3291,6 @@ }; modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 13>; trips { @@ -3333,8 +3309,6 @@ }; display-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 14>; trips { @@ -3353,8 +3327,8 @@ }; gpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; + polling-delay-passive = <250>; + thermal-sensors = <&tsens0 15>; cooling-maps { @@ -3366,13 +3340,13 @@ trips { gpu_alert0: trip-point0 { - temperature = <115000>; - hysteresis = <5000>; + temperature = <85000>; + hysteresis = <1000>; type = "passive"; }; trip-point1 { - temperature = <125000>; + temperature = <110000>; hysteresis = <1000>; type = "critical"; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 54da053a8042..9d78bb3f7190 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -359,6 +359,7 @@ }; &usb_dwc3 { + /delete-property/ usb-role-switch; maximum-speed = "high-speed"; dr_mode = "peripheral"; diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 08046f866f60..dcd05f303b78 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -90,8 +90,6 @@ thermal-zones { rf-pa0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm6125_adc_tm 0>; trips { @@ -104,8 +102,6 @@ }; quiet-thermal { - polling-delay-passive = <0>; - polling-delay = <5000>; thermal-sensors = <&pm6125_adc_tm 1>; trips { @@ -118,8 +114,6 @@ }; xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm6125_adc_tm 2>; trips { @@ -132,8 +126,6 @@ }; rf-pa1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm6125_adc_tm 3>; trips { diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts index a49d3ebb1931..994fb0412fcb 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts @@ -84,8 +84,6 @@ thermal-zones { rf-pa0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm6125_adc_tm 0>; trips { @@ -98,8 +96,6 @@ }; quiet-thermal { - polling-delay-passive = <0>; - polling-delay = <5000>; thermal-sensors = <&pm6125_adc_tm 1>; trips { @@ -112,8 +108,6 @@ }; xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm6125_adc_tm 2>; trips { diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 98ab08356088..777c380c2fa0 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -1588,10 +1588,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 1 0xf08 - GIC_PPI 2 0xf08 - GIC_PPI 3 0xf08 - GIC_PPI 0 0xf08>; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <19200000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index dddd6e44d280..bf23033a294e 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -293,7 +293,7 @@ compatible = "samsung,s6sy761"; reg = <0x48>; interrupt-parent = <&tlmm>; - interrupts = <22 0x2008>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&pm6350_l11>; avdd-supply = <&touch_en_vreg>; @@ -375,6 +375,7 @@ }; &usb_1_dwc3 { + /delete-property/ usb-role-switch; maximum-speed = "super-speed"; dr_mode = "peripheral"; }; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 84ff20a96c83..46e122c4421c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1197,6 +1197,8 @@ "ref_aux", "qref"; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -1713,10 +1715,39 @@ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; + orientation-switch; + #clock-cells = <1>; #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint { + }; + }; + }; }; dc_noc: interconnect@9160000 { @@ -1892,6 +1923,27 @@ snps,hird-threshold = /bits/ 8 <0x10>; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; + }; }; }; @@ -2831,9 +2883,6 @@ thermal-zones { aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; trips { @@ -2846,9 +2895,6 @@ }; aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 0>; trips { @@ -2861,9 +2907,6 @@ }; audio-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 2>; trips { @@ -2876,9 +2919,6 @@ }; camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 5>; trips { @@ -2891,9 +2931,6 @@ }; cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 1>; trips { @@ -2919,9 +2956,6 @@ }; cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 2>; trips { @@ -2947,9 +2981,6 @@ }; cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 3>; trips { @@ -2975,9 +3006,6 @@ }; cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 4>; trips { @@ -3003,9 +3031,6 @@ }; cpu4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 5>; trips { @@ -3031,9 +3056,6 @@ }; cpu5-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 6>; trips { @@ -3059,9 +3081,6 @@ }; cpu6-left-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; trips { @@ -3087,9 +3106,6 @@ }; cpu6-right-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 10>; trips { @@ -3115,9 +3131,6 @@ }; cpu7-left-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 11>; trips { @@ -3143,9 +3156,6 @@ }; cpu7-right-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 12>; trips { @@ -3171,9 +3181,6 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 7>; trips { @@ -3186,9 +3193,6 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; trips { @@ -3201,9 +3205,6 @@ }; cwlan-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 1>; trips { @@ -3216,9 +3217,6 @@ }; ddr-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 3>; trips { @@ -3231,21 +3229,20 @@ }; gpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; + polling-delay-passive = <250>; thermal-sensors = <&tsens0 13>; trips { gpuss0_alert0: trip-point0 { - temperature = <95000>; + temperature = <85000>; hysteresis = <2000>; type = "passive"; }; gpuss0-crit { - temperature = <115000>; - hysteresis = <0>; + temperature = <110000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -3259,21 +3256,20 @@ }; gpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; + polling-delay-passive = <250>; thermal-sensors = <&tsens0 14>; trips { gpuss1_alert0: trip-point0 { - temperature = <95000>; + temperature = <85000>; hysteresis = <2000>; type = "passive"; }; gpuss1-crit { - temperature = <115000>; - hysteresis = <0>; + temperature = <110000>; + hysteresis = <1000>; type = "critical"; }; }; @@ -3287,9 +3283,6 @@ }; modem-core0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 6>; trips { @@ -3302,9 +3295,6 @@ }; modem-core1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 7>; trips { @@ -3317,9 +3307,6 @@ }; modem-scl-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; trips { @@ -3332,9 +3319,6 @@ }; modem-vec-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; trips { @@ -3347,9 +3331,6 @@ }; npu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; trips { @@ -3362,9 +3343,6 @@ }; q6-hvx-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 4>; trips { @@ -3377,9 +3355,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 11>; trips { diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index cca2c2eb88ad..e04a3b8f81c5 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -142,7 +142,7 @@ compatible = "samsung,s6sy761"; reg = <0x48>; interrupt-parent = <&tlmm>; - interrupts = <22 0x2008>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&pm6125_l13>; avdd-supply = <&touch_avdd>; diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index f40509d91bbd..ddea681b536d 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1837,9 +1837,6 @@ thermal-zones { mapss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; trips { @@ -1864,9 +1861,6 @@ }; cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 1>; trips { @@ -1891,9 +1885,6 @@ }; cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 2>; trips { @@ -1918,9 +1909,6 @@ }; cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 3>; trips { @@ -1945,9 +1933,6 @@ }; cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 4>; trips { @@ -1972,9 +1957,6 @@ }; cpu4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 5>; trips { @@ -1999,9 +1981,6 @@ }; cpu5-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 6>; trips { @@ -2026,9 +2005,6 @@ }; cluster0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 7>; trips { @@ -2053,9 +2029,6 @@ }; cluster1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; trips { @@ -2080,9 +2053,6 @@ }; cpu6-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; trips { @@ -2107,9 +2077,6 @@ }; cpu7-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 10>; trips { @@ -2134,9 +2101,6 @@ }; cpu-unk0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 11>; trips { @@ -2161,9 +2125,6 @@ }; cpu-unk1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 12>; trips { @@ -2188,9 +2149,6 @@ }; gpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 13>; trips { @@ -2215,9 +2173,6 @@ }; gpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 14>; trips { @@ -2242,9 +2197,6 @@ }; mapss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 0>; trips { @@ -2269,9 +2221,6 @@ }; cwlan-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 1>; trips { @@ -2296,9 +2245,6 @@ }; audio-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 2>; trips { @@ -2323,9 +2269,6 @@ }; ddr-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 3>; trips { @@ -2350,9 +2293,6 @@ }; q6hvx-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 4>; trips { @@ -2377,9 +2317,6 @@ }; camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 5>; trips { @@ -2404,9 +2341,6 @@ }; mdm-core0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 6>; trips { @@ -2431,9 +2365,6 @@ }; mdm-core1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 7>; trips { @@ -2458,9 +2389,6 @@ }; mdm-vec-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; trips { @@ -2485,9 +2413,6 @@ }; msm-scl-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; trips { @@ -2512,9 +2437,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; trips { diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index bc67e8c1fe4d..4e67bb80a026 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -19,6 +19,7 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/usb/pd.h> #include "sm7225.dtsi" #include "pm6150l.dtsi" #include "pm6350.dtsi" @@ -94,8 +95,6 @@ thermal-zones { chg-skin-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm7250b_adc_tm 0>; trips { @@ -108,8 +107,6 @@ }; conn-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm7250b_adc_tm 1>; trips { @@ -120,6 +117,25 @@ }; }; }; + + pm8008-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pm8008>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; }; }; @@ -134,124 +150,145 @@ qcom,pmic-id = "a"; vreg_s1a: smps1 { + regulator-name = "vreg_s1a"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1200000>; }; vreg_s2a: smps2 { + regulator-name = "vreg_s2a"; regulator-min-microvolt = <1503000>; regulator-max-microvolt = <2048000>; }; vreg_l2a: ldo2 { + regulator-name = "vreg_l2a"; regulator-min-microvolt = <1503000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; regulator-min-microvolt = <352000>; regulator-max-microvolt = <801000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; regulator-min-microvolt = <1503000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; regulator-min-microvolt = <1710000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <3401000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l11a: ldo11 { + regulator-name = "vreg_l11a"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l12a: ldo12 { + regulator-name = "vreg_l12a"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l13a: ldo13 { + regulator-name = "vreg_l13a"; regulator-min-microvolt = <570000>; regulator-max-microvolt = <650000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l14a: ldo14 { + regulator-name = "vreg_l14a"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1900000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l15a: ldo15 { + regulator-name = "vreg_l15a"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1305000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l16a: ldo16 { + regulator-name = "vreg_l16a"; regulator-min-microvolt = <830000>; regulator-max-microvolt = <921000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l18a: ldo18 { + regulator-name = "vreg_l18a"; regulator-min-microvolt = <788000>; regulator-max-microvolt = <1049000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l19a: ldo19 { + regulator-name = "vreg_l19a"; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1305000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l20a: ldo20 { + regulator-name = "vreg_l20a"; regulator-min-microvolt = <530000>; regulator-max-microvolt = <801000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l21a: ldo21 { + regulator-name = "vreg_l21a"; regulator-min-microvolt = <751000>; regulator-max-microvolt = <825000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l22a: ldo22 { + regulator-name = "vreg_l22a"; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1305000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; @@ -263,41 +300,48 @@ qcom,pmic-id = "e"; vreg_s8e: smps8 { + regulator-name = "vreg_s8e"; regulator-min-microvolt = <313000>; regulator-max-microvolt = <1395000>; }; vreg_l1e: ldo1 { + regulator-name = "vreg_l1e"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l2e: ldo2 { + regulator-name = "vreg_l2e"; regulator-min-microvolt = <1170000>; regulator-max-microvolt = <1305000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l3e: ldo3 { + regulator-name = "vreg_l3e"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1299000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l4e: ldo4 { + regulator-name = "vreg_l4e"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l5e: ldo5 { + regulator-name = "vreg_l5e"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l6e: ldo6 { + regulator-name = "vreg_l6e"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2950000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; @@ -307,18 +351,21 @@ }; vreg_l7e: ldo7 { + regulator-name = "vreg_l7e"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l8e: ldo8 { + regulator-name = "vreg_l8e"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l9e: ldo9 { + regulator-name = "vreg_l9e"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2960000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; @@ -328,18 +375,21 @@ }; vreg_l10e: ldo10 { + regulator-name = "vreg_l10e"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3401000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_l11e: ldo11 { + regulator-name = "vreg_l11e"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3401000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; vreg_bob: bob { + regulator-name = "vreg_bob"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <5492000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; @@ -407,7 +457,79 @@ }; &i2c10 { - /* PM8008 PMIC @ 8 and 9 */ + clock-frequency = <400000>; + status = "okay"; + + pm8008: pmic@8 { + compatible = "qcom,pm8008"; + reg = <0x8>; + + interrupts-extended = <&tlmm 59 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply = <&vreg_s8e>; + vdd-l3-l4-supply = <&vreg_bob>; + vdd-l5-supply = <&vreg_bob>; + vdd-l6-supply = <&vreg_s2a>; + vdd-l7-supply = <&vreg_bob>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8008_default>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells = <2>; + + #thermal-sensor-cells = <0>; + + regulators { + vreg_l1p: ldo1 { + regulator-name = "vreg_l1p"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l2p: ldo2 { + regulator-name = "vreg_l2p"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l3p: ldo3 { + regulator-name = "vreg_l3p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2800000>; + }; + + vreg_l4p: ldo4 { + regulator-name = "vreg_l4p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2904000>; + }; + + vreg_l5p: ldo5 { + regulator-name = "vreg_l5p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2900000>; + }; + + vreg_l6p: ldo6 { + regulator-name = "vreg_l6p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l7p: ldo7 { + regulator-name = "vreg_l7p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3140000>; + }; + }; + }; + /* PX8618 @ 26 */ /* SMB1395 PMIC @ 34 */ /* awinic,aw8695 @ 5a */ @@ -543,6 +665,53 @@ }; }; +&pm7250b_typec { + vdd-pdphy-supply = <&vreg_l3a>; + + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + /* + * Disable USB Power Delivery for now, seems to need extra work + * to support role switching while also letting the battery + * charge still - without charger driver + */ + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pm7250b_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs_out>; + }; + }; + + port@1 { + reg = <1>; + pm7250b_ss_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + }; + }; +}; + +&pm7250b_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <1500000>; + status = "okay"; +}; + &pmk8350_rtc { status = "okay"; }; @@ -673,6 +842,22 @@ */ bias-pull-up; }; + + pm8008_default: pm8008-default-state { + int-pins { + pins = "gpio59"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + reset-n-pins { + pins = "gpio58"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; }; &uart1 { @@ -726,7 +911,11 @@ &usb_1_dwc3 { maximum-speed = "super-speed"; - dr_mode = "peripheral"; + dr_mode = "otg"; +}; + +&usb_1_dwc3_hs_out { + remote-endpoint = <&pm7250b_hs_in>; }; &usb_1_hsphy { @@ -744,6 +933,10 @@ status = "okay"; }; +&usb_1_qmpphy_out { + remote-endpoint = <&pm7250b_ss_in>; +}; + &wifi { vdd-0.8-cx-mx-supply = <&vreg_l4a>; vdd-1.8-xo-supply = <&vreg_l7a>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 6cb6f503fdac..bac08f00b303 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -470,7 +470,6 @@ &mdss_dp_out { data-lanes = <0 1>; - remote-endpoint = <&usb_1_qmpphy_dp_in>; }; &mdss_dsi0 { @@ -556,7 +555,7 @@ port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { + pm8150b_hs_in: endpoint { remote-endpoint = <&usb_1_dwc3_hs>; }; }; @@ -676,18 +675,10 @@ orientation-switch; }; -&usb_1_qmpphy_dp_in { - remote-endpoint = <&mdss_dp_out>; -}; - &usb_1_qmpphy_out { remote-endpoint = <&pm8150b_typec_mux_in>; }; -&usb_1_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &usb_2_qmpphy { status = "okay"; vdda-phy-supply = <&vreg_l3c_1p2>; @@ -708,11 +699,7 @@ }; &usb_1_dwc3_hs { - remote-endpoint = <&pm8150b_role_switch_in>; -}; - -&usb_1_dwc3_ss { - remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + remote-endpoint = <&pm8150b_hs_in>; }; &usb_2_dwc3 { diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index ff22e4346660..2471b158c76e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3507,6 +3507,7 @@ reg = <1>; usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; }; }; @@ -3514,6 +3515,7 @@ reg = <2>; usb_1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp_out>; }; }; }; @@ -3672,6 +3674,7 @@ reg = <1>; usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; }; }; @@ -3894,6 +3897,7 @@ reg = <1>; mdss_dp_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_in>; }; }; }; @@ -4577,7 +4581,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -4621,7 +4624,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -4665,7 +4667,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -4709,7 +4710,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -4753,7 +4753,6 @@ cpu4-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -4797,7 +4796,6 @@ cpu5-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -4841,7 +4839,6 @@ cpu6-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -4885,7 +4882,6 @@ cpu7-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -4929,7 +4925,6 @@ cpu4-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 11>; @@ -4973,7 +4968,6 @@ cpu5-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -5017,7 +5011,6 @@ cpu6-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 13>; @@ -5061,7 +5054,6 @@ cpu7-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 14>; @@ -5105,7 +5097,6 @@ aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 0>; @@ -5120,7 +5111,6 @@ cluster0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -5140,7 +5130,6 @@ cluster1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -5160,7 +5149,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 15>; @@ -5173,16 +5161,27 @@ trips { gpu_top_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; aoss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 0>; @@ -5197,7 +5196,6 @@ wlan-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -5212,7 +5210,6 @@ video-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -5227,7 +5224,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -5242,7 +5238,6 @@ q6-hvx-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; @@ -5257,7 +5252,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 5>; @@ -5272,7 +5266,6 @@ compute-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; @@ -5287,7 +5280,6 @@ modem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 7>; @@ -5302,7 +5294,6 @@ npu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 8>; @@ -5317,7 +5308,6 @@ modem-vec-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 9>; @@ -5332,7 +5322,6 @@ modem-scl-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 10>; @@ -5347,7 +5336,6 @@ gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 11>; @@ -5360,10 +5348,22 @@ trips { gpu_bottom_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 7ef99038cb37..21b2ca1def83 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -53,8 +53,6 @@ thermal-zones { camera-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150l_adc_tm 0>; trips { @@ -67,8 +65,6 @@ }; conn-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150b_adc_tm 0>; trips { @@ -81,8 +77,6 @@ }; mmw-pa1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150_adc_tm 2>; trips { @@ -95,8 +89,6 @@ }; mmw-pa2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150l_adc_tm 2>; trips { @@ -109,8 +101,6 @@ }; skin-msm-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150l_adc_tm 1>; trips { @@ -123,8 +113,6 @@ }; skin-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150_adc_tm 1>; trips { @@ -137,8 +125,6 @@ }; xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pm8150_adc_tm 0>; trips { diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index e07d0311ecb5..f6870d3f2886 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -520,7 +520,7 @@ compatible = "samsung,s6sy761"; reg = <0x48>; interrupt-parent = <&tlmm>; - interrupts = <39 0x2008>; + interrupts = <39 IRQ_TYPE_LEVEL_LOW>; /* It's "vddio" downstream but it works anyway! */ vdd-supply = <&vreg_l1c_1p8>; avdd-supply = <&vreg_l10c_3p3>; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 41f117474872..3596dd328c31 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -659,8 +659,8 @@ port@0 { reg = <0>; - pm8150b_role_switch_in: endpoint { - remote-endpoint = <&usb_1_role_switch_out>; + pm8150b_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs_out>; }; }; }; @@ -725,8 +725,8 @@ status = "okay"; }; -&usb_1_role_switch_out { - remote-endpoint = <&pm8150b_role_switch_in>; +&usb_1_dwc3_hs_out { + remote-endpoint = <&pm8150b_hs_in>; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 8ccade628f1f..9d6c97d1fd9d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2204,7 +2204,7 @@ status = "disabled"; - pcie@0 { + pcieport0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2580,6 +2580,8 @@ resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; + power-domains = <&gcc UFS_PHY_GDSC>; + #phy-cells = <0>; status = "disabled"; @@ -3936,6 +3938,8 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + ports { #address-cells = <1>; #size-cells = <0>; @@ -3947,6 +3951,10 @@ port@1 { reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss_out>; + }; }; port@2 { @@ -4225,8 +4233,24 @@ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; - port { - usb_1_role_switch_out: endpoint {}; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; }; }; }; @@ -6275,7 +6299,6 @@ thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -6319,7 +6342,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -6363,7 +6385,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -6407,7 +6428,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -6451,7 +6471,6 @@ cpu4-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -6495,7 +6514,6 @@ cpu5-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -6539,7 +6557,6 @@ cpu6-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -6583,7 +6600,6 @@ cpu7-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -6627,7 +6643,6 @@ cpu4-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 11>; @@ -6671,7 +6686,6 @@ cpu5-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -6715,7 +6729,6 @@ cpu6-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 13>; @@ -6759,7 +6772,6 @@ cpu7-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 14>; @@ -6803,7 +6815,6 @@ aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 0>; @@ -6818,7 +6829,6 @@ cluster0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -6838,7 +6848,6 @@ cluster1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -6858,7 +6867,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 15>; @@ -6871,16 +6879,27 @@ trips { gpu_top_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; aoss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 0>; @@ -6895,7 +6914,6 @@ wlan-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -6910,7 +6928,6 @@ video-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -6925,7 +6942,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -6940,7 +6956,6 @@ q6-hvx-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; @@ -6955,7 +6970,6 @@ camera-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 5>; @@ -6970,7 +6984,6 @@ compute-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; @@ -6985,7 +6998,6 @@ npu-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 7>; @@ -7000,7 +7012,6 @@ gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 8>; @@ -7013,10 +7024,22 @@ trips { gpu_bottom_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 4c25ab2f5670..895adce59e75 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -486,17 +486,10 @@ &mdss_dp { status = "okay"; +}; - ports { - port@1 { - reg = <1>; - - mdss_dp0_out: endpoint { - data-lanes = <0 1>; - remote-endpoint = <&usb_1_qmpphy_dp_in>; - }; - }; - }; +&mdss_dp_out { + data-lanes = <0 1>; }; &mpss { @@ -864,10 +857,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { status = "okay"; @@ -881,22 +870,12 @@ vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p88>; - - orientation-switch; -}; - -&usb_1_qmpphy_dp_in { - remote-endpoint = <&mdss_dp0_out>; }; &usb_1_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; -&usb_1_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &usb_2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index f7c4700f00c3..38ee0850c335 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -301,8 +301,18 @@ reg = <0x0 0x80000000 0x0 0x0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-x1 { + compatible = "arm,cortex-x1-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; @@ -1779,6 +1789,8 @@ "ref_aux", "qref"; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -2256,6 +2268,8 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + status = "disabled"; ports { @@ -2273,6 +2287,7 @@ reg = <1>; usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; }; }; @@ -2280,6 +2295,7 @@ reg = <2>; usb_1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp_out>; }; }; }; @@ -2405,6 +2421,7 @@ reg = <1>; usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; }; }; @@ -2626,6 +2643,14 @@ remote-endpoint = <&dpu_intf0_out>; }; }; + + port@1 { + reg = <1>; + + mdss_dp_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; + }; }; dp_opp_table: opp-table { @@ -3665,7 +3690,6 @@ thermal_zones: thermal-zones { cpu0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 1>; @@ -3709,7 +3733,6 @@ cpu1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 2>; @@ -3753,7 +3776,6 @@ cpu2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 3>; @@ -3797,7 +3819,6 @@ cpu3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 4>; @@ -3841,7 +3862,6 @@ cpu4-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 7>; @@ -3885,7 +3905,6 @@ cpu5-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 8>; @@ -3929,7 +3948,6 @@ cpu6-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 9>; @@ -3973,7 +3991,6 @@ cpu7-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 10>; @@ -4017,7 +4034,6 @@ cpu4-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 11>; @@ -4061,7 +4077,6 @@ cpu5-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 12>; @@ -4105,7 +4120,6 @@ cpu6-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 13>; @@ -4149,7 +4163,6 @@ cpu7-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 14>; @@ -4193,7 +4206,6 @@ aoss0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 0>; @@ -4208,7 +4220,6 @@ cluster0-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 5>; @@ -4228,7 +4239,6 @@ cluster1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens0 6>; @@ -4248,7 +4258,6 @@ aoss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 0>; @@ -4263,7 +4272,6 @@ gpu-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 1>; @@ -4276,16 +4284,27 @@ trips { gpu_top_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; gpu-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 2>; @@ -4298,16 +4317,27 @@ trips { gpu_bottom_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; hysteresis = <1000>; type = "hot"; }; + + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; }; }; nspss1-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 3>; @@ -4322,7 +4352,6 @@ nspss2-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 4>; @@ -4337,7 +4366,6 @@ nspss3-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 5>; @@ -4352,7 +4380,6 @@ video-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 6>; @@ -4367,7 +4394,6 @@ mem-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 7>; @@ -4382,7 +4408,6 @@ modem1-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 8>; @@ -4397,7 +4422,6 @@ modem2-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 9>; @@ -4412,7 +4436,6 @@ modem3-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 10>; @@ -4427,7 +4450,6 @@ modem4-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 11>; @@ -4442,7 +4464,6 @@ camera-top-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 12>; @@ -4457,7 +4478,6 @@ cam-bottom-thermal { polling-delay-passive = <250>; - polling-delay = <1000>; thermal-sensors = <&tsens1 13>; diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 3be46b56c723..a754b8fe9167 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -138,7 +138,7 @@ thermal-zones { camera-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 2>; trips { @@ -152,7 +152,7 @@ rear-tof-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 5>; trips { @@ -166,7 +166,7 @@ skin-msm-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 1>; trips { @@ -180,7 +180,7 @@ therm1-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 3>; trips { @@ -194,7 +194,7 @@ therm2-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 6>; trips { @@ -208,7 +208,7 @@ usb-conn-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 7>; trips { @@ -222,7 +222,7 @@ wide-rfc-thermal { polling-delay-passive = <250>; - polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 4>; trips { @@ -235,8 +235,6 @@ }; xo-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&pmk8350_adc_tm 0>; trips { @@ -674,17 +672,10 @@ &mdss_dp0 { status = "okay"; +}; - ports { - port@1 { - reg = <1>; - - mdss_dp0_out: endpoint { - data-lanes = <0 1>; - remote-endpoint = <&usb_1_qmpphy_dp_in>; - }; - }; - }; +&mdss_dp0_out { + data-lanes = <0 1>; }; &pcie0 { @@ -1114,10 +1105,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { status = "okay"; @@ -1131,22 +1118,12 @@ vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p91>; - - orientation-switch; -}; - -&usb_1_qmpphy_dp_in { - remote-endpoint = <&mdss_dp0_out>; }; &usb_1_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; -&usb_1_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &vamacro { pinctrl-0 = <&dmic01_default>, <&dmic23_default>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi index 8b29fcf483a3..17dbb67868ae 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi @@ -488,7 +488,7 @@ compatible = "samsung,s6sy761"; reg = <0x48>; interrupt-parent = <&tlmm>; - interrupts = <21 0x2008>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&pm8350c_l2>; avdd-supply = <&pm8350c_l3>; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 616461fcbab9..9bafb3b350ff 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -754,8 +754,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <0>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -1803,6 +1803,12 @@ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, <&pcie0_phy>, @@ -1845,8 +1851,35 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + operating-points-v2 = <&pcie0_opp_table>; + status = "disabled"; + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + }; + pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; @@ -1932,6 +1965,12 @@ <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, <&pcie1_phy>, @@ -1972,8 +2011,56 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; + operating-points-v2 = <&pcie1_opp_table>; + status = "disabled"; + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + }; + }; + pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; @@ -2001,7 +2088,7 @@ "pipe"; clock-output-names = "pcie_1_pipe_clk"; - #clock-cells = <0>; + #clock-cells = <1>; #phy-cells = <0>; @@ -2304,6 +2391,8 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + status = "disabled"; ports { @@ -2321,6 +2410,7 @@ reg = <1>; usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; }; }; @@ -2328,6 +2418,7 @@ reg = <2>; usb_1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -3119,6 +3210,14 @@ remote-endpoint = <&dpu_intf0_out>; }; }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + remote-endpoint = <&usb_1_qmpphy_dp_in>; + }; + }; }; dp_opp_table: opp-table { @@ -4362,9 +4461,10 @@ compatible = "qcom,sm8450-llcc"; reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, - <0 0x19a00000 0 0x80000>; + <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", - "llcc3_base", "llcc_broadcast_base"; + "llcc3_base", "llcc_broadcast_base", + "llcc_broadcast_and_base"; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; }; @@ -4429,6 +4529,8 @@ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, <&gcc GCC_UFS_0_CLKREF_EN>; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; @@ -4584,6 +4686,7 @@ reg = <1>; usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; }; }; @@ -4610,8 +4713,6 @@ thermal-zones { aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 0>; trips { @@ -4630,8 +4731,6 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; trips { @@ -4650,8 +4749,6 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; trips { @@ -4670,8 +4767,6 @@ }; cpuss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; trips { @@ -4690,8 +4785,6 @@ }; cpuss4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; trips { @@ -4710,8 +4803,6 @@ }; cpu4-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; trips { @@ -4736,8 +4827,6 @@ }; cpu4-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; trips { @@ -4762,8 +4851,6 @@ }; cpu5-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; trips { @@ -4788,8 +4875,6 @@ }; cpu5-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 8>; trips { @@ -4814,8 +4899,6 @@ }; cpu6-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 9>; trips { @@ -4840,8 +4923,6 @@ }; cpu6-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 10>; trips { @@ -4866,8 +4947,6 @@ }; cpu7-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 11>; trips { @@ -4892,8 +4971,6 @@ }; cpu7-middle-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 12>; trips { @@ -4918,8 +4995,6 @@ }; cpu7-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 13>; trips { @@ -4945,7 +5020,7 @@ gpu-top-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens0 14>; cooling-maps { @@ -4956,35 +5031,29 @@ }; trips { - thermal-engine-config { - temperature = <125000>; + gpu_top_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; + type = "hot"; }; - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu_top_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; gpu-bottom-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens0 15>; cooling-maps { @@ -4995,35 +5064,27 @@ }; trips { - thermal-engine-config { - temperature = <125000>; + gpu_bottom_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu_bottom_alert0: trip-point0 { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 0>; trips { @@ -5042,8 +5103,6 @@ }; cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; trips { @@ -5068,8 +5127,6 @@ }; cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; trips { @@ -5094,8 +5151,6 @@ }; cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 3>; trips { @@ -5120,8 +5175,6 @@ }; cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 4>; trips { @@ -5147,7 +5200,7 @@ cdsp0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 5>; trips { @@ -5179,7 +5232,7 @@ cdsp1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 6>; trips { @@ -5211,7 +5264,7 @@ cdsp2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 7>; trips { @@ -5242,8 +5295,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 8>; trips { @@ -5263,7 +5314,7 @@ mem-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 9>; trips { @@ -5288,8 +5339,6 @@ }; modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 10>; trips { @@ -5320,8 +5369,6 @@ }; modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 11>; trips { @@ -5352,8 +5399,6 @@ }; modem2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 12>; trips { @@ -5384,8 +5429,6 @@ }; modem3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 13>; trips { @@ -5416,8 +5459,6 @@ }; camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 14>; trips { @@ -5436,8 +5477,6 @@ }; camera1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 15>; trips { diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 12d60a0ee095..2e12219006c9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -940,7 +940,6 @@ }; &mdss_dp0_out { - remote-endpoint = <&usb_dp_qmpphy_dp_in>; data-lanes = <0 1>; }; @@ -979,10 +978,6 @@ status = "okay"; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; -}; - &pm8550_gpios { sdc2_card_det_n: sdc2-card-det-state { pins = "gpio12"; @@ -1111,6 +1106,7 @@ #sound-dai-cells = <0>; sound-name-prefix = "SpkrLeft"; + qcom,port-mapping = <1 2 3 7 10 13>; }; /* WSA8845, Speaker South */ @@ -1128,6 +1124,7 @@ #sound-dai-cells = <0>; sound-name-prefix = "SpkrRight"; + qcom,port-mapping = <4 5 6 7 11 13>; }; }; @@ -1258,19 +1255,10 @@ status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "otg"; - usb-role-switch; -}; - &usb_1_dwc3_hs { remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { vdd-supply = <&vreg_l1e_0p88>; vdda12-supply = <&vreg_l3e_1p2>; @@ -1284,23 +1272,13 @@ vdda-phy-supply = <&vreg_l3e_1p2>; vdda-pll-supply = <&vreg_l3f_0p88>; - orientation-switch; - status = "okay"; }; -&usb_dp_qmpphy_dp_in { - remote-endpoint = <&mdss_dp0_out>; -}; - &usb_dp_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; -&usb_dp_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &xo_board { clock-frequency = <76800000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 3d4ad5aac70f..ab447fc252f7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -736,11 +736,6 @@ &mdss_dp0_out { data-lanes = <0 1>; - remote-endpoint = <&usb_dp_qmpphy_dp_in>; -}; - -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; }; &pcie0 { @@ -847,6 +842,7 @@ sound-name-prefix = "SpkrLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3g_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; }; /* WSA8845 */ @@ -860,6 +856,7 @@ sound-name-prefix = "SpkrRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3g_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; }; }; @@ -951,19 +948,10 @@ status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "otg"; - usb-role-switch; -}; - &usb_1_dwc3_hs { remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { vdd-supply = <&vreg_l1e_0p88>; vdda12-supply = <&vreg_l3e_1p2>; @@ -977,23 +965,13 @@ vdda-phy-supply = <&vreg_l3e_1p2>; vdda-pll-supply = <&vreg_l3f_0p91>; - orientation-switch; - status = "okay"; }; -&usb_dp_qmpphy_dp_in { - remote-endpoint = <&mdss_dp0_out>; -}; - &usb_dp_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; -&usb_dp_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &xo_board { clock-frequency = <76800000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 92f015017418..774bdfcffec3 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -214,6 +214,68 @@ regulator-always-on; regulator-boot-on; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en>, <&pmk8550_sleep_clk>; + + wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>; + /* + * TODO Add bt-enable-gpios once the Bluetooth driver is + * converted to using the power sequencer. + */ + + vdd-supply = <&vreg_s5g_0p85>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_s2g_0p85>; + vdddig-supply = <&vreg_s4e_0p95>; + vddrfa1p2-supply = <&vreg_s4g_1p25>; + vddrfa1p8-supply = <&vreg_s6g_1p86>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -720,17 +782,6 @@ status = "okay"; }; -&gcc { - clocks = <&bi_tcxo_div2>, <&sleep_clk>, - <&pcie0_phy>, - <&pcie1_phy>, - <0>, - <&ufs_mem_phy 0>, - <&ufs_mem_phy 1>, - <&ufs_mem_phy 2>, - <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; -}; - &gpi_dma1 { status = "okay"; }; @@ -807,11 +858,6 @@ &mdss_dp0_out { data-lanes = <0 1>; - remote-endpoint = <&usb_dp_qmpphy_dp_in>; -}; - -&pcie_1_phy_aux_clk { - status = "disabled"; }; &pcie0 { @@ -824,6 +870,23 @@ status = "okay"; }; +&pcieport0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1e_0p88>; vdda-pll-supply = <&vreg_l3e_1p2>; @@ -907,8 +970,15 @@ status = "okay"; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; +&pmk8550_gpios { + pmk8550_sleep_clk: sleep-clk-state { + pins = "gpio3"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + }; }; &qupv3_id_0 { @@ -955,6 +1025,7 @@ sound-name-prefix = "SpkrLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3g_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; }; /* WSA8845, Speaker South */ @@ -968,6 +1039,7 @@ sound-name-prefix = "SpkrRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3g_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; }; }; @@ -1084,6 +1156,13 @@ bias-disable; output-low; }; + + wlan_en: wlan-en-state { + pins = "gpio80"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; }; &uart7 { @@ -1135,19 +1214,10 @@ status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "otg"; - usb-role-switch; -}; - &usb_1_dwc3_hs { remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { vdd-supply = <&vreg_l1e_0p88>; vdda12-supply = <&vreg_l3e_1p2>; @@ -1161,23 +1231,13 @@ vdda-phy-supply = <&vreg_l3e_1p2>; vdda-pll-supply = <&vreg_l3f_0p88>; - orientation-switch; - status = "okay"; }; -&usb_dp_qmpphy_dp_in { - remote-endpoint = <&mdss_dp0_out>; -}; - &usb_dp_qmpphy_out { remote-endpoint = <&redriver_ss_in>; }; -&usb_dp_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &xo_board { clock-frequency = <76800000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts new file mode 100644 index 000000000000..3d351e90bb39 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Alexandru Marc Serdeliuc <serdeliuk@yahoo.com> + * Copyright (c) 2024, David Wronek <david@mainlining.org> + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sm8550.dtsi" +#include "pm8550.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +/delete-node/ &adspslpi_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mpss_dsm_mem; +/delete-node/ &mpss_mem; +/delete-node/ &rmtfs_mem; + +/ { + model = "Samsung Galaxy Z Fold5"; + compatible = "samsung,q5q", "qcom,sm8550"; + chassis-type = "handset"; + + aliases { + serial0 = &uart7; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@b8000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0xb8000000 0x0 0x2b00000>; + width = <2176>; + height = <1812>; + stride = <(2176 * 4)>; + format = "a8r8g8b8"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + adspslpi_mem: adspslpi@9ea00000 { + reg = <0x0 0x9ea00000 0x0 0x59b4000>; + no-map; + }; + + cdsp_mem: cdsp-region@9c900000 { + reg = <0 0x9c900000 0 0x2000000>; + no-map; + }; + + mpss_dsm_mem: mpss-dsm@d4d00000 { + reg = <0x0 0xd4d00000 0x0 0x3300000>; + no-map; + }; + + mpss_mem: mpss@8b400000 { + reg = <0x0 0x8b400000 0x0 0xfc00000>; + no-map; + }; + + rmtfs_mem: rmtfs-region@d4a80000 { + reg = <0x0 0xd4a80000 0x0 0x280000>; + no-map; + }; + + /* + * The bootloader will only keep display hardware enabled + * if this memory region is named exactly 'splash_region' + */ + splash_region@b8000000 { + reg = <0x0 0xb8000000 0x0 0x2b00000>; + no-map; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + regulator-always-on; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l3c_0p91: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + vreg_s4e_0p9: smps4 { + regulator-name = "vreg_s4e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5e_1p1: smps5 { + regulator-name = "vreg_s5e_1p1"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name = "vreg_l1e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + vreg_s4f_0p5: smps4 { + regulator-name = "vreg_s4f_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name = "vreg_l1f_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name = "vreg_l2f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f_0p91: ldo3 { + regulator-name = "vreg_l3f_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + + vreg_s1g_1p2: smps1 { + regulator-name = "vreg_s1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2g_0p8: smps2 { + regulator-name = "vreg_s2g_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s3g_0p7: smps3 { + regulator-name = "vreg_s3g_0p7"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s4g_1p3: smps4 { + regulator-name = "vreg_s4g_1p3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5g_0p8: smps5 { + regulator-name = "vreg_s5g_0p8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s6g_1p8: smps6 { + regulator-name = "vreg_s6g_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2g_1p2: ldo2 { + regulator-name = "vreg_l2g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-6 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vreg_l1m_1p056: ldo1 { + regulator-name = "vreg_l1m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name = "vreg_l2m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name = "vreg_l4m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name = "vreg_l5m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6m_1p8: ldo6 { + regulator-name = "vreg_l6m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7m_2p9: ldo7 { + regulator-name = "vreg_l7m_2p9"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "n"; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2n_1p1: ldo2 { + regulator-name = "vreg_l2n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3n_2p8: ldo3 { + regulator-name = "vreg_l3n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4n_2p8: ldo4 { + regulator-name = "vreg_l4n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5n_1p8: ldo5 { + regulator-name = "vreg_l5n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6n_3p3: ldo6 { + regulator-name = "vreg_l6n_3p3"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7n_2p96: ldo7 { + regulator-name = "vreg_l7n_2p96"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&dispcc { + status = "disabled"; +}; + +&i2c_master_hub_0 { + status = "okay"; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + linux,code = <KEY_VOLUMEDOWN>; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/adsp.mdt", + "qcom/sm8550/adsp_dtb.mdt"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8550/cdsp.mdt", + "qcom/sm8550/cdsp_dtb.mdt"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm8550/modem.mdt", + "qcom/sm8550/modem_dtb.mdt"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + gpio-reserved-ranges = <36 4>, <50 2>; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1g_1p2>; + vccq-max-microamp = <1200000>; + vdd-hba-supply = <&vreg_l3g_1p2>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&xo_board { + clock-frequency = <76800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index 85e0d3d66e16..85d487ef80a0 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -737,19 +737,10 @@ status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "otg"; - usb-role-switch; -}; - &usb_1_dwc3_hs { remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { vdd-supply = <&pm8550vs_2_l1>; vdda12-supply = <&pm8550vs_2_l3>; @@ -761,7 +752,6 @@ &usb_dp_qmpphy { vdda-phy-supply = <&pm8550vs_2_l3>; vdda-pll-supply = <&pm8550ve_l3>; - orientation-switch; status = "okay"; }; @@ -770,10 +760,6 @@ remote-endpoint = <&pmic_glink_ss_in>; }; -&usb_dp_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &xo_board { clock-frequency = <76800000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index bc5aeb05ffc3..4c9820adcf52 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -58,11 +58,6 @@ clock-mult = <1>; clock-div = <2>; }; - - pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; }; cpus { @@ -357,8 +352,23 @@ reg = <0 0xa0000000 0 0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a510 { + compatible = "arm,cortex-a510-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a710 { + compatible = "arm,cortex-a710-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a715 { + compatible = "arm,cortex-a715-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-x3 { + compatible = "arm,cortex-x3-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; @@ -776,8 +786,8 @@ #power-domain-cells = <1>; clocks = <&bi_tcxo_div2>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <&pcie_1_phy_aux_clk>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -1774,7 +1784,7 @@ status = "disabled"; - pcie@0 { + pcieport0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1928,7 +1938,7 @@ power-domains = <&gcc PCIE_1_PHY_GDSC>; - #clock-cells = <0>; + #clock-cells = <1>; clock-output-names = "pcie1_pipe_clk"; #phy-cells = <0>; @@ -2910,6 +2920,7 @@ port@1 { reg = <1>; mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; }; @@ -3169,6 +3180,8 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + status = "disabled"; ports { @@ -3186,6 +3199,7 @@ reg = <1>; usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; }; }; @@ -3193,6 +3207,7 @@ reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -3264,6 +3279,7 @@ snps,has-lpm-erratum; tx-fifo-resize; dma-coherent; + usb-role-switch; ports { #address-cells = <1>; @@ -3280,6 +3296,7 @@ reg = <1>; usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; }; }; @@ -4295,12 +4312,14 @@ <0 0x25200000 0 0x200000>, <0 0x25400000 0 0x200000>, <0 0x25600000 0 0x200000>, - <0 0x25800000 0 0x200000>; + <0 0x25800000 0 0x200000>, + <0 0x25a00000 0 0x200000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", "llcc3_base", - "llcc_broadcast_base"; + "llcc_broadcast_base", + "llcc_broadcast_and_base"; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; }; @@ -4571,8 +4590,6 @@ thermal-zones { aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 0>; trips { @@ -4591,8 +4608,6 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; trips { @@ -4611,8 +4626,6 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; trips { @@ -4631,8 +4644,6 @@ }; cpuss2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; trips { @@ -4651,8 +4662,6 @@ }; cpuss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; trips { @@ -4671,8 +4680,6 @@ }; cpu3-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; trips { @@ -4697,8 +4704,6 @@ }; cpu3-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; trips { @@ -4723,8 +4728,6 @@ }; cpu4-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; trips { @@ -4749,8 +4752,6 @@ }; cpu4-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 8>; trips { @@ -4775,8 +4776,6 @@ }; cpu5-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 9>; trips { @@ -4801,8 +4800,6 @@ }; cpu5-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 10>; trips { @@ -4827,8 +4824,6 @@ }; cpu6-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 11>; trips { @@ -4853,8 +4848,6 @@ }; cpu6-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 12>; trips { @@ -4879,8 +4872,6 @@ }; cpu7-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 13>; trips { @@ -4905,8 +4896,6 @@ }; cpu7-middle-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 14>; trips { @@ -4931,8 +4920,6 @@ }; cpu7-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 15>; trips { @@ -4957,8 +4944,6 @@ }; aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 0>; trips { @@ -4977,8 +4962,6 @@ }; cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; trips { @@ -5003,8 +4986,6 @@ }; cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; trips { @@ -5029,8 +5010,6 @@ }; cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 3>; trips { @@ -5056,7 +5035,7 @@ cdsp0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 4>; trips { @@ -5088,7 +5067,7 @@ cdsp1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 5>; trips { @@ -5120,7 +5099,7 @@ cdsp2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 6>; trips { @@ -5152,7 +5131,7 @@ cdsp3-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 7>; trips { @@ -5183,8 +5162,6 @@ }; video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 8>; trips { @@ -5204,7 +5181,7 @@ mem-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 9>; trips { @@ -5229,8 +5206,6 @@ }; modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 10>; trips { @@ -5261,8 +5236,6 @@ }; modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 11>; trips { @@ -5293,8 +5266,6 @@ }; modem2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 12>; trips { @@ -5325,8 +5296,6 @@ }; modem3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 13>; trips { @@ -5357,8 +5326,6 @@ }; camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 14>; trips { @@ -5377,8 +5344,6 @@ }; camera1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 15>; trips { @@ -5397,8 +5362,6 @@ }; aoss2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 0>; trips { @@ -5418,312 +5381,264 @@ gpuss-0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 1>; cooling-maps { map0 { - trip = <&gpu0_junction_config>; + trip = <&gpu0_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu0_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu0_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; gpuss-1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 2>; cooling-maps { map0 { - trip = <&gpu1_junction_config>; + trip = <&gpu1_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu1_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; + type = "hot"; }; - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu1_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; gpuss-2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 3>; cooling-maps { map0 { - trip = <&gpu2_junction_config>; + trip = <&gpu2_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu2_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; + type = "hot"; }; - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu2_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; gpuss-3-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 4>; cooling-maps { map0 { - trip = <&gpu3_junction_config>; + trip = <&gpu3_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu3_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu3_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; gpuss-4-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 5>; cooling-maps { map0 { - trip = <&gpu4_junction_config>; + trip = <&gpu4_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu4_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; + type = "hot"; }; - gpu4_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; gpuss-5-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 6>; cooling-maps { map0 { - trip = <&gpu5_junction_config>; + trip = <&gpu5_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu5_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; + type = "hot"; }; - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu5_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; gpuss-6-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 7>; cooling-maps { map0 { - trip = <&gpu6_junction_config>; + trip = <&gpu6_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu6_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; + type = "hot"; }; - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu6_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; gpuss-7-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 8>; cooling-maps { map0 { - trip = <&gpu7_junction_config>; + trip = <&gpu7_alert0>; cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; trips { - thermal-engine-config { - temperature = <125000>; + gpu7_alert0: trip-point0 { + temperature = <85000>; hysteresis = <1000>; type = "passive"; }; - thermal-hal-config { - temperature = <125000>; + trip-point1 { + temperature = <90000>; hysteresis = <1000>; - type = "passive"; + type = "hot"; }; - reset-mon-config { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu7_junction_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; + trip-point2 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso b/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso new file mode 100644 index 000000000000..cb102535838d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Linaro Limited + */ + +/* + * Display Card kit overlay + * This requires S5702 Switch 7 to be turned to OFF to route DSI0 to the display panel + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/dts-v1/; +/plugin/; + +/* Disable HDMI bridge related nodes (mutually exclusive with the display card) */ + +&i2c6 { + status = "disabled"; +}; + +<9611_1v2 { + status = "disabled"; +}; + +<9611_3v3 { + status = "disabled"; +}; + +&vreg_bob_3v3 { + status = "disabled"; +}; + +<9611_codec { + status = "disabled"; +}; + +&mdss_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + + pinctrl-0 = <&disp0_reset_n_active>, <&mdp_vsync>; + pinctrl-1 = <&disp0_reset_n_suspend>, <&mdp_vsync>; + pinctrl-names = "default", "sleep"; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + remote-endpoint = <&panel0_in>; + }; + }; + }; +}; + +&spi4 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <162 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 161 GPIO_ACTIVE_LOW>; + + avdd-supply = <&vreg_l14b_3p2>; + + spi-max-frequency = <1000000>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2400>; + + pinctrl-0 = <&ts_irq>, <&ts_reset>; + pinctrl-names = "default"; + }; +}; + +&tlmm { + disp0_reset_n_active: disp0-reset-n-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + disp0_reset_n_suspend: disp0-reset-n-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + mdp_vsync: mdp-vsync-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_irq: ts-irq-state { + pins = "gpio161"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-disable; + }; + + ts_reset: ts-reset-state { + pins = "gpio162"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts new file mode 100644 index 000000000000..591e6ab9bf5b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -0,0 +1,1355 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sm8650.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 8 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8650 HDK"; + compatible = "qcom,sm8650-hdk", "qcom,sm8650"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart15; + serial1 = &uart14; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_out: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_BLUETOOTH; + color = <LED_COLOR_ID_BLUE>; + gpios = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + + led-1 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pm8550b_gpios 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + + led-2 { + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_ORANGE>; + gpios = <&pm8550b_gpios 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + }; + + pmic-glink { + compatible = "qcom,sm8650-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&wcd_usbss_sbu_mux>; + }; + }; + }; + }; + }; + + lt9611_1v2: regulator-lt9611-1v2 { + compatible = "regulator-fixed"; + + regulator-name = "LT9611_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + vin-supply = <&vph_pwr>; + gpio = <&tlmm 79 GPIO_ACTIVE_HIGH>; + + enable-active-high; + }; + + lt9611_3v3: regulator-lt9611-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "LT9611_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vreg_bob_3v3>; + gpio = <&tlmm 78 GPIO_ACTIVE_HIGH>; + + enable-active-high; + }; + + sound { + compatible = "qcom,sm8650-sndcard", "qcom,sm8450-sndcard"; + model = "SM8650-HDK"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC5", "MIC BIAS4", + "TX SWR_INPUT0", "ADC1_OUTPUT", + "TX SWR_INPUT1", "ADC2_OUTPUT", + "TX SWR_INPUT3", "ADC4_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&north_spkr>, <&south_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_bob_3v3: regulator-vreg-bob-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_BOB_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vph_pwr>; + }; + + wcd939x: audio-codec { + compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en>; + + wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + /* + * TODO Add bt-enable-gpios once the Bluetooth driver is + * converted to using the power sequencer. + */ + + vdd-supply = <&vreg_s4i_0p85>; + vddio-supply = <&vreg_l15b_1p8>; + vddio1p2-supply = <&vreg_l3c_1p2>; + vddaon-supply = <&vreg_s2c_0p8>; + vdddig-supply = <&vreg_s3c_0p9>; + vddrfa1p2-supply = <&vreg_s1c_1p2>; + vddrfa1p8-supply = <&vreg_s6c_1p8>; + + clocks = <&rpmhcc RPMH_RF_CLK1>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s1c_1p2>; + vdd-l12-supply = <&vreg_s6c_1p8>; + vdd-l15-supply = <&vreg_s6c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + qcom,pmic-id = "b"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s1c_1p2>; + vdd-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + qcom,pmic-id = "c"; + + vreg_s1c_1p2: smps1 { + regulator-name = "vreg_s1c_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1348000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2c_0p8: smps2 { + regulator-name = "vreg_s2c_0p8"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <1036000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s3c_0p9: smps3 { + regulator-name = "vreg_s3c_0p9"; + regulator-min-microvolt = <976000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s4c_1p2: smps4 { + regulator-name = "vreg_s4c_1p2"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1280000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5c_0p7: smps5 { + regulator-name = "vreg_s5c_0p7"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s6c_1p8: smps6 { + regulator-name = "vreg_s6c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_1p2: ldo3 { + regulator-name = "vreg_l3c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "d"; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l3-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "e"; + + vreg_l3e_0p9: ldo3 { + regulator-name = "vreg_l3e_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + vdd-l3-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "g"; + + vreg_l1g_0p91: ldo1 { + regulator-name = "vreg_l1g_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3g_0p91: ldo3 { + regulator-name = "vreg_l3g_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + vdd-l2-supply = <&vreg_s3c_0p9>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-s4-supply = <&vph_pwr>; + + qcom,pmic-id = "i"; + + vreg_s4i_0p85: smps4 { + regulator-name = "vreg_s4i_0p85"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1i_0p88: ldo1 { + regulator-name = "vreg_l1i_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2i_0p88: ldo2 { + regulator-name = "vreg_l2i_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3i_1p2: ldo3 { + regulator-name = "vreg_l3i_0p91"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-6 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "m"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_bob2>; + vdd-l5-supply = <&vreg_s6c_1p8>; + vdd-l6-supply = <&vreg_bob1>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1m_1p1: ldo1 { + regulator-name = "vreg_l1m_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name = "vreg_l2m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name = "vreg_l4m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name = "vreg_l5m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name = "vreg_l6m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7m_2p96: ldo7 { + regulator-name = "vreg_l7m_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "n"; + + vdd-l1-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-l4-supply = <&vreg_s6c_1p8>; + vdd-l5-supply = <&vreg_bob2>; + vdd-l6-supply = <&vreg_bob2>; + vdd-l7-supply = <&vreg_bob1>; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2n_1p056: ldo2 { + regulator-name = "vreg_l2n_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name = "vreg_l3n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name = "vreg_l4n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name = "vreg_l5n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name = "vreg_l6n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name = "vreg_l7n_3p3"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&dispcc { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + wcd_usbss: typec-mux@e { + compatible = "qcom,wcd9395-usbss", "qcom,wcd9390-usbss"; + reg = <0xe>; + + vdd-supply = <&vreg_l15b_1p8>; + reset-gpios = <&tlmm 152 GPIO_ACTIVE_HIGH>; + + mode-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + wcd_usbss_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; + }; +}; + +&i2c6 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-0 = <<9611_irq_pin>, <<9611_rst_pin>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + }; +}; + +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sm8650/ipa_fws.mbn"; + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; + }; +}; + +&lpass_tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1i_0p88>; + + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcieport0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1i_0p88>; + vdda-pll-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3e_0p9>; + vdda-pll-supply = <&vreg_l3i_1p2>; + vdda-qref-supply = <&vreg_l1i_0p88>; + + status = "okay"; +}; + +&pm8550_gpios { + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio12"; + function = "normal"; + bias-pull-up; + input-enable; + output-disable; + power-source = <1>; /* 1.8 V */ + }; + + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + bias-pull-up; + input-enable; + power-source = <1>; + }; +}; + +/* The RGB signals are routed to 3 separate LEDs on the HDK8650 */ +&pm8550_pwm { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + led@1 { + reg = <1>; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + default-state = "off"; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + }; + + led@3 { + reg = <3>; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + default-state = "off"; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + +&pmk8550_rtc { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + + status = "okay"; +}; + +&qup_i2c3_data_clk { + /* Use internal I2C pull-up */ + bias-pull-up = <2200>; +}; + +&qupv3_id_0 { + iommus = <&apps_smmu 0xa3 0x3>; + + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8650/adsp.mbn", + "qcom/sm8650/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8650/cdsp.mbn", + "qcom/sm8650/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm8650/modem.mbn", + "qcom/sm8650/modem_dtb.mbn"; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + bus-width = <4>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&swr0 { + status = "okay"; + + /* WSA8845, Speaker North */ + north_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&lpass_tlmm 21 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Speaker South */ + south_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9395 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010e00"; + reg = <0 4>; + + /* + * WCD9395 RX Port 1 (HPH_L/R) <=> SWR1 Port 1 (HPH_L/R) + * WCD9395 RX Port 2 (CLSH) <=> SWR1 Port 2 (CLSH) + * WCD9395 RX Port 3 (COMP_L/R) <=> SWR1 Port 3 (COMP_L/R) + * WCD9395 RX Port 4 (LO) <=> SWR1 Port 4 (LO) + * WCD9395 RX Port 5 (DSD_L/R) <=> SWR1 Port 5 (DSD_L/R) + * WCD9395 RX Port 6 (HIFI_PCM_L/R) <=> SWR1 Port 9 (HIFI_PCM_L/R) + */ + qcom,rx-port-mapping = <1 2 3 4 5 9>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9395 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010e00"; + reg = <0 3>; + + /* + * WCD9395 TX Port 1 (ADC1,2,3,4) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 2 (ADC3,4 & DMIC0,1) <=> SWR2 Port 2 (TX SWR_INPUT 0,1,2,3) + * WCD9395 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 (TX SWR_INPUT 4,5,6,7) + * WCD9395 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 (TX SWR_INPUT 8,9,10,11) + */ + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + /* Reserved I/Os for NFC */ + gpio-reserved-ranges = <32 8>, <74 1>; + + bt_default: bt-default-state { + bt-en-pins { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins = "gpio18"; + function = "gpio"; + bias-pull-down; + }; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio85"; + function = "gpio"; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio28"; + function = "gpio"; + output-high; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio77"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wlan_en: wlan-en-state { + pins = "gpio16"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddio-supply = <&vreg_l3c_1p2>; + vddaon-supply = <&vreg_l15b_1p8>; + vdddig-supply = <&vreg_s3c_0p9>; + vddrfa0p8-supply = <&vreg_s3c_0p9>; + vddrfa1p2-supply = <&vreg_s1c_1p2>; + vddrfa1p9-supply = <&vreg_s6c_1p8>; + + max-speed = <3200000>; + + enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&bt_default>; + pinctrl-names = "default"; + }; +}; + +&uart15 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1c_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + +/* + * DPAUX -> WCD9395 -> USB_SBU -> USB-C + * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> WCD9395 -> USB-C + * USB SS -> USB-C + */ + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1i_0p88>; + vdda12-supply = <&vreg_l3i_1p2>; + + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3i_1p2>; + vdda-pll-supply = <&vreg_l3g_0p91>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&xo_board { + clock-frequency = <76800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index d04ceaa73c2b..c63822f5b127 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -59,7 +59,7 @@ reg = <1>; pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; + remote-endpoint = <&usb_dp_qmpphy_out>; }; }; }; @@ -641,10 +641,6 @@ status = "okay"; }; -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; @@ -755,6 +751,16 @@ sound-name-prefix = "SpkrLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <1 2 3 7 10 13>; }; /* WSA8845, Speaker Right */ @@ -768,6 +774,16 @@ sound-name-prefix = "SpkrRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <4 5 6 7 11 13>; }; }; @@ -853,10 +869,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&pmic_glink_ss_in>; -}; - &usb_1_hsphy { vdd-supply = <&vreg_l1i_0p88>; vdda12-supply = <&vreg_l3i_1p2>; @@ -873,6 +885,10 @@ status = "okay"; }; +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + &xo_board { clock-frequency = <76800000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 4e94f7fe4d2d..b0d7927b708f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -203,6 +203,71 @@ }; }; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en>; + + wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + /* + * TODO Add bt-enable-gpios once the Bluetooth driver is + * converted to using the power sequencer. + */ + + vdd-supply = <&vreg_s4i_0p85>; + vddio-supply = <&vreg_l15b_1p8>; + vddio1p2-supply = <&vreg_l3c_1p2>; + vddaon-supply = <&vreg_s2c_0p8>; + vdddig-supply = <&vreg_s3c_0p9>; + vddrfa1p2-supply = <&vreg_s1c_1p2>; + vddrfa1p8-supply = <&vreg_s6c_1p8>; + + clocks = <&rpmhcc RPMH_RF_CLK1>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -832,11 +897,6 @@ &mdss_dp0_out { data-lanes = <0 1>; - remote-endpoint = <&usb_dp_qmpphy_dp_in>; -}; - -&pcie_1_phy_aux_clk { - clock-frequency = <1000>; }; &pcie0 { @@ -849,6 +909,23 @@ status = "okay"; }; +&pcieport0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1i_0p88>; vdda-pll-supply = <&vreg_l3i_1p2>; @@ -1012,6 +1089,16 @@ sound-name-prefix = "SpkrLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <1 2 3 7 10 13>; }; /* WSA8845, Speaker Right */ @@ -1025,6 +1112,16 @@ sound-name-prefix = "SpkrRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; vdd-io-supply = <&vreg_l3c_1p2>; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <4 5 6 7 11 13>; }; }; @@ -1143,6 +1240,13 @@ bias-disable; output-low; }; + + wlan_en: wlan-en-state { + pins = "gpio16"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; }; &uart14 { @@ -1211,10 +1315,6 @@ remote-endpoint = <&pmic_glink_hs_in>; }; -&usb_1_dwc3_ss { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; -}; - &usb_1_hsphy { vdd-supply = <&vreg_l1i_0p88>; vdda12-supply = <&vreg_l3i_1p2>; @@ -1228,23 +1328,13 @@ vdda-phy-supply = <&vreg_l3i_1p2>; vdda-pll-supply = <&vreg_l3g_0p91>; - orientation-switch; - status = "okay"; }; -&usb_dp_qmpphy_dp_in { - remote-endpoint = <&mdss_dp0_out>; -}; - &usb_dp_qmpphy_out { remote-endpoint = <&redriver_ss_in>; }; -&usb_dp_qmpphy_usb_ss_in { - remote-endpoint = <&usb_1_dwc3_ss>; -}; - &xo_board { clock-frequency = <76800000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 62a6e77730bc..9d9bbb9aca64 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4,10 +4,12 @@ */ #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm8650-camcc.h> #include <dt-bindings/clock/qcom,sm8650-dispcc.h> #include <dt-bindings/clock/qcom,sm8650-gcc.h> #include <dt-bindings/clock/qcom,sm8650-gpucc.h> #include <dt-bindings/clock/qcom,sm8650-tcsr.h> +#include <dt-bindings/clock/qcom,sm8650-videocc.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/firmware/qcom,scm.h> #include <dt-bindings/gpio/gpio.h> @@ -60,11 +62,6 @@ clock-mult = <1>; clock-div = <2>; }; - - pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - }; }; cpus { @@ -371,6 +368,7 @@ firmware { scm: scm { compatible = "qcom,scm-sm8650", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x19000>; interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; @@ -394,8 +392,18 @@ reg = <0 0xa0000000 0 0>; }; - pmu { - compatible = "arm,armv8-pmuv3"; + pmu-a520 { + compatible = "arm,cortex-a520-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-a720 { + compatible = "arm,cortex-a720-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pmu-x4 { + compatible = "arm,cortex-x4-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; @@ -758,8 +766,8 @@ <&bi_tcxo_ao_div2>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <&pcie_1_phy_aux_clk>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -2208,7 +2216,7 @@ reg = <0 0x010c3000 0 0x1000>; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; reg = <0 0x01c00000 0 0x3000>, @@ -2294,7 +2302,7 @@ status = "disabled"; - pcie@0 { + pcieport0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2336,7 +2344,7 @@ status = "disabled"; }; - pcie1: pci@1c08000 { + pcie1: pcie@1c08000 { device_type = "pci"; compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; reg = <0 0x01c08000 0 0x3000>, @@ -2467,7 +2475,7 @@ power-domains = <&gcc PCIE_1_PHY_GDSC>; - #clock-cells = <0>; + #clock-cells = <1>; clock-output-names = "pcie1_pipe_clk"; #phy-cells = <0>; @@ -2626,6 +2634,7 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + #cooling-cells = <2>; status = "disabled"; @@ -3309,6 +3318,30 @@ }; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8650-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8650-camcc"; + reg = <0 0x0ade0000 0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,sm8650-mdss"; reg = <0 0x0ae00000 0 0x1000>; @@ -3675,6 +3708,7 @@ reg = <1>; mdss_dp0_out: endpoint { + remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; }; @@ -3750,6 +3784,8 @@ #clock-cells = <1>; #phy-cells = <1>; + orientation-switch; + status = "disabled"; ports { @@ -3767,6 +3803,7 @@ reg = <1>; usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; }; }; @@ -3774,6 +3811,7 @@ reg = <2>; usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; }; }; }; @@ -3864,6 +3902,7 @@ reg = <1>; usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; }; }; @@ -4982,12 +5021,14 @@ <0 0x25400000 0 0x200000>, <0 0x25200000 0 0x200000>, <0 0x25600000 0 0x200000>, - <0 0x25800000 0 0x200000>; + <0 0x25800000 0 0x200000>, + <0 0x25a00000 0 0x200000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", "llcc3_base", - "llcc_broadcast_base"; + "llcc_broadcast_base", + "llcc_broadcast_and_base"; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; }; @@ -5328,8 +5369,6 @@ thermal-zones { aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 0>; trips { @@ -5348,8 +5387,6 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 1>; trips { @@ -5368,8 +5405,6 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 2>; trips { @@ -5388,8 +5423,6 @@ }; cpuss2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 3>; trips { @@ -5408,8 +5441,6 @@ }; cpuss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 4>; trips { @@ -5428,8 +5459,6 @@ }; cpu2-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 5>; trips { @@ -5454,8 +5483,6 @@ }; cpu2-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 6>; trips { @@ -5480,8 +5507,6 @@ }; cpu3-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 7>; trips { @@ -5506,8 +5531,6 @@ }; cpu3-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 8>; trips { @@ -5532,8 +5555,6 @@ }; cpu4-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 9>; trips { @@ -5558,8 +5579,6 @@ }; cpu4-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 10>; trips { @@ -5584,8 +5603,6 @@ }; cpu5-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 11>; trips { @@ -5610,8 +5627,6 @@ }; cpu5-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 12>; trips { @@ -5636,8 +5651,6 @@ }; cpu6-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 13>; trips { @@ -5662,8 +5675,6 @@ }; cpu6-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens0 14>; trips { @@ -5688,8 +5699,6 @@ }; aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 0>; trips { @@ -5708,8 +5717,6 @@ }; cpu7-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 1>; trips { @@ -5734,8 +5741,6 @@ }; cpu7-middle-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 2>; trips { @@ -5760,8 +5765,6 @@ }; cpu7-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 3>; trips { @@ -5786,8 +5789,6 @@ }; cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 4>; trips { @@ -5812,8 +5813,6 @@ }; cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 5>; trips { @@ -5839,7 +5838,7 @@ nsphvx0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 6>; trips { @@ -5859,7 +5858,7 @@ nsphvx1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 7>; trips { @@ -5879,7 +5878,7 @@ nsphmx0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 8>; trips { @@ -5899,7 +5898,7 @@ nsphmx1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 9>; trips { @@ -5919,7 +5918,7 @@ nsphmx2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 10>; trips { @@ -5939,7 +5938,7 @@ nsphmx3-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 11>; trips { @@ -5959,7 +5958,7 @@ video-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 12>; trips { @@ -5979,7 +5978,7 @@ ddr-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens1 13>; trips { @@ -5998,8 +5997,6 @@ }; camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 14>; trips { @@ -6018,8 +6015,6 @@ }; camera1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens1 15>; trips { @@ -6038,8 +6033,6 @@ }; aoss2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 0>; trips { @@ -6059,19 +6052,32 @@ gpuss0-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 1>; + cooling-maps { + map0 { + trip = <&gpu0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu0_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss0-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6079,19 +6085,32 @@ gpuss1-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 2>; + cooling-maps { + map0 { + trip = <&gpu1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu1_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss1-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6099,19 +6118,32 @@ gpuss2-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 3>; + cooling-maps { + map0 { + trip = <&gpu2_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu2_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss2-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6119,19 +6151,32 @@ gpuss3-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + cooling-maps { + map0 { + trip = <&gpu3_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu3_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss3-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6139,19 +6184,32 @@ gpuss4-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 5>; + cooling-maps { + map0 { + trip = <&gpu4_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu4_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss4-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6159,19 +6217,32 @@ gpuss5-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + cooling-maps { + map0 { + trip = <&gpu5_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu5_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss5-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6179,19 +6250,32 @@ gpuss6-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + cooling-maps { + map0 { + trip = <&gpu6_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu6_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss6-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; @@ -6199,27 +6283,38 @@ gpuss7-thermal { polling-delay-passive = <10>; - polling-delay = <0>; + thermal-sensors = <&tsens2 8>; + cooling-maps { + map0 { + trip = <&gpu7_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpu7_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { temperature = <90000>; - hysteresis = <2000>; + hysteresis = <1000>; type = "hot"; }; - gpuss7-critical { + trip-point2 { temperature = <110000>; - hysteresis = <0>; + hysteresis = <1000>; type = "critical"; }; }; }; modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 9>; trips { @@ -6238,8 +6333,6 @@ }; modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 10>; trips { @@ -6258,8 +6351,6 @@ }; modem2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 11>; trips { @@ -6278,8 +6369,6 @@ }; modem3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; thermal-sensors = <&tsens2 12>; trips { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts new file mode 100644 index 000000000000..7fb980fcb307 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Xilin Wu <wuxilin123@gmail.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> + +#include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" + +/ { + model = "ASUS Vivobook S 15"; + compatible = "asus,vivobook-s15", "qcom,x1e80100"; + chassis-type = "laptop"; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + /* Left-side port, closer to the screen */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + }; + }; + + /* Left-side port, farther from the screen */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + /* PS8830 USB4 Retimer? @ 0x8 */ +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + /* PS8830 USB4 Retimer? @ 0x8 */ +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + /* EC? @ 0x5b, 0x76 */ +}; + +&i2c7 { + clock-frequency = <400000>; + status = "okay"; + + /* PS8830 USB4 Retimer? @ 0x8 */ +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcadsp8380.mbn", + "qcom/x1e80100/ASUSTeK/vivobook-s15/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qccdsp8380.mbn", + "qcom/x1e80100/ASUSTeK/vivobook-s15/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status = "disabled"; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie6a_default: pcie2a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + orientation-switch; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + orientation-switch; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index c5c2895b37c7..96f51850644b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -49,6 +49,113 @@ stdout-path = "serial0:115200n8"; }; + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + /* Left-side rear port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + }; + }; + + /* Left-side front port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + }; + }; + + /* Right-side port */ + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + sound { compatible = "qcom,x1e80100-sndcard"; model = "X1E80100-CRD"; @@ -164,6 +271,20 @@ regulator-always-on; regulator-boot-on; }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&nvme_reg_en>; + }; }; &apps_rsc { @@ -646,11 +767,19 @@ }; &pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie6a_default>; + status = "okay"; }; &pcie6a_phy { - vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-phy-supply = <&vreg_l1d_0p8>; vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; @@ -795,6 +924,36 @@ bias-disable; }; + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie6a_default: pcie2a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + tpad_default: tpad-default-state { pins = "gpio3"; function = "gpio"; @@ -831,8 +990,8 @@ }; &usb_1_ss0_hsphy { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_0_eusb2_repeater>; @@ -840,6 +999,9 @@ }; &usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + status = "okay"; }; @@ -849,12 +1011,19 @@ &usb_1_ss0_dwc3 { dr_mode = "host"; - usb-role-switch; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; }; &usb_1_ss1_hsphy { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_1_eusb2_repeater>; @@ -862,6 +1031,9 @@ }; &usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + status = "okay"; }; @@ -871,12 +1043,19 @@ &usb_1_ss1_dwc3 { dr_mode = "host"; - usb-role-switch; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; }; &usb_1_ss2_hsphy { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_2_eusb2_repeater>; @@ -884,6 +1063,9 @@ }; &usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + status = "okay"; }; @@ -893,5 +1075,12 @@ &usb_1_ss2_dwc3 { dr_mode = "host"; - usb-role-switch; +}; + +&usb_1_ss2_dwc3_hs { + remote-endpoint = <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint = <&pmic_glink_ss2_ss_in>; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi index 04301f772fbd..e34e70922cd3 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi @@ -3,10 +3,477 @@ * Copyright (c) 2024, Linaro Limited */ +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/spmi/spmi.h> / { + thermal-zones { + pm8550-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8550_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550ve-2-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8550ve_2_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pmc8380-3-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmc8380_3_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pmc8380-4-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmc8380_4_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pmc8380-5-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmc8380_5_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pmc8380-6-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmc8380_6_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550ve-8-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8550ve_8_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550ve-9-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8550ve_9_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8010-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8010_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + /* PMK8380 */ + pmk8550: pmic@0 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8550_pon: pon@1300 { + compatible = "qcom,pmk8350-pon"; + reg = <0x1300>, <0x800>; + reg-names = "hlos", "pbs"; + + pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_POWER>; + }; + + pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status = "disabled"; + }; + }; + + pmk8550_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + /* Not yet sure what blocks access */ + status = "reserved"; + }; + + pmk8550_sdam_2: nvram@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7100 0x100>; + + reboot_reason: reboot-reason@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + }; + + pmk8550_gpios: gpio@8800 { + compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio"; + reg = <0xb800>; + gpio-controller; + gpio-ranges = <&pmk8550_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* PMC8380C */ + pm8550: pmic@1 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550_gpios: gpio@8800 { + compatible = "qcom,pm8550-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm8550_flash: led-controller@ee00 { + compatible = "qcom,pm8550-flash-led", "qcom,spmi-flash-led"; + reg = <0xee00>; + status = "disabled"; + }; + + pm8550_pwm: pwm { + compatible = "qcom,pm8550-pwm", "qcom,pm8350c-pwm"; + #pwm-cells = <2>; + + status = "disabled"; + }; + }; + + /* PMC8380VE */ + pm8550ve_2: pmic@2 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550ve_2_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550ve_2_gpios: gpio@8800 { + compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550ve_2_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* PMC8380 is actually not a PM8550 series rebrand */ + pmc8380_3: pmic@3 { + compatible = "qcom,pmc8380", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8380_3_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmc8380_3_gpios: gpio@8800 { + compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8380_3_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmc8380_4: pmic@4 { + compatible = "qcom,pmc8380", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8380_4_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmc8380_4_gpios: gpio@8800 { + compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8380_4_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmc8380_5: pmic@5 { + compatible = "qcom,pmc8380", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8380_5_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmc8380_5_gpios: gpio@8800 { + compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8380_5_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmc8380_6: pmic@6 { + compatible = "qcom,pmc8380", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmc8380_6_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmc8380_6_gpios: gpio@8800 { + compatible = "qcom,pmc8380-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmc8380_6_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* PMC8380VE */ + pm8550ve_8: pmic@8 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x8 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550ve_8_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550ve_8_gpios: gpio@8800 { + compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550ve_8_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + /* PMC8380VE */ + pm8550ve_9: pmic@9 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x9 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550ve_9_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550ve_9_gpios: gpio@8800 { + compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550ve_9_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8010: pmic@c { + compatible = "qcom,pm8010", "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010_temp_alarm: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; }; &spmi_bus1 { @@ -48,4 +515,19 @@ #phy-cells = <0>; }; }; + + smb2360_3: pmic@c { + compatible = "qcom,smb2360", "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + smb2360_3_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2360-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 2061fbe7b75a..72a4f4138616 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -19,10 +19,200 @@ serial0 = &uart21; }; + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + chosen { stdout-path = "serial0:115200n8"; }; + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + }; + }; + + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-QCP"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, + <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -50,6 +240,20 @@ regulator-always-on; regulator-boot-on; }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&nvme_reg_en>; + }; }; &apps_rsc { @@ -402,6 +606,16 @@ }; }; +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + &mdss { status = "okay"; }; @@ -457,11 +671,19 @@ }; &pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie6a_default>; + status = "okay"; }; &pcie6a_phy { - vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-phy-supply = <&vreg_l1d_0p8>; vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; @@ -493,6 +715,10 @@ status = "okay"; }; +&smb2360_3 { + status = "okay"; +}; + &smb2360_0_eusb2_repeater { vdd18-supply = <&vreg_l3d_1p8>; vdd3-supply = <&vreg_l2b_3p0>; @@ -508,6 +734,57 @@ vdd3-supply = <&vreg_l8b_3p0>; }; +&swr0 { + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + status = "okay"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + #sound-dai-cells = <0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + #sound-dai-cells = <0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + &tlmm { gpio-reserved-ranges = <33 3>, /* Unused */ <44 4>, /* SPI (TPM) */ @@ -519,6 +796,44 @@ drive-strength = <16>; bias-disable; }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie6a_default: pcie2a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; }; &uart21 { @@ -527,8 +842,8 @@ }; &usb_1_ss0_hsphy { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_0_eusb2_repeater>; @@ -536,6 +851,9 @@ }; &usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + status = "okay"; }; @@ -545,12 +863,19 @@ &usb_1_ss0_dwc3 { dr_mode = "host"; - usb-role-switch; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; }; &usb_1_ss1_hsphy { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_1_eusb2_repeater>; @@ -558,6 +883,9 @@ }; &usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + status = "okay"; }; @@ -567,12 +895,19 @@ &usb_1_ss1_dwc3 { dr_mode = "host"; - usb-role-switch; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; }; &usb_1_ss2_hsphy { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; phys = <&smb2360_2_eusb2_repeater>; @@ -580,6 +915,9 @@ }; &usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + status = "okay"; }; @@ -589,5 +927,12 @@ &usb_1_ss2_dwc3 { dr_mode = "host"; - usb-role-switch; +}; + +&usb_1_ss2_dwc3_hs { + remote-endpoint = <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint = <&pmic_glink_ss2_ss_in>; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 5f90a0b3c016..7bca5fcd7d52 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> #include <dt-bindings/clock/qcom,x1e80100-gcc.h> +#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> #include <dt-bindings/clock/qcom,x1e80100-tcsr.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/interconnect/qcom,icc.h> @@ -2505,6 +2506,66 @@ }; }; + tsens0: thermal-sensor@c271000 { + compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; + reg = <0 0x0c271000 0 0x1000>, + <0 0x0c222000 0 0x1000>; + + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c272000 { + compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; + reg = <0 0x0c272000 0 0x1000>, + <0 0x0c223000 0 0x1000>; + + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c273000 { + compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; + reg = <0 0x0c273000 0 0x1000>, + <0 0x0c224000 0 0x1000>; + + interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c274000 { + compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; + reg = <0 0x0c274000 0 0x1000>, + <0 0x0c225000 0 0x1000>; + + interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + usb_1_ss0_hsphy: phy@fd3000 { compatible = "qcom,x1e80100-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy"; @@ -2543,6 +2604,34 @@ #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss0_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; }; usb_1_ss1_hsphy: phy@fd9000 { @@ -2583,6 +2672,34 @@ #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss1_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp1_out>; + }; + }; + }; }; usb_1_ss2_hsphy: phy@fde000 { @@ -2623,6 +2740,34 @@ #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_ss2_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp2_out>; + }; + }; + }; }; cnoc_main: interconnect@1500000 { @@ -2737,15 +2882,17 @@ device_type = "pci"; compatible = "qcom,pcie-x1e80100"; reg = <0 0x01bf8000 0 0x3000>, - <0 0x70000000 0 0xf1d>, - <0 0x70000f20 0 0xa8>, + <0 0x70000000 0 0xf20>, + <0 0x70000f40 0 0xa8>, <0 0x70001000 0 0x1000>, - <0 0x70100000 0 0x100000>; + <0 0x70100000 0 0x100000>, + <0 0x01bfb000 0 0x1000>; reg-names = "parf", "dbi", "elbi", "atu", - "config"; + "config", + "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, @@ -2985,6 +3132,200 @@ #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43050c01", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + + zap-shader { + memory-region = <&gpu_microcode_mem>; + firmware-name = "qcom/gen70500_zap.mbn"; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + opp-peak-kBps = <16500000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + opp-peak-kBps = <14398438>; + }; + + opp-925000000 { + opp-hz = /bits/ 64 <925000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + opp-peak-kBps = <14398438>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-peak-kBps = <12449219>; + }; + + opp-744000000 { + opp-hz = /bits/ 64 <744000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + opp-peak-kBps = <10687500>; + }; + + opp-687000000 { + opp-hz = /bits/ 64 <687000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <8171875>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-peak-kBps = <6074219>; + }; + + opp-390000000 { + opp-hz = /bits/ 64 <390000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-peak-kBps = <3000000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + opp-peak-kBps = <2136719>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-220000000 { + opp-hz = /bits/ 64 <220000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,x1e80100-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + gem_noc: interconnect@26400000 { compatible = "qcom,x1e80100-gem-noc"; reg = <0 0x26400000 0 0x311200>; @@ -3445,8 +3786,23 @@ dma-coherent; - port { - usb_1_ss2_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3514,8 +3870,15 @@ phy-names = "usb2-phy"; maximum-speed = "high-speed"; - port { - usb_2_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_2_dwc3_hs: endpoint { + }; }; }; }; @@ -3590,8 +3953,23 @@ dma-coherent; - port { - usb_1_ss0_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3673,8 +4051,23 @@ dma-coherent; - port { - usb_1_ss1_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; + }; }; }; }; @@ -3860,6 +4253,7 @@ reg = <1>; mdss_dp0_out: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; }; }; }; @@ -3942,6 +4336,7 @@ reg = <1>; mdss_dp1_out: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; }; }; }; @@ -4021,6 +4416,10 @@ port@1 { reg = <1>; + + mdss_dp2_out: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; + }; }; }; @@ -5155,6 +5554,129 @@ }; }; + pmu@24091000 { + compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0 0x24091000 0 0x1000>; + + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <800000>; + }; + + opp-1 { + opp-peak-kBps = <2188000>; + }; + + opp-2 { + opp-peak-kBps = <3072000>; + }; + + opp-3 { + opp-peak-kBps = <6220800>; + }; + + opp-4 { + opp-peak-kBps = <6835200>; + }; + + opp-5 { + opp-peak-kBps = <8371200>; + }; + + opp-6 { + opp-peak-kBps = <10944000>; + }; + + opp-7 { + opp-peak-kBps = <12748800>; + }; + + opp-8 { + opp-peak-kBps = <14745600>; + }; + + opp-9 { + opp-peak-kBps = <16896000>; + }; + }; + }; + + /* cluster0 */ + pmu@240b3400 { + compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b3400 0 0x600>; + + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <4800000>; + }; + + opp-1 { + opp-peak-kBps = <7464000>; + }; + + opp-2 { + opp-peak-kBps = <9600000>; + }; + + opp-3 { + opp-peak-kBps = <12896000>; + }; + + opp-4 { + opp-peak-kBps = <14928000>; + }; + + opp-5 { + opp-peak-kBps = <17064000>; + }; + }; + }; + + /* cluster2 */ + pmu@240b5400 { + compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b5400 0 0x600>; + + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + + /* cluster1 */ + pmu@240b6400 { + compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b6400 0 0x600>; + + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + system-cache-controller@25000000 { compatible = "qcom,x1e80100-llcc"; reg = <0 0x25000000 0 0x200000>, @@ -5224,6 +5746,55 @@ label = "lpass"; qcom,remote-pid = <2>; + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1063 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1064 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1065 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1066 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x80>, + <&apps_smmu 0x1067 0x0>; + dma-coherent; + }; + }; + gpr { compatible = "qcom,gpr"; qcom,glink-channels = "adsp_apps"; @@ -5313,6 +5884,101 @@ label = "cdsp"; qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0c01 0x20>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0c02 0x20>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0c03 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0c04 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0c05 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0c06 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x0c07 0x20>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x0c08 0x20>; + dma-coherent; + }; + + /* note: compute-cb@9 is secure */ + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + iommus = <&apps_smmu 0x0c0c 0x20>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&apps_smmu 0x0c0d 0x20>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x0c0e 0x20>; + dma-coherent; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x0c0f 0x20>; + dma-coherent; + }; + }; }; }; }; @@ -5325,4 +5991,1158 @@ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; + + thermal-zones { + aoss0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu0-0-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-0-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-1-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-1-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-2-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-2-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-3-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-3-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss0-top-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss0-btm-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mem-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + mem-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens0 12>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + aoss1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu1-0-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-0-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-1-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-1-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-2-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-2-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-3-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-3-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens1 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss1-top-thermal { + thermal-sensors = <&tsens1 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-btm-thermal { + thermal-sensors = <&tsens1 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss2-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu2-0-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-0-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-1-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-1-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-2-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-2-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-3-top-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-3-btm-thermal { + polling-delay-passive = <250>; + + thermal-sensors = <&tsens2 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss2-top-thermal { + thermal-sensors = <&tsens2 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss2-btm-thermal { + thermal-sensors = <&tsens2 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss3-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp0-thermal { + thermal-sensors = <&tsens3 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsp0-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp1-thermal { + thermal-sensors = <&tsens3 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsp1-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp2-thermal { + thermal-sensors = <&tsens3 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsp2-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp3-thermal { + thermal-sensors = <&tsens3 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsp3-critical { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 5>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 6>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 7>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-3-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 8>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-4-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 9>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-5-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 10>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-6-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 11>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-7-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens3 12>; + + trips { + trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + trip-point2 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera0-thermal { + thermal-sensors = <&tsens3 13>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + camera0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera1-thermal { + thermal-sensors = <&tsens3 14>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + camera0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; }; diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 1bb51a058872..46369edfc07a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -827,6 +827,14 @@ config SM_CAMCC_8550 Support for the camera clock controller on SM8550 devices. Say Y if you want to support camera devices and camera functionality. +config SM_CAMCC_8650 + tristate "SM8650 Camera Clock Controller" + depends on ARM64 || COMPILE_TEST + select SM_GCC_8650 + help + Support for the camera clock controller on SM8650 devices. + Say Y if you want to support camera devices and camera functionality. + config SM_DISPCC_6115 tristate "SM6115 Display Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index dec5b6db6860..28bffa1eb8dd 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -109,6 +109,7 @@ obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o +obj-$(CONFIG_SM_CAMCC_8650) += camcc-sm8650.o obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o diff --git a/drivers/clk/qcom/camcc-sm8650.c b/drivers/clk/qcom/camcc-sm8650.c new file mode 100644 index 000000000000..a37e52a67ed4 --- /dev/null +++ b/drivers/clk/qcom/camcc-sm8650.c @@ -0,0 +1,3591 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,sm8650-camcc.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + DT_IFACE, + DT_BI_TCXO, + DT_BI_TCXO_AO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_BI_TCXO_AO, + P_CAM_CC_PLL0_OUT_EVEN, + P_CAM_CC_PLL0_OUT_MAIN, + P_CAM_CC_PLL0_OUT_ODD, + P_CAM_CC_PLL1_OUT_EVEN, + P_CAM_CC_PLL2_OUT_EVEN, + P_CAM_CC_PLL2_OUT_MAIN, + P_CAM_CC_PLL3_OUT_EVEN, + P_CAM_CC_PLL4_OUT_EVEN, + P_CAM_CC_PLL5_OUT_EVEN, + P_CAM_CC_PLL6_OUT_EVEN, + P_CAM_CC_PLL7_OUT_EVEN, + P_CAM_CC_PLL8_OUT_EVEN, + P_CAM_CC_PLL9_OUT_EVEN, + P_CAM_CC_PLL9_OUT_ODD, + P_CAM_CC_PLL10_OUT_EVEN, + P_SLEEP_CLK, +}; + +static const struct pll_vco lucid_ole_vco[] = { + { 249600000, 2300000000, 0 }, +}; + +static const struct pll_vco rivian_ole_vco[] = { + { 777000000, 1285000000, 0 }, +}; + +static const struct alpha_pll_config cam_cc_pll0_config = { + .l = 0x3e, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00008400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { + .offset = 0x0, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll0_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { + .offset = 0x0, + .post_div_shift = 14, + .post_div_table = post_div_table_cam_cc_pll0_out_odd, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll0_out_odd", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll1_config = { + .l = 0x31, + .alpha = 0x7aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll1", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { + .offset = 0x1000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll1_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll1_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll2_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x10000030, + .config_ctl_hi_val = 0x80890263, + .config_ctl_hi1_val = 0x00000217, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000000, +}; + +static struct clk_alpha_pll cam_cc_pll2 = { + .offset = 0x2000, + .vco_table = rivian_ole_vco, + .num_vco = ARRAY_SIZE(rivian_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll2", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_rivian_evo_ops, + }, + }, +}; + +static const struct alpha_pll_config cam_cc_pll3_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll3 = { + .offset = 0x3000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { + .offset = 0x3000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll3_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll3_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll4_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll4 = { + .offset = 0x4000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll4", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { + .offset = 0x4000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll4_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll4_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll4.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll5_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll5 = { + .offset = 0x5000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll5", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { + .offset = 0x5000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll5_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll5_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll5.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll6_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll6 = { + .offset = 0x6000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll6", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { + .offset = 0x6000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll6_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll6_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll7_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll7 = { + .offset = 0x7000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll7", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = { + .offset = 0x7000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll7_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll7_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll7.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll8_config = { + .l = 0x14, + .alpha = 0xd555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll8 = { + .offset = 0x8000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll8", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = { + .offset = 0x8000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll8_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll8_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll8.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll9_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00008400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll9 = { + .offset = 0x9000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll9", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll9_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll9_out_even = { + .offset = 0x9000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll9_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll9_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll9.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll9_out_odd[] = { + { 0x2, 3 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll9_out_odd = { + .offset = 0x9000, + .post_div_shift = 14, + .post_div_table = post_div_table_cam_cc_pll9_out_odd, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_odd), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll9_out_odd", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll9.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct alpha_pll_config cam_cc_pll10_config = { + .l = 0x30, + .alpha = 0x8aaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + +static struct clk_alpha_pll cam_cc_pll10 = { + .offset = 0xa000, + .vco_table = lucid_ole_vco, + .num_vco = ARRAY_SIZE(lucid_ole_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr = { + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll10", + .parent_data = &(const struct clk_parent_data) { + .index = DT_BI_TCXO, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_cam_cc_pll10_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv cam_cc_pll10_out_even = { + .offset = 0xa000, + .post_div_shift = 10, + .post_div_table = post_div_table_cam_cc_pll10_out_even, + .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll10_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_pll10_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll10.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, + }, +}; + +static const struct parent_map cam_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL0_OUT_MAIN, 1 }, + { P_CAM_CC_PLL0_OUT_EVEN, 2 }, + { P_CAM_CC_PLL0_OUT_ODD, 3 }, + { P_CAM_CC_PLL9_OUT_ODD, 4 }, + { P_CAM_CC_PLL9_OUT_EVEN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll0.clkr.hw }, + { .hw = &cam_cc_pll0_out_even.clkr.hw }, + { .hw = &cam_cc_pll0_out_odd.clkr.hw }, + { .hw = &cam_cc_pll9_out_odd.clkr.hw }, + { .hw = &cam_cc_pll9_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL2_OUT_EVEN, 3 }, + { P_CAM_CC_PLL2_OUT_MAIN, 5 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll2.clkr.hw }, + { .hw = &cam_cc_pll2.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL8_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll8_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL3_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll3_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL4_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_4[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll4_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL5_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_5[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll5_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_6[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL1_OUT_EVEN, 4 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_6[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll1_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_7[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL6_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_7[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll6_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_8[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL7_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_8[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll7_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_9[] = { + { P_BI_TCXO, 0 }, + { P_CAM_CC_PLL10_OUT_EVEN, 6 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_9[] = { + { .index = DT_BI_TCXO }, + { .hw = &cam_cc_pll10_out_even.clkr.hw }, +}; + +static const struct parent_map cam_cc_parent_map_10[] = { + { P_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_10[] = { + { .index = DT_SLEEP_CLK }, +}; + +static const struct parent_map cam_cc_parent_map_11_ao[] = { + { P_BI_TCXO_AO, 0 }, +}; + +static const struct clk_parent_data cam_cc_parent_data_11_ao[] = { + { .index = DT_BI_TCXO_AO }, +}; + +static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(400000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_bps_clk_src = { + .cmd_rcgr = 0x10050, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_2, + .freq_tbl = ftbl_cam_cc_bps_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_clk_src", + .parent_data = cam_cc_parent_data_2, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_camnoc_axi_rt_clk_src[] = { + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_camnoc_axi_rt_clk_src = { + .cmd_rcgr = 0x1325c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_camnoc_axi_rt_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_rt_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cci_0_clk_src = { + .cmd_rcgr = 0x131cc, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_1_clk_src = { + .cmd_rcgr = 0x131e8, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_cci_2_clk_src = { + .cmd_rcgr = 0x13204, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cci_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_2_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { + .cmd_rcgr = 0x1104c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cphy_rx_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = { + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_cre_clk_src = { + .cmd_rcgr = 0x13144, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_cre_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cre_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { + .cmd_rcgr = 0x150e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { + .cmd_rcgr = 0x15104, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { + .cmd_rcgr = 0x15124, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi2phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { + .cmd_rcgr = 0x15144, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi3phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { + .cmd_rcgr = 0x15164, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { + .cmd_rcgr = 0x15184, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi5phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi6phytimer_clk_src = { + .cmd_rcgr = 0x151a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi6phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_csi7phytimer_clk_src = { + .cmd_rcgr = 0x151c4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi7phytimer_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_csid_clk_src = { + .cmd_rcgr = 0x13238, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { + .cmd_rcgr = 0x10018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_fast_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_icp_clk_src = { + .cmd_rcgr = 0x131a4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_icp_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(466000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_0_clk_src = { + .cmd_rcgr = 0x11018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_3, + .freq_tbl = ftbl_cam_cc_ife_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_clk_src", + .parent_data = cam_cc_parent_data_3, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(466000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_1_clk_src = { + .cmd_rcgr = 0x12018, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_4, + .freq_tbl = ftbl_cam_cc_ife_1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_clk_src", + .parent_data = cam_cc_parent_data_4, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(466000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ife_2_clk_src = { + .cmd_rcgr = 0x12068, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_5, + .freq_tbl = ftbl_cam_cc_ife_2_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_clk_src", + .parent_data = cam_cc_parent_data_5, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_clk_src = { + .cmd_rcgr = 0x13000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { + .cmd_rcgr = 0x13028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_csid_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { + F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { + .cmd_rcgr = 0x10094, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_6, + .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_clk_src", + .parent_data = cam_cc_parent_data_6, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), + F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_jpeg_clk_src = { + .cmd_rcgr = 0x13168, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_jpeg_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_CAM_CC_PLL2_OUT_EVEN, 10, 1, 4), + F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_mclk0_clk_src = { + .cmd_rcgr = 0x15000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk0_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk1_clk_src = { + .cmd_rcgr = 0x1501c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk1_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk2_clk_src = { + .cmd_rcgr = 0x15038, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk2_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk3_clk_src = { + .cmd_rcgr = 0x15054, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk3_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk4_clk_src = { + .cmd_rcgr = 0x15070, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk4_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk5_clk_src = { + .cmd_rcgr = 0x1508c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk5_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk6_clk_src = { + .cmd_rcgr = 0x150a8, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk6_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 cam_cc_mclk7_clk_src = { + .cmd_rcgr = 0x150c4, + .mnd_width = 8, + .hid_width = 5, + .parent_map = cam_cc_parent_map_1, + .freq_tbl = ftbl_cam_cc_mclk0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk7_clk_src", + .parent_data = cam_cc_parent_data_1, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), + F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { + .cmd_rcgr = 0x1329c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = { + F(466000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sfe_0_clk_src = { + .cmd_rcgr = 0x1306c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_7, + .freq_tbl = ftbl_cam_cc_sfe_0_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_clk_src", + .parent_data = cam_cc_parent_data_7, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = { + F(466000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sfe_1_clk_src = { + .cmd_rcgr = 0x130bc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_8, + .freq_tbl = ftbl_cam_cc_sfe_1_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_clk_src", + .parent_data = cam_cc_parent_data_8, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sfe_2_clk_src[] = { + F(466000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), + F(594000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), + F(675000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), + F(785000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sfe_2_clk_src = { + .cmd_rcgr = 0x1310c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_9, + .freq_tbl = ftbl_cam_cc_sfe_2_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_2_clk_src", + .parent_data = cam_cc_parent_data_9, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_9), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { + F(32000, P_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_sleep_clk_src = { + .cmd_rcgr = 0x132f0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_10, + .freq_tbl = ftbl_cam_cc_sleep_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sleep_clk_src", + .parent_data = cam_cc_parent_data_10, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_10), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { + .cmd_rcgr = 0x10034, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_0, + .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_slow_ahb_clk_src", + .parent_data = cam_cc_parent_data_0, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO_AO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_xo_clk_src = { + .cmd_rcgr = 0x132d4, + .mnd_width = 0, + .hid_width = 5, + .parent_map = cam_cc_parent_map_11_ao, + .freq_tbl = ftbl_cam_cc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "cam_cc_xo_clk_src", + .parent_data = cam_cc_parent_data_11_ao, + .num_parents = ARRAY_SIZE(cam_cc_parent_data_11_ao), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch cam_cc_bps_ahb_clk = { + .halt_reg = 0x1004c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1004c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_clk = { + .halt_reg = 0x10068, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10068, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_bps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_fast_ahb_clk = { + .halt_reg = 0x10030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_bps_shift_clk = { + .halt_reg = 0x10078, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x10078, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_bps_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_nrt_clk = { + .halt_reg = 0x13284, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13284, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_nrt_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_axi_rt_clk = { + .halt_reg = 0x13274, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13274, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_axi_rt_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_camnoc_axi_rt_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { + .halt_reg = 0x13290, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13290, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_dcd_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_camnoc_xo_clk = { + .halt_reg = 0x13294, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13294, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_camnoc_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_0_clk = { + .halt_reg = 0x131e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131e4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_1_clk = { + .halt_reg = 0x13200, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13200, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cci_2_clk = { + .halt_reg = 0x1321c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1321c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cci_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cci_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_core_ahb_clk = { + .halt_reg = 0x132d0, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x132d0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_core_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ahb_clk = { + .halt_reg = 0x13220, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13220, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_bps_clk = { + .halt_reg = 0x10074, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10074, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_bps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_bps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_cre_clk = { + .halt_reg = 0x13160, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13160, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_cre_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cre_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_fast_ahb_clk = { + .halt_reg = 0x1322c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1322c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_0_clk = { + .halt_reg = 0x1103c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1103c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_1_clk = { + .halt_reg = 0x1203c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1203c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_2_clk = { + .halt_reg = 0x1208c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1208c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ife_lite_clk = { + .halt_reg = 0x13024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13024, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_ipe_nps_clk = { + .halt_reg = 0x100b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_ipe_nps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sbi_clk = { + .halt_reg = 0x10104, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10104, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sbi_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sfe_0_clk = { + .halt_reg = 0x13090, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13090, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sfe_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sfe_1_clk = { + .halt_reg = 0x130e0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130e0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sfe_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cpas_sfe_2_clk = { + .halt_reg = 0x13130, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13130, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cpas_sfe_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cre_ahb_clk = { + .halt_reg = 0x13164, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13164, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cre_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_cre_clk = { + .halt_reg = 0x1315c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1315c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_cre_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cre_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi0phytimer_clk = { + .halt_reg = 0x150f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi0phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi0phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi1phytimer_clk = { + .halt_reg = 0x1511c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1511c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi1phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi1phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi2phytimer_clk = { + .halt_reg = 0x1513c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1513c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi2phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi2phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi3phytimer_clk = { + .halt_reg = 0x1515c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1515c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi3phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi3phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi4phytimer_clk = { + .halt_reg = 0x1517c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1517c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi4phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi4phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi5phytimer_clk = { + .halt_reg = 0x1519c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1519c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi5phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi5phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi6phytimer_clk = { + .halt_reg = 0x151bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi6phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi6phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csi7phytimer_clk = { + .halt_reg = 0x151dc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csi7phytimer_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csi7phytimer_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_clk = { + .halt_reg = 0x13250, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13250, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csid_csiphy_rx_clk = { + .halt_reg = 0x15100, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15100, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csid_csiphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy0_clk = { + .halt_reg = 0x150fc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150fc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy1_clk = { + .halt_reg = 0x15120, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15120, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy2_clk = { + .halt_reg = 0x15140, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15140, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy3_clk = { + .halt_reg = 0x15160, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15160, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy3_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy4_clk = { + .halt_reg = 0x15180, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15180, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy4_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy5_clk = { + .halt_reg = 0x151a0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151a0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy5_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy6_clk = { + .halt_reg = 0x151c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151c0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy6_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_csiphy7_clk = { + .halt_reg = 0x151e0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x151e0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_csiphy7_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_ahb_clk = { + .halt_reg = 0x131c8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131c8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_icp_clk = { + .halt_reg = 0x131bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x131bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_icp_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_icp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_clk = { + .halt_reg = 0x11030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { + .halt_reg = 0x11048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_0_shift_clk = { + .halt_reg = 0x11064, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x11064, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_0_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_clk = { + .halt_reg = 0x12030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12030, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { + .halt_reg = 0x12048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12048, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_1_shift_clk = { + .halt_reg = 0x1204c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1204c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_1_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_clk = { + .halt_reg = 0x12080, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12080, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_fast_ahb_clk = { + .halt_reg = 0x12098, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12098, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_2_shift_clk = { + .halt_reg = 0x1209c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1209c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_2_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_ahb_clk = { + .halt_reg = 0x13050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_clk = { + .halt_reg = 0x13018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { + .halt_reg = 0x1304c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1304c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_cphy_rx_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_cphy_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ife_lite_csid_clk = { + .halt_reg = 0x13040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13040, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ife_lite_csid_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_lite_csid_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_ahb_clk = { + .halt_reg = 0x100d0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100d0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_slow_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_clk = { + .halt_reg = 0x100ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100ac, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { + .halt_reg = 0x100d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100d4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_nps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_clk = { + .halt_reg = 0x100bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_pps_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ipe_nps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { + .halt_reg = 0x100d8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100d8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_pps_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_ipe_shift_clk = { + .halt_reg = 0x100dc, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x100dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_ipe_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_1_clk = { + .halt_reg = 0x1318c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1318c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_jpeg_clk = { + .halt_reg = 0x13180, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13180, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_jpeg_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_jpeg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk0_clk = { + .halt_reg = 0x15018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk1_clk = { + .halt_reg = 0x15034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15034, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk2_clk = { + .halt_reg = 0x15050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15050, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk3_clk = { + .halt_reg = 0x1506c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1506c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk3_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk4_clk = { + .halt_reg = 0x15088, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15088, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk4_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk5_clk = { + .halt_reg = 0x150a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk5_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk6_clk = { + .halt_reg = 0x150c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150c0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk6_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk6_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_mclk7_clk = { + .halt_reg = 0x150dc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x150dc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_mclk7_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_mclk7_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_clk = { + .halt_reg = 0x132b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x132b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_qdss_debug_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk = { + .halt_reg = 0x132b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x132b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_qdss_debug_xo_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_clk = { + .halt_reg = 0x100f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x100f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sbi_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_ife_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_fast_ahb_clk = { + .halt_reg = 0x10108, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x10108, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sbi_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sbi_shift_clk = { + .halt_reg = 0x1010c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1010c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sbi_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_0_clk = { + .halt_reg = 0x13084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13084, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = { + .halt_reg = 0x1309c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1309c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_0_shift_clk = { + .halt_reg = 0x130a0, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x130a0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_0_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_1_clk = { + .halt_reg = 0x130d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130d4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = { + .halt_reg = 0x130ec, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x130ec, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_1_shift_clk = { + .halt_reg = 0x130f0, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x130f0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_1_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_2_clk = { + .halt_reg = 0x13124, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13124, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_2_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_sfe_2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_2_fast_ahb_clk = { + .halt_reg = 0x1313c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1313c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_2_fast_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_fast_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_sfe_2_shift_clk = { + .halt_reg = 0x13140, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x13140, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_sfe_2_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_titan_top_shift_clk = { + .halt_reg = 0x1330c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x1330c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "cam_cc_titan_top_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc cam_cc_titan_top_gdsc = { + .gdscr = 0x132bc, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_titan_top_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_bps_gdsc = { + .gdscr = 0x10004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_bps_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_0_gdsc = { + .gdscr = 0x11004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_1_gdsc = { + .gdscr = 0x12004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ife_2_gdsc = { + .gdscr = 0x12054, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ife_2_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_ipe_0_gdsc = { + .gdscr = 0x10080, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_ipe_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_sbi_gdsc = { + .gdscr = 0x100e4, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_sbi_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_sfe_0_gdsc = { + .gdscr = 0x13058, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_sfe_0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_sfe_1_gdsc = { + .gdscr = 0x130a8, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_sfe_1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc cam_cc_sfe_2_gdsc = { + .gdscr = 0x130f8, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, + .pd = { + .name = "cam_cc_sfe_2_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .parent = &cam_cc_titan_top_gdsc.pd, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *cam_cc_sm8650_clocks[] = { + [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, + [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, + [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, + [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, + [CAM_CC_BPS_SHIFT_CLK] = &cam_cc_bps_shift_clk.clkr, + [CAM_CC_CAMNOC_AXI_NRT_CLK] = &cam_cc_camnoc_axi_nrt_clk.clkr, + [CAM_CC_CAMNOC_AXI_RT_CLK] = &cam_cc_camnoc_axi_rt_clk.clkr, + [CAM_CC_CAMNOC_AXI_RT_CLK_SRC] = &cam_cc_camnoc_axi_rt_clk_src.clkr, + [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, + [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, + [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, + [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, + [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, + [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, + [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, + [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, + [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, + [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, + [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, + [CAM_CC_CPAS_CRE_CLK] = &cam_cc_cpas_cre_clk.clkr, + [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, + [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, + [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, + [CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr, + [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, + [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, + [CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr, + [CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr, + [CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr, + [CAM_CC_CPAS_SFE_2_CLK] = &cam_cc_cpas_sfe_2_clk.clkr, + [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, + [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr, + [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr, + [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr, + [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, + [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, + [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, + [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, + [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, + [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, + [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, + [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, + [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, + [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, + [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, + [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, + [CAM_CC_CSI6PHYTIMER_CLK] = &cam_cc_csi6phytimer_clk.clkr, + [CAM_CC_CSI6PHYTIMER_CLK_SRC] = &cam_cc_csi6phytimer_clk_src.clkr, + [CAM_CC_CSI7PHYTIMER_CLK] = &cam_cc_csi7phytimer_clk.clkr, + [CAM_CC_CSI7PHYTIMER_CLK_SRC] = &cam_cc_csi7phytimer_clk_src.clkr, + [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, + [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, + [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, + [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, + [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, + [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, + [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, + [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, + [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, + [CAM_CC_CSIPHY6_CLK] = &cam_cc_csiphy6_clk.clkr, + [CAM_CC_CSIPHY7_CLK] = &cam_cc_csiphy7_clk.clkr, + [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, + [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, + [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, + [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, + [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, + [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, + [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, + [CAM_CC_IFE_0_SHIFT_CLK] = &cam_cc_ife_0_shift_clk.clkr, + [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, + [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, + [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, + [CAM_CC_IFE_1_SHIFT_CLK] = &cam_cc_ife_1_shift_clk.clkr, + [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr, + [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr, + [CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr, + [CAM_CC_IFE_2_SHIFT_CLK] = &cam_cc_ife_2_shift_clk.clkr, + [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, + [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, + [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, + [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, + [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, + [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, + [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, + [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, + [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, + [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, + [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, + [CAM_CC_IPE_SHIFT_CLK] = &cam_cc_ipe_shift_clk.clkr, + [CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr, + [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, + [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, + [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, + [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, + [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, + [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, + [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, + [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, + [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, + [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, + [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, + [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, + [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, + [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, + [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, + [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, + [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, + [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, + [CAM_CC_PLL0] = &cam_cc_pll0.clkr, + [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, + [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, + [CAM_CC_PLL1] = &cam_cc_pll1.clkr, + [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, + [CAM_CC_PLL2] = &cam_cc_pll2.clkr, + [CAM_CC_PLL3] = &cam_cc_pll3.clkr, + [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, + [CAM_CC_PLL4] = &cam_cc_pll4.clkr, + [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, + [CAM_CC_PLL5] = &cam_cc_pll5.clkr, + [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, + [CAM_CC_PLL6] = &cam_cc_pll6.clkr, + [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, + [CAM_CC_PLL7] = &cam_cc_pll7.clkr, + [CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr, + [CAM_CC_PLL8] = &cam_cc_pll8.clkr, + [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr, + [CAM_CC_PLL9] = &cam_cc_pll9.clkr, + [CAM_CC_PLL9_OUT_EVEN] = &cam_cc_pll9_out_even.clkr, + [CAM_CC_PLL9_OUT_ODD] = &cam_cc_pll9_out_odd.clkr, + [CAM_CC_PLL10] = &cam_cc_pll10.clkr, + [CAM_CC_PLL10_OUT_EVEN] = &cam_cc_pll10_out_even.clkr, + [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, + [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, + [CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr, + [CAM_CC_SBI_FAST_AHB_CLK] = &cam_cc_sbi_fast_ahb_clk.clkr, + [CAM_CC_SBI_SHIFT_CLK] = &cam_cc_sbi_shift_clk.clkr, + [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr, + [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr, + [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr, + [CAM_CC_SFE_0_SHIFT_CLK] = &cam_cc_sfe_0_shift_clk.clkr, + [CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr, + [CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr, + [CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr, + [CAM_CC_SFE_1_SHIFT_CLK] = &cam_cc_sfe_1_shift_clk.clkr, + [CAM_CC_SFE_2_CLK] = &cam_cc_sfe_2_clk.clkr, + [CAM_CC_SFE_2_CLK_SRC] = &cam_cc_sfe_2_clk_src.clkr, + [CAM_CC_SFE_2_FAST_AHB_CLK] = &cam_cc_sfe_2_fast_ahb_clk.clkr, + [CAM_CC_SFE_2_SHIFT_CLK] = &cam_cc_sfe_2_shift_clk.clkr, + [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, + [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, + [CAM_CC_TITAN_TOP_SHIFT_CLK] = &cam_cc_titan_top_shift_clk.clkr, + [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, +}; + +static struct gdsc *cam_cc_sm8650_gdscs[] = { + [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc, + [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc, + [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc, + [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc, + [CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc, + [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc, + [CAM_CC_SBI_GDSC] = &cam_cc_sbi_gdsc, + [CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc, + [CAM_CC_SFE_1_GDSC] = &cam_cc_sfe_1_gdsc, + [CAM_CC_SFE_2_GDSC] = &cam_cc_sfe_2_gdsc, +}; + +static const struct qcom_reset_map cam_cc_sm8650_resets[] = { + [CAM_CC_BPS_BCR] = { 0x10000 }, + [CAM_CC_DRV_BCR] = { 0x13310 }, + [CAM_CC_ICP_BCR] = { 0x131a0 }, + [CAM_CC_IFE_0_BCR] = { 0x11000 }, + [CAM_CC_IFE_1_BCR] = { 0x12000 }, + [CAM_CC_IFE_2_BCR] = { 0x12050 }, + [CAM_CC_IPE_0_BCR] = { 0x1007c }, + [CAM_CC_QDSS_DEBUG_BCR] = { 0x13298 }, + [CAM_CC_SBI_BCR] = { 0x100e0 }, + [CAM_CC_SFE_0_BCR] = { 0x13054 }, + [CAM_CC_SFE_1_BCR] = { 0x130a4 }, + [CAM_CC_SFE_2_BCR] = { 0x130f4 }, +}; + +static const struct regmap_config cam_cc_sm8650_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1603c, + .fast_io = true, +}; + +static struct qcom_cc_desc cam_cc_sm8650_desc = { + .config = &cam_cc_sm8650_regmap_config, + .clks = cam_cc_sm8650_clocks, + .num_clks = ARRAY_SIZE(cam_cc_sm8650_clocks), + .resets = cam_cc_sm8650_resets, + .num_resets = ARRAY_SIZE(cam_cc_sm8650_resets), + .gdscs = cam_cc_sm8650_gdscs, + .num_gdscs = ARRAY_SIZE(cam_cc_sm8650_gdscs), +}; + +static const struct of_device_id cam_cc_sm8650_match_table[] = { + { .compatible = "qcom,sm8650-camcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, cam_cc_sm8650_match_table); + +static int cam_cc_sm8650_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + regmap = qcom_cc_map(pdev, &cam_cc_sm8650_desc); + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); + return PTR_ERR(regmap); + } + + clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); + clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); + clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); + clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); + clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); + clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); + clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); + clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); + clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); + clk_lucid_ole_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config); + clk_lucid_ole_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config); + + /* Keep clocks always enabled */ + qcom_branch_set_clk_en(regmap, 0x13318); /* CAM_CC_DRV_AHB_CLK */ + qcom_branch_set_clk_en(regmap, 0x13314); /* CAM_CC_DRV_XO_CLK */ + qcom_branch_set_clk_en(regmap, 0x132ec); /* CAM_CC_GDSC_CLK */ + qcom_branch_set_clk_en(regmap, 0x13308); /* CAM_CC_SLEEP_CLK */ + + ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8650_desc, regmap); + + pm_runtime_put(&pdev->dev); + + return ret; +} + +static struct platform_driver cam_cc_sm8650_driver = { + .probe = cam_cc_sm8650_probe, + .driver = { + .name = "camcc-sm8650", + .of_match_table = cam_cc_sm8650_match_table, + }, +}; + +module_platform_driver(cam_cc_sm8650_driver); + +MODULE_DESCRIPTION("QTI CAMCC SM8650 Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index d73f747d2474..c601c35e6724 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include <linux/clk-provider.h> @@ -10,7 +10,7 @@ #include <linux/pm_runtime.h> #include <linux/regmap.h> -#include <dt-bindings/clock/qcom,sm8450-videocc.h> +#include <dt-bindings/clock/qcom,sm8650-videocc.h> #include "clk-alpha-pll.h" #include "clk-branch.h" @@ -35,7 +35,7 @@ static const struct pll_vco lucid_ole_vco[] = { { 249600000, 2300000000, 0 }, }; -static const struct alpha_pll_config video_cc_pll0_config = { +static struct alpha_pll_config video_cc_pll0_config = { .l = 0x25, .alpha = 0x8000, .config_ctl_val = 0x20485699, @@ -66,7 +66,7 @@ static struct clk_alpha_pll video_cc_pll0 = { }, }; -static const struct alpha_pll_config video_cc_pll1_config = { +static struct alpha_pll_config video_cc_pll1_config = { .l = 0x36, .alpha = 0xb000, .config_ctl_val = 0x20485699, @@ -117,6 +117,14 @@ static const struct clk_parent_data video_cc_parent_data_1[] = { { .hw = &video_cc_pll1.clkr.hw }, }; +static const struct parent_map video_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, +}; + static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), @@ -126,6 +134,16 @@ static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = { { } }; +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src_sm8650[] = { + F(588000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(900000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1140000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1305000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1440000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + static struct clk_rcg2 video_cc_mvs0_clk_src = { .cmd_rcgr = 0x8000, .mnd_width = 0, @@ -149,6 +167,15 @@ static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = { { } }; +static const struct freq_tbl ftbl_video_cc_mvs1_clk_src_sm8650[] = { + F(840000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1110000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + static struct clk_rcg2 video_cc_mvs1_clk_src = { .cmd_rcgr = 0x8018, .mnd_width = 0, @@ -164,6 +191,26 @@ static struct clk_rcg2 video_cc_mvs1_clk_src = { }, }; +static const struct freq_tbl ftbl_video_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_xo_clk_src = { + .cmd_rcgr = 0x810c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_2, + .freq_tbl = ftbl_video_cc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "video_cc_xo_clk_src", + .parent_data = video_cc_parent_data_2, + .num_parents = ARRAY_SIZE(video_cc_parent_data_2), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_shared_ops, + }, +}; + static struct clk_regmap_div video_cc_mvs0_div_clk_src = { .reg = 0x80c4, .shift = 0, @@ -244,6 +291,26 @@ static struct clk_branch video_cc_mvs0_clk = { }, }; +static struct clk_branch video_cc_mvs0_shift_clk = { + .halt_reg = 0x8128, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x8128, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x8128, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch video_cc_mvs0c_clk = { .halt_reg = 0x8064, .halt_check = BRANCH_HALT, @@ -262,6 +329,26 @@ static struct clk_branch video_cc_mvs0c_clk = { }, }; +static struct clk_branch video_cc_mvs0c_shift_clk = { + .halt_reg = 0x812c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x812c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x812c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs0c_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch video_cc_mvs1_clk = { .halt_reg = 0x80e0, .halt_check = BRANCH_HALT_SKIP, @@ -282,6 +369,26 @@ static struct clk_branch video_cc_mvs1_clk = { }, }; +static struct clk_branch video_cc_mvs1_shift_clk = { + .halt_reg = 0x8130, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x8130, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x8130, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch video_cc_mvs1c_clk = { .halt_reg = 0x8090, .halt_check = BRANCH_HALT, @@ -300,6 +407,26 @@ static struct clk_branch video_cc_mvs1c_clk = { }, }; +static struct clk_branch video_cc_mvs1c_shift_clk = { + .halt_reg = 0x8134, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x8134, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x8134, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "video_cc_mvs1c_shift_clk", + .parent_hws = (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct gdsc video_cc_mvs0c_gdsc = { .gdscr = 0x804c, .en_rest_wait_val = 0x2, @@ -363,6 +490,7 @@ static struct clk_regmap *video_cc_sm8550_clocks[] = { [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr, [VIDEO_CC_PLL0] = &video_cc_pll0.clkr, [VIDEO_CC_PLL1] = &video_cc_pll1.clkr, + [VIDEO_CC_XO_CLK_SRC] = NULL, }; static struct gdsc *video_cc_sm8550_gdscs[] = { @@ -380,6 +508,7 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = { [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 }, [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 }, [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 }, + [VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 }, }; static const struct regmap_config video_cc_sm8550_regmap_config = { @@ -402,6 +531,7 @@ static struct qcom_cc_desc video_cc_sm8550_desc = { static const struct of_device_id video_cc_sm8550_match_table[] = { { .compatible = "qcom,sm8550-videocc" }, + { .compatible = "qcom,sm8650-videocc" }, { } }; MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table); @@ -410,6 +540,7 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) { struct regmap *regmap; int ret; + u32 sleep_clk_offset = 0x8140; ret = devm_pm_runtime_enable(&pdev->dev); if (ret) @@ -425,12 +556,27 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) return PTR_ERR(regmap); } + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) { + sleep_clk_offset = 0x8150; + video_cc_pll0_config.l = 0x1e; + video_cc_pll0_config.alpha = 0xa000; + video_cc_pll1_config.l = 0x2b; + video_cc_pll1_config.alpha = 0xc000; + video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_sm8650; + video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_sm8650; + video_cc_sm8550_clocks[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr; + video_cc_sm8550_clocks[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr; + video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr; + video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr; + video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr; + } + clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); /* Keep some clocks always-on */ qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */ - qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */ + qcom_branch_set_clk_en(regmap, sleep_clk_offset); /* VIDEO_CC_SLEEP_CLK */ qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */ ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap); diff --git a/include/dt-bindings/clock/qcom,qcm2290-gpucc.h b/include/dt-bindings/clock/qcom,qcm2290-gpucc.h new file mode 100644 index 000000000000..7c76dd05278f --- /dev/null +++ b/include/dt-bindings/clock/qcom,qcm2290-gpucc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_QCM2290_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_QCM2290_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_GFX3D_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CX_SNOC_DVM_CLK 4 +#define GPU_CC_CXO_AON_CLK 5 +#define GPU_CC_CXO_CLK 6 +#define GPU_CC_GMU_CLK_SRC 7 +#define GPU_CC_GX_GFX3D_CLK 8 +#define GPU_CC_GX_GFX3D_CLK_SRC 9 +#define GPU_CC_PLL0 10 +#define GPU_CC_SLEEP_CLK 11 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 12 + +/* Resets */ +#define GPU_GX_BCR 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8650-camcc.h b/include/dt-bindings/clock/qcom,sm8650-camcc.h new file mode 100644 index 000000000000..df73bf35f4bf --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8650-camcc.h @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8650_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8650_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_CLK 1 +#define CAM_CC_BPS_CLK_SRC 2 +#define CAM_CC_BPS_FAST_AHB_CLK 3 +#define CAM_CC_BPS_SHIFT_CLK 4 +#define CAM_CC_CAMNOC_AXI_NRT_CLK 5 +#define CAM_CC_CAMNOC_AXI_RT_CLK 6 +#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 7 +#define CAM_CC_CAMNOC_DCD_XO_CLK 8 +#define CAM_CC_CAMNOC_XO_CLK 9 +#define CAM_CC_CCI_0_CLK 10 +#define CAM_CC_CCI_0_CLK_SRC 11 +#define CAM_CC_CCI_1_CLK 12 +#define CAM_CC_CCI_1_CLK_SRC 13 +#define CAM_CC_CCI_2_CLK 14 +#define CAM_CC_CCI_2_CLK_SRC 15 +#define CAM_CC_CORE_AHB_CLK 16 +#define CAM_CC_CPAS_AHB_CLK 17 +#define CAM_CC_CPAS_BPS_CLK 18 +#define CAM_CC_CPAS_CRE_CLK 19 +#define CAM_CC_CPAS_FAST_AHB_CLK 20 +#define CAM_CC_CPAS_IFE_0_CLK 21 +#define CAM_CC_CPAS_IFE_1_CLK 22 +#define CAM_CC_CPAS_IFE_2_CLK 23 +#define CAM_CC_CPAS_IFE_LITE_CLK 24 +#define CAM_CC_CPAS_IPE_NPS_CLK 25 +#define CAM_CC_CPAS_SBI_CLK 26 +#define CAM_CC_CPAS_SFE_0_CLK 27 +#define CAM_CC_CPAS_SFE_1_CLK 28 +#define CAM_CC_CPAS_SFE_2_CLK 29 +#define CAM_CC_CPHY_RX_CLK_SRC 30 +#define CAM_CC_CRE_AHB_CLK 31 +#define CAM_CC_CRE_CLK 32 +#define CAM_CC_CRE_CLK_SRC 33 +#define CAM_CC_CSI0PHYTIMER_CLK 34 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 35 +#define CAM_CC_CSI1PHYTIMER_CLK 36 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 37 +#define CAM_CC_CSI2PHYTIMER_CLK 38 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 39 +#define CAM_CC_CSI3PHYTIMER_CLK 40 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 41 +#define CAM_CC_CSI4PHYTIMER_CLK 42 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 43 +#define CAM_CC_CSI5PHYTIMER_CLK 44 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 45 +#define CAM_CC_CSI6PHYTIMER_CLK 46 +#define CAM_CC_CSI6PHYTIMER_CLK_SRC 47 +#define CAM_CC_CSI7PHYTIMER_CLK 48 +#define CAM_CC_CSI7PHYTIMER_CLK_SRC 49 +#define CAM_CC_CSID_CLK 50 +#define CAM_CC_CSID_CLK_SRC 51 +#define CAM_CC_CSID_CSIPHY_RX_CLK 52 +#define CAM_CC_CSIPHY0_CLK 53 +#define CAM_CC_CSIPHY1_CLK 54 +#define CAM_CC_CSIPHY2_CLK 55 +#define CAM_CC_CSIPHY3_CLK 56 +#define CAM_CC_CSIPHY4_CLK 57 +#define CAM_CC_CSIPHY5_CLK 58 +#define CAM_CC_CSIPHY6_CLK 59 +#define CAM_CC_CSIPHY7_CLK 60 +#define CAM_CC_DRV_AHB_CLK 61 +#define CAM_CC_DRV_XO_CLK 62 +#define CAM_CC_FAST_AHB_CLK_SRC 63 +#define CAM_CC_GDSC_CLK 64 +#define CAM_CC_ICP_AHB_CLK 65 +#define CAM_CC_ICP_CLK 66 +#define CAM_CC_ICP_CLK_SRC 67 +#define CAM_CC_IFE_0_CLK 68 +#define CAM_CC_IFE_0_CLK_SRC 69 +#define CAM_CC_IFE_0_FAST_AHB_CLK 70 +#define CAM_CC_IFE_0_SHIFT_CLK 71 +#define CAM_CC_IFE_1_CLK 72 +#define CAM_CC_IFE_1_CLK_SRC 73 +#define CAM_CC_IFE_1_FAST_AHB_CLK 74 +#define CAM_CC_IFE_1_SHIFT_CLK 75 +#define CAM_CC_IFE_2_CLK 76 +#define CAM_CC_IFE_2_CLK_SRC 77 +#define CAM_CC_IFE_2_FAST_AHB_CLK 78 +#define CAM_CC_IFE_2_SHIFT_CLK 79 +#define CAM_CC_IFE_LITE_AHB_CLK 80 +#define CAM_CC_IFE_LITE_CLK 81 +#define CAM_CC_IFE_LITE_CLK_SRC 82 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 83 +#define CAM_CC_IFE_LITE_CSID_CLK 84 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 85 +#define CAM_CC_IPE_NPS_AHB_CLK 86 +#define CAM_CC_IPE_NPS_CLK 87 +#define CAM_CC_IPE_NPS_CLK_SRC 88 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 89 +#define CAM_CC_IPE_PPS_CLK 90 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 91 +#define CAM_CC_IPE_SHIFT_CLK 92 +#define CAM_CC_JPEG_1_CLK 93 +#define CAM_CC_JPEG_CLK 94 +#define CAM_CC_JPEG_CLK_SRC 95 +#define CAM_CC_MCLK0_CLK 96 +#define CAM_CC_MCLK0_CLK_SRC 97 +#define CAM_CC_MCLK1_CLK 98 +#define CAM_CC_MCLK1_CLK_SRC 99 +#define CAM_CC_MCLK2_CLK 100 +#define CAM_CC_MCLK2_CLK_SRC 101 +#define CAM_CC_MCLK3_CLK 102 +#define CAM_CC_MCLK3_CLK_SRC 103 +#define CAM_CC_MCLK4_CLK 104 +#define CAM_CC_MCLK4_CLK_SRC 105 +#define CAM_CC_MCLK5_CLK 106 +#define CAM_CC_MCLK5_CLK_SRC 107 +#define CAM_CC_MCLK6_CLK 108 +#define CAM_CC_MCLK6_CLK_SRC 109 +#define CAM_CC_MCLK7_CLK 110 +#define CAM_CC_MCLK7_CLK_SRC 111 +#define CAM_CC_PLL0 112 +#define CAM_CC_PLL0_OUT_EVEN 113 +#define CAM_CC_PLL0_OUT_ODD 114 +#define CAM_CC_PLL1 115 +#define CAM_CC_PLL1_OUT_EVEN 116 +#define CAM_CC_PLL2 117 +#define CAM_CC_PLL3 118 +#define CAM_CC_PLL3_OUT_EVEN 119 +#define CAM_CC_PLL4 120 +#define CAM_CC_PLL4_OUT_EVEN 121 +#define CAM_CC_PLL5 122 +#define CAM_CC_PLL5_OUT_EVEN 123 +#define CAM_CC_PLL6 124 +#define CAM_CC_PLL6_OUT_EVEN 125 +#define CAM_CC_PLL7 126 +#define CAM_CC_PLL7_OUT_EVEN 127 +#define CAM_CC_PLL8 128 +#define CAM_CC_PLL8_OUT_EVEN 129 +#define CAM_CC_PLL9 130 +#define CAM_CC_PLL9_OUT_EVEN 131 +#define CAM_CC_PLL9_OUT_ODD 132 +#define CAM_CC_PLL10 133 +#define CAM_CC_PLL10_OUT_EVEN 134 +#define CAM_CC_QDSS_DEBUG_CLK 135 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 136 +#define CAM_CC_QDSS_DEBUG_XO_CLK 137 +#define CAM_CC_SBI_CLK 138 +#define CAM_CC_SBI_FAST_AHB_CLK 139 +#define CAM_CC_SBI_SHIFT_CLK 140 +#define CAM_CC_SFE_0_CLK 141 +#define CAM_CC_SFE_0_CLK_SRC 142 +#define CAM_CC_SFE_0_FAST_AHB_CLK 143 +#define CAM_CC_SFE_0_SHIFT_CLK 144 +#define CAM_CC_SFE_1_CLK 145 +#define CAM_CC_SFE_1_CLK_SRC 146 +#define CAM_CC_SFE_1_FAST_AHB_CLK 147 +#define CAM_CC_SFE_1_SHIFT_CLK 148 +#define CAM_CC_SFE_2_CLK 149 +#define CAM_CC_SFE_2_CLK_SRC 150 +#define CAM_CC_SFE_2_FAST_AHB_CLK 151 +#define CAM_CC_SFE_2_SHIFT_CLK 152 +#define CAM_CC_SLEEP_CLK 153 +#define CAM_CC_SLEEP_CLK_SRC 154 +#define CAM_CC_SLOW_AHB_CLK_SRC 155 +#define CAM_CC_TITAN_TOP_SHIFT_CLK 156 +#define CAM_CC_XO_CLK_SRC 157 + +/* CAM_CC power domains */ +#define CAM_CC_TITAN_TOP_GDSC 0 +#define CAM_CC_BPS_GDSC 1 +#define CAM_CC_IFE_0_GDSC 2 +#define CAM_CC_IFE_1_GDSC 3 +#define CAM_CC_IFE_2_GDSC 4 +#define CAM_CC_IPE_0_GDSC 5 +#define CAM_CC_SBI_GDSC 6 +#define CAM_CC_SFE_0_GDSC 7 +#define CAM_CC_SFE_1_GDSC 8 +#define CAM_CC_SFE_2_GDSC 9 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_DRV_BCR 1 +#define CAM_CC_ICP_BCR 2 +#define CAM_CC_IFE_0_BCR 3 +#define CAM_CC_IFE_1_BCR 4 +#define CAM_CC_IFE_2_BCR 5 +#define CAM_CC_IPE_0_BCR 6 +#define CAM_CC_QDSS_DEBUG_BCR 7 +#define CAM_CC_SBI_BCR 8 +#define CAM_CC_SFE_0_BCR 9 +#define CAM_CC_SFE_1_BCR 10 +#define CAM_CC_SFE_2_BCR 11 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8650-videocc.h b/include/dt-bindings/clock/qcom,sm8650-videocc.h new file mode 100644 index 000000000000..4e3c2d87280f --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8650-videocc.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8650_H + +#include "qcom,sm8450-videocc.h" + +/* SM8650 introduces below new clocks and resets compared to SM8450 */ + +/* VIDEO_CC clocks */ +#define VIDEO_CC_MVS0_SHIFT_CLK 12 +#define VIDEO_CC_MVS0C_SHIFT_CLK 13 +#define VIDEO_CC_MVS1_SHIFT_CLK 14 +#define VIDEO_CC_MVS1C_SHIFT_CLK 15 +#define VIDEO_CC_XO_CLK_SRC 16 + +/* VIDEO_CC resets */ +#define VIDEO_CC_XO_CLK_ARES 7 + +#endif |