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path: root/drivers/gpu/drm/amd/display/dc/inc
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2026-10-01drm/amd/display: Dispatch HUBBUB_SOFT_RESET through hubbub_funcsPiotr Maziarz
[WHY] hubbub_soft_reset_params carried the callee itself as a function pointer, so the step was not fully described by its parameters. The core_gtest dumper could only record hubbub and reset, which means two sequences calling different functions compare equal. It also forced dcn401_hwseq to name the dcn10 symbol hubbub1_soft_reset directly, because hubbub_funcs had no slot for a soft reset. [HOW] Added soft_reset to hubbub_funcs and pointed hubbub4_01_funcs, hubbub42_funcs and hubbub60_funcs at hubbub1_soft_reset, the same way allow_self_refresh_control is already shared. Dropped the function pointer from the params struct and the add helper, and had the executor call hubbub->funcs->soft_reset. The dcn10_hubbub.h include in dcn401_hwseq.c is no longer needed. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Flatten OPP_SET_DISP_PATTERN_GENERATOR parametersPiotr Maziarz
[WHY] opp2_set_disp_pattern_generator read debug.disable_dynamic_expansion_for_test_pattern through opp->ctx->dc while the sequence was executing. A block sequence operation must take its inputs from a flat parameter list resolved during the build phase, so this hid an input from the recorded sequence and left the FMT_DYNAMIC_EXP_CNTL branch unreachable from the OPP unit tests. [HOW] Added disable_dyn_exp_for_test_pattern to opp_funcs::opp_set_disp_pattern_generator and to opp_set_disp_pattern_generator_params, and updated every caller to pass dc->debug.disable_dynamic_expansion_for_test_pattern explicitly. Updated the unit test mocks and the core_gtest dumper, and extended opp_gtest to cover both values of the new flag. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Add temporary programming for port control in dc_initAlvin Lee
[Description] Add the POR setting for SDP_PORT_CONTROL into dc init sequence. This is temporary until the initialization moves into pre-OS DMCUB. Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Keep public DC lifecycle APIs stable beside Core 2Cheng, Tony
DMs still call dc_hardware_init and dc_hardware_release while Core 2 lands next to legacy. Those entry points live in dc/dc_api_dispatch: LEGACY calls the old bodies directly, CORE2 uses core2_funcs. dc_create allocates struct dc2 and returns the inner dc (TO_DC2). The shim only records selection; dc_construct still constructs Core2. No dispatch fields on public struct dc, and no architect spec edits. TO_DC2 is a typed upcast (struct dc is the first member of struct dc2). Shim headers are included for UNIT_TEST as well as production so TO_DC2 is defined when core_gtest compiles dc.c. Assisted-by: Cursor:cursor Signed-off-by: Cheng, Tony <Tony.Cheng@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Synchronize UTM overrides with SMUWenjing Liu
[Why] Keep the display QoS model and firmware table consistent when test overrides are enabled. [How] Serialize the overridden QoS values into a dedicated transfer buffer and send the table after clock initialization. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Move struct dtbclk_dto_params to dc_hw_types.hTony Cheng
This can simplify includes Assisted-by: Cursor:composer-2.5 Signed-off-by: Tony Cheng <tony.cheng@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Resync cursor cache after offload abort on DCN60Ivan Lipski
[Why&How] The cursor programming path caches the last-written cursor state in SW and, for the enable bit, skips the register write when the cache already matches the request. Under cursor offload the SW cache is updated even though the actual register write is deferred to firmware. When an offloaded cursor update is aborted (e.g. an overlay geometry change reprograms the cursor directly in the same frame), the queued firmware write is dropped but the cache is left stale, so the following direct programming pass skips the enable write and the cursor disappears over the overlay plane. Add a refresh_cursor_state() hubp/dpp hook that reads the cursor position and attribute registers back from hardware into the SW cache, and call it from dcn35_abort_cursor_offload_update() so the cache is truthful after an abort. This keeps the enable-change optimization intact for all ASICs and is race-robust regardless of whether firmware applied the queued write before the abort. Only dcn60 (the sole offload user) wires up the hook. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Rename build_cursor_position to ↵Piotr Maziarz
dcn10_build_cursor_pos_update_params This commit contains renames, adding const to pipe_ctx in build_cursor_pos_update_params and also removing unnecessary checks before dc_dmub_srv_is_cursor_offload_enabled(). [Why] It improves code clarity. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Add inst field to clock_source and dioTony Cheng
Add an inst member to struct clock_source and struct dio. The DCE110 and DCE112 clock sources derive it from their clock_source_id; the DCN10 DIO is a singleton and uses 0. Also move the (void)encoding cast in dcn401_program_pix_clk() below the local declarations, where it belongs. No functional change; the inst field has no readers yet. Reviewed-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Add inst field to encoder structsTony Cheng
Add an inst member to struct link_encoder, struct stream_encoder and struct hpo_frl_stream_encoder, and populate it in the DCN10 through DCN60 construct paths. No functional change; the field has no readers yet. Reviewed-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Add inst field to struct pg_cntlTony Cheng
Add an inst member to struct pg_cntl and set it to 0 in pg_cntl35_create() and pg_cntl42_create(), since PG cntl is a singleton. No functional change; the field has no readers yet. Reviewed-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Add inst field to struct abmTony Cheng
Add an inst member to struct abm and set it to 0 in dce_abm_construct() and dmub_abm_construct(), since ABM is a singleton. No functional change; the field has no readers yet. Reviewed-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Add inst field to struct clk_mgrTony Cheng
Add an inst member to struct clk_mgr and set it to 0 in the DCN401, DCN42, DCN42B and DCN60 construct paths, since clk_mgr is a singleton on all of them. No functional change; the field has no readers yet. Reviewed-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Add inst field to struct hubbubTony Cheng
Add an inst member and initialize it to 0 in every hubbub*_construct() from DCN10 through DCN60. No functional change. Reviewed-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: add SPDX-License-IdentifierTony Cheng
Add the AMD Open-Source SPDX line to dc files. Reviewed-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Add instance field to struct dccgTony Cheng
[Why] struct dccg has no instance identifier, unlike other DC hardware blocks. Debug and tracing helpers need one to identify the block. [How] Add an inst member to struct dccg and initialize it to 0 in every dccgX_create(), since there is one DCCG instance per ASIC. Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Program DCC as part of address updateAlvin Lee
[Description] - DCC register is latched on the surface address register being updated - In this case couple the DCC programming and the address update together to ensure the DCC programming is always taken as expected - Update address programming function to take in DCC bool, use for DCN6+ and leave older DCN unchanged. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Add is_odm_enabled callback to skip init_odm on active ODM ↵Wang, Sung-huai
pipes [Why] dcn10_init_pipes unconditionally calls init_odm on all enabled TGs, resetting ODM combine state even when it should be preserved. [How] Add is_odm_enabled callback to timing_generator_funcs and guard init_odm to skip when ODM is already active. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Danny Wang <Danny.Wang@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Add instance field to struct mpcTony Cheng
[Why] struct mpc has no instance identifier, unlike other DC hardware blocks. Debug and tracing helpers need one to identify the block. [How] Add an inst member to struct mpc and initialize it to 0 in every dcnXX_mpc_construct(), since there is one MPC instance per ASIC. Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Add Replay cumulative residency queryWei-Guang Li
[Why&How] Add driver-side support for querying boot-time cumulative PHY-off residency via the REPLAY_SNAPSHOT_CUMULATIVE_RESIDENCY GPINT command implemented in DMUB FW. Reviewed-by: Jack Chang <jack.chang@amd.com> Signed-off-by: Wei-Guang Li <wei-guang.li@amd.com> Signed-off-by: Jack Chang <jack.chang@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Refactor RMCM into a separate moduleRafal Ostrowski
[WHY] The RMCM logic was embedded inside the MPC block, sharing its source files, functions, register definitions and other logic. This tight coupling created several problems: - The RMCM vtable was bolted onto struct mpc_funcs, making it impossible to instantiate RMCM independently of MPC - RMCM resource acquisition had no tracking - there was no mechanism to allocate the 2 available RMCM instances to pipes or release them [HOW] RMCM is now a separate module: - dc/rmcm/ directory with per-ASIC implementations - new struct rmcm with its own funcs vtable containing shaper, 3DLUT, and fast-load operations - removed all RMCM code from MPC - added RMCM resource lifecycle management in dc_resource.c: - resource_assign_rmcm(): Assigns the instances for a whole context, so a plane that is only now asking never evicts one already using an instance - resource_release_rmcm(): Clears the pipe's allocation. - updated resource pool constructors (dcn42, dcn42b, dcn60) to create RMCM instances via the new dcnXX_rmcm_create() and destroy them in pool teardown Reviewed-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Update LLS and UPSP programming pathsAlvin Lee
[Description] - UPSP should only be enabled when we want linear scaling for 420/422 - In DC for non-FP16 formats that are told to scale in non-linear, program bypass for PRE_GAM since these formats are already non-linear (i.e., YUV420, YUV422, RGB, etc.) Reviewed-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Taimur Hassan <syed.hassan@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17Merge tag 'amd-drm-next-7.4-2026-09-10' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/amdgpu/kernel into drm-next amd-drm-next-7.4-2026-09-10: amdgpu: - Freesync fixes - GPUVM fix - Debugfs fixes - HDMI updates - IPS fix - GPU reset fix - RGB quantization fixes - SMU 13.0.x fixes - MES updates - UserQ updates - UVD fix - Various bounds checks - DML fixes - DCN 6 updates - NBIO 7.11.5 support - Audio fixes - More display KUnit tests - SMU 15 updates - RAS updates - VCN 5.0.2 updates - JPEG 5.0.2 updates - DCN 4.2 updates - PSR fixes - Misc cleanups - PSP 15.0.8 updates - RAS BERT support - RAS CPER updates - vblank fixes - LSDMA updates - GC 12.1 updates - MMHUB 4.2 updates - NBIO 6.3.2 updates - SMU 15.0.8 updates - IP discovery updates - GPU spatial partitioning updates - HDMI 2.1 freesync support - HDMI 2.1 ALLM support - HDMI 2.1 VRR support - Require jobs for IBs - Enable FRL for HDMI - MES oversubscription fixes - IH 6-7 updates - GMC 11-12 fault handling updates - Fixed point cleanup - Backlight fixes - GPUVM cleanup - Devcoredump fixes - UALoE (UALink over Ethernet) Support - SDMA userq fixes - GC 8 fix amdkfd: - Various bounds checks - SVM fixes - GC 12.1 updates - MES updates - Trap handler fixes - Debugfs fixes drm: - Add gem callback for when handle count goes to 0 - Rust fix UAPI: - INFO IOCTL fix for 32 bit userspace on 64 bit kernel - Add syncobj_points to USERQ signal ioctl Proposed userspace: * radeonsi NV_timeline_semaphore https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37335 * RADV user queues https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40808 - Add UALink support IOCTLs Proposed userspace: https://github.com/ROCm/rocm-systems/blob/35959f8e1260c7cee3e51a740e320be3856ee4ff/projects/rocr-runtime/libhsakmt/src/memory.c#L971 https://github.com/ROCm/rocm-systems/blob/35959f8e1260c7cee3e51a740e320be3856ee4ff/projects/rocr-runtime/libhsakmt/src/memory.c#L1036 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260910213040.826425-1-alexander.deucher@amd.com
2026-09-10drm/amd/display: Add stressed peak bandwidth probe with DMA contentionWenjing Liu
[Why] Peak-bandwidth-under-contention validation currently needs an external tool to manufacture memory contention while querying peak bandwidth. Expose this as an explicit probe variant so the driver can generate that contention itself. [How] Add a new probe type that builds the same gated perfmon sequence as the plain peak-BW probe, with a DMA copy of the current surface into a scratch buffer inserted before the measurement window to synthesize a competing memory client. Move the scratch buffer fields onto the base resource pool struct instead of an ASIC-specific subclass, and reject the probe with a new status code when the buffer was never allocated. Also fixes a stack- corruption bug where a local variable's address was captured by a deferred callback and used after the local went out of scope, and a missing NULL check on a similar output parameter used by an early-return path. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/display: Do not use panel_inst in prPeichen Huang
[WHY] Panel Replay has different index definition from other eDP features. So we should avoid using panel_index in pr. [HOW] Rename the it to pr_panel_inst Reviewed-by: Leon Huang <leon.huang1@amd.com> Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/display: Move custom float structures from opp.h to custom_float.hSamson Tam
[WHY] Currently it needs to include opp.h to access custom_float structures, which pulls in additional include files that are not necessary. [HOW] Move custom_float structures to custom_float.h, and include this header in opp.h. Add only os_types.h and fixed31_32.h in custom_float.h Suggested-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-31Merge drm/drm-next into drm-misc-nextThomas Zimmermann
Getting drm-misc-next up to v7.3-rc1. In exynos, there was a conflict in exynos_dbi_bind(). The merge resolves it to the state of commit 3cc8eee9f346 ("drm/exynos: remove dependency on DRM simple helpers"). Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2026-08-25drm/amd/display: Remove RMCM tetrahedral cube from dc_plane_stateRafal Ostrowski
[Why&How] MCM and RMCM both took their cube from struct tetrahedral_params, which is embedded by value in dc_3dlut and therefore in dc_plane_state and dc.scratch. RMCM needs a 33x33x33 cube, but that cube is ~421KB, so enabling it in the shared union - where tetrahedral_33 was left commented out - would push sizeof(struct dc) past the kmalloc MAX_PAGE_ORDER limit and break kunit and other allocations. Drop the unused struct tetrahedral_33x33x33 definition and lut_dim. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Reviewed-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: eDP panel polarity control and test supportHarry VanZyllDeJong
eDP panels can require explicit polarity control during power transitions to ensure correct signal behavior. Without this, panels that depend on polarity state may behave incorrectly when combined with refresh rate drop logic, since the two features previously had no coordination point. To address this, a set/reset/query API is introduced and integrated into the resource layer so polarity is managed as a first-class concern within the existing power optimization flow. RamlessPowerOptimization is updated to coordinate polarity state alongside refresh rate drop decisions, preventing the two paths from conflicting during transitions. Reviewed-by: Sreeja Golui <sreeja.golui@amd.com> Signed-off-by: Harry VanZyllDeJong <hvanzyll@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Add support for overriding UTM client QC profileDillon Varone
[WHY&HOW] Support overriding UTM client QC profiles for testing. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-10drm/amd/display: Remove unused DMCU/DMUB EDID CEA parserAlex Huang
With HDMI FreeSync detection now sourced from the common DRM EDID parser, the DMUB parsing for AMD VSDB is no longer used. Remove all relevant fields and files for this flow, it is no longer necessary to ever take firmware round-trip for this. Signed-off-by: Alex Huang <Alex.Huang2@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Link: https://patch.msgid.link/20260804143339.714548-5-Alex.Huang2@amd.com Signed-off-by: Mario Limonciello <superm1@kernel.org>
2026-08-06drm/amd/display: Migrate color manager HW and fix MCM blend LUT issuesRafal Ostrowski
Combine two related color manager improvements: 1. Migrate MCM/RMCM, shaper and 3DLUT HW programming to dc_plane_cm - Continue convergence with upstream Color Manager refactor - Migrate MCM/RMCM, shaper and 3DLUT programming for dcn401+ to dc_plane_cm - Unify MCM programming across both legacy and 3DLUT DMA paths - Add 3DLUT DMA broadcast support for multi-pipe planes 2. Reprogram MCM blend LUT on blend_enable falling edge - Fix issue where SDR desktop remained desaturated after video playback - Detect blend_enable falling edge (1->0) in surface update detection - Force MCM LUT reprogramming on blend state change Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Ensure dtbclk is enabledCharlene Liu
[why] ensure dtbclk is enabled before hdmistreamclk_en pmfw could stop dtbclk on idle. driver needs to ensure dtbclk enabled is enabled before hdmistreamclk_en also disable debounce timer on dcn42. Reviewed-by: Chris Park <chris.park@amd.com> Reviewed-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Enable DCN6 sources compilationAurabindo Pillai
- Add hooks in various entry points to perform hw/sw init for DCN6 asic - Add dependent changes needed to enable DCN6 asic - Update the Makefiles so that DCN6 related newly added sources are compiled Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Register DCN as a PMFW DF C-state client on DCN42Leo Chen
[Why] DCN must not gate DF C-state locally via the DCHUBBUB ALLOW_SELF_REFRESH controls: forcing a local "disallow" during MM-stutter re-entry can wedge the fabric and hang boot. When DCN is disallowing c-state or has invalid watermarks we should be explicit about it rather than using the watermark force selector. [How] Register DCN as a client of PMFW's DF C-state arbiter and signal over DALSMC whether DCN permits DF C-state; PMFW allows DF C-state only once every client (including DCN) has voted "allow". - dc_clocks.cstate_allow: last DCN vote acked by PMFW - clk_mgr_funcs::notify_cstate_disable(clk_mgr, disable) prepare_bandwidth and headless dc_power_down_on_boot vote Allow; hardware_release votes Disallow; init_clocks (D0 entry) only clears the cache (cstate_allow) so the next allow re-syncs with PMFW. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Wire probe commit path into dc_update_stateWenjing Liu
[Why] The dc_update_state commit interface and the dc_probe object model existed but were not connected: there was no path to validate, commit, and program a probe through the update pipeline, nor to read the result back. The measurement waits on OTG frame edges and must not block fast updates. [How] - Move the per-commit scratch off dc_stream_state onto a dc-owned pool; acquire at init, release on cleanup or prepare failure, serialized by the DM global lock every commit path already holds. - dc_update_state drives stream commits, probe-only commits, or both through one staged init/prepare/execute/cleanup loop with a null-arg guard. prepare releases the scratch slot on failure; cleanup releases it on success. - Probe prepare installs the absolute probe set in place; execute calls the perfmon programming hook in the unlocked window and latches results. - Add resource_validate_probe_set, a context-free achievability check shared by dc_validate_global_state (full update) and probe prepare (probe-only). - dc_state_get_status gains a probe status class with a probe filter and a by-type mapping; dc_validation_set gains probes/probe_count. Drop the dead actual_* fields from struct dc_qos_info. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Introduce program_perfmon hwss hook and BLS perfmon sequenceWenjing Liu
[Why] The hubbub perfmon peak-bandwidth path used a monolithic function combining counter configuration and enable in one call, and wrote results into a caller-supplied struct outside the dc_state model. A BLS-driven approach builds the measurement from stateless primitives, gates it to OTG frame boundaries, and stores results in dc_state. [How] - Rename the peak-BW vtable members from "unbounded_bandwidth" to "out_of_order_bandwidth" and split them into arm and start operations. - Add the full set of perfmon BLS primitives - param structs, union members, enum entries, executors, and hwss_add_* builders - for reset, arm, every start_measuring_* and every get_* operation. - Add dc_probe_status (valid, type, result union) plus probe_status[] to dc_state. - Replace the measure_memory_qos hook with program_perfmon(dc, context), which writes results into probe_status[]. - dc_get_qos_info no longer calls the removed hook. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Refactor dc_validation_set array into single root structWenjing Liu
[Why] dc_validate_with_context() took a C array of per-stream elements plus a separate count. This flat array cannot be extended to carry global objects without widening the signature further. [How] Rename the per-stream element to dc_validation_stream, and make dc_validation_set a root struct holding streams[MAX_STREAMS] and stream_count. Update dc_validate_with_context() to take a single const dc_validation_set * and propagate the new shape through all DC-layer callers and helpers. Remove the never-implemented dce112_validate_with_context declaration and the orphaned dce100 forward-declare. No behavior change. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Introduce dc_probe public object modelWenjing Liu
[Why] Performance measurement needs to commit through the same update entry point as planes and streams, with DM working against an abstraction of what to measure rather than the hardware block that performs it. [How] Add dc_probe.h defining dc_probe_type (the measurable quantity), dc_probe_target_state (not measuring / measuring / measured), dc_probe_scope (global only, per-stream/plane deferred), and dc_probe_state (an inline descriptor with copy semantics, no refcount). dc_state carries the committed set as probes[MAX_PROBES] plus probe_count. dc_state_update carries dc_probe_updates as the desired absolute set that DC diffs against the committed set. Reviewed-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Split DPMS ON into partsDominik Kaszewski
[Why] Ongoing optimization efforts require splitting DPMS ON around enable_link, in order to enable running multiple sequences in parallel. [How] * Split link_set_dpms_on across enable_link * Add return value indicating whether the programming sequence succeeded and/or run to the end. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/amd/display: Add updated MCIF ARB register definitionsDillon Varone
[WHY&HOW] DCN4+ use a new structure for MCIF arbiter registers. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-14drm/amd/display: Enable CACP on LinuxChenyu Chen
[Why] Enable OLED panels to save more power on the Linux platform by enabling CACP support on Linux. [How] Update abm_feature_support() to return ABM_CACP_SUPPORT for OLED panels. Enable ABM property for all eDP panels including OLED to support CACP via set_abm_level. Reviewed-by: Sun peng (Leo) Li <sunpeng.li@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Add block sequence support for bandwidth programming operationsBhuvanachandra Pinninti
[why] Bandwidth clock programming build and execution phases were coupled, preventing the HWSS from orchestrating them through block sequencing. [how] Separate clock programming into build and execute phases across latest versions. Build phase populates the clk_mgr internal block sequence array, then registers a single CLK_MGR_UPDATE_CLOCKS HWSS step. Execute phase dispatches the pre-built sequence. Add HWSS operations for clk_mgr_set_max_memclk, hubbub_program_watermarks, hubbub_program_arbiter, and hubbub_program_compbuf_segments. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Bhuvanachandra Pinninti <BhuvanaChandra.Pinninti@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Replace repeated no-native-i2c checks with ↵Wenjing Liu
force_i2c_over_aux field [Why] The compound condition checking dp_connector_no_native_i2c and no_ddc_pin was duplicated across many files, obscuring intent at every call site. [How] Add bool force_i2c_over_aux to struct dc_link, initialized once during link creation. Add link_get_ddc_aux_inst() helper to select the correct aux instance. Wire into link_service via construct_link_service_ddc(). Replace all duplicated condition checks and aux instance selection blocks with the new field and helper. No functional change. Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-01drm/amd/display: Update ONO PG Workaround for DCN42Leo Chen
[Why & How] There is an updated workaround for PG Repeater issue in DCN42. This PR is addressing the dynamic power gating use cases (Driver PG) to align with the new sequence. Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com> Signed-off-by: Leo Chen <leo.chen@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Introduce dc_plane_cm and migrate surface update color pathRafal Ostrowski
[Why] Begin convergence with upstream Color Manager refactor (fda768acb2a1 "drm/amd/display: Sync dcn42 with DC 3.2.373") by consolidating fragmented per-plane CM state (shaper, 3DLUT, blend, CM2) into a single dc_plane_cm structure shared by dc_plane_state and dc_surface_update. Legacy fields are gated behind TRIM_CM2 so that it keeps compatibility with other repositories. [How] Refactored to use newer structures. No functional behavior change intended. Under !TRIM_CM2 the legacy fields are still populated for compatibility with other repositories. v2: squash in conflicting types fix Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Remove get_utm_qos_model from soc_and_ip_translatorWenjing Liu
[Why] The QoS model is now populated directly in clock manager from firmware data. The translator function pointer is no longer needed. [How] - Remove get_utm_qos_model function pointer from soc_and_ip_translator_funcs - Remove associated forward declarations from soc_and_ip_translator.h Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add utm_qos_model pointer to clk_bw_paramsWenjing Liu
[Why] Add support for passing QoS model data from clock manager to bandwidth calculation consumers. [How] - Add forward declaration and const pointer for utm_qos_model in clk_bw_params Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add a new interface to set idle opts in clock managerNicholas Kazlauskas
[Why & How] For future use in migrating the idle optimizations message to PMFW to DC core. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Deprecate DMUB register offload functionalityAustin Zheng
[Why] The DMUB register offload feature should no longer be used. This was originally a debug feature for DCN21. No longer applicable to the DMUB programming model. [How] Remove DMUB register offload infrastructure including helper functions, structures, debug options, and register sequence macros. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>