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path: root/drivers/gpu/drm/amd/display/dc
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4 daysMerge tag 'drm-next-2026-10-31' of https://gitlab.freedesktop.org/drm/kernelLinus Torvalds
Pull drm fixes from Dave Airlie: "The final set of merge window fixes, from AMD mostly. with one set of panthor mmu fixes. amdgpu: - UALink fixes - Runtime PM fixes - GPUVM fixes - Mac fixes - HDMI fixes - DP MST fix - Userptr fix - SMU fixes - DSC fix - VCE/UVD sched teardown fix - Display runpm reference fix - Display TD-LUT fix - SMU 13.x fixes - SMU 14.x fixes - Gang submit fix - Passive DVI sink fix - USB4 tunnel fix - Freesync fix amdkfd: - SVM fixes - Fix doorbell allocation race - GC 12.1 fix - GPU reset fix - Buffer accounting fixes - Bounds checking fixes - Hotplug fixes - SVM fixes - CRIU fixes - GFX12 fix panthor: - Fix bugs in MMU handling" * tag 'drm-next-2026-10-31' of https://gitlab.freedesktop.org/drm/kernel: (52 commits) drm/amd/display: refresh cached HDMI FreeSync state drm/amd/display: Cap DSC bpp for USB4 DP tunnels drm/amd/display: Poll passive DVI sinks for EDID readiness drm/amdgpu: re-enable GFXOFF for compute on GFX12 drm/amdkfd: evict the queues only once for CRIU PROCESS_INFO drm/amdgpu: drop the gang leader reference when freeing gang jobs drm/amdkfd: send SMI process and VM fault events only to allowed clients drm/amdkfd: validate SRAT subtables before parsing drm/amd/pm: preserve committed OD features for SMU 14.0.2 drm/amd/pm: add zero fan stop temperature support on smu 14.0.2 drm/amd/pm: preserve committed OD features for SMU 13.0.0/13.0.7 drm/amd/display: Initialize missing TD-LUT programming inputs drm/amdkfd: split vram_pages of SVM ranges prefetched without a GPU mapping drm/amdgpu: reject CS chunks too large for kvmalloc() drm/amd/display: take a runtime PM reference only when a CRTC turns on drm/amdgpu: guard VCE/UVD sched entity teardown on failed probe drm/amdkfd: stop restore retries on device unplug drm/amdkfd: tear down KFD processes before early fini_sw on disconnect drm/amdkfd: Validate the control stack of a restored queue drm/amdkfd: correct vram_available calculation ...
7 daysdrm/amd/display: Initialize missing TD-LUT programming inputsAvi Weiss
dml_core_mode_programming() memsets (clears) its scratch structure before calculating TD-LUT settings, but does not initialize tdlut_mpc_width_flag or is_gfx11. Both inputs therefore remain false regardless of the plane configuration which can result in incorrect calculations. Initialize both fields using the same sources as the mode support path (now both paths are aligned). Fixes: 70839da63605 ("drm/amd/display: Add new DCN401 sources") Signed-off-by: Avi Weiss <thnkslprpt@gmail.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit ad8d216e7d9fc050cdf39278e5fae17f61c36931) Cc: stable@vger.kernel.org
10 daysMerge tag 'drm-next-2026-10-21' of https://gitlab.freedesktop.org/drm/kernelLinus Torvalds
Pull drm updates from Dave Airlie: "Highlights: - core: a lot of atomic refactoring in progress, panic got split into a core/helpers model - amdgpu: enables HDMI 2.1 FRL and other good things finally, UAlink over Ethernet support - xe: has a bunch of CRI support, ras error for bad vram, memory offlining support. - msm: enables a bunch more GPUs. Otherwise it's a the usual mountain of stuff all over the place. Details: rust: - I/O tree shared with driver-core - DMA tree shared with driver-core - allow aux registration data closures to return covariant sub-fields - Implement Send and Sync for MapleTree - add pci resource flags and IORESOURCE_MEM_64 drm/rust: - add dma_fence abstraction - init DRM registrations and their data in place - drop unused flags argument to registration vgaarb: - rework API to pass a private ptr instead of pci device sound: - adapt to omapdrm changes gem: - add callback for handle count going to 0 gpusvm: - share one HMM fault and keep single mappings inline pagemap: - Prevent CPU stalls during unbounded pagemap teardown dma-fence: - fix docs vga_switcheroo: - disconnect from fbcon - update fbcon from within fbdev emulation atomic: - move DRM from state reset callbacks to atomic_create_state - remove drm_simple_encoder_init panic: - split into core and helpers buddy: - improve dirty tracking clients: - improve vmap handling - fbdev: Move helpers from drm_kms_helper.ko to drm_client_lib.ko display: - export HDMI SCDC status data via debugfs - rework SCDC for better HDMI 2.0 support - dp/mst: improve DPCD compliance edid: - parse AMD VSDB - parse ALLM/VRR capabilities - support detecting panel size log: - add drm_warn_ratelimited sched: - cleanup interface - add missing locking - fix run-queue cleanup - fix locking sysfb: - remove obsolete quirk for Lenovo D330 - fix panel orientation for non-native display modes - drop drm_class_device_register colorop: - provide DRM_COLOR_OP_FIXED_MATRIX bridge: - analogix: Support eDP lane mapping - ti-sn65dsi83: Support LVDS Channel B on SN65DSI84 - Select DRM_PANEL_BRIDGE for various drivers that require it - add chrontel ch7218a support panel: - panel-edp: Support MNE007QS3-F, TM140VDXP15, and KD116N36-30NB-A001 - samsung-s6d16d0: Use mipi_dsi_*_multi() functions - support Ilitek ILI7836A OLED plus DT bindings - support Novatek NT36532 plus DT bindings - convert several drivers to managed cleanup - fix Kconfig selections - edp: - Add support for BOE NV140FHM-T0A - Support CSOT MNE007QB1-1 - NV140WU2-M70 - ebbg-ft8719: Fix MODULE_LICENSE() string; Improve initialization - samsung: Share test-key helpers - ilitek-ili9882t: Support Ilitek IL79600A plus DT bindings - simple: Support Truly TFT320240-229-E plus DT bindings; Support BOE DV215FHM-R01 plus DT bindings - Refactor struct drm_panel to contain struct drm_bridge plus fallout in various panel drivers - Add support for BOE Novatek NT51021, Retroid Pocket 6, Raydium RM69220 DDIC panels, Sharp LQ138P1JX61 eDP, BOE NV140FHD-N43, AUO B140HAN04.0, AUO 0x0db3, panels. amdgpu: - use AMD VSDB for freesync - implement YUV-to-RGB with fixed-matrix colorop - enable FRL for HDMI - HDMI 2.1 freesync support - HDMI 2.1 ALLM support - HDMI 2.1 VRR support - UALoE (UALink over Ethernet) support - add syncobj_points to userq signal ioctl - drop unused kunit tests - NBIO/GC/MMHUB/SMU updates/fixes - GPU spatial partitioning updates - display kunit fixes - userq fixes - RGB quantization fixes - DC RMCM refactor - DP MST fixes - USB4 fixes - add new trace events - Rework display instance handling - stack frame size fixes for various compilers/configs - VCN 4/5 reset fixes - freesync updates - cursor refactor - Fix direct scanout alpha on some DRM_FORMATs - Expand Mac reserved memory workaround - Make runtime pm more fine grained amdkfd: - updates and fixes - GC 10 CU occupancy support radeon: - eDP fix for DCE3.2 iMacs xe: - add drm_ras netlink error event support - add memory page offlining support - introduce error threshold to drm_ras - fix stale GTT mappings on unmap - reject page faults for non-page fault mode scratch VM - enable CRI package and VRAM temperatures - introduce cold reset recovery - handle CRI+ power interval encoding - VF migration for multi-queue - handle exec queue teardown after hot unplug - alerts and controller enabling modifications - use IBCv3 on PTL - VRAM health check - report GT TDR and VM rebind faults using SIGID - add multi_queue_active_lrca debugfs - shrinker: Runtime PM reference for non-system memory - guc: Add simple KLV decoder helpers - debugfs: Expose per-engine idle status - Keep walking on SVM eviction failure - Nuke PTs only after unlinking contested VMAs - limit sg segment size to PAGE_SIZE on Xen PV - keep VF LMEM bar size low if no VFs - CPU binds and ULLS on migration queue - New PTL PCI ID - Enable PXP for NVL-S - Do not dma_fence_put zero fences in err_out path - Refresh TTM LRU on SVM prefetch - export device UID in sysfs i915: - rename GEN6_PCODE_DATA to match spec - fix incorrect RCU teardown order - fix potential UAF in command parsing - avoid WARN splat during RPS boosting race - use simpler min functions - Fixes to make i915 work well with PREEMPT_RT i915/display: - Enable CMRR (Content Match Refresh Rate) in fixed-RR VRR path - Switch DG2 MPLL to DPLL framework - DP-HDMI PCON DSC fixes - limit invalid joiner combinations - CDCLK related fixes and refactor around PCODE integration - Gate UHBR SST SDP splitting on sink caps - add HDMI TMDS audio bandwidth check - vswing/preemph override - enable AS SDP Skip frames - Handle negative configuration index on DP link caps for robustness - Preparation for enabling SDR plane color pipeline - An eDP quirk for HP Pavilion Plus - Introduce PME (Power Management Event) support on display hotplug - Handle VSC SDP revision 7 in unpack msm: - CI: - Dropped sc7180 trogdor lazor from the CI - Core: - Fixed msm_ioremap for resources without a name - Changed msm.separate_gpu_kms to default to auto selection - GPU: - Enable CLX (Current Limit eXtension) for gen8 to avoid exceeding limits on CX/GX rails - New GPUs: a830 (Pakala), a845 (Maili), a850 (Hawi), x2-85 (Mahua) - Fix VBIF halt mask on a306, which was preventing runpm suspend - Enable THP support for GEM buffers - Add modparam to disable waiting on fences in shrinker - Drop use of drm_prime_sg_to_page_array() - a5xx: don't read the GPMU registers on GPUs without a GPMU - a2xx/a3xx/a5xx: hangcheck progress detection - a6xx: gmuwrapper runpm fix - Calculate reported GMEM size based on active slices - Split a6xx/a7xx/a8xx catalog - DP: - Picked up some preparation patches for the MST support - Fixed reported status of the link training - DPU: - Fixed CRTC bandwidth computation - Fixed DSC programming - Fixed encoder disablement path - DSI: - Fixed VM leak in error path - Indention fix - MDP5: - Added MSM8952 configuration - Dropped incorrect cursor pipe on MSM8976/56 - HDMI: - Small fixes nouveau: - improve runtime PM on R570 GSP firmware - various fixes throughout the driver - dispnv50: support 2.147 GHz pixel clock in GB20x nova: - add initial uapi concept - add initial PRAMIN access support - add GpuMm centralized memory manager - add GPU VM and BAR1 support - add GPU interrupts and GSP events support - GSP messaging fixes tyr: - use bitfield! - zero unsupported and newly added GPU info fields - limit doorbell array to 17 entries exynos: - FIMD fixes - Fix clock leak on resume error path - Fix Sparse warnings by adding missing __iomem annotation - VIDI cleanup - Replace kmalloc() and copy_from_user() with memdup_user() amdxdna: - fix BO handling - Support AIE2 rev 9 - Fix UAF access in scheduler fences - Update workqueue interface - expose busy time via fdinfo ast: - support 256-byte EDID hyperv_drm: - remove support for pre win10 hosts komeda: - fix GLB_CORE_ID usage omap: - report HDMI hotplug events to ASoC HDMI codec panthor: - provide gpu_cache_flush tracepoint - improve dma_fence signalling latency - improve locking - export scheduling information via debugfs - Validate user-space input against firmware limits qaic: - reject BOs that exceed maximum page count - add missing include statements verisilicon: - fix hardware cursor offsets vkms: - implement YUV-to-RGB with fixed-matrix colorop gma500: - avoid unsupported ARGB formats in primary plane hibmc: - handle vblank interrupts correctly ivpu: - add DRM_IVPU_CAP_CMDQ_SET_PRIORITY - support command-queue priority ioctl - Simplify NULL-pointer handling in cleanup code arcpgu: - replace simple-display pipeline with regular atomic helpers aspeed: - replace simple-display pipeline with regular atomic helpers gm12u320: - replace simple-display pipeline with regular atomic helpers imagination: - various improvement to firmware interaction - add job to pvr_job_submit_fw trace event mali-dp: - fix runtime PM leak mcde: - replace simple-display pipeline with regular atomic helpers p111: - replace simple-display pipeline with regular atomic helpers - drop unsupported alpha formats from primary plane rcar-du: - support Renesas R-Car V4H DSC - dsi: Support larger transfers with AXI memory - Support RZ/G3L SoC repaper: - replace simple-display pipeline with regular atomic helpers rockchip: - dsi: improve PHY timings ssd130x: - support Solomon SSD1351 OLED plus DT bindings - ssd133x: upgrade color format to RGB565 - ssd132x: Set correct hardware window when clearing screen tve200: - replace simple-display pipeline with regular atomic helpers xen: - replace simple-display pipeline with regular atomic helpers v3d: - improve job handling under perfmon vc4: - reliably reset V3D - drop brcm,vc4-v3d compatible virtio: - fix damage handling - Support ARGB8888 for virtio primary planes. host1x: - Support partitioning imx: - Replace simple-display with regular atomic helpers mxsfb: - Support bus formats plus DT bindings tegra: - improve syncobj handling on submit panfrost: - add Mali-G68 support - improve GPU reset handling rockchip: - add HDMI 2.0 support to dw-hdmi-qp - improve HPD handling" * tag 'drm-next-2026-10-21' of https://gitlab.freedesktop.org/drm/kernel: (2324 commits) drm/adp: Switch to drm_atomic_helper_connector_create_state drm/malidp: Convert to atomic_create_state drm/vc4: Switch to drm_atomic_helper_connector_create_state drm/sysfb: Switch to drm_atomic_helper_connector_create_state drm/solomon: ssd130x: Switch to drm_atomic_helper_connector_create_state drm/imx: ipuv3: Switch to drm_atomic_helper_connector_create_state drm/hyperv: Switch to drm_atomic_helper_connector_create_state drm/bridge: megachips: Switch to drm_atomic_helper_connector_create_state drm/bridge: lontium-lt8912b: Switch to drm_atomic_helper_connector_create_state drm/arm: komeda: Switch to drm_atomic_helper_connector_create_state drm/appletbdrm: Fix incorrect error message on encoder attach failure drm/sun4i: hdmi: Convert to drmm_connector_hdmi_init() drm/rockchip: rk3066_hdmi: Advertise HDMI 1.4 capabilities drm/bridge: lontium-lt9611: Advertise HDMI 1.4 capabilities drm/bridge: ite-it66121: Advertise HDMI 1.2 capabilities drm/bridge: ite-it6263: Advertise HDMI 1.3 capabilities drm/bridge: ite-it6263: Drop redundant .mode_valid hook drm/bridge: inno-hdmi: Advertise HDMI 1.2 capabilities drm/bridge: adv7511: Advertise HDMI 1.2 capabilities drm/sched: Document entity->stopped is protected by entity->lock ...
14 daysdrm/amd/display: Fix swap in median3() for DSC rate controlKeita Morisaki
median3() is meant to return the median of three values, but its last compare-and-swap step swaps b and c instead of a and b. When c is smaller than both a and b, it returns max(a, b) instead of min(a, b). For example, median3(2, 3, 1) returns 3 instead of 2. _do_calc_rc_params() always passes 0 as the first argument, and the second argument is never below 12. So whenever the third argument is negative, first_line_bpg_offset (and second_line_bpg_offset for 4:2:0) is set to the second argument instead of 0. Fix this by swapping a and b in the last step, as intended. Note that this change does not affect valid DSC configurations. The third argument is negative only when bits per pixel exceeds the uncompressed rate of the colour format: - 3 * bpc for 4:4:4, 3 * bpc + 2 for RGB - 2 * bpc for 4:2:2 - 1.5 * bpc for 4:2:0 Fixes: 97bda0322b8a ("drm/amd/display: Add DSC support for Navi (v2)") Signed-off-by: Keita Morisaki <kmta1236@gmail.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 1ddc4bc97a62fc89d9d3681413d9f977e1fa1a83) Cc: stable@vger.kernel.org
14 daysdrm/amd/display: Adjust HDMI FRL LT timeoutIlya Bakoulin
[Why & How] Extend LT timeout for link rates <16G to avoid intermittent compliance failures. Reviewed-by: Relja Vojvodic <relja.vojvodic@amd.com> Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 378e096423269a466d23a5d5ce65051e8ef1e474)
14 daysdrm/amd/display: Fix HDMI FRL FFE compliance testIlya Bakoulin
[Why & How] The FFE electrical compliance test behavior is not correct. The driver doesn't properly iterate over the FFE levels and select PS/DE based on test request and/or cable-ID. Fix the initialization of the link state so that when the polling loop takes over, the test proceeds as described in the spec. Reviewed-by: Relja Vojvodic <relja.vojvodic@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 1903c3389c81bc65f57f0edeea879359d674bb33)
2026-10-15drm/amd/display: Fix NULL sink dereference in USB4 bandwidth functionsSrinivasan Shanmugam
allocate_usb4_bandwidth_for_stream() and allocate_usb4_bandwidth() both use ASSERT(stream->sink) before dereferencing stream->sink->link. ASSERT is compiled out in production builds, so a NULL stream->sink causes a NULL pointer dereference. link_set_dpms_off() already guards two earlier accesses to stream->sink with explicit NULL checks, confirming that stream->sink can legitimately be NULL. The subsequent call to deallocate_usb4_bandwidth() had no equivalent guard. Replace the ASSERT() calls with proper NULL checks that return false early, and add a matching stream->sink guard at the call site in link_set_dpms_off() consistent with the surrounding pattern. v2: Keep the existing ASSERT() calls for diagnostics (to report unexpected NULL sink), and add explicit NULL checks that return false before dereferencing stream->sink. Also add a matching stream->sink guard at the deallocation call site in link_set_dpms_off(). (Alex) Fixes: 8fa813b7fd1e ("drm/amd/display: Remove sink usage from DPMS") Reported-by: Dan Carpenter <error27@gmail.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: Dominik Kaszewski <dominik.kaszewski@amd.com> Cc: George Zhang <george.zhang@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Roman Li <Roman.Li@amd.com> Cc: Ivan Lipski <ivan.lipski@amd.com> Cc: Dan Wheeler <daniel.wheeler@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 98029a0ce61feb52c563f65349dd9b25f672e355) Cc: stable@vger.kernel.org
2026-10-07drm/amd/display: Promote DC to 3.2.401Ashwin Santhosh
This version brings along the following updates: - Add HDMI RR and SCDC skips. - Add debug option to override low power SR latencies. - Allow skipping link bandwidth clear. - Handle virtual link encoder. - Improve MCM shaper/3DLUT programming and DTN logging. - Only reprogram DRR when v_total values change. - Refactor DMUB fast lock sequencing. - Send HDMI VRR metadata in VTEM info packet slot. - Set cursor_offload for all pipes for a given stream. - Skip link off frame count for general UI. - Update link training no timeout behaviour on HDMI. Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ashwin Santhosh <Ashwin.Santhosh@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Add debug option to override low power SR latenciesAlvin Lee
[Description] - Add debug options to override low power SR latencies - Match regular SR latency debug override Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Add dcn42b project idDillon Varone
[WHY&HOW] Add project ID to distinguish dcn42b from dcn42. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Handle virtual link encoderSridevi Arvindekar
[Why/How] Fix check for virtual link encoder Reviewed-by: Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Revert "avoid to write signal specific for tmds"Joshua Aberback
This reverts commit 93179870ae52d1663080655fb8f0170a82cf9951. The change regressed HDMI output on the TMDS-to-FRL switch. Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Update link training no timeout behaviour on HDMIRelja Vojvodic
[Why & How] - HMDI link training compliance testing fails when no timeout bit is set - Update condition to skip some link training logic when no timeout is set Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Assign alt wa bit in fams2 cmdAlvin Lee
[Description] Assign the workaround bit to ensure it propagates to FW Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Prepare DSC configuration before BLS executionRafal Ostrowski
[Why] DSC sequence operations calculated configuration during execution and passed OPTC outputs through pointers into other sequence steps. This coupled consumers to step storage and mixed calculation with programming. [How] Merge the DSC configuration operations into DSC_SET_CONFIG. Prepare register values in each DSC instance during build and pass OPTC values by value to timing-generator and stream-encoder operations. Share stream composition while preserving link-update and ODM padding. Use the correct DCN401 preparation callback and remove the legacy ops. Validate local composition inputs and capacity, stop immediate programming on preparation failure, and publish prepared caches only on success. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: allow skipping link bandwidth clearMartin Tsai
[why] To set link bandwidth with zero could hit error protection from Sink panel to fail link training and cause screen corruption. [how] To skip link bw cleaning in two conditions: 1. eDP v1.5 or latter, because the last write will take effect. 2. Sink requires not to clear it. Reviewed-by: Anthony Koo <anthony.koo@amd.com> Signed-off-by: Martin Tsai <Martin.Tsai@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Skip link off frame count for general UIAllen Li
[Why&How] To improve power saving of Replay, skip the link off frame count check for general UI in DC mode. Also disable timing sync in the same condition. Reviewed-by: ChunTao (Chun-Tao) Tso <chuntao.tso@amd.com> Signed-off-by: Allen Li <Allen.Li@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Refactor DMUB fast lock sequencingRafal Ostrowski
[WHY] Resolve fast-lock policy before execution and avoid queuing no-op steps. Remove duplicated per-ASIC command construction. [HOW] Use one fast-lock opcode, parameter structure and executor. Capture the service handle and precomputed Inbox0 command. Keep separate SubVP and generic capability hooks and preserve the lock manager's original support and split feature gates. Retain the unused SubVP enumerator and existing opcode values. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Set cursor_offload for all pipes for a given streamAlvin Lee
[Description] - When using the cursor offload path, the cursor_offload flag must be set for each DPP and HUBP driving the stream - Previous implementation only sets the flag in the DPP and HUBP for the OTG master pipe - Add helper function to populate an array of DPP's and HUBP's that need to have the cursor_offload flag set - This is to avoid passing in pipe_ctx to hwss execution params Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Add HDMI RR and SCDC skipsIlya Bakoulin
[Why/How] - Add debug key to avoid enabling RR by default. - Skip SCDC access if sink or SCDC cap not present Reviewed-by: Relja (Reggie) Vojvodic <relja.vojvodic@amd.com> Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: only reprogram DRR when v_total values changeAric Cyr
[Why] dc_stream_adjust_vmin_vmax() programmed the OTG on every call. FreeSync BTR calls it once per vblank, so identical v_total values were rewritten every frame, each one paying dc_exit_ips_for_hw_access() and, when FAMS is enabled, a blocking DMUB round trip from setup_manual_trigger(). [How] Return early when timing_adjust_pending is clear and every v_total field already matches the request, so hardware is only touched when the values change. stream->adjust is still updated on every path that continues, so a later commit programs the requested values. timing_adjust_pending is the existing "stream->adjust has not reached hardware" marker, so keep it accurate wherever hardware is left untouched: set_drr_and_clear_adjust_pending() now sets it when called with null params, which resets DRR in the OTG during pipe back-end teardown, and the max_v_total overflow path only clears it when set_long_vtotal() runs. Reviewed-by: Josip Pavic <josip.pavic@amd.com> Signed-off-by: Aric Cyr <Aric.Cyr@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: log MCM shaper and 3D LUT mode in the DTN logHarry Wentland
On DCN4 the per-plane MCM shaper and 3D LUT state wasn't visible in the DTN log: dcn401 wired read_mpcc_state to mpc1_read_mpcc_state, which only reads the base MPCC blend registers, and the MPCC section didn't print the LUT fields even where they were populated. Add mpc401_read_mpcc_state to also read MPCC_MCM_3DLUT_MODE (mode current and size) and MPCC_MCM_SHAPER_CONTROL (mode current), and print SHAPER, 3DLUT and 3DLUT_SIZE columns in the MPCC section. Mode is 0 bypass, 1 RAM_A, 2 RAM_B; 3DLUT_SIZE is 0 for 17x17x17 and 1 for 9x9x9. Assisted-by: Copilot:claude-opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-02Revert "drm/amd/display: replace STATIC_IFN_KUNIT with VISIBLE_IF_KUNIT"Alex Deucher
This reverts commit 7e9fca772695c65f97493272e2e7cd475f202965. This series breaks the build when CONFIG_KUNIT=y and CONFIG_DRM_AMD_DC_KUNIT_TEST=n. When CONFIG_KUNIT=y, the functions are not static, but when CONFIG_DRM_AMD_DC_KUNIT_TEST=n, they should be. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-02Revert "drm/amd/display: replace EXPORT_IF_KUNIT with EXPORT_SYMBOL_IF_KUNIT"Alex Deucher
This reverts commit b6b813e046e475bb3fe209d74f1df70033b5b98e. This series breaks the build when CONFIG_KUNIT=y and CONFIG_DRM_AMD_DC_KUNIT_TEST=n. When CONFIG_KUNIT=y, the functions are not static, but when CONFIG_DRM_AMD_DC_KUNIT_TEST=n, they should be. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-02Revert "drm/amd/display: drop INLINE_IFN_KUNIT"Alex Deucher
This reverts commit 5a98f454a61197761c4c5e8eed948dea2b9f5a69. This series breaks the build when CONFIG_KUNIT=y and CONFIG_DRM_AMD_DC_KUNIT_TEST=n. When CONFIG_KUNIT=y, the functions are not static, but when CONFIG_DRM_AMD_DC_KUNIT_TEST=n, they should be. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Fix sanitizer check for the DML frame size limitSasha Levin
Building x86_64 allmodconfig with clang fails: .../dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c:10491:13: error: stack frame size (3128) exceeds limit (3072) in 'dml_core_mode_programming' [-Werror,-Wframe-larger-than] That config enables both KASAN and UBSAN, and should get the 4096 byte limit meant for clang COMPILE_TEST sanitizer builds. The check in the dml and dml2_0 Makefiles concatenates the three symbols with no separator: ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)$(CONFIG_UBSAN)),y) KASAN and KCSAN cannot be enabled together, so before UBSAN was added the string was at most "y". UBSAN can be enabled alongside either of them, and with both set the string becomes "yy", $(filter y,yy) is empty, and the build falls through to the non-sanitizer limit of 3072. Adding UBSAN to the check therefore lowered the limit for the most heavily instrumented builds instead of raising it. Separate the symbols with spaces so that $(filter) sees individual words, and test for a non-empty result. Only the configs with two sanitizers enabled change behaviour. Found by KernelCI builds of the linus-next tree. Fixes: ebf8b0fd8508 ("drm/amd/display: Relax DML frame limit with UBSAN") Assisted-by: LLM Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 0400d53fd03e7d4beb09fdabda42a7b2c4ca465d) Cc: stable@vger.kernel.org
2026-10-01drm/amd/display: Mark DCE 6.4 as not APUTimur Kristóf
DCE 6.4 is found in Oland chips, which were advertised as low-end gaming GPUs in 2013~2015 and then have been sold as low-end workstation GPUs until 2017~2019. These are not APUs. Fixes: 7c15fd86aaec ("drm/amd/display: dc/dce: add initial DCE6 support (v10)") Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://patch.msgid.link/20260923122033.1046651-3-timur.kristof@gmail.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 1072aa811ea1e61d5f763e4ec1bc6d24bb61f14a) Cc: stable@vger.kernel.org
2026-10-01drm/amd/display: Fix fast updates on DCE 8.1Timur Kristóf
DCE8 should use legacy fast updates. This was already set for DCE 8.0 and 8.3, but it seems that DCE 8.1 (found in Kaveri chips) was forgotten. This fix should be backported to all kernel versions that have "Refactor fast update to use new HWSS build sequence", but this patch won't apply cleanly to older kernels due to another refactor in "Remove dc param from check_update". Fixes: 0baae6246307 ("drm/amd/display: Refactor fast update to use new HWSS build sequence") Fixes: 9ec11bb842b6 ("drm/amd/display: Remove dc param from check_update") Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://patch.msgid.link/20260923122033.1046651-2-timur.kristof@gmail.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 57605379559e3b5044c8274a1010ec658e5e73af) Cc: stable@vger.kernel.org
2026-10-01drm/amd/display: Fix fast updates on DCE 6.xTimur Kristóf
DCE6 should use legacy fast updates, just like all DCE8 - DCN2. Set that flag for DCE 6.0, 6.1 and 6.4 (all DCE6 versions). Technically DCE6 should have been included when the fast update code was refactored, but it just happened to work until now. A recent commit "Attach only plane updates that actually changed" has exposed this issue because with that commit, DC accidentally took the new fast update code path for DCE6 as well, which caused it to boot into a black screen with a flip done timeout. This fix should be backported to all kernel versions that have "Refactor fast update to use new HWSS build sequence", but this patch won't apply cleanly to older kernels due to another refactor in "Remove dc param from check_update". Fixes: 0baae6246307 ("drm/amd/display: Refactor fast update to use new HWSS build sequence") Fixes: 9ec11bb842b6 ("drm/amd/display: Remove dc param from check_update") Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://patch.msgid.link/20260923122033.1046651-1-timur.kristof@gmail.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 698fda6e360625850413a2d1a90b72ae5f03073d) Cc: stable@vger.kernel.org
2026-10-01drm/amd/display: Preserve eDP mode on initial ASSR failureArthur Heymans
Commit 56d8ce9d8c17 ("drm/amd/display: Apply correct panel mode when reinitializing hardware") made ASSR failure fall back to the default panel mode unless eDP mode had previously been applied. However, dc_link is zero-initialized and DP_PANEL_MODE_DEFAULT is zero. Before the first call to dp_set_panel_mode(), panel_mode therefore looks like a previously applied default mode. If ASSR setup fails during the first link training attempt, the driver incorrectly trains the eDP link using the default scrambling mode. On a Google Vilboz Chromebook running self-built coreboot firmware and PSP verstage, this leaves the panel mostly black with corrupted output along the top edge. Track whether panel_mode has actually been initialized, and only consult the saved mode after it has been applied. This retains the recovery behavior while preserving eDP mode during initial link training. Fixes: 56d8ce9d8c17 ("drm/amd/display: Apply correct panel mode when reinitializing hardware") Assisted-by: Pi:gpt-5.6-sol Reviewed-by: George Zhang <george.zhang@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit ccb6c2702033f1002b45807fb3cc938760f26f78) Cc: stable@vger.kernel.org # 6.4.x
2026-10-01drm/amd/display: fix unused function warningsArnd Bergmann
When CONFIG_DRM_AMD_DC_DCE is disabled, most functions insde dce110_hwseq.c are no longer referenced, causing a lot of warnings such as drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dce110/dce110_hwseq.c:3510:13: error: 'dce110_enable_analog_link_output' defined but not used [-Werror=unused-function] 3510 | static void dce110_enable_analog_link_output( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dce110/dce110_hwseq.c:3391:13: error: 'dce110_set_cursor_attribute' defined but not used [-Werror=unused-function] 3391 | static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) Replace the #ifdef with an IS_ENABLED() check that leads to an empty function in this configuration, so the compiler can eliminate the unused functions and not complain about it. Fixes: cd2cfe4d1504 ("drm/amd/display: gate DCE ASIC code behind CONFIG_DRM_AMD_DC_DCE") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Fix sanitizer check for the DML frame size limitSasha Levin
Building x86_64 allmodconfig with clang fails: .../dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c:10491:13: error: stack frame size (3128) exceeds limit (3072) in 'dml_core_mode_programming' [-Werror,-Wframe-larger-than] That config enables both KASAN and UBSAN, and should get the 4096 byte limit meant for clang COMPILE_TEST sanitizer builds. The check in the dml and dml2_0 Makefiles concatenates the three symbols with no separator: ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)$(CONFIG_UBSAN)),y) KASAN and KCSAN cannot be enabled together, so before UBSAN was added the string was at most "y". UBSAN can be enabled alongside either of them, and with both set the string becomes "yy", $(filter y,yy) is empty, and the build falls through to the non-sanitizer limit of 3072. Adding UBSAN to the check therefore lowered the limit for the most heavily instrumented builds instead of raising it. Separate the symbols with spaces so that $(filter) sees individual words, and test for a non-empty result. Only the configs with two sanitizers enabled change behaviour. Found by KernelCI builds of the linus-next tree. Fixes: ebf8b0fd8508 ("drm/amd/display: Relax DML frame limit with UBSAN") Assisted-by: LLM Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Promote DC to 3.2.400Ashwin Santhosh
This DC patchset brings improvements in multiple areas. - Stabilizes public lifecycle APIs, and adds DCN42/DCN60 support. - Adds DCN60 clock overrides, DCN42 PMO/P-state support, QoS handling for invalid PMFW tables, urgent-watermark overrides, and improved self-refresh timing. - Improve HDMI 2.1 reliability - Enables DMUB hardware cursor offload and improves cursor/cache behavior. Signed-off-by: Ashwin Santhosh <Ashwin.Santhosh@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Sunpeng Li <sunpeng.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: adjust floating point format for gamut remap when neededClay King
[Why] The MPCCs different gamut remap matrices allow for S2D13 and S3D12 floating point formats, but only S2D13 is used. There may be cases where more integer bits are required. [How] Switch to S3D12 if any entries in the remap matrix cannot fit in S2D13. Otherwise, prefer the extra precision of S2D13. Communicate the max value that hw can support to dm via dc color caps. Signed-off-by: Clay King <clayking@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Don't round up cursor width to nearest 64Alvin Lee
[Description] Rounding up cursor width was only used to calculate total size in previous generations. Do not use the rounded up cursor width in hardware programming. Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Update default clocks for DCN60 lite3 variantNicholas Kazlauskas
[Why] These are important for getting correct DP and audio output. The wrong pixel clock will be used otherwise. [How] Update the default clocks for the DCN60 lite3 variant. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Enable dcn42 pstate pmoDmytro Laktyushkin
Set a flag to enable pstate pmo, we want to always allow pstate support on dcn42 Partial application: DCN42B resource constructor only. Fixes: 6352e6027307 ("drm/amd/display: Enable dcn42 pstate pmo") Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Block DSC Padding on DPRelja Vojvodic
[Why & How] - BSOD was found on a DP config due to incomplete DSC padding implementation for DP - Block DSC padding on DP until fully implemented Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: George Shen <george.shen@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Fix zero dlg_reg write to program_ext_vblankCharlene Liu
[why] fix some non initialized reg_offset allow z8_only to program_ext_vblank [CLEANED] for dml2.1, dlg_reg moved inside hubp_reg add current_compbuf_size check ensure HW state reached. Partial application: DCN42 register-list additions only. Fixes: 0a5e0416e191 ("drm/amd/display: Add DCN42B code to DC") Fixes: 002f32db0d42 ("drm/amd/display: Fix dcn401_optimize_bandwidth") Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Reviewed-by: Leo Chen <leo.chen@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Add urgent watermark override for DCN42Ovidiu Bunea
[why & how] Out-of-urgent bandwidth delivery to DCN is very poor under workloads. Even after asserting urgent, empirical data shows urgent return BW delays of up to 100 μs. Override the value when programming watermarks to avoid modifying mode support. Maintain the DML's calculated value as a floor. Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Fix VTG programming for dcn60Dillon Varone
[WHY&HOW] VTG params should be corrected based on HW expectation: - FP2 = v_bp - vstartup_start (if vstartup is after vsync), else 0 - vcount_init = OTG SOF position from vsync (0) or vtotal depending on vstartup position Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Fix HDMI2.2 LT timeout durationIlya Bakoulin
[Why/How] Current method of keeping track of the LT timeout can cause the actual elapsed time to creep past the spec-defined limits. Adjust the behavior to make timeouts more consistent. Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Chris Park <chris.park@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: avoid to write signal specific for tmdsCharlene Liu
[why] some panel will generate HPD if receive invalid the action. Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Remove dead self-refresh BLS stepsPiotr Maziarz
[WHY] The DCN10 post-unlock BLS path still emitted self-refresh suppression steps that are dead for this flow. Keeping them also left non-compliant BLS enums and documentation behind after the architecture cleanup. [HOW] Removed the dead DCN10 BLS producer path, dropped the associated BLS enums, params, helpers, dispatcher cases, unit-test dumper cases, and updated the BLS documentation. Kept the shared dcn10_update_pending_status consumer because later DCN generations still use it. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Dispatch HUBBUB_SOFT_RESET through hubbub_funcsPiotr Maziarz
[WHY] hubbub_soft_reset_params carried the callee itself as a function pointer, so the step was not fully described by its parameters. The core_gtest dumper could only record hubbub and reset, which means two sequences calling different functions compare equal. It also forced dcn401_hwseq to name the dcn10 symbol hubbub1_soft_reset directly, because hubbub_funcs had no slot for a soft reset. [HOW] Added soft_reset to hubbub_funcs and pointed hubbub4_01_funcs, hubbub42_funcs and hubbub60_funcs at hubbub1_soft_reset, the same way allow_self_refresh_control is already shared. Dropped the function pointer from the params struct and the add helper, and had the executor call hubbub->funcs->soft_reset. The dcn10_hubbub.h include in dcn401_hwseq.c is no longer needed. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Drop disallow_self_refresh_applied output paramPiotr Maziarz
[WHY] Besides programming the hubbub, the HUBBUB_ALLOW_SELF_REFRESH_CONTROL executor wrote through an output pointer into hwseq->wa_state to record that the MPO stutter workaround had been applied. That bookkeeping has no relationship to the register write and makes the operation mutate a logical object while the sequence runs. [HOW] Removed the pointer from hubbub_allow_self_refresh_control_params and from the add helper, leaving the executor a plain pass through to hubbub->funcs->allow_self_refresh_control. hwss_build_post_unlock_full_sequence now sets the workaround flag itself, inside the same condition that decides to emit the step. TG_GET_FRAME_COUNT is left as is: its out parameter is the read back register value, and reading it after the write matches the legacy implementations. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Rename HUBBUB_FORCE_PSTATE_CHANGE_CONTROL wait fieldPiotr Maziarz
[WHY] hubbub_force_pstate_change_control_params::wait was passed as the allow argument of hubbub_funcs::force_pstate_change_control, which drives DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE. Sitting three lines above a udelay(500), the name read as a timing control and invited the wrong conclusion about what the field does. [HOW] Renamed the field to allow and updated the add helper signature, the executor, the core_gtest dumper and comparator, and the affected core_golden entry. No functional change. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Remove OPP_SET_MPCC_DISCONNECT_PENDINGPiotr Maziarz
[WHY] The operation wrote no hardware register. Its executor only set opp->mpcc_disconnect_pending, a driver side flag, which breaks the rule that a block sequence step programs a hardware block rather than mutating logical objects. It was also split across phases: written while the pre-unlock sequence executed, then read and cleared while the post-unlock sequence was still being built. [HOW] Deleted the enum value, the params struct, the add helper, the executor and the dispatch case. dcn401_plane_atomic_disconnect_sequence now sets the flag during the build phase, matching what dcn10, dcn20, dcn201, dcn35, dcn3ag and dcn42b already do. Updated the operation specs and the core_gtest dumper. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Flatten OPP_SET_DISP_PATTERN_GENERATOR parametersPiotr Maziarz
[WHY] opp2_set_disp_pattern_generator read debug.disable_dynamic_expansion_for_test_pattern through opp->ctx->dc while the sequence was executing. A block sequence operation must take its inputs from a flat parameter list resolved during the build phase, so this hid an input from the recorded sequence and left the FMT_DYNAMIC_EXP_CNTL branch unreachable from the OPP unit tests. [HOW] Added disable_dyn_exp_for_test_pattern to opp_funcs::opp_set_disp_pattern_generator and to opp_set_disp_pattern_generator_params, and updated every caller to pass dc->debug.disable_dynamic_expansion_for_test_pattern explicitly. Updated the unit test mocks and the core_gtest dumper, and extended opp_gtest to cover both values of the new flag. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Add temporary programming for port control in dc_initAlvin Lee
[Description] Add the POR setting for SDP_PORT_CONTROL into dc init sequence. This is temporary until the initialization moves into pre-OS DMCUB. Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>