summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/display/dc/hwss
AgeCommit message (Collapse)Author
2026-10-07drm/amd/display: Prepare DSC configuration before BLS executionRafal Ostrowski
[Why] DSC sequence operations calculated configuration during execution and passed OPTC outputs through pointers into other sequence steps. This coupled consumers to step storage and mixed calculation with programming. [How] Merge the DSC configuration operations into DSC_SET_CONFIG. Prepare register values in each DSC instance during build and pass OPTC values by value to timing-generator and stream-encoder operations. Share stream composition while preserving link-update and ODM padding. Use the correct DCN401 preparation callback and remove the legacy ops. Validate local composition inputs and capacity, stop immediate programming on preparation failure, and publish prepared caches only on success. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Chris Park <chris.park@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Refactor DMUB fast lock sequencingRafal Ostrowski
[WHY] Resolve fast-lock policy before execution and avoid queuing no-op steps. Remove duplicated per-ASIC command construction. [HOW] Use one fast-lock opcode, parameter structure and executor. Capture the service handle and precomputed Inbox0 command. Keep separate SubVP and generic capability hooks and preserve the lock manager's original support and split feature gates. Retain the unused SubVP enumerator and existing opcode values. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: Set cursor_offload for all pipes for a given streamAlvin Lee
[Description] - When using the cursor offload path, the cursor_offload flag must be set for each DPP and HUBP driving the stream - Previous implementation only sets the flag in the DPP and HUBP for the OTG master pipe - Add helper function to populate an array of DPP's and HUBP's that need to have the cursor_offload flag set - This is to avoid passing in pipe_ctx to hwss execution params Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-07drm/amd/display: log MCM shaper and 3D LUT mode in the DTN logHarry Wentland
On DCN4 the per-plane MCM shaper and 3D LUT state wasn't visible in the DTN log: dcn401 wired read_mpcc_state to mpc1_read_mpcc_state, which only reads the base MPCC blend registers, and the MPCC section didn't print the LUT fields even where they were populated. Add mpc401_read_mpcc_state to also read MPCC_MCM_3DLUT_MODE (mode current and size) and MPCC_MCM_SHAPER_CONTROL (mode current), and print SHAPER, 3DLUT and 3DLUT_SIZE columns in the MPCC section. Mode is 0 bypass, 1 RAM_A, 2 RAM_B; 3DLUT_SIZE is 0 for 17x17x17 and 1 for 9x9x9. Assisted-by: Copilot:claude-opus-4.8 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: fix unused function warningsArnd Bergmann
When CONFIG_DRM_AMD_DC_DCE is disabled, most functions insde dce110_hwseq.c are no longer referenced, causing a lot of warnings such as drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dce110/dce110_hwseq.c:3510:13: error: 'dce110_enable_analog_link_output' defined but not used [-Werror=unused-function] 3510 | static void dce110_enable_analog_link_output( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dce110/dce110_hwseq.c:3391:13: error: 'dce110_set_cursor_attribute' defined but not used [-Werror=unused-function] 3391 | static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) Replace the #ifdef with an IS_ENABLED() check that leads to an empty function in this configuration, so the compiler can eliminate the unused functions and not complain about it. Fixes: cd2cfe4d1504 ("drm/amd/display: gate DCE ASIC code behind CONFIG_DRM_AMD_DC_DCE") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Remove dead self-refresh BLS stepsPiotr Maziarz
[WHY] The DCN10 post-unlock BLS path still emitted self-refresh suppression steps that are dead for this flow. Keeping them also left non-compliant BLS enums and documentation behind after the architecture cleanup. [HOW] Removed the dead DCN10 BLS producer path, dropped the associated BLS enums, params, helpers, dispatcher cases, unit-test dumper cases, and updated the BLS documentation. Kept the shared dcn10_update_pending_status consumer because later DCN generations still use it. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Dispatch HUBBUB_SOFT_RESET through hubbub_funcsPiotr Maziarz
[WHY] hubbub_soft_reset_params carried the callee itself as a function pointer, so the step was not fully described by its parameters. The core_gtest dumper could only record hubbub and reset, which means two sequences calling different functions compare equal. It also forced dcn401_hwseq to name the dcn10 symbol hubbub1_soft_reset directly, because hubbub_funcs had no slot for a soft reset. [HOW] Added soft_reset to hubbub_funcs and pointed hubbub4_01_funcs, hubbub42_funcs and hubbub60_funcs at hubbub1_soft_reset, the same way allow_self_refresh_control is already shared. Dropped the function pointer from the params struct and the add helper, and had the executor call hubbub->funcs->soft_reset. The dcn10_hubbub.h include in dcn401_hwseq.c is no longer needed. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Drop disallow_self_refresh_applied output paramPiotr Maziarz
[WHY] Besides programming the hubbub, the HUBBUB_ALLOW_SELF_REFRESH_CONTROL executor wrote through an output pointer into hwseq->wa_state to record that the MPO stutter workaround had been applied. That bookkeeping has no relationship to the register write and makes the operation mutate a logical object while the sequence runs. [HOW] Removed the pointer from hubbub_allow_self_refresh_control_params and from the add helper, leaving the executor a plain pass through to hubbub->funcs->allow_self_refresh_control. hwss_build_post_unlock_full_sequence now sets the workaround flag itself, inside the same condition that decides to emit the step. TG_GET_FRAME_COUNT is left as is: its out parameter is the read back register value, and reading it after the write matches the legacy implementations. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Rename HUBBUB_FORCE_PSTATE_CHANGE_CONTROL wait fieldPiotr Maziarz
[WHY] hubbub_force_pstate_change_control_params::wait was passed as the allow argument of hubbub_funcs::force_pstate_change_control, which drives DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE. Sitting three lines above a udelay(500), the name read as a timing control and invited the wrong conclusion about what the field does. [HOW] Renamed the field to allow and updated the add helper signature, the executor, the core_gtest dumper and comparator, and the affected core_golden entry. No functional change. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Remove OPP_SET_MPCC_DISCONNECT_PENDINGPiotr Maziarz
[WHY] The operation wrote no hardware register. Its executor only set opp->mpcc_disconnect_pending, a driver side flag, which breaks the rule that a block sequence step programs a hardware block rather than mutating logical objects. It was also split across phases: written while the pre-unlock sequence executed, then read and cleared while the post-unlock sequence was still being built. [HOW] Deleted the enum value, the params struct, the add helper, the executor and the dispatch case. dcn401_plane_atomic_disconnect_sequence now sets the flag during the build phase, matching what dcn10, dcn20, dcn201, dcn35, dcn3ag and dcn42b already do. Updated the operation specs and the core_gtest dumper. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Flatten OPP_SET_DISP_PATTERN_GENERATOR parametersPiotr Maziarz
[WHY] opp2_set_disp_pattern_generator read debug.disable_dynamic_expansion_for_test_pattern through opp->ctx->dc while the sequence was executing. A block sequence operation must take its inputs from a flat parameter list resolved during the build phase, so this hid an input from the recorded sequence and left the FMT_DYNAMIC_EXP_CNTL branch unreachable from the OPP unit tests. [HOW] Added disable_dyn_exp_for_test_pattern to opp_funcs::opp_set_disp_pattern_generator and to opp_set_disp_pattern_generator_params, and updated every caller to pass dc->debug.disable_dynamic_expansion_for_test_pattern explicitly. Updated the unit test mocks and the core_gtest dumper, and extended opp_gtest to cover both values of the new flag. Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Add temporary programming for port control in dc_initAlvin Lee
[Description] Add the POR setting for SDP_PORT_CONTROL into dc init sequence. This is temporary until the initialization moves into pre-OS DMCUB. Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Program OPP formatter for plane-less ODM segmentsAshwin Santhosh
why: When a display is disabled the surviving DSC stream is committed with no planes but the dynamic ODM policy still expands it to a four to one combine. The added plane-less segments skip program_pipe so their OPP formatter is never configured. The DPG blank then feeds an unprogrammed formatter and the OPTC input underflows which flashes grey on screen. how: Program the OPP formatter for each plane-less OPP head in update_odm and update_odm_sequence the same way program_pipe does for planed pipes. Both function pointers are checked for null before calling. Every ODM segment now feeds valid data to the OPTC so the four to one combine no longer underflows. Signed-off-by: Ashwin Santhosh <Ashwin.Santhosh@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Fix null deref of link_enc in dce110_enable_tmds_link_outputSrinivasan Shanmugam
Smatch reports that link->link_enc is unconditionally dereferenced at the top of dce110_enable_tmds_link_output() while the later setup_ri_pj_check_in_sw_or_hw_mode calls guard against it being NULL, making those checks contradictory. Add an early return when link_enc is NULL and drop the redundant NULL checks from the two call sites that follow, since link_enc is guaranteed non-NULL past the guard Fixes: 992694ad2858 ("drm/amd/display: Enable DCN6 sources compilation") Reported-by: Dan Carpenter <error27@gmail.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Roman Li <Roman.Li@amd.com> Cc: Ivan Lipski <ivan.lipski@amd.com> Cc: Dan Wheeler <daniel.wheeler@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Fangzhi Zuo <jerry.zuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Resync cursor cache after offload abort on DCN60Ivan Lipski
[Why&How] The cursor programming path caches the last-written cursor state in SW and, for the enable bit, skips the register write when the cache already matches the request. Under cursor offload the SW cache is updated even though the actual register write is deferred to firmware. When an offloaded cursor update is aborted (e.g. an overlay geometry change reprograms the cursor directly in the same frame), the queued firmware write is dropped but the cache is left stale, so the following direct programming pass skips the enable write and the cursor disappears over the overlay plane. Add a refresh_cursor_state() hubp/dpp hook that reads the cursor position and attribute registers back from hardware into the SW cache, and call it from dcn35_abort_cursor_offload_update() so the cache is truthful after an abort. This keeps the enable-change optimization intact for all ASICs and is race-robust regardless of whether firmware applied the queued write before the abort. Only dcn60 (the sole offload user) wires up the hook. Assisted-by: Copilot:Claude-Opus-4.8 Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Rename build_cursor_position to ↵Piotr Maziarz
dcn10_build_cursor_pos_update_params This commit contains renames, adding const to pipe_ctx in build_cursor_pos_update_params and also removing unnecessary checks before dc_dmub_srv_is_cursor_offload_enabled(). [Why] It improves code clarity. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: clamp cursor hotspot at the register writePiotr Maziarz
[Why] dcn401_build_cursor_position() clamped x_hotspot to 0xFF before publishing *pos_out, but that field is also stored into hubp->curs_pos and forwarded to dpp1_set_cursor_position(), which derives src_x_offset from it. The ODM/MPC slice adjustments earlier in the same function deliberately grow x_hotspot past 255 to keep the cursor visible across a slice boundary, so the clamp corrupted DPP source addressing in exactly the case it was meant to handle. [How] Clamp in hubp401_cursor_set_position() instead, where the 8-bit CURSOR_HOT_SPOT_X field lives. A local is used for the register write only; pos->x_hotspot passes through unmodified. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: fix cursor refactor fallout and sync UT headersPiotr Maziarz
[Why] UT mirror headers still declared the old prototypes and hwss_gtest still called the callback directly. Separately, the divide by param.pixel_clk_khz used to sit after hubp401_cursor_set_position()'s "curs_attr.address == 0" early return; hoisting the math into the builder moved it ahead of that guard, so it now traps on streams with no timing programmed. [How] Guard the dst_x_offset block with "if (param.pixel_clk_khz)" Route the test through hwss_program_cursor_position(). Update dc_hwss_ut.h / dc_hwseq_ut.h and the BLS docs to the new signatures. Move the pos/param declarations to the top of the loop body. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: refactor hwss SET_CURSOR_POSITION block sequenceRafal Ostrowski
Flatten the executor params for the initial set of HWSS block sequence ops for SET_CURSOR_POSITION to separate SW and HW logic Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Drop pipe_ctx from hwss block sequence operationsRafal Ostrowski
[Why] pipe_ctx is not allowed to reach a block sequence step. Several operations still carried it into the executor, which then walked the logical state at execute time (pipe_ctx->stream->timing, pipe_ctx->plane_state and similar) instead of acting on data resolved during build. [How] Give each operation a flat parameter list holding only the hardware objects and values the final hwss call needs, and change the matching hooks to take it. The function pointer, the params struct, the executor, the builder helpers and all call sites are updated together. Operations covered: - OPTC_PROGRAM_MANUAL_TRIGGER - takes tg - HUBP_PROGRAM_TRIPLEBUFFER - program_triplebuffer takes (hubp, bool) - DPP_SETUP_DPP, DPP_PROGRAM_BIAS_AND_SCALE - take (dpp, plane_state) - DSC_ENABLE_WITH_OPP - takes (dsc, opp_inst) - OPP_PROGRAM_BIT_DEPTH_REDUCTION - opp Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Remove phantom SW state ops from block sequencePiotr Maziarz
[Why] HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM and HWS_UPDATE_PHANTOM_VP_POSITION program no hardware. They only mutate driver state: pipe update flags, the phantom plane viewport and the phantom scaling params. A block sequence is built first and executed later, so both ops ran only after the builder had already inspected pipe_ctx->update_flags to decide which steps to emit. The phantom pipe was therefore built from stale flags. [How] Call apply_update_flags_for_phantom() and update_phantom_vp_position() directly from hwss_build_post_unlock_full_sequence(), before program_pipe_sequence(), matching the legacy dcn401_post_unlock_program_front_end() ordering. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/display: Refactor DPP_PROGRAM_UPSP to drop pipe_ctxPiotr Maziarz
[Why] Hwss executors shouldn't be coupled to complex dc structs such as pipe_ctx. The DPP_PROGRAM_UPSP executor took a whole pipe_ctx only to reach two fields. [How] Change program_upsp_params to hold the dpp and the dscl_prog_data that dpp_program_upsp() actually needs, and extract them in the generic HWSS layer. Add hwss_add_dpp_program_upsp() so the build site uses a helper with the standard bounds check instead of assigning the step inline. Update the BLS specs. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Piotr Maziarz <piotr.maziarz@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: fix MALL hysteresis timer underflow at high refresh ratesFrancis Marlou Pacaro
dcn30_apply_idle_power_optimizations() derives the MALL frame cache hysteresis timer with tmr_delay = (uint32_t)(div_u64(..., denom) - 64LL); div_u64() returns a u64, so when the quotient is smaller than 64 the subtraction wraps instead of going negative and tmr_delay ends up huge. The loop that follows tries to squeeze it into the 6 bit register field by doubling denom, but that only makes the quotient smaller, so tmr_delay can never converge. tmr_scale is bumped past 3 and the function gives up with /* Delay exceeds range of hysteresis timer */ ASSERT(false); even though the requested delay is too *short* to encode, not too long. With mall_additional_timer_percent left at its default of 0, the quotient drops below 64 once the refresh rate used for the calculation goes above ~243 Hz. Every DCN 3.0 display above that loses MALL static screen entirely and splats a WARN once per boot. Reproduced on Navi 23 (RX 6600) driving 1920x1080, resetting /sys/kernel/debug/clear_warn_once between modes: refresh MALL ASSERT 144 Hz enabled no 240 Hz enabled no 280 Hz skipped yes 360 Hz skipped yes Commit 3bb68cec4db8 ("drm/amd/display: Add Overflow check to skip MALL") already covered the other end of the range, where a large stutter period makes the delay too long to encode. Cover the short end by clamping to 0, which selects the shortest hysteresis the register can express, 65.28us * 64 = ~4.18ms. That is marginally longer than what the formula asks for at these refresh rates, and erring long is the safe direction: it only delays MALL entry, it can never enter early. The numerator does not change between iterations, only denom does, so compute it once and keep both call sites inside 100 columns. The genuinely out of range case at very low refresh rates still reaches the ASSERT, which is where it belongs. Fixes: 52f2e83e2fe5 ("drm/amdgpu/display: add MALL support (v2)") Signed-off-by: Francis Marlou Pacaro <pacaro.francis.marlou.n@gmail.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Fix redundant NULL check on dc->clk_mgr in ↵Srinivasan Shanmugam
dcn42_prepare_bandwidth dc->clk_mgr is already dereferenced inside dcn401_prepare_bandwidth(), so the dc->clk_mgr NULL check that follows is redundant and misleading. Drop it. Fixes: 53845307d52e ("drm/amd/display: Register DCN as a PMFW DF C-state client on DCN42") Reported-by: Dan Carpenter <error27@gmail.com> Cc: Roman Li <roman.li@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Ivan Lipski <ivan.lipski@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: Wayne Lin <wayne.lin@amd.com> Cc: Dan Wheeler <daniel.wheeler@amd.com> Cc: Leo Chen <leo.chen@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Fix NULL dereference in dcn50/dcn60 init_hwSrinivasan Shanmugam
dc->clk_mgr is checked for NULL earlier in dcn50_init_hw() and dcn60_init_hw(), but dcn50_initialize_min_clocks() and dcn401_initialize_min_clocks() are called without any guard, causing Smatch to report potential NULL dereferences. Guard both call sites with the same pattern used throughout both functions: if (dc->clk_mgr && dc->clk_mgr->funcs) Also fix dcn50_initialize_min_clocks() which calls get_dispclk_from_dentist without checking the function pointer, unlike the dcn401 equivalent which guards that call. Fix kernel-doc in dcn60_hwseq.c by adding missing parameter descriptions for @probe in dcn60_update_probe_status() and @type in is_probe_measurement_type_for_hubbub(). Fixes: 7f7d7ea1fa51 ("drm/amd/display: Add new sources for DCN6") Reported-by: Dan Carpenter <error27@gmail.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Ivan Lipski <ivan.lipski@amd.com> Cc: Dan Wheeler <daniel.wheeler@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Unify fast update classification pathsRafal Ostrowski
[Why] The dc_fast_update intermediate struct created code duplication and complexity with multiple classification paths (populate_fast_updates, fast_nonaddr_updates_exist, full_update_required). This refactoring simplifies the update classification system by consolidating to a single path while maintaining compatibility. [How] Remove entire dc_fast_update struct and associated helper functions: - populate_fast_updates - fast_nonaddr_updates_exist - full_update_required Refactor check_update_surfaces_for_stream as the single classification path with explicit handling for func_shaper, lut3d_func, cursor_csc_color_matrix_change, and scaler_sharpener_update. Add a reserved bitfield to the stream_update_flags union for completeness guards. Extract dc_check_address_only_update and dc_check_update_surfaces_for_stream as public. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Add inbox0 HW lock helpers for DCN35Tom Chung
Add dcn35_dmub_hw_control_lock() and dcn35_dmub_hw_control_lock_fast(), a SW lock mechanism to prevent racing between driver and FW. The helpers are not wired into dcn35_funcs/dcn351_funcs yet, so there is no functional change: DCN3.5/3.5.1/3.6 keep using the existing inbox1 lock path. Enabling them will come in a follow-up patch. Reviewed-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Program DCC as part of address updateAlvin Lee
[Description] - DCC register is latched on the surface address register being updated - In this case couple the DCC programming and the address update together to ensure the DCC programming is always taken as expected - Update address programming function to take in DCC bool, use for DCN6+ and leave older DCN unchanged. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Add is_odm_enabled callback to skip init_odm on active ODM ↵Wang, Sung-huai
pipes [Why] dcn10_init_pipes unconditionally calls init_odm on all enabled TGs, resetting ODM combine state even when it should be preserved. [How] Add is_odm_enabled callback to timing_generator_funcs and guard init_odm to skip when ODM is already active. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Danny Wang <Danny.Wang@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Decouple HUBP_UPDATE_PLANE_ADDR from pipe_ctxTomasz Siemek
[Why] Every HWSS Block Level Sequence operation should have flat parameter list and an explicit instance pointer. Global state should not be accessed at execute time. HUBP_UPDATE_PLANE_ADDR does not adhere. It stashes pipe_ctx in its params. Pipe context is mutated during execution. [How] - Adjust HUBP_UPDATE_PLANE_ADDR params to hubp_program_surface_flip_and_addr parameter list. - Add a build-phase hwss vtable entry - prepare_plane_addr_update that does parameter preparation and all global state mutation. - Execute hubp_program_surface_flip_and_addr with precalculated parameters during execution phase. Reviewed-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Add urgent assertion counter probeWenjing Liu
[Why] Expose continuous urgent assertion counts for memory QoS debugging. [How] Track probe running state and poll the counter through the update path. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Refactor RMCM into a separate moduleRafal Ostrowski
[WHY] The RMCM logic was embedded inside the MPC block, sharing its source files, functions, register definitions and other logic. This tight coupling created several problems: - The RMCM vtable was bolted onto struct mpc_funcs, making it impossible to instantiate RMCM independently of MPC - RMCM resource acquisition had no tracking - there was no mechanism to allocate the 2 available RMCM instances to pipes or release them [HOW] RMCM is now a separate module: - dc/rmcm/ directory with per-ASIC implementations - new struct rmcm with its own funcs vtable containing shaper, 3DLUT, and fast-load operations - removed all RMCM code from MPC - added RMCM resource lifecycle management in dc_resource.c: - resource_assign_rmcm(): Assigns the instances for a whole context, so a plane that is only now asking never evicts one already using an instance - resource_release_rmcm(): Clears the pipe's allocation. - updated resource pool constructors (dcn42, dcn42b, dcn60) to create RMCM instances via the new dcnXX_rmcm_create() and destroy them in pool teardown Reviewed-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Update LLS and UPSP programming pathsAlvin Lee
[Description] - UPSP should only be enabled when we want linear scaling for 420/422 - In DC for non-FP16 formats that are told to scale in non-linear, program bypass for PRE_GAM since these formats are already non-linear (i.e., YUV420, YUV422, RGB, etc.) Reviewed-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Taimur Hassan <syed.hassan@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/display: Decouple cursor offload hwss executors from pipe contextTomasz Siemek
[Why] Hwss executors shouldn't be coupled to complex dc structs such as pipe_ctx. [How] Refactor cursor offload hardware sequencer extension to accept only the parameters required for programming cursor offload state. Extract these parameters in the generic HWSS layer for both immediate execution and block-sequence construction. Reviewed-by: Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-10drm/amd/display: Add stressed peak bandwidth probe with DMA contentionWenjing Liu
[Why] Peak-bandwidth-under-contention validation currently needs an external tool to manufacture memory contention while querying peak bandwidth. Expose this as an explicit probe variant so the driver can generate that contention itself. [How] Add a new probe type that builds the same gated perfmon sequence as the plain peak-BW probe, with a DMA copy of the current surface into a scratch buffer inserted before the measurement window to synthesize a competing memory client. Move the scratch buffer fields onto the base resource pool struct instead of an ASIC-specific subclass, and reject the probe with a new status code when the buffer was never allocated. Also fixes a stack- corruption bug where a local variable's address was captured by a deferred callback and used after the local went out of scope, and a missing NULL check on a similar output parameter used by an early-return path. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-10drm/amd/display: Refactor DC_SEND_CURSOR_INFO_TO_DMU to drop pipe_ctxTomasz Siemek
[Why] Pipe_ctx shouldn't be passed as block sequence parameter. [How] Pass needed parameters explicitly to executor. Reviewed-by: Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/display: use translate_curve_to_degamma_hw_format on DCN30Melissa Wen
DCN3.01 presents the same banding issue as reported in the link below, but the previous fix doesn't cover this hw. Change the helper used to translate degamma/blend curves to HW points for DCN30, DCN 301, DCN31 and DCN314 similar to what was done for DCN32+ by commit 3719314af322 ("drm/amd/display: use a separate helper to translate degamma curves"). Link: https://lore.kernel.org/amd-gfx/20260623160112.1636801-1-mwen@igalia.com/ Fixes: 222e63bddae5 ("drm/amd/display: use a separate helper to translate degamma curves") Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/display: Change RBBMIF timeout control conditionsDillon Varone
[WHY&HOW] RBBMIF timeout should not be disabled to prevent register access hang. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/display: Remove pipe_ctx param from MPC_VISUAL_CONFIRMTomasz Siemek
[WHY] Hwss executors shouldn't be coupled to complex dc structs such as pipe_ctx. [HOW] - Use mpc function instead of hwseq extension. - Swap pipe_ctx for tg_color struct as BLS param. Reviewed-by: Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/display: Move cursor SDR white level calculation out of hwss executorTomasz Siemek
[WHY] Cursor SDR white level calculation is common across DCN generations and does not require an ASIC-specific HWSS implementation. Keeping it in the DCN10 HWSS extension duplicated generic policy in generation-specific code and made block sequence execution depend on mutable pipe context. [HOW] Move cursor SDR white level calculation into dc_hw_sequencer. Store the calculated DPP cursor attributes in the block sequence so execution only invokes set_optional_cursor_attributes. Reviewed-by: Ilya Bakoulin <ilya.bakoulin@amd.com> Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Split OPTC_PIPE_CONTROL_LOCK into smaller HWSS blocksTomasz Siemek
[why] Block level sequence operations should not use global state structs such as pipe_ctx. OPTC_PIPE_CONTROL_LOCK is a BLS with complex logic dispatching a lot of smaller hardware programming operations. BLS should be a simple and atomic hardware operation without performing mutations or having an access to global state. All operations on global state should be moved to build step in HWSS. [how] - Split OPTC_PIPE_CONTROL_LOCK into substeps: - HUBP_WAIT_FLIP_PENDING, - TG_SET_GSL, - TG_SET_GSL_SOURCE_SELECT, - TG_LOCK, - TG_3DLUT_WA_UNLOCK. - Add hwss_pipe_control_lock - for in place build + execution. - Remove timeout from HUBP_WAIT_FOR_FLIP_PENDING. - Move software logic to builder. which fills pipe_control_lock_params containing data for programming actual hwss blocks. - Due to differences in what pipe control lock means bettween asics following builder variants are added: - dce_build_pipe_control_lock_sequence for asics pre DCN20, - dcn20_build_pipe_control_lock_sequence. - Rework gsl group programming to use builder / executor pattern. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Refactor DPP_SET_INPUT_TRANSFER_FUNC to drop pipe_ctxTomasz Siemek
[Why] Pipe_ctx shouldn't be passed as block sequence block parameter. [How] - Adjust arguments for: - set_input_transfer_func, - populate_mcm_luts, - set_mcm_location_post_blend, - set_mcm_luts, - program_rmcm_luts. - Remove const qualifier from plane_state in set_mcm_luts since it is mutated. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Tomasz Siemek <Tomasz.Siemek@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Fixes for HPO test regressionsSridevi Arvindekar
[Why&How] Updates and fixes to HPO functionality, initialization, encoder configuration and platform-specific behavior. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Skip eDP teardown while forced PSR is activeKarthi Kandasamy
[Why & How] During the HDR<->SDR toggle when the eDP link is held in a forced PSR (freeze) state, the normal stream/link teardown re-programming the panel would blank the frozen frame and disrupt the freeze; to prevent this, gate the eDP teardown path, keeping the link and PSR/Replay state intact for the duration of the forced PSR hold. The blank_stream and disable_link_output gates already exist. Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Refactor HUBP_WAIT_FOR_DCC_META_PROP to drop pipe_ctxTomasz Siemek
[why] Pipe_ctx shouldn't be passed as block sequence block parameter. [how] Precalculate delay during building stage instead during execution. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Move periodic interrupt calculations to HWSSTomasz Siemek
[why] Periodic interrupt line calculations depends on stream and pipe state, not ASIC-specific register programming. Keeping it in the DCN10 implementation also prevents block-sequence callers from carrying fully resolved parameters. We want HWSS block parameters to not include complex structures like pipe_ctx. [how] - Move the vertical interrupt line calculation into common HWSS code. - Update the periodic interrupt callback. - Calculate the values before direct or block-sequence execution. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com> Signed-off-by: James Lin <pinglei.lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Fix DCN6 peak bandwidth measurement overshootWenjing Liu
[Why] The out-of-order (peak prefetch) bandwidth probe could report bandwidth far above the physical clock ceiling. The data and duration counters could latch on different edges of the shared stop event, and very short measurement windows amplified refclk tick quantization into large relative errors. [How] Add a dedicated counter (2) that generates the single stop event both the data counter (1) and duration counter (4) key off of, so they always latch on the same edge. Reject samples where the data counter overshoots the generator's target, or where the duration is too short to trust. Also drop the single-timing-group restriction on the peak-BW probe. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Update dcn60 clkmgr interfacesAlvin Lee
[Description] Update clk_mgr interfaces to match with the DAL<->PMFW message interfaces for DCN6. - dalsmc.h MAX_PPCLK_COUNT must match PPCLK count in driver_if header - include driver_if header as a local copy for now since PMFW carried one will not build - clk table returned by PMFW is in Khz, must convert to Mhz accordingly - boot snapshot for dispclk is in Khz - Get*Clk interfaces should return frequency in Khz, ensure that DAL interfaces are implemented to handle this - Move structure definitions into dcn60_clk_mgr_smu_msg.h header since the official dalsmc.h header does not carry all these definitions yet Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: gate DCE ASIC code behind CONFIG_DRM_AMD_DC_DCEGaghik Khachatrian
[Why&How] Refactor to make DCE support optional. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/display: Add support for overriding UTM client QC profileDillon Varone
[WHY&HOW] Support overriding UTM client QC profiles for testing. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>