summaryrefslogtreecommitdiff
path: root/drivers/clk/renesas
AgeCommit message (Collapse)Author
8 daysMerge branches 'clk-renesas', 'clk-samsung', 'clk-starfive', ↵Brian Masney
'clk-tenstorrent' and 'clk-pile' into clk-next * clk-renesas: (25 commits) clk: renesas: r8a78000: Add SGASYNCD8_PERW_BUS clk: renesas: rzg2l: Fix internal clock names clk: renesas: r9a08g046: Add TSU and ADC1 clocks and resets clk: renesas: Add support for RZ/G2M v3.0 clk: renesas: r9a08g046: Add CANFD clocks and resets clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions clk: renesas: r8a779g0: Add ZG clocks clk: renesas: rcar-gen4: Tidy up DEF_GEN4_Z() clk: renesas: r9a09g077: Register SYSC regmap clk: renesas: rcar-gen3: Use FIELD_GET() clk: renesas: rzv2h: Convert to clk_hw based provider API clk: renesas: rzv2h: Drop duplicated parent lookup in fixed_mod_status_clk_register() clk: renesas: r9a08g046: Add PCIe clocks and reset clk: renesas: Make sure clk_init_data is fully initialized clk: renesas: r9a08g046: Add clock and reset entries for LVDS clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entries clk: renesas: r9a08g046: Sort macro definitions alphabetically clk: renesas: rzg2l: Add support for RZ/G3L DSI mux clk: renesas: rzg2l: Add support for LVDS fixed-factor divider with 4:7 duty cycle ... * clk-samsung: clk: samsung: acpm: add Exynos850 support clk: samsung: acpm: introduce driver data for SoC-specific clocks clk: samsung: Introduce Exynos5515 clock driver clk: samsung: clk-pll: Add support for pll_309 dt-bindings: clock: Add Exynos5515 SoC * clk-starfive: dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator * clk-tenstorrent: MAINTAINERS: Update RISC-V Tenstorrent SoC entry clk: tenstorrent: use regmap_assign_bits() for conditional set/clear clk: tenstorrent: Fix refcount leak on shared gate clk enable failure clk: tenstorrent: Assign .num before accessing .hws * clk-pile: (126 commits) clk: imx: pll14xx: support spread spectrum clock generation clk: cdce925: Size the PLL child name buffer for any int clk: stm32: fix clock array size for STM32MP21 dt-bindings: clock: Convert HiSilicon clocks to DT schema clk: lmk04832: Handle reset GPIO lookup errors dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional clk: tegra: bpmp: remove kcalloc clk: mmp2-audio: add missing PM_CLK dependency clk: zte: Introduce a driver for zx297520v3 LSP clocks clk: zte: Introduce a driver for zx297520v3 matrix clocks clk: zte: Introduce a driver for zx297520v3 top clocks clk: zte: Add zx PLL support infrastructure clk: zte: Add regmap-based clocks clk: zte: Add Clock registration infrastructure dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define ...
2026-09-28clk: renesas: r8a78000: Add SGASYNCD8_PERW_BUSWolfram Sang
Add support for the SGASYNCD8_PERW_BUS clock, which is a fixed 133 MHz clock serving as the functional clock parent for I2C cores 1 to 8. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/8c4912ada9c3d6776ae64d3896ffc1f45a98c51a.1790326477.git.geert+renesas@glider.be
2026-09-24clk: renesas: rzg2l: Fix internal clock namesGeert Uytterhoeven
By convention, internal clock names start with a dot and use lower-case. Fix the outliers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/8254a5b1dccf33252042a366a3839a70020d6487.1790154594.git.geert+renesas@glider.be
2026-09-24clk: renesas: r9a08g046: Add TSU and ADC1 clocks and resetsBiju Das
Add clock P20 (PLL2_DIV2/8), module clocks for ADC1 (ADCLK, PCLK) and TSU (PCLK), along with the corresponding module resets for ADC1 and TSU on the RZ/G3S (R9A08G046) SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260922042707.116378-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-09-24clk: renesas: Add support for RZ/G2M v3.0Ayman Chaudhry
Add initial support for the Renesas RZ/G2M v3.0 (a.k.a. R8A774A3) SoC, including basic core clocks, and SCIF2 (serial console) and INTC-AP (GIC) module clocks. The RZ/G2M v3.0 CPG is similar to RZ/G2M v1.3, however it lacks some modules such as the FCPCI. Signed-off-by: Ayman Chaudhry <ayman.chaudhry.kc@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260921134432.50338-7-ayman.chaudhry.kc@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-09-24clk: renesas: r9a08g046: Add CANFD clocks and resetsBiju Das
Add the P4 and P4_DIV2 core clocks, CANFD module clocks (canfd_pclk, canfd_clk_ram), and CANFD resets (RSTP_N, RSTC_N) for the RZ/G3L (R9A08G046) SoC, needed to enable the CANFD driver on this SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260921131951.187981-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-09-24clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocksBiju Das
Add CLK_SET_RATE_PARENT flag to the sel_eth0_tx and sel_eth1_tx mux clocks so that rate-setting requests on these clocks propagate up to their parent clocks. Without this flag, a clk_set_rate() call on the downstream GBETH clocks has no effect on the actual PLL/divider chain feeding the TX clock, leaving the requested rate unapplied. Fixes: d55a0dfec40b ("clk: renesas: r9a08g046: Add GBETH clocks and resets") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260914165026.184612-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-09-23clk: renesas: convert drivers over to use subsys_platform_driver()Brian Masney
Reduce boilerplate code in the drivers and convert them over to use subsys_platform_driver(). Signed-off-by: Brian Masney <bmasney@redhat.com> Assisted-by: Claude:claude-opus-4-8 Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260908-subsys_initcall-v1-4-cbccf4cd4288@redhat.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-09-21clk: renesas: r8a779g0: Add ZG clocksKuninori Morimoto
Add ZG related clocks for GSX. Signed-off-by: Anh Nguyen <anh.nguyen.pv@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/878q52vu4q.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-09-21clk: renesas: rcar-gen4: Tidy up DEF_GEN4_Z()Kuninori Morimoto
Current DEF_GEN4_Z() is using .offset to get "reg" and "pos", but the offset positions and calculations differ from intuition (the registers are located in the order B -> C0 -> C1, but it is using C0 -> C1 -> B). Tidy them up. Include CLK_TYPE_GEN4_Z in DEF_GEN4_Z(), as it is duplicated everywhere else. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/87a4pivu4v.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-09-14clk: renesas: r9a09g077: Register SYSC regmapLad Prabhakar
Register a syscon regmap for the System Controller (SYSC) integrated into the RZ/T2H and RZ/N2H CPG block. Unlike traditional Renesas CPG/MSSR implementations, the RZ/T2H and RZ/N2H CPG block also integrates the SYSC, which provides low-power management, clock monitoring, write protection and peripheral configuration registers shared by multiple drivers. Implement the RZ/T2H-specific .post_init() callback to create and register a syscon regmap covering the SYSC register space using the CPG device node. For backward compatibility, return without registering the regmap when the mapped resources correspond to older Device Trees that expose only the legacy 64 KiB CPG register window. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260817192540.423994-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-09-09clk: renesas: rcar-gen3: Use FIELD_GET()Geert Uytterhoeven
Improve readability by using the FIELD_GET() helper instead of open-coding the same operation, and by adding field definitions to get rid of hardcoded values. While at it, move register definitions that are only used inside the rcar-gen3-cpg.c source file out of the rcar-gen3-cpg.h header file. Add comments where appropriate. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://patch.msgid.link/17c50847f86b814150573e34cc64913f09598f0f.1788437047.git.geert+renesas@glider.be
2026-09-07clk: renesas: rzv2h: Convert to clk_hw based provider APIJohn Madieu
The driver mixes the clk consumer API with the clk_hw provider API for its internal clock storage and OF lookup callback. Convert it to use clk_hw consistently. No functional change intended. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260902104939.25522-3-ovidiu.panait.rb@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-09-07clk: renesas: rzv2h: Drop duplicated parent lookup in ↵John Madieu
fixed_mod_status_clk_register() rzv2h_cpg_fixed_mod_status_clk_register() looks up priv->clks[core->parent] twice, with an IS_ERR() check after each lookup. The second lookup is a leftover from an earlier refactor: the value cannot have changed between the two reads, so the second IS_ERR() check is dead code. Drop the duplicated lookup and check. No functional change intended. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260902104939.25522-2-ovidiu.panait.rb@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-09-07clk: renesas: r9a08g046: Add PCIe clocks and resetBiju Das
Add the PCIe module clocks (ACLK, CLKL1PM, CLK_PMU) and the PCIe reset signal for the RZ/G3L (R9A08G046) SoC, along with the P8 fixed clock required as the parent for CLKL1PM. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260825095047.9971-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-09-01clk: renesas: Make sure clk_init_data is fully initializedGeert Uytterhoeven
The clk_init_data structure contains several mutually-exclusive members for different methods to specify the possible parents of a clock, prompting drivers to initialize only the members they need. However, not initializing all members may cause subtle issues, which are only exposed when CONFIG_INIT_STACK_ALL_PATTERN or CONFIG_INIT_STACK_NONE is enabled. Make sure all members are fully initialized, to avoid such bugs, and to prevent future breakage when converting drivers to a different method for specifying the parents. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Brian Masney <bmasney@redhat.com> Link: https://patch.msgid.link/b3473adc50c71aec5bc5f7ce6f5cda1727e26635.1787239813.git.geert+renesas@glider.be
2026-08-31clk: renesas: r9a08g046: Add clock and reset entries for LVDSBiju Das
Add clock and reset entries for LVDS. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20260811182729.360959-10-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-08-31clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entriesBiju Das
Add clock and reset entries for the MIPI DSI and LCDC peripherals on the RZ/G3L (R9A08G046) SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260811182729.360959-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-08-31clk: renesas: r9a08g046: Sort macro definitions alphabeticallyBiju Das
Reorder the DDIV_PACK() and SEL_PLL_PACK() macro definitions so they are grouped alphabetically by name, improving readability and making it easier to spot duplicates or gaps. No functional change. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260811182729.360959-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-08-31clk: renesas: rzg2l: Add support for RZ/G3L DSI muxBiju Das
Add support for RZ/G3L DSI mux that supports 2 duty cycles. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260811182729.360959-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-08-31clk: renesas: rzg2l: Add support for LVDS fixed-factor divider with 4:7 duty ↵Biju Das
cycle Add a new CLK_TYPE_G3L_LVDS_DIV clock type and register function for a fixed-factor divider used by the LVDS clock, which cannot produce a 50% duty cycle for odd divider values. Implement a custom get_duty_cycle() callback that reports the actual (div + 1) / 2 : div duty cycle, and add the DEF_G3L_LVDS_DIV() macro to define such clocks. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260811182729.360959-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-08-31clk: renesas: rzg2l: Add support for divider flagsBiju Das
Add support for passing divider flags apart from clock flags from soc specific clock drivers. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20260811182729.360959-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-08-31clk: renesas: rzg2l: Rename cpg_core_clk::flag to core_flagsBiju Das
Rename the 'flag' member of struct cpg_core_clk to 'core_flags' for clarity and to better distinguish it from mux_flags. Update all users and DEF_* macros accordingly. No functional change. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260811182729.360959-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-08-31clk: renesas: rzg2l: Add PLL7 DSI clock support for RZ/G3LBiju Das
Add a new fractional PLL clock type (CLK_TYPE_G3L_PLLDSI) for the RZ/G3L SoC's PLL7, which drives the DSI interface and requires a dedicated parameter calculation and programming sequence distinct from other PLLs in the RZ/G2L family. PLL7 output frequency is determined by the formula: Ffdco = (NIR + NFR / 4096) * (Fosc / MR) Ffout = Ffdco / (1 << PR) where: - Fosc = 24 MHz (oscillator input) - PR in [0, 4] (post divider, power-of-two) - MR in [1, 12] (input pre-divider) - NIR in [56, 375], NFR in [0, 4095] (integer and fractional parts) The FDCO must fall within one of two valid ranges: 900–2000 MHz (rangesel=0) or 2000–3000 MHz (rangesel=1). The parameter search in rzg3l_dsi_get_pll_parameters_values() iterates over all valid (MR, PR) combinations, filtering by the required FPFD range of 8–16 MHz, then delegates to rzg3l_dsi_compute_pll_parameters() to find the NIR/NFR pair that best approximates the requested rate. An exact match returns immediately; otherwise the combination with the smallest absolute frequency error is used. Computed parameters are cached in pll7_dsi_params within pll_clk to avoid redundant recalculation in determine_rate() when the requested rate has not changed. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260811182729.360959-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-08-31clk: renesas: rzg2l: Add DSI divider clock support for RZ/G3LBiju Das
Add a new DSI divider clock type (CLK_TYPE_G3L_PLLDSI_DIV) for the RZ/G3L SoC, which requires a different divider implementation than the existing RZ/G2L DSI divider clock. The RZ/G3L DSI divider uses two cascaded dividers, DIV_DSI_A and DIV_DSI_B, where the effective divider is: rate = parent_rate / ((1 << div_a) * (div_b + 1)) DIV_DSI_A is a power-of-two divider with values in the range [0, 5], and DIV_DSI_B is a linear divider with values in the range [1, 16]. Introduce the g3l_dsi_div_hw_data structure, rzg3l_cpg_dsi_div_ops, and rzg3l_cpg_dsi_div_clk_register() to implement the new clock type, and add the DEF_G3L_PLLDSI_DIV() macro for use in clock table definitions. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260811182729.360959-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-08-31clk: renesas: Clean-up simple provider misuse of the consumer APIJerome Brunet
Clock provider should not be using the consumer interface. In other words, a provider should not be dealing with struct clk. This change targets occurrences for which the provider uses the consumer interface and corresponding clk_hw interface exist. Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260724-clk-provider-simple-clean-v2-3-56f306156d25@baylibre.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-08-20Merge branches 'clk-pile' and 'clk-microchip' into clk-nextStephen Boyd
* clk-pile: (111 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 ... * clk-microchip: clk: at91: Read "reg" with helper
2026-08-17Merge tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux into clk-pileStephen Boyd
Pull clk patches picked up by Brian Masney: Here's various improvements and fixes for the clk subsystem that was posted prior to the opening of the last merge window. - Add spread spectrum clock (SSC) support to the clk framework, including a new assigned-clock-sscs devicetree property and clk_hw_set_spread_spectrum() API with KUnit tests (Peng Fan) - Add SCMI clock OEM extensions for the i.MX95 clock driver and introduce a common SCMI clock header (Peng Fan) - Add clock, reset, and devicetree bindings for the ESWIN EIC7700 HSP clock and reset generator (Xuyang Dong) - Add clk_determine_rate_noop() helper for clock drivers that can do any rate, and convert existing open-coded implementations across hisilicon, imx, qcom, renesas, rp1, samsung, scpi, sprd, mediatek phy, and mediatek pmdomain drivers (Brian Masney) - Add kernel-doc documentation for struct clk_core and the core clock flags, and wire up clk identifiers into the documentation build (Brian Masney) - Fix clk_divider_bestdiv() returning the minimum rate instead of the maximum rate for large rate requests, with KUnit tests (Lad Prabhakar) - Fix Nuvoton MA35D1 PLL frequency calculation including ignored div_u64 return values, incorrect PLL_CTL1_FRAC bit field width, and broken determine_rate logic (Joey Lu) - Support unique clock names for multi-socket Tegra platforms (Jon Hunter) - Allow COMPILE_TEST builds for HiSilicon clock drivers (Rosen Penev) - Various fixes and cleanups from Akari Tsuyukusa, Alexander A. Klimov, Brian Masney, David Carlier, David Laight, Min zhang, Myeonghun Pak, Pavel Löbl, Randy Dunlap, Rob Herring, Rosen Penev, Uwe Kleine-König, William Theesfeld, Xuyang Dong, and Yu-Chun Lin Signed-off-by: Brian Masney <bmasney@redhat.com> [sboyd@kernel.org: Fix allmodconfig modpost failure in scmi] * tag 'clk-misc-for-v7.3' of ssh://github.com/masneyb/linux: (53 commits) pmdomain: mediatek: mtk-mfg: use clk_determine_rate_noop() pmdomain: mediatek: airoha: use clk_determine_rate_noop() phy: mediatek: phy-mtk-hdmi-mt2701: use clk_determine_rate_noop() clk: sprd: use clk_determine_rate_noop() clk: scpi: use clk_determine_rate_noop() clk: samsung: acpm: use clk_determine_rate_noop() clk: rp1: use clk_determine_rate_noop() clk: renesas: rzg2l-cpg: use clk_determine_rate_noop() clk: qcom: smd-rpm: use clk_determine_rate_noop() clk: qcom: rpmh: use clk_determine_rate_noop() clk: qcom: rpm: use clk_determine_rate_noop() clk: imx: scu: use clk_determine_rate_noop() clk: hisilicon: hi3660-stub: use clk_determine_rate_noop() clk: add clk_determine_rate_noop() clk: imx: scu: drop redundant init.ops variable assignment clk: test: convert constants to use HZ_PER_MHZ docs: clk: include some identifiers to keep documentation up to date clk: add kernel docs for struct clk_core clk: add kernel docs for the core flags clk: hisilicon: allow COMPILE_TEST builds ...
2026-08-06clk: renesas: Add R-Car X5H CPG driverGeert Uytterhoeven
Add a minimal Clock Pulse Generator driver for the R-Car X5H (R8A78000) SoC. For now this supports just the few fixed-rate clocks that are needed by the current minimal DTS. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/3f981753722de1ba871667be63460e89d299d635.1785941595.git.geert+renesas@glider.be
2026-08-05Merge tag 'renesas-r8a78000-dt-binding-defs-tag2' into renesas-clk-for-v7.3Geert Uytterhoeven
Renesas R-Car X5H CPG DT Binding Definitions DT bindings and binding definitions for the Renesas R-Car X5H (R8A78000) Clock Pulse Generator (CPG), shared by driver and DT source files.
2026-07-13clk: r9a08g045: Add clocks and resets for CAN-FDClaudiu Beznea
Renesas RZ/G3S SoC has a CAN-FD IP. Add clocks and resets for it. Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260709182332.876408-2-claudiu.beznea+renesas@tuxon.dev Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-07-03Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c ↵Uwe Kleine-König (The Capable Hub)
files) Replace the #include of <linux/mod_devicetable.h> by the more specific <linux/device-id/*.h> where applicable. For most cases the include can be dropped completely, only a few drivers need one or two headers added. Acked-by: Danilo Krummrich <dakr@kernel.org> Acked-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
2026-06-30clk: renesas: r9a09g047: Add LVDS clocks and resetsTommaso Merciai
Add LVDS clocks and resets entries to the r9a09g047 CPG driver. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260623152851.478573-1-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-30clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display ↵Lad Prabhakar
pipeline Add the clock definitions and PLL logic required to supply the LCDC (VSPD/FCPVD/DU) blocks on the RZ/T2H (R9A09G077) SoC. The RZ/T2H display subsystem depends on a dedicated PLL (PLL3) and a set of new derived clocks. Introduce a new PLL clock type and implement rate recalculation, programming and locking sequences for PLL3 using the RZ/T2H specific divider and VCO limits. Add the corresponding muxes and divider entries, expose the LCDC core clock, and register the LCDC module clock using the correct PCLK parent. This enables the RZ/T2H clock driver to generate the display pipeline clocking tree needed by the DU and VSP-based composition engines, allowing upcoming display support to be integrated without duplicating CPG logic. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260618181949.3036280-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-30clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared libraryLad Prabhakar
Move the RZ/V2H PLL and divider parameter calculation helpers from rzv2h-cpg.c into a new reusable library. Introduce the CLK_RZV2H_CPG_LIB Kconfig symbol and add rzv2h-cpg-lib.c to host the PLL parameter search algorithms currently implemented by rzv2h_get_pll_pars() and rzv2h_get_pll_divs_pars(). Export the helpers as rzv2h_cpg_get_pll_pars() and rzv2h_cpg_get_pll_divs_pars() for use by other drivers. Update the public clock header to expose the new interfaces and provide compatibility aliases for the existing helper names, avoiding build breakage for current users while allowing future conversions to the new API. This prepares for reuse of the PLL and divider calculation logic by other Renesas clock drivers, including upcoming RZ/T2H and RZ/N2H CPG support, without duplicating the implementation. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260618181949.3036280-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-30clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculationsLad Prabhakar
Introduce a per-SoC PLL reference input frequency parameter to avoid relying on a hardcoded 24MHz constant during PLL configuration math. Add an input_fref member to struct rzv2h_pll_limits. In the core calculation helper rzv2h_get_pll_pars(), derive the base input clock rate from limits->input_fref, utilizing the conditional ternary operator to fall back to 24MHz if the struct field is left uninitialized (0), and drop the obsolete macro RZ_V2H_OSC_CLK_IN_MEGA. This abstraction permits the reuse of the common PLL divider logic on newer SoC platforms like the RZ/T2H, which feature a 48 MHz PLL reference clock input instead of the 24 MHz signal used by RZ/V2H(P), without disrupting existing platforms. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260618181949.3036280-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-30clk: renesas: r9a08g046: Add USB2.0 clock and reset entriesBiju Das
Add module clock and reset definitions for the USB2.0 interfaces on the RZ/G3L (r9a08g046) SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260616104459.410743-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-30clk: renesas: r9a09g077: Add RTC clocksLad Prabhakar
Add the core and module clock definitions for the Real-Time Clock (RTC) peripheral on the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260615143943.1610095-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-30clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC ↵Lad Prabhakar
and RTC Introduce a dedicated clock delay mechanism, cpg_rzt2h_mstp_delay(), to satisfy the module-stop (MSTP) state release requirements specified in the RZ/T2H hardware manual. Per the hardware manual, while a standard 10 us delay (satisfying 7 dummy reads) is sufficient for most IP blocks, the LCDC requires 100 dummy reads (142 us) and the RTC requires 300 dummy reads (428 us) to stabilize after being released from a module-stop state. Implement a conditional bitmask filter helper that switches wait intervals based on the packaged module clock index. In cpg_mstp_clock_endisable(), the clock index and individual target bits are known, allowing an exact match. In the resume path cpg_mssr_resume_noirq(), where individual bits are not tracked, pass a fallback register index base (`reg * 32`) with bit verification masked out to match on the peripheral's register group block instead. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260615104845.4122868-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-30clk: renesas: r9a08g046: Add clock and reset entries for GE3DBiju Das
Add clock and reset entries for GE3D. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260604151855.307772-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-30clk: renesas: r9a08g046: Add clock and reset entries for SDHIBiju Das
Add clock and reset entries for SDHI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260603065731.93243-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-30clk: renesas: r9a09g047: Add audio clock and reset supportJohn Madieu
Add clock and reset entries for audio-related modules on the RZ/G3E SoC. Target modules are: - SSIU (Serial Sound Interface Unit) with SSI ch0-ch9, - SCU (Sampling Rate Converter Unit) with SRC ch0-ch9, DVC ch0-ch1, CTU/MIX ch0-ch1, - DMACpp (Audio DMA Controller), - ADG (Audio Clock Generator) with divider input clocks and audio master clock outputs. The ADG SSI clock outputs (adg_ssi[0-9]_clk) are parented on CLK_PLLCLN_DIV8 as a deliberate simplification: the ADG dynamically muxes each output between adg_0_clk_195m and audio_clk[a,b,c] at runtime via ADG_AUDIO_CLK_SEL{0,1,2}, owned by the rsnd-adg driver. While at it, reorder plldty_div16 to group it with the other plldty fixed dividers. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260525110603.4018170-3-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-29clk: renesas: rzg2l-cpg: use clk_determine_rate_noop()Brian Masney
Drop the driver-specific empty determine_rate() function and use the new shared clk_determine_rate_noop() helper. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-05-28clk: renesas: r9a08g045: Drop unused pm_domain header fileBiju Das
The linux/pm_domain.h header is not used in this file. Remove it to keep the includes clean. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260524082657.19335-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-28clk: renesas: r8a779g0: Add DSC clockMarek Vasut
Add the DSC module clock for Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260515-rcar-du-dsc-v3-1-164157820498@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-25clk: renesas: rzg2l: Rename iterator in for_each_mod_clock() to avoid shadowingLad Prabhakar
Rename the internal loop iterator variable in the for_each_mod_clock() macro from 'i' to '__i'. The current naming conflicts with local loop variables named 'i' inside code blocks that utilize the macro, triggering compiler warnings due to variable shadowing: drivers/clk/renesas/rzg2l-cpg.c:1494:36: warning: declaration of `i` shadows a previous local [-Wshadow] 1494 | for (unsigned int i = 0; i < clk->num_shared_mstop_clks; i++) Using a unique identifier for the macro-internal iterator resolves the shadowing warnings globally across all macro expansions. Fixes: 3fd4a8bb4b63 ("clk: renesas: rzg2l: Add macro to loop through module clocks") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260520092947.70596-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-25clk: renesas: r9a08g045: Drop unused DEF_G3S_MUX macroLad Prabhakar
Drop the unused DEF_G3S_MUX helper macro from the r9a08g045 CPG driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260520092516.69819-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-22clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed onesBiju Das
Rename RZG3L_PLL_STBY_OFFSET(), RZG3L_PLL_STBY_RESETB, RZG3L_PLL_STBY_RESETB_WEN, RZG3L_PLL_MON_OFFSET(), RZG3L_PLL_MON_RESETB, and RZG3L_PLL_MON_LOCK to their CPG_PLL_* equivalents to reflect that these macros are not RZG3L-specific and are shared across SoCs. Also fold CPG_PLL_MON_OFFSET() into rzg2l-cpg.c alongside the other CPG_PLL_*_OFFSET() helpers introduced in previous patches. No functional changes. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20260519141518.389670-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-22clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macroBiju Das
Replace the per-SoC G3S_PLL146_CONF() and G3L_PLL1467_CONF() macros with a unified CPG_PLL_CONF(stby, setting) macro defined in rzg2l-cpg.h. Drop the now-redundant GET_REG_SAMPLL_{CLK1, SETTING}() macros, replacing the latter with CPG_PLL1_SETTING_OFFSET() using FIELD_GET() to extract the offset value. Update RZG3L_PLL_{STBY,MON}_OFFSET() macros to derive offsets directly from CPG_PLL_STBY_OFFSET(). No functional changes. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260519141518.389670-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-22clk: renesas: rzg2l: Simplify SAM PLL configuration macroBiju Das
Replace the PLL146_CONF() macro and its associated CPG_SAMPLL_CLK{1,2}(n) helpers with a single CPG_SAM_PLL_CONF(stby) macro that takes the PLL standby register offset directly. This removes the implicit coupling between PLL index n and register layout and eliminates the now-redundant GET_REG_SAMPLL_CLK2() macro. The RZ/V2M PLL4 definition is also updated to use the new macro with its explicit standby offset (0x100), removing the local PLL4_CONF define. No functional changes. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20260519141518.389670-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>