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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Here's the clk changes for the merge window which is dominated in the
diffstat by Qualcomm churning out new SoCs that need clk drivers.
Looking beyond the sheer amount of lines of mostly data there we have
a clk nexus DT binding change in the core clk framework and a driver
core patch to add a subsys driver macro.
The clock nexus support is useful for devices that map clks internally
or for connectors on a board that route clock signals to another
board. I suspect the use of this will expand in the future, so we have
unit tests to make sure it doesn't break.
The driver core change adds subsys_driver() and
subsys_platform_driver() so we can register early drivers without
open-coding that all (module_platform_driver() is at device initcall
level so it isn't be used).
Beyond the core framework bits we have lots of changes all over the
tree to initialize 'struct clk_init_data'. The potential risk here is
that someone forgets to initialize all the members of that structure
and either the clk flags cause weird behavior later on or the parents
are pointing at junk and the clk is orphaned forever. The patches just
initialize the thing with zeroes to be safe. Longer term we should
probably move this struct out of 'struct clk_hw' and pass it during
clk registration time. That's a much bigger change and would require
restructuring entire drivers that rely on the pointer being there.
Finally, we have the usual fixes like calculation updates for
dividers, handling error paths during clk registration, or fixing clk
data now that drivers are using them. Those patches are dwarfed by the
amount of new SoC support and only affect those SoCs and the consumers
of those clks. Overall I'm more concerned the clk_init_data patches
are going to expose some latent bugs that we didn't notice before
because something was relying on clks being orphaned and now they're
not.
Core:
- subsys_driver() / subsys_platform_driver() macros
- Clock nexus DT binding support (with KUnit tests)
- Spread-spectrum configuration validation
- Fully initialize struct clk_init_data across many drivers
New Drivers:
- Anlogic DR1V90 CRU
- ZTE zx297520v3 top, matrix, and LSP clocks
- Samsung Exynos5515 and ACPM driver extended to Exynos850.
- Qualcomm Eliza camera, camera-BIST, GPU, and video clks
- Qualcomm Hawi / Maili camera and GPU controllers
- Qualcomm Kuno global, RPMh
- Qualcomm MSM8952 global, RPM
- Qualcomm Nord camera/video clocks, EMAC interconnect, PHY resets
- Qualcomm IPQ5210 / IPQ9650 network clocks
- i.MX93 350 MHz fractional-N GP-PLL for display
- i.MX pll14xx spread-spectrum clock generation
- Amlogic A9 SCMI clock controller
- Allwinner single-divider "update bit" support
- EN7523 Serdes port selection"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (316 commits)
clk: imx: pll14xx: support spread spectrum clock generation
clk: cdce925: Size the PLL child name buffer for any int
clk: stm32: fix clock array size for STM32MP21
dt-bindings: clock: Convert HiSilicon clocks to DT schema
clk: lmk04832: Handle reset GPIO lookup errors
dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional
clk: tegra: bpmp: remove kcalloc
clk: mmp2-audio: add missing PM_CLK dependency
clk: zte: Introduce a driver for zx297520v3 LSP clocks
clk: zte: Introduce a driver for zx297520v3 matrix clocks
clk: zte: Introduce a driver for zx297520v3 top clocks
clk: zte: Add zx PLL support infrastructure
clk: zte: Add regmap-based clocks
clk: zte: Add Clock registration infrastructure
dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller
dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller
dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller
clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks
dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks
dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define
...
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'clk-tenstorrent' and 'clk-pile' into clk-next
* clk-renesas: (25 commits)
clk: renesas: r8a78000: Add SGASYNCD8_PERW_BUS
clk: renesas: rzg2l: Fix internal clock names
clk: renesas: r9a08g046: Add TSU and ADC1 clocks and resets
clk: renesas: Add support for RZ/G2M v3.0
clk: renesas: r9a08g046: Add CANFD clocks and resets
clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks
dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions
clk: renesas: r8a779g0: Add ZG clocks
clk: renesas: rcar-gen4: Tidy up DEF_GEN4_Z()
clk: renesas: r9a09g077: Register SYSC regmap
clk: renesas: rcar-gen3: Use FIELD_GET()
clk: renesas: rzv2h: Convert to clk_hw based provider API
clk: renesas: rzv2h: Drop duplicated parent lookup in fixed_mod_status_clk_register()
clk: renesas: r9a08g046: Add PCIe clocks and reset
clk: renesas: Make sure clk_init_data is fully initialized
clk: renesas: r9a08g046: Add clock and reset entries for LVDS
clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entries
clk: renesas: r9a08g046: Sort macro definitions alphabetically
clk: renesas: rzg2l: Add support for RZ/G3L DSI mux
clk: renesas: rzg2l: Add support for LVDS fixed-factor divider with 4:7 duty cycle
...
* clk-samsung:
clk: samsung: acpm: add Exynos850 support
clk: samsung: acpm: introduce driver data for SoC-specific clocks
clk: samsung: Introduce Exynos5515 clock driver
clk: samsung: clk-pll: Add support for pll_309
dt-bindings: clock: Add Exynos5515 SoC
* clk-starfive:
dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator
dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator
dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator
dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator
dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator
dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator
dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator
* clk-tenstorrent:
MAINTAINERS: Update RISC-V Tenstorrent SoC entry
clk: tenstorrent: use regmap_assign_bits() for conditional set/clear
clk: tenstorrent: Fix refcount leak on shared gate clk enable failure
clk: tenstorrent: Assign .num before accessing .hws
* clk-pile: (126 commits)
clk: imx: pll14xx: support spread spectrum clock generation
clk: cdce925: Size the PLL child name buffer for any int
clk: stm32: fix clock array size for STM32MP21
dt-bindings: clock: Convert HiSilicon clocks to DT schema
clk: lmk04832: Handle reset GPIO lookup errors
dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional
clk: tegra: bpmp: remove kcalloc
clk: mmp2-audio: add missing PM_CLK dependency
clk: zte: Introduce a driver for zx297520v3 LSP clocks
clk: zte: Introduce a driver for zx297520v3 matrix clocks
clk: zte: Introduce a driver for zx297520v3 top clocks
clk: zte: Add zx PLL support infrastructure
clk: zte: Add regmap-based clocks
clk: zte: Add Clock registration infrastructure
dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller
dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller
dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller
clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks
dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks
dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define
...
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and 'clk-qcom' into clk-next
* clk-allwinner:
clk: sunxi-ng: ccu_common: Use readl_relaxed_poll_timeout_atomic for PLL lock
clk: sunxi-ng: sun55i-a523-r-ccu: Use P-only clocks for timers
clk: sunxi-ng: sun55i-a523-ccu: Use P-only clocks for high-speed timers
clk: sunxi-ng: sun55i-a523-ccu: Use M-only clocks for MBUS, IOMMU and DRAM
clk: sunxi-ng: div: Add feature support to M clock macro
* clk-amlogic:
clk: meson: t7: don't mark sys_ampipe_nand as critical
dt-bindings: clock: Add Amlogic A9 SCMI clock controller
clk: meson: t7: keep the memory fabric clocks running
* clk-imx:
clk: imx: Fix clock reference leak in imx_obtain_fixed_clock_hw()
clk: imx: Fix clock reference leak in imx_get_clk_hw_by_name()
clk: imx: fracn-gppll: Add 350 MHz support
clk: imx: composite-93: return timeout from gate enable
* clk-microchip:
clk: at91: main: Drop unneeded cast in at91_clk_register_main_osc()
* clk-qcom: (156 commits)
clk: qcom: Add support for camera clock controller on Maili
clk: qcom: ipq9650: Use icc-clk for enabling NoC related clocks
clk: qcom: ipq5210: add 24MHz rate for USB UTMI clock
clk: qcom: ipq5332: add 24MHz rate for USB UTMI clock
clk: qcom: ipq5018: add 24MHz rate for USB UTMI clock
clk: qcom: Fix camera rivian PLL configuration settings
clk: qcom: videocc-sm8350: Use common probe handling for always-on clocks
clk: qcom: videocc-sm8250: Use common probe handling for always-on clocks
clk: qcom: videocc-sm7150: Use common probe handling for always-on clocks
clk: qcom: videocc-sm6350: Use common probe handling for always-on clocks
clk: qcom: videocc-sa8775p: Use common probe handling for always-on clocks
clk: qcom: lpasscorecc-sc7180: Use common probe handling for always-on clocks
clk: qcom: gpucc-x1p42100: Use common probe handling for always-on clocks
clk: qcom: gpucc-x1e80100: Use common probe handling for always-on clocks
clk: qcom: gpucc-sm8550: Use common probe handling for always-on clocks
clk: qcom: gpucc-sm4450: Use common probe handling for always-on clocks
clk: qcom: gpucc-sc8280xp: Use common probe handling for always-on clocks
clk: qcom: gpucc-sc7280: Use common probe handling for always-on clocks
clk: qcom: gpucc-sar2130p: Use common probe handling for always-on clocks
clk: qcom: gcc-x1e80100: Use common clock controller probe data
...
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Add support for spread spectrum clock (SSC) generation to the pll14xx
driver.
Tested on the video PLL of i.MX8MN and i.MX8MP based boards.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Acked-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260904101243.412006-5-dario.binacchi@amarulasolutions.com
Signed-off-by: Brian Masney <bmasney@redhat.com>
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The PLL child node name is built from "PLL%d" in a 6 byte stack buffer.
The PLL index is bounded by the chip's num_plls, at most 4, but GCC
cannot see that bound and, with W=1, warns that the formatted string
may not fit.
Make the buffer large enough to hold any int and use snprintf() with
sizeof() so the size stays tied to the declaration.
Fixes: 19fbbbbcd3a3 ("Add TI CDCE925 I2C controlled clock synthesizer driver")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://patch.msgid.link/20261014-cdce925-truncate-child-name-v1-1-00136be00c49@baylibre.com
Signed-off-by: Brian Masney <bmasney@redhat.com>
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STM32MP21_LAST_CLK is used as the number of entries of the onecell
clk_hw array allocated in stm32_rcc_clock_init(), and as the bound of
the clock IDs it can hold. It was wrongly set to CK_SCMI_KER_ETR (112),
which belongs to the SCMI clock ID range, whereas the RCC clock IDs
go up to CK_KER_STM (289).
As a result the array is too small, and registering a clock whose ID
is greater than 111 writes past the end of the allocated clk_hw array
(hws[cfg_clock->id] = hw), and consumers requesting such a clock
get rejected or read out of bounds.
Define STM32MP21_LAST_CLK as CK_KER_STM + 1 so that the array covers
all the RCC clock IDs.
No device tree node uses the STM32MP21 RCC driver yet, so there is no
need to backport this patch to stable kernels.
Fixes: 37ae8501cdb0 ("clk: stm32: introduce clocks for STM32MP21 platform")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Link: https://patch.msgid.link/20261012131859.215240-1-gabriel.fernandez@foss.st.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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devm_gpiod_get_optional() may return -EPROBE_DEFER or other errors,
but lmk04832_probe() currently ignores them.
Check the return value and propagate errors from the reset GPIO lookup.
Fixes: 3bc61cfd6f4a ("clk: add support for the lmk04832")
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
Link: https://patch.msgid.link/20261006110501.57051-1-phucduc.bui@gmail.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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Use a flexible array member to avoid allocating separately.
Use __counted_by for extra runtime analysis.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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pm_clk_suspend() and pm_clk_resume() are used but a PM_CLK dependency is
needed to expose them as actual functions. Otherwise they are defined as
NULL, which does not work with functions having parameters. NULL is
probably used as these functions are normally passed as function
pointers.
While here, convert the block from spaces to tabs so it matches the
surrounding Kconfig style.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202610010151.2W0MrmxE-lkp@intel.com/
Assisted-by: LLM
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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"LSP" is ZTE's term for this part of the SoC, I suspect it stands for
"low speed peripherals". The main UART is here, together with the flash
controller and more surplus proprietary timers.
It also has one more I2C controller that supposedly connects to a
battery charger, SPI for displays and I2S for analog telephones. The
boards I have don't have any of these components though.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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This clock controller controls high speed devices: CPU, DMA, RAM, SDIO,
Ethernet. The only non-clock, non-reset registers I have spotted here
are hardware spinlocks.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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This register space controls core devices: PLLs, the AHB bus, a lot of
timers, the USB controller, the Cortex M0 processor that boots the board
and a few other devices. For some reason the LTE coprocessor is also
partially controlled by it. The main application processor and DDR
memory are not found here though.
The register to reboot the board is found here, as well as a register to
control whether watchdog expiries cause a board reset.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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This patch adds code to decode and program PLL settings on ZTE's
zx297520v3 SoC. The PLLs on this SoC are usually programmed to static
values by the boot loader. The only situation where .set_rate matters is
dpll, which is not programmed in some cases. The bootloader always sets
fixed rates though: 624 MHz for mpll, 200 for gpll, 480 for upll.
Parsing the bootloader-programmed values allows the clock driver to fill
the clock tree with appropriately clocked parent clocks instead of
registering fixed clocks with hardcoded rates.
I only tested the code on zx297520v3. From looking at the hardcoded PLL
values in the old zx296702 / zx296718 code I believe that these PLLs use
the same encoding, so the code added by this patch should be reusable
and the file has a relatively generic name pll-zx.c.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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This is based on meson/clk-regmap.c, although slightly simplified. I
have kept the copyright lines at the top of the file to indicate its
origin.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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The next patches will implement the regmap clocks and PLL driver. The
actual hardware specific clock listing will live in a separate module.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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The WDT and WWDT muxes list PCLK3/4096 and PCLK4/4096 among their
possible parents, but the driver never registers the corresponding
clocks, so these parents could never be used.
Add pclk3_div4096 and pclk4_div4096 as fixed factor children of pclk3
and pclk4 and expose them through the clock provider.
Reported-by: Jacky Huang <ychuang570808@gmail.com>
Closes: https://lore.kernel.org/linux-clk/b8a8a65b-e302-4747-bc90-4920fc48795a@gmail.com/
Suggested-by: Jacky Huang <ychuang570808@gmail.com>
Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller")
Cc: stable@vger.kernel.org
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20260930-perso-ma35d1-upstream-clk-v6-5-48937ee6c9bb@bootlin.com
[jbrunet@baylibre.com: removed stale link trailer]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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The number of clocks is not a binding since this is a value that can
change. As such, in order to support the missing watchdog clocks and
allow the deprecation and removal of CLK_MAX_IDX from the bindings, we
need to switch to a local definition first.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20260930-perso-ma35d1-upstream-clk-v6-1-48937ee6c9bb@bootlin.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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The message is also stored as the probe deferral reason, where it wrongly
claims the 'enable'/'select' property is missing while it is the GPIO
provider that has not probed (yet?).
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patch.msgid.link/20260930114907.153690-1-francesco@dolcini.it
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
Pull gpio updates from Bartosz Golaszewski:
"Nothing stands out as particularly interesting, it's been a calm
cycle. We have three new drivers, support for more models and lots of
updates across many modules (details are in the signed tag as usual).
There are also some minor changes and additions to the in-kernel GPIO
API.
GPIO core:
- provide a new controller API: gpiochip_generic_get_config()
- return -EOPNOTSUPP instead of -ENODEV to user-space if it requests
hardware timestamping on systems where it's unavailable (no
user-space regressions reported)
New drivers:
- add a driver for ROHM BD73800 PMIC GPIO controller
- add a driver for Axiado AX3005 SGPIO controller
- add a driver for Analog Devices AD7768 GPIO controller
New hardware support:
- extend gpio-rcar with support for R-Car X5H (R8A78000)
- extend gpio-tegra186 with support for Tegra 268
Driver changes:
- refactor and improve gpio-rtd1625: switch to modern or better
fitting interfaces and improve coding style
- improve error handling of return values of
platform_get_irq_optional() in several drivers
- normalize the return value of the gpio_chip::get() callback in
gpio-siox in order to not propagate invalid values up to the GPIO
core
- implement gpio_chip::get_direction() for gpio-pcf857x
- use managed variants of notifier registration functions in several
drivers
- remove legacy gpio_set_value_cansleep() as it has no more users
- add pinctrl support to gpio-realtek-otto
- add runtime PM support to the gpio-regmap helper module
- add more ACPI GPIO quirks for various hardware
- stop needlessly reading gpio_chip::base in gpio-pxa
- add support for tracking of direction of generic GPIO chips with no
direction registers via pinctrl backend to gpio-mmio (use the new
core API: gpiochip_generic_get_config())
- use the "safe" variants of debugfs_create_file() in
gpio-sloppy-analyzer
- use device name as GPIO chip label in gpio-omap
- refactor bit ops in gpio-dln2
- prepare gpio-it87 for upcoming kmalloc_obj() conversion
Devicetree bindings:
- document new model in gpio-pca95xx
- allow the gpio-hogs property in gpio-zynq and fsl,qoriq-gpio
- allow the gpio-ranges property in gpio-realtek-otto
Misc fixes:
- add missing MODULE_ALIAS() to gpio-crystalcove
- fix a comment typo in example GPIO tools
- fix unbalanced brackets in documentation
- add names to regmaps in gpio-mvebu to avoid collisions in debugfs
output
- fix GPIO lookup using relative paths in GPIO ACPI"
* tag 'gpio-updates-for-v7.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (63 commits)
gpiolib: acpi: Fix GPIO lookup using relative path
gpio: legacy: Kill gpio_set_value_cansleep()
dt-bindings: gpio: pca95xx: add onnn,pca9655 with nxp,pca9555 fallback
gpiolib: acpi: Ignore GPIO 11 interrupt on Acer Nitro V 16S AI
gpio: pxa: stop reading gpio_chip::base in direction callbacks
gpio: axiado: add AX3005 SGPIO controller support
dt-bindings: gpio: add Axiado AX3005 SGPIO controller
gpiolib: acpi: Add quirk for Lenovo IdeaPad Slim 3 15ABR8
MAINTAINERS: Add ROHM BD73800 PMIC files
gpio: bd73800: Support ROHM BD73800 PMIC GPIOs
clk: bd718x7: Support ROHM BD73800
regulator: bd71828: Support ROHM BD73800
rtc: bd70528: Support RTC on ROHM BD73800
mfd: Support for ROHM BD73800 PMIC core
dt-bindings: mfd: ROHM BD73800 PMIC
dt-bindings: regulator: ROHM BD73800 regulators
dt-bindings: rohm,bd*: Ref common ROHM bindings
dt-bindings: mfd: Common ROHM PMIC properties
gpio: siox: normalize return value of gpio_get()
gpio: dln2: use assign_bit() where applicable
...
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Maili camcc is mostly identical to Hawi camcc, with a few clocks
removed, frequency table updates for a few other clocks, and PLL
configuration changes. Hence, reuse the Hawi camera clock controller
driver and extend it for the Qualcomm Maili SoC.
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260922-maili_camcc-v4-2-87704b664dde@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Register NoC clocks for PCIe and USB interconnect paths using the
icc-clk framework. Without this, the clocks required to create
interconnect paths and access peripherals connected to these NoCs are
not properly managed.
Also add icc_sync_state to ensure clock states are synchronized after all
consumers have probed.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://patch.msgid.link/20260811-ipq9650_icc-v2-2-55b8efbd62c6@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The USB UTMI reference clock must operate at 24 MHz, as recommended
by the hardware team, for reliable USB operation.
Validation showed that USB 3.2 hub enumeration with USB 2.0 devices
fails when the UTMI reference clock is not configured to the required
24 MHz rate. Configuring the UTMI reference clock to 24 MHz to resolve
the enumeration failure and ensure successful device detection.
Cc: stable@vger.kernel.org
Fixes: 844be6e24afd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5210 SoC")
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260921-ipq_clk_changes-v1-3-d242e3d49648@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The USB UTMI reference clock must operate at 24 MHz, as recommended
by the hardware team, for reliable USB operation.
Validation showed that USB 3.2 hub enumeration with USB 2.0 devices
fails when the UTMI reference clock is not configured to the required
24 MHz rate. Configuring the UTMI reference clock to 24 MHz to resolve
the enumeration failure and ensure successful device detection.
Cc: stable@vger.kernel.org
Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC")
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260921-ipq_clk_changes-v1-2-d242e3d49648@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The USB UTMI reference clock must operate at 24 MHz, as recommended
by the hardware team, for reliable USB operation.
Validation showed that USB 3.2 hub enumeration with USB 2.0 devices
fails when the UTMI reference clock is not configured to the required
24 MHz rate. Configuring the UTMI reference clock to 24 MHz to resolve
the enumeration failure and ensure successful device detection.
Cc: stable@vger.kernel.org
Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018")
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260921-ipq_clk_changes-v1-1-d242e3d49648@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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clk_alpha_pll_write_config() in the PLL configure function skips writes
to PLL registers when the configured value is 0. However, hardware
requires USER_CTL_U and CONFIG_CTL_U2 to be explicitly programmed to 0
for a few rivian PLLs.
Add a clk_regs_configure() callback to ensure these rivian PLL registers
are correctly initialized on Glymur, SM8750, and Kaanapali platforms.
Fixes: 97255eedd690 ("clk: qcom: camcc-glymur: Add camera clock controller driver")
Fixes: f9580bafd39c ("clk: qcom: camcc: Add camera clock controller driver for SM8750 SoC")
Fixes: 92aae35f667c ("clk: qcom: camcc: Add support for camera clock controller for Kaanapali")
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://patch.msgid.link/20260801-cam-rivian-pll-config-fix-v1-1-6918d58cd823@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Keep separate CBCR arrays for SM8350 and SC8280XP to preserve their
different XO clock register offsets.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-48-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-47-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-46-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-45-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-44-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Move the PLL register setup into the clk_regs_configure callback so it
still follows the SYSNOC branch enable. Attach this data only to the
LPASS core clock controller descriptor.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-43-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-42-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-41-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-40-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-39-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-38-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Move the GMU branch register update into the clk_regs_configure callback
so it still follows the always-on branch enables.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-37-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-36-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Move the always-on branch register offsets into a critical_cbcrs array,
describe the DFS RCGs through qcom_cc_driver_data and move the register
programming into the clk_regs_configure callback.
Use qcom_cc_probe() to perform the common initialization instead of
open-coding it in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-35-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Move the always-on branch register offsets into a critical_cbcrs array,
describe the DFS RCGs through qcom_cc_driver_data and move the register
programming into the clk_regs_configure callback.
Use qcom_cc_probe() to perform the common initialization instead of
open-coding it in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-34-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Move the always-on branch register offsets into a critical_cbcrs array,
describe the DFS RCGs through qcom_cc_driver_data and move the register
programming into the clk_regs_configure callback.
Use qcom_cc_probe() to perform the common initialization instead of
open-coding it in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-33-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Move the always-on branch register offsets into a critical_cbcrs array,
describe the DFS RCGs through qcom_cc_driver_data and move the register
programming into the clk_regs_configure callback.
Use qcom_cc_probe() to perform the common initialization instead of
open-coding it in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-32-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Move the always-on branch register offsets into a critical_cbcrs array
and describe the DFS RCGs through qcom_cc_driver_data.
Move the UFS PHY ICE core FORCE_MEM_CORE_ON setting into the
clk_regs_configure callback. This moves the UFS setting after the
always-on branch enables. Those branches serve the camera, display, GPU
and video blocks, not the UFS PHY ICE core clock. The UFS setting is
still applied before GDSC and CCF clock registration.
Keep the SM8475-specific PLL and RCG adjustments in the driver's probe
before calling qcom_cc_probe(), which now handles register mapping and
the common initialization sequence.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-31-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Move the always-on branch register offsets into a critical_cbcrs array,
describe the DFS RCGs through qcom_cc_driver_data and move the register
programming into the clk_regs_configure callback.
Use qcom_cc_probe() to perform the common initialization instead of
open-coding it in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-30-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Move the always-on branch register offsets into a critical_cbcrs array,
describe the DFS RCGs through qcom_cc_driver_data and move the register
programming into the clk_regs_configure callback.
Use qcom_cc_probe() to perform the common initialization instead of
open-coding it in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-29-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Move the always-on branch register offsets into a critical_cbcrs array,
describe the DFS RCGs through qcom_cc_driver_data and move the register
programming into the clk_regs_configure callback.
Use qcom_cc_probe() to perform the common initialization instead of
open-coding it in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-28-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the always-on branches, DFS RCGs and GPLL3 through
qcom_cc_driver_data. Associate GPLL3 with its existing configuration so
the common PLL setup invokes the Lucid EVO configuration helper.
Move the UFS PHY ICE core FORCE_MEM_CORE_ON setting and the video branch
register update into the clk_regs_configure callback. This moves the UFS
setting after the always-on branch enables. Those branches serve the
camera, display, GPU and video blocks, not the UFS PHY ICE core clock.
The UFS setting is still applied before GDSC and CCF clock registration,
while GPLL3 configuration still precedes the branch enables.
Use qcom_cc_probe() for the resulting common initialization sequence
instead of open-coding it in gcc_sm4450_probe().
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-26-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Move the always-on branch register offsets into a critical_cbcrs array
and describe the DFS RCGs through qcom_cc_driver_data.
Use qcom_cc_probe() to perform the common initialization instead of
open-coding it in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-25-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Move the always-on branch register offsets into a critical_cbcrs array
and move the register programming into the clk_regs_configure callback.
Use qcom_cc_probe() to perform the common initialization instead of
open-coding it in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-24-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Move the always-on branch register offsets into a critical_cbcrs array
and move the register programming into the clk_regs_configure callback.
Use qcom_cc_probe() to perform the common initialization instead of
open-coding it in the driver's probe.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-23-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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