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| author | Luca Coelho <luciano.coelho@intel.com> | 2026-06-09 12:52:37 +0300 |
|---|---|---|
| committer | Luca Coelho <luciano.coelho@intel.com> | 2026-08-13 11:20:22 +0300 |
| commit | f80c812804c3c07b891594cfc3db02326cba36aa (patch) | |
| tree | b48c9cae57d6d1ea1ac9e6bb1cc015dcf326e2e1 /tools/perf/scripts/python/stackcollapse.py | |
| parent | e26c92e712724e46ab707110a1bc379980f8d573 (diff) | |
| download | linux-f80c812804c3c07b891594cfc3db02326cba36aa.tar.gz linux-f80c812804c3c07b891594cfc3db02326cba36aa.zip | |
drm/i915/display: harden shifts in ICL_DPCLKA_CFGCR0_DDI_CLK_SEL macros
ICL_DPCLKA_CFGCR0 has a 2-bit DDI_CLK_SEL field per combo PHY, for
PHY_A..PHY_D only. Any other phy value (PHY_NONE, TypeC/SNPS PHYs) is
not valid here.
This is not a problem with the current implementation, because phy is
always valid when these macros are called, but it's more robust to
cast to unsigned so the shift is always well-defined.
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Link: https://patch.msgid.link/20260609095525.570614-3-luciano.coelho@intel.com
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions