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| author | Luca Coelho <luciano.coelho@intel.com> | 2026-06-09 12:52:36 +0300 |
|---|---|---|
| committer | Luca Coelho <luciano.coelho@intel.com> | 2026-08-13 11:20:22 +0300 |
| commit | e26c92e712724e46ab707110a1bc379980f8d573 (patch) | |
| tree | b9621fc7fd572d637d520c771ae542b8152d7bf7 /tools/perf/scripts/python/stackcollapse.py | |
| parent | eaed815ca3483c227e4ec80b86d1b3ce5c2508be (diff) | |
| download | linux-e26c92e712724e46ab707110a1bc379980f8d573.tar.gz linux-e26c92e712724e46ab707110a1bc379980f8d573.zip | |
drm/i915/display: harden masks in HSW_AUD_PIN_ELD_CP_VLD macros
HSW_AUD_PIN_ELD_CP_VLD has a 4-bit field per transcoder for
TRANSCODER_A..TRANSCODER_D only (bits 0..15). Any other transcoder
value (TRANSCODER_EDP, TRANSCODER_DSI_*, INVALID_TRANSCODER) is not
valid here.
This is not a problem with the current implementation, because trans
is always valid when these macros are called, but it's more robust to
mask the index to the low 2 bits so the shift is always well-defined.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Link: https://patch.msgid.link/20260609095525.570614-2-luciano.coelho@intel.com
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions