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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-08-26 16:40:23 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-08-27 13:54:36 +0300 |
| commit | e68e1b80d1639d017bc99857c0c0194df2461334 (patch) | |
| tree | 10968a4940bbfbca4a517ef239706914de2c4383 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 3f8c7b2fdd0e8256b4b7a314e1dd4e1a35e7e9dd (diff) | |
| download | linux-e68e1b80d1639d017bc99857c0c0194df2461334.tar.gz linux-e68e1b80d1639d017bc99857c0c0194df2461334.zip | |
drm/i915/cdclk: Notify DG2 pcode about pipe power wells regardless of CDCLK
We're currently skipping the pcode notifies on DG2 if the CDCLK isn't
changing while the power well counts would still need updating.
Do the pcode notifications also for pure pipe power well changes.
The lower level intel_set_cdclk() will skip doing any real work if the
actual CDCLK stuff doesn't need to change, so it's fine to call it even
if only the power wells need updating.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260826134033.13976-5-ville.syrjala@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
