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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-08-26 16:40:22 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-08-27 13:54:26 +0300 |
| commit | 3f8c7b2fdd0e8256b4b7a314e1dd4e1a35e7e9dd (patch) | |
| tree | 0ea06c9cd268a5bf7bb7952cd95c16359f9b564c /tools/perf/scripts/python/stackcollapse.py | |
| parent | dc2a960b6435477b3c769ab925e63d398ce4d336 (diff) | |
| download | linux-3f8c7b2fdd0e8256b4b7a314e1dd4e1a35e7e9dd.tar.gz linux-3f8c7b2fdd0e8256b4b7a314e1dd4e1a35e7e9dd.zip | |
drm/i915/cdclk: Do the DG2 CDCLK/pipe power well notify properly
The pcode post notify needs to happen after the CDCLK has been
changed, not before. Also move the pre_notify call a bit for the
sake of symmetry.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260826134033.13976-4-ville.syrjala@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions