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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-08-26 16:40:21 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-08-27 13:53:48 +0300 |
| commit | dc2a960b6435477b3c769ab925e63d398ce4d336 (patch) | |
| tree | be715d72e5893d757b2be86f6dd4e1d95d9f9e5a /tools/perf/scripts/python/stackcollapse.py | |
| parent | bed6347ae41b03bb80786b623c648cf221d7ed43 (diff) | |
| download | linux-dc2a960b6435477b3c769ab925e63d398ce4d336.tar.gz linux-dc2a960b6435477b3c769ab925e63d398ce4d336.zip | |
drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2
We are currently trying to pass the CDCLK in kHz to the pcode
on DG2, while the pcode expects a value in MHz units. Adjust
the units appropriately.
v2: Call it 'cdclk_mhz' (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260826134033.13976-3-ville.syrjala@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions