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| author | Guodong Xu <guodong.xu@oss.qualcomm.com> | 2026-09-20 03:18:27 -0400 |
|---|---|---|
| committer | Paul Walmsley <pjw@kernel.org> | 2026-10-08 15:24:49 -0600 |
| commit | ca0c312bdf6a1dd20ac2f5da1d0760b7925da4f3 (patch) | |
| tree | 2716420911f16ce43bfdc0febc68b94e15516831 /scripts/basic/split-include.c | |
| parent | 1fc72ff0d3fc38759bd050420eefc7aabc18936d (diff) | |
| download | linux-ca0c312bdf6a1dd20ac2f5da1d0760b7925da4f3.tar.gz linux-ca0c312bdf6a1dd20ac2f5da1d0760b7925da4f3.zip | |
riscv: dts: sophgo: sg2044: Add Zic64b ISA extension
The SG2044 cores have 64-byte cache blocks, described by their
cbom/cbop/cboz-block-size of 64, so they implement Zic64b. Declare it in
each core's riscv,isa-extensions.
Acked-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Guodong Xu <guodong.xu@oss.qualcomm.com>
Link: https://patch.msgid.link/20260920-rva23u64-hwprobe-v2-v8-7-5f14bc5c23d3@oss.qualcomm.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Diffstat (limited to 'scripts/basic/split-include.c')
0 files changed, 0 insertions, 0 deletions