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| author | Guodong Xu <guodong.xu@oss.qualcomm.com> | 2026-09-20 03:18:26 -0400 |
|---|---|---|
| committer | Paul Walmsley <pjw@kernel.org> | 2026-10-08 15:24:49 -0600 |
| commit | 1fc72ff0d3fc38759bd050420eefc7aabc18936d (patch) | |
| tree | a3969ff87bc11834d6bea93970e84f7701dcaf71 /scripts/basic/split-include.c | |
| parent | 7c4752c60f99be4a9a4c573ba86eacbe5d3cc823 (diff) | |
| download | linux-1fc72ff0d3fc38759bd050420eefc7aabc18936d.tar.gz linux-1fc72ff0d3fc38759bd050420eefc7aabc18936d.zip | |
riscv: dts: spacemit: k1: Add Zic64b ISA extension
The K1 X60 cores have 64-byte cache blocks, described by their
cbom/cbop/cboz-block-size of 64, so they implement Zic64b. Declare it in
each core's riscv,isa-extensions and in the deprecated riscv,isa string.
Signed-off-by: Guodong Xu <guodong.xu@oss.qualcomm.com>
Link: https://patch.msgid.link/20260920-rva23u64-hwprobe-v2-v8-6-5f14bc5c23d3@oss.qualcomm.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Diffstat (limited to 'scripts/basic/split-include.c')
0 files changed, 0 insertions, 0 deletions