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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-09-03 14:33:11 +0100 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> | 2026-09-11 10:15:37 +0200 |
| commit | c56d39e0f68d49ee45e610714bcfc87e14208498 (patch) | |
| tree | ac031a62bcad9894111a1f44720dd710828ce40c /scripts/basic/split-include.c | |
| parent | 55f914fdc951fe86a4845dedaf7ffe8e9ff66574 (diff) | |
| download | linux-c56d39e0f68d49ee45e610714bcfc87e14208498.tar.gz linux-c56d39e0f68d49ee45e610714bcfc87e14208498.zip | |
PCI: rzg3s-host: Add support for RZ/G3L SoC
Add SoC-specific data for the RZ/G3L (R9A08G046) PCIe controller and
register its "renesas,r9a08g046-pcie" compatible string. RZ/G3L reuses
the RZ/G3E config init/deinit callbacks and power resets, with its own
L1-allow syscon offset and mask.
Also increase the timeout in rzg3s_pcie_set_max_link_speed() to fix
the "Failed to set max link speed" message seen on RZ/G3L.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260903133320.144245-3-biju.das.jz@bp.renesas.com
Diffstat (limited to 'scripts/basic/split-include.c')
0 files changed, 0 insertions, 0 deletions