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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-09-03 14:33:10 +0100 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> | 2026-09-11 10:15:36 +0200 |
| commit | 55f914fdc951fe86a4845dedaf7ffe8e9ff66574 (patch) | |
| tree | 913169c960c6954509b2abb61202db0f53d17c38 /scripts/basic/split-include.c | |
| parent | 5d9e9b3a27994a2fadce283801b7104a68ea4c48 (diff) | |
| download | linux-55f914fdc951fe86a4845dedaf7ffe8e9ff66574.tar.gz linux-55f914fdc951fe86a4845dedaf7ffe8e9ff66574.zip | |
dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3L SoC
Extend the existing device tree bindings for Renesas RZ/G3S PCIe
controller to include support for the RZ/G3L (renesas,r9a08g046-pcie)
PCIe controller. The RZ/G3L PCIe controller is similar to RZ/G3S but has
some key differences:
- Has 3 clocks compared to 2 on other SoCs.
- Has a different set of reset signals
Add device tree bindings for renesas,r9a08g046-pcie compatible IPs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260903133320.144245-2-biju.das.jz@bp.renesas.com
Diffstat (limited to 'scripts/basic/split-include.c')
0 files changed, 0 insertions, 0 deletions