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path: root/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
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4 daysphy: qcom: qmp-pcie: Add IPQ9650 PCIe PHY supportKathiravan Thirumoorthy
Add support for the IPQ9650 platform, which includes three Gen3 x2 PCIe controllers and two Gen3 x1 PCIe controllers. The PHY instances require the on-chip refgen supply. Add the IPQ9650 Gen3 x1 and x2 QMP PCIe PHY configurations along with the refgen regulator supply. Note that an on-chip LDO, driven by the SoC CX, supplies the PHY voltages without requiring software control. Note that IPQ9650 does not support CX power collapse or rail scaling. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Link: https://patch.msgid.link/20260710-ipq9650_pcie_phy-v3-2-ef6018818d33@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
4 daysphy: qcom-qmp-pcie: Add support for ipq5210 PCIe physVaradarajan Narayanan
Add support for a PCIe phys found on Qualcomm ipq5210 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Link: https://patch.msgid.link/20260721-pcie-phy-v5-2-8d403ef7e780@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
6 daysphy: qcom: qmp-pcie: Skip PHY reset if already upKrishna Chaitanya Chundru
If the bootloader has already powered up the PCIe PHY, performing a full reset and waiting for the PHY to come up again adds unnecessary delay during boot. Extend the existing skip_init handling by introducing a skip_reset condition. When skip_init is active and the PHY status indicates that the PHY is already operational, skip asserting and deasserting the no-csr reset while still enabling the required resources during power-on. This allows reusing the bootloader-initialized PHY state and avoids redundant PHY reinitialization and PCIe link retraining, which can add hundred's of milliseconds of delay. This relies on the assumption that when skip_init is enabled and the PHY is reported as up, the bootloader has already configured the PHY correctly and the link is in a usable state. Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Link: https://patch.msgid.link/20260709-link_retain-v3-1-81a9d187bb61@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
6 daysphy: qcom: qmp-pcie: Add QMP PCIe PHY support for HawiMatthew Leung
Add the QMP PCIe PHY support for the Gen3 x2 and Gen4 x1 PHY found on the Hawi platform. Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20260707-hawi-phy-pcie-v4-4-8d9cc6324947@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
6 daysphy: qcom-qmp: Add v10.60 register offsetsMatthew Leung
Hawi SoC uses v10.60 register definitions for PCIe Gen4 x1. Add the new register offset headers for all four sub-blocks: - QSERDES-COM offsets - QSERDES TX/RX offsets - PCS offsets - PCS PCIe-specific offsets Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20260707-hawi-phy-pcie-v4-3-8d9cc6324947@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
6 daysphy: qcom-qmp: Add v10 register offsetsMatthew Leung
Hawi SoC uses v10 register definitions for PCIe Gen3 x2. Add the new register offset headers for all four sub-blocks: - QSERDES-COM offsets - QSERDES TX/RX offsets - PCS offsets - PCS PCIe-specific offsets Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20260707-hawi-phy-pcie-v4-2-8d9cc6324947@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-06-11phy: qcom: qmp-pcie: Add QMP PCIe PHY support for ElizaKrishna Chaitanya Chundru
Add QMP PCIe PHY support for the Eliza SoC. Introduce a new Gen3x1 PHY configuration with Eliza-specific initialization tables, and reuse the existing sm8550 Gen3x2 configuration for the Gen3x2 PHY instance. Also add the missing QPHY_PCIE_V6_PCS_PCIE_INT_AUX_CLK_CONFIG1 register definition to the PCIe V6 PCS header. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20260608-eliza-v3-3-9bdeb7434b28@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-10phy: qcom-qmp: Make QSERDES TXRX v2 registers explicitShawn Guo
Rename QSERDES TXRX v2 registers and the header to make version explicit. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20260314051325.198137-7-shengchao.guo@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-05-10phy: qcom-qmp: Use explicit QSERDES COM v2 register definitionsShawn Guo
As the code comments in the headers say, both qserdes-com and qserdes-com-v2 define QSERDES COM registers for QMP V2 PHY. Switch phy-qcom-qmp drivers to use register definitions in qserdes-com-v2 to make the QSERDES COM version explicit. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20260314051325.198137-3-shengchao.guo@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-01-01phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen4x2 PHYAbel Vesa
Glymur platform has two Gen4 2-lanes controllers, the fourth and sixth instances. Add support for their PHYs. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20251224-phy-qcom-pcie-add-glymur-v3-2-57396145bc22@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23phy: qcom: qmp-pcie: add QMP PCIe PHY tables for KaanapaliQiang Yu
Add QMP PCIe PHY support for the Kaanapali platform. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/20251124-kaanapali-pcie-phy-v4-5-d04ee9cca83b@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-11-20phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHYPrudhvi Yarlagadda
Add support for Gen5 x4 PCIe QMP PHY found on Glymur platform. Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com> Signed-off-by: Wenbin Yao <wenbin.yao@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Link: https://patch.msgid.link/20251103-glymur-pcie-upstream-v6-3-18a5e0a538dc@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-10-06Merge tag 'phy-for-6.18' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "The usual bunch of device support and update to drivers. New Support - Qualcomm SM8750 QMP PCIe PHY dual lane support, PMIV0104 eusb2 repeater support, QCS8300 eDP PHY support - Renesas RZ/T2H and RZ/N2H support and updates to driver for that - TI TCAN1051 phy support - Rockchip rk3588 dphy support, RK3528 combphy support Updates: - cadence updates for calibration and polling for ready and enabling of lower resolutions, runtime pm support, - Rockchip: enable U3 otg port - Renesas USXGMII mode support - Qualcomm UFS PHY and PLL regulator load support" * tag 'phy-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (64 commits) phy: rockchip: phy-rockchip-inno-csidphy: add support for rk3588 variant phy: rockchip: phy-rockchip-inno-csidphy: allow for different reset lines phy: rockchip: phy-rockchip-inno-csidphy: allow writes to grf register 0 dt-bindings: phy: rockchip-inno-csi-dphy: add rk3588 variant dt-bindings: phy: rockchip-inno-csi-dphy: make power-domains non-required phy: cadence: cdns-dphy: Enable lower resolutions in dphy phy: renesas: r8a779f0-ether-serdes: add new step added to latest datasheet phy: renesas: r8a779f0-ether-serdes: add USXGMII mode phy: sophgo: Add USB 2.0 PHY driver for Sophgo CV18XX/SG200X dt-bindings: phy: Add Sophgo CV1800 USB phy phy: cadence: cdns-dphy: Update calibration wait time for startup state machine phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY polling phy: renesas: rcar-gen3-usb2: Fix ID check logic with VBUS valid dt-bindings: phy: ti,tcan104x-can: Document TI TCAN1051 phy: lynx-28g: check return value when calling lynx_28g_pll_get phy: qcom: m31-eusb2: Fix the error log while enabling clock phy: rockchip: usbdp: Remove redundant ternary operators phy: renesas: rcar-gen3-usb2: Remove redundant ternary operators phy: hisilicon: Remove redundant ternary operators phy: qcom-qmp-ufs: Add PHY and PLL regulator load ...
2025-09-01phy: qcom: qmp-pcie: Fix PHY initialization when powered down by firmwareStephan Gerhold
Commit 0cc22f5a861c ("phy: qcom: qmp-pcie: Add PHY register retention support") added support for using the "no_csr" reset to skip configuration of the PHY if the init sequence was already applied by the boot firmware. The expectation is that the PHY is only turned on/off by using the "no_csr" reset, instead of powering it down and re-programming it after a full reset. The boot firmware on X1E does not fully conform to this expectation: If the PCIe3 link fails to come up (e.g. because no PCIe card is inserted), the firmware powers down the PHY using the QPHY_PCS_POWER_DOWN_CONTROL register. The QPHY_START_CTRL register is kept as-is, so the driver assumes the PHY is already initialized and skips the configuration/power up sequence. The PHY won't come up again without clearing the QPHY_PCS_POWER_DOWN_CONTROL, so eventually initialization fails: qcom-qmp-pcie-phy 1be0000.phy: phy initialization timed-out phy phy-1be0000.phy.0: phy poweron failed --> -110 qcom-pcie 1bd0000.pcie: cannot initialize host qcom-pcie 1bd0000.pcie: probe with driver qcom-pcie failed with error -110 This can be reliably reproduced on the X1E CRD, QCP and Devkit when no card is inserted for PCIe3. Fix this by checking the QPHY_PCS_POWER_DOWN_CONTROL register in addition to QPHY_START_CTRL. If the PHY is powered down with the register, it doesn't conform to the expectations for using the "no_csr" reset, so we fully re-initialize with the normal reset sequence. Also check the register more carefully to ensure all of the bits we expect are actually set. A simple !!(readl()) is not enough, because the PHY might be only partially set up with some of the expected bits set. Cc: stable@vger.kernel.org Fixes: 0cc22f5a861c ("phy: qcom: qmp-pcie: Add PHY register retention support") Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250821-phy-qcom-qmp-pcie-nocsr-fix-v3-1-4898db0cc07c@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-08-19phy: qcom-qmp-pcie: add dual lane PHY support for SM8750Krishna Chaitanya Chundru
The PCIe Gen3 x2 PHY for SM8750 uses new phy, add the required registers and offsets for this phy. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250809-pakala-v1-2-abf1c416dbaa@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-06-26phy: qcom: qmp-pcie: Update PHY settings for QCS8300 & SA8775PMrinmay Sarkar
Update the PHY settings to align with the latest PCIe PHY Hardware Programming Guide for both PCIe controllers on the SA8775P platform. Add the ln_shrd region for SA8775P, incorporating new register writes as specified in the updated Hardware Programming Guide. Update pcs table for QCS8300, since both QCS8300 and SA8775P are closely related and share same pcs settings. Signed-off-by: Mrinmay Sarkar <mrinmay.sarkar@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250617-update_phy-v5-1-2df83ed6a373@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-05-14phy: qcom: qmp-pcie: drop bogus x1e80100 qref supplyJohan Hovold
The PCIe PHYs on x1e80100 do not a have a qref supply so stop requesting one. This also avoids the follow warning at boot: qcom-qmp-pcie-phy 1be0000.phy: supply vdda-qref not found, using dummy regulator Fixes: e961ec81a39b ("phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3") Cc: Qiang Yu <quic_qianyu@quicinc.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20250429075440.19901-1-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-11phy: qcom: qmp-pcie: Add PHY register retention supportQiang Yu
Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the whole PHY (hardware and register), no_csr reset only resets PHY hardware but retains register values, which means PHY setting can be skipped during PHY init if PCIe link is enabled in bootloader and only no_csr is toggled after that. Hence, determine whether the PHY has been enabled in bootloader by verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is available, skip BCR reset and PHY register setting to establish the PCIe link with bootloader - programmed PHY settings. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Link: https://lore.kernel.org/r/20250411113120.651363-3-quic_wenbyao@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-04-11phy: qcom: pcie: Determine has_nocsr_reset dynamicallyKonrad Dybcio
Decide the in-driver logic based on whether the nocsr reset is present and defer checking the appropriateness of that to dt-bindings to save on boilerplate. Reset controller APIs are fine consuming a nullptr, so no additional checks are necessary there. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Link: https://lore.kernel.org/r/20250411113120.651363-2-quic_wenbyao@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-03-11phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300Ziyue Zhang
The PCIe Gen4x2 PHY for qcs8300 has a lot of difference with sa8775p. So the qcs8300_qmp_gen4x2_pcie_rx_alt_tbl for qcs8300 is added. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> Link: https://lore.kernel.org/r/20250310063103.3924525-3-quic_ziyuzhan@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHYKonrad Dybcio
Add a new, common configuration for Gen4x4 V6 PHYs without an init sequence. The bootloader configures the hardware once and the OS retains that configuration by using the NOCSR reset line (which doesn't drop register state on assert) in place of the "full reset" one. Use this new configuration for X1P42100's Gen4x4 PHY. Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-3-72cd4cdc767b@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: qualcomm: qmp-pcie: add support for SAR2130PDmitry Baryshkov
Add PCIe QMP PHY configuration for the Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-6-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: qualcomm: qmp-pcie: split PCS_LANE1 regionDmitry Baryshkov
The PCS_LANE1 region isn't a part of the PCS_PCIE region. It was handled this way as it simplified handled of devices with the old bindings. Nowadays it can be handled as is, without hacks. Split the PCS_LANE1 region from the PCS_PCIE / PCS_MISC region space. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-4-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: qcom: qmp: Add phy register and clk setting for QCS615 PCIeKrishna chaitanya chundru
Add support for GEN3 x1 PCIe PHY found on Qualcomm QCS615 platform. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241122023314.1616353-3-quic_ziyuzhan@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-11-27Merge tag 'phy-for-6.13' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New hardware support: - ST STM32MP25 combophy support - Sparx5 support for lan969x serdes and updates to driver to support this - NXP PTN3222 eUSB2 to USB2 redriver - Qualcomm SAR2130P eusb2 support, QCS8300 USB DW3 and QMP USB2 support, X1E80100 QMP PCIe PHY Gen4 support, QCS615 and QCS8300 QMP UFS PHY support and SA8775P eDP PHY support - Rockchip rk3576 usbdp and rk3576 usb2 phy support - Binding for Microchip ATA6561 can phy Updates: - Freescale driver updates from hdmi support - Conversion of rockchip rk3228 hdmi phy binding to yaml - Broadcom usb2-phy deprecated support dropped and USB init array update for BCM4908 - TI USXGMII mode support in J7200 - Switch back to platform_driver::remove() subsystem update" * tag 'phy-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (59 commits) phy: qcom: qmp: Fix lecacy-legacy typo phy: lan969x-serdes: add support for lan969x serdes driver dt-bindings: phy: sparx5: document lan969x phy: sparx5-serdes: add support for branching on chip type phy: sparx5-serdes: add indirection layer to register macros phy: sparx5-serdes: add function for getting the CMU index phy: sparx5-serdes: add ops to match data phy: sparx5-serdes: add constant for the number of CMU's phy: sparx5-serdes: add constants to match data phy: sparx5-serdes: add support for private match data phy: bcm-ns-usb2: drop support for old binding variant dt-bindings: phy: bcm-ns-usb2-phy: drop deprecated variant dt-bindings: phy: Add QMP UFS PHY compatible for QCS8300 dt-bindings: phy: qcom: snps-eusb2: Add SAR2130P compatible dt-bindings: phy: ti,tcan104x-can: Document Microchip ATA6561 phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions phy: airoha: Fix REG_CSR_2L_JCPLL_SDM_HREN config in airoha_pcie_phy_init_ssc_jcpll() phy: airoha: Fix REG_PCIE_PMA_TX_RESET config in airoha_pcie_phy_init_csr_2l() phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in airoha_pcie_phy_init_clk_out() phy: phy-rockchip-samsung-hdptx: Don't request RST_PHY/RST_ROPLL/RST_LCPLL ...
2024-10-17phy: qcom: qmp-pcie: drop bogus x1e80100 qref suppliesJohan Hovold
The PCIe PHYs on x1e80100 do not a have a qref supply so stop requesting one. This also avoids the follow warning at boot: qcom-qmp-pcie-phy 1bfc000.phy: supply vdda-qref not found, using dummy regulator Fixes: 9dab00ee9544 ("phy: qcom: qmp-pcie: Add Gen4 4-lanes mode for X1E80100") Fixes: 606060ce8fd0 ("phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE") Cc: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241015121406.15033-1-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3Qiang Yu
Currently driver supports only x4 lane based functionality using tx/rx and tx2/rx2 pair of register sets. To support 8 lane functionality with PCIe3, PCIe3 related QMP PHY provides additional programming which are available as txz and rxz based register set. Hence add txz and rxz based registers usage and programming sequences. As soon as software programs the txz and rxz based register set, hardware shall "broadcast" the same settings to the tx/rx pair of registers for all the 8 lanes, which saves the effort of software programming them one by one. There might be some tx and/or rx registers on some lanes need minor tweaks, program them after programming the txz and rxz reigster set. In addition, x1e80100 uses QMP PHY ver 6.30 for PCIe Gen4 x8, hence add two new header files to reflect the new register offsets. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20241017030412.265000-5-quic_qianyu@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-09-23Merge tag 'phy-for-6.12' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New hw support: - Rcar usb2 support for RZ/G3S SoC - Nuvoton MA35 SoC USB 2.0 PHY driver Removed: - obsolete qcom,usb-8x16-phy bindings Updates: - 4 lane PCIe support for Qualcomm X1E80100 - Constify structure in subsystem update - Subsystem simplification with scoped for each OF child loop update - Yaml conversion for Qualcomm sata phy, Hiilicon hi3798cv200-combphy bindings" * tag 'phy-for-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (40 commits) phy: renesas: rcar-gen3-usb2: Add support for the RZ/G3S SoC dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S phy bindings phy: renesas: rcar-gen3-usb2: Add support to initialize the bus phy: ti: j721e-wiz: Simplify with scoped for each OF child loop phy: ti: j721e-wiz: Drop OF node reference earlier for simpler code phy: ti: gmii-sel: Simplify with dev_err_probe() phy: ti: am654-serdes: Use scoped device node handling to simplify error paths phy: qcom: qmp-pcie-msm8996: Simplify with scoped for each OF child loop phy: mediatek: xsphy: Simplify with scoped for each OF child loop phy: mediatek: tphy: Simplify with scoped for each OF child loop phy: hisilicon: usb2: Simplify with scoped for each OF child loop phy: cadence: sierra: Simplify with scoped for each OF child loop phy: broadcom: brcm-sata: Simplify with scoped for each OF child loop phy: broadcom: bcm-cygnus-pcie: Simplify with scoped for each OF child loop phy: nuvoton: add new driver for the Nuvoton MA35 SoC USB 2.0 PHY dt-bindings: phy: nuvoton,ma35-usb2-phy: add new bindings phy: qcom: qmp-pcie: Configure all tables on port B PHY phy: airoha: adjust initialization delay in airoha_pcie_phy_init() dt-bindings: phy: socionext,uniphier: add top-level constraints phy: qcom: qmp-pcie: Add Gen4 4-lanes mode for X1E80100 ...
2024-08-29phy: qcom: qmp-pcie: Configure all tables on port B PHYQiang Yu
Currently, only the RX and TX tables are written to the second PHY (port B) when the 4-lanes mode is configured, but according to Qualcomm internal documentation, the pcs, pcs_misc, serdes and ln_shrd tables need to be written as well. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240805-phy-qcom-qmp-pcie-write-all-tbls-second-port-v3-1-6967c6bf61d1@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-29phy: qcom: qmp-pcie: Add Gen4 4-lanes mode for X1E80100Abel Vesa
The sixth PCIe controller on X1E80100 can be used in either 4-lanes mode or 2-lanes mode. Add the configuration and compatible for the 4-lane mode. Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20240823-x1e80100-phy-add-gen4x4-v3-2-b7765631ca01@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-04phy: qcom: qmp-pcie: Fix X1E80100 PCIe Gen4 PHY initialisationAbel Vesa
Update the PCIe Gen4 PHY init sequence with the latest based on internal Qualcomm documentation. Fixes: 606060ce8fd0 ("phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240801-x1e80100-phy-qmp-pcie-fix-config-v2-1-cdc0f22b4169@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-31phy: qcom: qmp: Add debug prints for register writesManivannan Sadhasivam
These register prints are useful to validate the init sequence against the Qcom internal documentation and also to share with the Qcom hw engineers to debug issues related to PHY. Sample debug prints: qcom-qmp-pcie-phy 1c0e000.phy: Writing Reg: QSERDES_V5_COM_SYSCLK_EN_SEL Offset: 0x0094 Val: 0xd9 qcom-qmp-pcie-phy 1c0e000.phy: Writing Reg: QSERDES_V5_COM_HSCLK_SEL Offset: 0x0158 Val: 0x11 Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240731152548.102987-1-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-15phy: qcom: qmp-pcie: restore compatibility with existing DTsDmitry Baryshkov
Existing device trees specify only a single clock-output-name for the PCIe PHYs. The function phy_aux_clk_register() expects a second entry in that property. When it doesn't find it, it returns an error, thus failing the probe of the PHY and thus breaking support for the corresponding PCIe host. Follow the approach of the combo USB+DT PHY and generate the name for the AUX clocks instead of requiring it in DT. Fixes: 583ca9ccfa80 ("phy: qcom: qmp-pcie: register second optional PHY AUX clock") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-1-730d1811acf4@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-06-03phy: qcom-qmp-pcie: Add support for IPQ9574 g3x1 and g3x2 PCIEsdevi priya
Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm IPQ9574 platform. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-5-quic_devipriy@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-05-04phy: qcom-qmp-pcie: add x4 lane EP support for sa8775pMrinmay Sarkar
Add support for x4 lane end point mode PHY found on sa8755p platform. Reusing existing serdes and pcs_misc table for EP and moved BIAS_EN_CLKBUFLR_EN register from RC serdes table to common serdes table as this register is part of both RC and EP. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1714494089-7917-2-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-05phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHYNeil Armstrong
The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock, enable this second clock by setting the proper 20MHz hardware rate in the Gen4x2 SM8[456]50 aux_clock_rate config fields. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-4-3ec0a966d52f@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-05phy: qcom: qmp-pcie: register second optional PHY AUX clockNeil Armstrong
The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock, add the code to register it for PHYs configs that sets a aux_clock_rate. In order to get the right clock, add qmp_pcie_clk_hw_get() which uses the newly introduced QMP_PCIE_PIPE_CLK & QMP_PCIE_PHY_AUX_CLK clock IDs and also supports the legacy bindings by returning the PIPE clock when #clock-cells=0. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-3-3ec0a966d52f@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-04-05phy: qcom: qmp-pcie: refactor clock register codeNeil Armstrong
The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock, in order to expose it, split the current clock registering in two parts: - CCF clock registering - DT clock registering Keep the of_clk_add_hw_provider/devm_add_action_or_reset to keep compatibility with the legacy subnode bindings. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-2-3ec0a966d52f@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-30phy: qcom: qmp: move common bits definitions to common headerDmitry Baryshkov
Move bit definitions for the common headers to the common phy-qcom-qmp.h header. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-5-a463d0b57836@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-30phy: qcom: qmp: move common functions to common headerDmitry Baryshkov
Move common init tables code to the common header phy-qcom-qmp-common.h. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-3-a463d0b57836@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-30phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550Qiang Yu
Align PCIe0 PHY settings with SM8550 latest PCIe PHY Hardware Programming Guide. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Link: https://lore.kernel.org/r/1703742157-69840-3-git-send-email-quic_qianyu@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-30phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550Can Guo
Align PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware Programming Guide. Signed-off-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Link: https://lore.kernel.org/r/1703742157-69840-2-git-send-email-quic_qianyu@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-24phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIEAbel Vesa
Add the X1E80100 G3 and G4 configurations. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20231223-x1e80100-phy-pcie-v2-3-223c0556908a@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-01-24phy: qcom: qmp-pcie: Add QMP v6 registers layoutAbel Vesa
For consistency, add the QMP v6 registers layout even though they are the same as v5. Also switch all QMP v6 PHYs to use this new layout. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20231223-x1e80100-phy-pcie-v2-2-223c0556908a@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-11-16phy: qcom: qmp-pcie: add QMP PCIe PHY tables for SM8650Neil Armstrong
Add QMP PCIe PHY support for the SM8650 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-phy-v2-6-a543a4c4b491@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-10-23phy: qcom-qmp-pcie: add endpoint support for sa8775pMrinmay Sarkar
Add support for dual lane end point mode PHY found on sa8755p platform. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1697715430-30820-4-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22phy: qcom-qmp-pcie: support SM8150 PCIe QMP PHYsDmitry Baryshkov
Reuse sm8250 configuration to add support for both single lane and dual lane PCIe PHYs on the Qualcomm SM8150 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230820142035.89903-8-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22phy: qcom-qmp-pcie: populate offsets configurationDmitry Baryshkov
Populate offsets configuration for the rest of UFS PHYs to make it possible to switch them to the new (single-node) bindings style. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230820142035.89903-7-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22phy: qcom-qmp-pcie: simplify clock handlingDmitry Baryshkov
For some of existing PHYs for new binding we are going to change refgen to more correct "rchng". Rather than introducing additional code to handle legacy vs current bindings (and clock names), use devm_clk_bulk_get_optional(). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230820142035.89903-6-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-08-22phy: qcom-qmp-pcie: keep offset tables sortedDmitry Baryshkov
In order to simplify adding new PHY configurations, keep register offset structs sorted by the version. Fixes: a05b6d5135ec ("phy: qcom-qmp-pcie: add support for sa8775p") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230820142035.89903-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>