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path: root/drivers/gpu/drm/amd/ras/core
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44 hoursdrm/amd/ras: Add pcie bif ras aca bank infoStanley.Yang
Support set pcie bif feature mask to support error injection. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
44 hoursdrm/amd/ras: Support invoke ras commandStanley.Yang
Use uniras core to invoke ras command. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
44 hoursdrm/amd/ras: Fix APU platform ras block feature maskStanley.Yang
the register c2pmsg_127 design only applies to dGPU not APU platform, so hard code ras block feature mask on APU platform. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
45 hoursdrm/amd/ras: use page units in EEPROM status messagesXiang Liu
Report the actual bad page count and convert the record threshold to pages using the per-ASIC row size. Keep threshold decisions in record units. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
45 hoursdrm/amd/ras: report bad page threshold only when exceededXiang Liu
Report a bad page threshold breach only when the saved record count exceeds the configured limit. Allow unlocking at equality to keep the EEPROM status consistent with that boundary. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
45 hoursdrm/amdgpu/ras: Use MP1 feature status to select fw-managed EEPROMCe Sun
Read the feature status of RAS_CORE_FW_FEATURE_BIT_RAS_EEPROM to determine whether to use firmware-managed EEPROM. Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
45 hoursdrm/amd/ras: report the bad page threshold in every work modeXiang Liu
Only the mode that halts runtime services flags the device once the bad page threshold is reached, so on a default or warn-only threshold the in-band CPER record and the out-of-band RMA reason are not emitted even though the table records that the threshold was hit. Track the threshold condition separately from the halt decision and use it to drive the report, so every mode except the debug one tells the host that the device reached its bad page budget. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
45 hoursdrm/amd/ras: report threshold status after bad pages are savedXiang Liu
The EEPROM table is tagged as over threshold while the new bad page records are written out, so the table status queried while the records are only queued still reports the table as writable. The device is therefore never flagged as having reached the threshold and neither the in-band CPER record nor the out-of-band RMA reason is emitted. Re-evaluate the table status once the records have been appended, so the report is driven by the state that was just persisted. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu : Update psp 13_0_15 ip block support for unirasCe Sun
Included psp_13_0_15 ip block for uniras Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: use __le32 pointer type to resolve the sparse warningsYiPeng Chai
Use __le32 pointer type to resolve the sparse warnings. sparse warnings: ras/core/eeprom.c:275:15: sparse: expected unsigned int [usertype] ras/core/eeprom.c:275:15: sparse: got restricted __le32 [usertype] ras/core/eeprom.c:277:15: sparse: expected unsigned int [usertype] ras/core/eeprom.c:277:15: sparse: got restricted __le32 [usertype] ras/core/eeprom.c:288:33: sparse: sparse: cast to restricted __le32 ras/core/eeprom.c:289:33: sparse: sparse: cast to restricted __le32 ras/core/eeprom.c:290:33: sparse: sparse: cast to restricted __le32 ras/core/eeprom.c:291:33: sparse: sparse: cast to restricted __le32 ras/core/eeprom.c:333:15: sparse: expected unsigned int [usertype] ras/core/eeprom.c:333:15: sparse: got restricted __le32 [usertype] ras/core/eeprom.c:343:15: sparse: sparse: cast to restricted __le32 Fixes: 5c3be5defc92 ("drm/amd/ras: Add eeprom ras functions") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202609101657.kczNjTnY-lkp@intel.com/ Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: use PCRU0 C2PMSG for Uniras on psp v15_0_3Candice Li
Add a dedicated ras_psp_v15_0_3 ip_func using PCRU0 C2PMSG_67/127 for psp ring wptr and RAS capability query. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for psp v15_0_3Gangliang Xie
add uniras support for psp v15_0_3 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for nbio v7_10_0Gangliang Xie
add uniras support for nbio v7_10_0 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for smu v15_0_3Gangliang Xie
add uniras support for smu_v15_0_3 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for GC 13Gangliang Xie
add uniras support for GC 13 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for umc v13Gangliang Xie
add uniras support for umc v13 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/ras: remove obsolete ras mp1 v13 manager codeYiPeng Chai
Remove obsolete ras mp1 v13 manager code. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/ras: add MP1 RAS feature status queryYiPeng Chai
Add a generic MP1 interface to query the status of RAS-related SMU features, including the PMFW EEPROM feature. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/ras: support aca debug mode for mp1 v13_0YiPeng Chai
Use uniras generic mp1 message to enable/disable aca debug mode on mp1 v13_0. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/ras: add pmfw-managed eeprom support for mp1_v13_0YiPeng Chai
Add pmfw-managed eeprom support for mp1_v13_0. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/ras: retrieve ras error info via common interface and message for ↵YiPeng Chai
mp1_v13_0 Retrieve ras error info via common interface and message for mp1_v13_0. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17Merge tag 'amd-drm-next-7.4-2026-09-10' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/amdgpu/kernel into drm-next amd-drm-next-7.4-2026-09-10: amdgpu: - Freesync fixes - GPUVM fix - Debugfs fixes - HDMI updates - IPS fix - GPU reset fix - RGB quantization fixes - SMU 13.0.x fixes - MES updates - UserQ updates - UVD fix - Various bounds checks - DML fixes - DCN 6 updates - NBIO 7.11.5 support - Audio fixes - More display KUnit tests - SMU 15 updates - RAS updates - VCN 5.0.2 updates - JPEG 5.0.2 updates - DCN 4.2 updates - PSR fixes - Misc cleanups - PSP 15.0.8 updates - RAS BERT support - RAS CPER updates - vblank fixes - LSDMA updates - GC 12.1 updates - MMHUB 4.2 updates - NBIO 6.3.2 updates - SMU 15.0.8 updates - IP discovery updates - GPU spatial partitioning updates - HDMI 2.1 freesync support - HDMI 2.1 ALLM support - HDMI 2.1 VRR support - Require jobs for IBs - Enable FRL for HDMI - MES oversubscription fixes - IH 6-7 updates - GMC 11-12 fault handling updates - Fixed point cleanup - Backlight fixes - GPUVM cleanup - Devcoredump fixes - UALoE (UALink over Ethernet) Support - SDMA userq fixes - GC 8 fix amdkfd: - Various bounds checks - SVM fixes - GC 12.1 updates - MES updates - Trap handler fixes - Debugfs fixes drm: - Add gem callback for when handle count goes to 0 - Rust fix UAPI: - INFO IOCTL fix for 32 bit userspace on 64 bit kernel - Add syncobj_points to USERQ signal ioctl Proposed userspace: * radeonsi NV_timeline_semaphore https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37335 * RADV user queues https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40808 - Add UALink support IOCTLs Proposed userspace: https://github.com/ROCm/rocm-systems/blob/35959f8e1260c7cee3e51a740e320be3856ee4ff/projects/rocr-runtime/libhsakmt/src/memory.c#L971 https://github.com/ROCm/rocm-systems/blob/35959f8e1260c7cee3e51a740e320be3856ee4ff/projects/rocr-runtime/libhsakmt/src/memory.c#L1036 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260910213040.826425-1-alexander.deucher@amd.com
2026-09-04treewide: refresh kmalloc_obj() conversionsKees Cook
This is another run of the Coccinelle script for converting kmalloc() family of allocations to kmalloc_obj() via the existing rules in scripts/coccinelle/api/kmalloc_objs.cocci This catches both the set of kmalloc() uses added since the first kmalloc_obj() conversions in v7.0 and adds a large group missed in the first pass due to Coccinelle not interacting well with the cleanup.h scoped_...() family of macros[1]. I worked around this with spatch's "--macro-file" argument to a file with all the scoped_...() macros mapped to Coccinelle's YACFE_ITERATOR[2] as that was the closest viable control flow indicator I could find. Build tested allmodconfig on x86, arm64, arm, loongarch, mips, powerpc, riscv, and s390 with no new warnings. Link: https://lore.kernel.org/lkml/202609021314.8A9C0B8@keescook/ [1] Link: https://github.com/coccinelle/coccinelle/blob/master/standard.h [2] Signed-off-by: Kees Cook <kees+treewide@kernel.org>
2026-09-02drm/amd/ras: take a log batch id only once there is something to logXiang Liu
The id is claimed before the banks are read, so a poll that ends up logging nothing still burns one and leaves a gap that every reader of the log then has to walk over. Claim it when the first record of the batch is about to go in. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/ras: report how far a CPER record query gotXiang Liu
The caller walks the log with cper_start_id and resumes at cper_start_id + real_cper_num, but the reply only counts the ids that held a record. A batch id that holds nothing therefore never moves the caller forward, and every such id makes it read the next populated batch one more time. Count the ids covered instead. The rewind to the last populated batch when the query starts at the end has the same effect once the caller has drained the log, and the latest id is already reported by the snapshot query, so drop it. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/ras: report the banks the scrubber loggedXiang Liu
A bank carrying the scrub bit was found by the background scrubber rather than by an access, which is worth telling apart from the rest when reading a log. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/ras: drop the ras_ prefix from the ACA v5 file namesXiang Liu
The prefix marks the files that back a hardware IP block. ACA is a bank format rather than an IP, and the rest of its files are named after it alone, so the v5 pair is the odd one out. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/ras: skip poison banks read through the UE channelXiang Liu
Outside of UMC a bank with the poison bit set describes the consumption of an error that was already reported, not a new uncorrectable one. Injecting an uncorrectable error while a workload is running therefore buries the real bank under a dump of GFX poison banks collected from every other device of the hive. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: add supported aca blocks mappingStanley.Yang
Add dacee_be, ucie_pcs, lsdma aca blocks mapping, add pcs_xgmi aca block info. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: tolerate an unsupported MCA debug mode controlXiang Liu
ras_mp1_set_debug_mode() reports -EOPNOTSUPP where the control does not exist, an SR-IOV guest among them. Treating that as fatal fails ras_core_sw_init() and takes RAS down on every VF. Nothing else in the MP1 block depends on it, so carry on. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: request GFX RAS features through ras_mgrXiang Liu
psp_ras_enable_features() returns 0 without sending anything once the RAS TA is loaded by ras_mgr, and nothing on that path sends ENABLE_FEATURES either. GFX RAS features therefore end up enabled by no one, silently, because the helper still reports success. This is harmless at boot, where the TA is loaded with poison_mode_en set while GFX is freshly initialized. It is not harmless across a reset: a mode2 reset clears the GFX side, amdgpu_gfx_ras_late_init() re-runs from the reset handler but its enable request goes nowhere, and GFX stops raising SQ EDC_FED. The visible effect is that only the first poison injection after boot is ever consumed. Every later one creates the poison in HBM and is never reported, since the first injection triggers the reset that breaks reporting. Add ras_psp_enable_features() to send ENABLE_FEATURES/DISABLE_FEATURES to the TA owned by ras_mgr, and route amdgpu_ras_feature_enable() through it. Newer parts arm RAS features inside the TA and must not be toggled by the driver, so restrict the request to GFX IP versions below 12.1.0. Fixes: e21b4356a304 ("drm/amdgpu: add switch to select firmware loading path for RAS RL and TA") Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: fix CPER command record retrievalXiang Liu
The CPER command reports the next batch ID as the latest valid record and does not handle a request starting at the write pointer. Batch trace responses also copy only the ACA interpretation of the log union. Report the latest valid CPER ID, select the preceding record for a write pointer request, expose a bounded command transfer size, and copy the complete log body for batch trace records. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: parse and route BERT sectionsXiang Liu
BERT may contain structured AMD crashdump, IA processor, Platform Memory, PCIe, and SMN sections. Replaying all sections for every GPU either duplicates GPU records or drops CPU and platform records when their topology IDs are compared with GPU OAM IDs. Parse the supported section formats in rascore. Route GPU records using the OAM identity and gate CPU and platform sections through an explicit owner selected by the operating-system integration layer. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: generate Platform Memory CPER recordsXiang Liu
Preserve standard Platform Memory sections recovered from BERT instead of wrapping them in the AMD crashdump format. Validate each boot section, copy its raw payload unchanged, align each complete record to a 32-bit boundary, and report the exact serialized size. Route Platform Memory records through a dedicated generator, independently of crashdump and processor records. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: generate processor CPER recordsXiang Liu
Encode runtime CPU machine checks with the standard IA Processor section, including APIC ID, machine-check status, bank MSR address, and SMCA register context. Also preserve IA Processor sections recovered from BERT as boot-notified records with their original context metadata and variable payload size. Route both forms through a processor-specific generator so they remain separate from AMD crashdump records. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: generate AMD crashdump CPER recordsXiang Liu
Populate the AMD crashdump common header and error information before serializing fatal and boot records. Validate that batched boot records share a section type, clamp the register context to the crashdump payload, and account for each record header when sizing the output. Keep AMD record dispatch in a dedicated helper so processor and Platform Memory generation can be added independently. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: define processor and memory CPER formatsXiang Liu
CPU machine-check and platform boot errors require standard processor and Platform Memory section definitions. The AMD crashdump format also uses a 64-byte common header followed by a common error information structure. Add the required GUIDs, validity fields, processor structures, and AMD crashdump wire layout so rascore can generate each record type. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: preserve CPU MCE context in the log ringXiang Liu
Processor CPER generation needs the APIC ID and machine-check bank number in addition to the ACA register values. Logging the full internal ACA bank also exceeds the stable fixed-size log body representation. Carry the APIC ID and bank number with incoming ACA banks and store CPU MCE events in a compact 128-byte log context for later CPER encoding. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: classify ACA v5 MCE statusXiang Liu
Machine-check records may not carry the hardware-maintained UMC error count expected by the normal polling path. As a result, valid deferred, uncorrected, and corrected MCE status values can remain unclassified. For MCE-originated banks, classify the error directly from the MCA status bits when normal UMC decoding does not produce an error count. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: allow waking RAS processing without an eventXiang Liu
GPU MCE handling queues bank data directly in the MCE FIFO and only needs to wake the RAS processing thread. Requiring a separate event request prevents this path from scheduling processing when no event object is available. Permit a NULL request to skip event queue insertion while still incrementing the interrupt request count and waking the processing thread. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: fix and improve bad page count calculationYiPeng Chai
Fix an issue where the saved bad page count is always zero. The cur_nps_valid_page_num field in the record already tracks the available bad page count, so use it directly to calculate the correct saved bad page number. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: filter out invalid pages from extended page addressesYiPeng Chai
Filter out invalid pages from extended page addresses. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: populate cper aca register info for rma deviceYiPeng Chai
Populate cper aca register info for rma device. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: add interface and improve extensibilityYiPeng Chai
Add interface and improve extensibility. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: fix ras cmd returning incorrect cper countYiPeng Chai
Fix ras cmd returning incorrect cper count. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: refactor ras cper to simplify adding new cper eventsYiPeng Chai
Restructure ras cper to improve extensibility, making it straightforward to add and handle new cper event types. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: add module parameter for unirasYiPeng Chai
Add module parameter for uniras. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: improve ras log timestamp precisionYiPeng Chai
Improve ras log timestamp precision. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: record crashdump BERT sections as boot CPERXiang Liu
Add a small section dispatch table and record AMD crashdump sections as RAS_LOG_EVENT_BOOT events. Preserve the original section GUID, severity, and a bounded copy of the section payload so the existing boot CPER generator can emit records for debugfs consumers. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: add BERT CPER table helpersXiang Liu
Add local HEST status and data entry layouts. Also add local helpers for revision-aware payload access, entry walking, and basic status validation. Move the BERT record processing prototype into a dedicated BERT header so the parser interface stays local to the BERT parser code. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>