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path: root/drivers/gpu/drm/amd/ras
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2026-10-01drm/amdgpu : Update psp 13_0_15 ip block support for unirasCe Sun
Included psp_13_0_15 ip block for uniras Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/ras: allow ClearMcaOnRead during GPU recover resumeCe Sun
Allow RAS_MP1_MSG_ClearMcaOnRead MP1 message in Mode1 reset, to support device debug mode setup on GPU recovery resume. Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: use __le32 pointer type to resolve the sparse warningsYiPeng Chai
Use __le32 pointer type to resolve the sparse warnings. sparse warnings: ras/core/eeprom.c:275:15: sparse: expected unsigned int [usertype] ras/core/eeprom.c:275:15: sparse: got restricted __le32 [usertype] ras/core/eeprom.c:277:15: sparse: expected unsigned int [usertype] ras/core/eeprom.c:277:15: sparse: got restricted __le32 [usertype] ras/core/eeprom.c:288:33: sparse: sparse: cast to restricted __le32 ras/core/eeprom.c:289:33: sparse: sparse: cast to restricted __le32 ras/core/eeprom.c:290:33: sparse: sparse: cast to restricted __le32 ras/core/eeprom.c:291:33: sparse: sparse: cast to restricted __le32 ras/core/eeprom.c:333:15: sparse: expected unsigned int [usertype] ras/core/eeprom.c:333:15: sparse: got restricted __le32 [usertype] ras/core/eeprom.c:343:15: sparse: sparse: cast to restricted __le32 Fixes: 5c3be5defc92 ("drm/amd/ras: Add eeprom ras functions") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202609101657.kczNjTnY-lkp@intel.com/ Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: suppress warning for unsupported early init serviceYiPeng Chai
Suppress warning for unsupported early init service. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add error log for unhandled gpu mce dataYiPeng Chai
Add error log for unhandled gpu mce data. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: use PCRU0 C2PMSG for Uniras on psp v15_0_3Candice Li
Add a dedicated ras_psp_v15_0_3 ip_func using PCRU0 C2PMSG_67/127 for psp ring wptr and RAS capability query. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for psp v15_0_3Gangliang Xie
add uniras support for psp v15_0_3 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for nbio v7_10_0Gangliang Xie
add uniras support for nbio v7_10_0 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for smu v15_0_3Gangliang Xie
add uniras support for smu_v15_0_3 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for GC 13Gangliang Xie
add uniras support for GC 13 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for umc v13Gangliang Xie
add uniras support for umc v13 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/ras: remove obsolete ras mp1 v13 manager codeYiPeng Chai
Remove obsolete ras mp1 v13 manager code. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/ras: use common mp1 ras interface for v13YiPeng Chai
Use the common mp1 ras manager interface for MP1 v13_0. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/ras: add MP1 RAS feature status queryYiPeng Chai
Add a generic MP1 interface to query the status of RAS-related SMU features, including the PMFW EEPROM feature. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/ras: support aca debug mode for mp1 v13_0YiPeng Chai
Use uniras generic mp1 message to enable/disable aca debug mode on mp1 v13_0. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/ras: add pmfw-managed eeprom support for mp1_v13_0YiPeng Chai
Add pmfw-managed eeprom support for mp1_v13_0. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/ras: retrieve ras error info via common interface and message for ↵YiPeng Chai
mp1_v13_0 Retrieve ras error info via common interface and message for mp1_v13_0. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/pm: Add GetRmaStatus messageYiPeng Chai
Add GetRmaStatus message for smu_v13_0_12 and smu_v15_0_8. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Kevin Wang <kevin.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/ras: enable UniRAS for psp v15_0_8Candice Li
Enable UniRAS for psp v15_0_8. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amdgpu: Extend logical to device instance lookup to all devicesTvrtko Ursulin
A subset of supported devices can have a mismatch between the logical and device engine instance numbers which the driver currently solves by a combination of lookup table generated at driver init time, and a conditionally set vfunc checked and used at runtime to do the lookup. As the requirement to do these lookups is relatively widespread in the code base, plus the fact the mapping table is already allocated for all possible hw ips and instances, we can significantly streamline them by initializing the said lookup table unconditionally to the predominant "identity map" (logical instance numbers equal to device instances), and allow affected parts to re-configure the table based on their configuration. The effect is that for each lookup site we replace the conditional followed by a indirect function call with a simple two-dimensional table lookup. Bloat-o-meter agrees the savings are significant: add/remove: 13/12 grow/shrink: 23/279 up/down: 51626/-198973 (-147347) ... Total: Before=10139692, After=9992345, chg -1.45% Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Cc: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/ras: apply the MCA debug mode on every RAS resumeXiang Liu
amdgpu_ras_late_init() sends the MCA configuration to PMFW, but it runs before RAS is ready on a device that still needs a hive reset, so the request is dropped and CE polling stays disabled. A reset loses the setting too, since PMFW is reloaded and nothing programs it again. The request is a single SMU message and does not depend on the RAS block being up, so amdgpu_ras_mgr_set_debug_mode() no longer requires it. Send it from amdgpu_ras_resume(), which covers modprobe, resume from suspend, GPU reset and reset on init, and drop it from amdgpu_ras_late_init(). Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17Merge tag 'amd-drm-next-7.4-2026-09-10' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/amdgpu/kernel into drm-next amd-drm-next-7.4-2026-09-10: amdgpu: - Freesync fixes - GPUVM fix - Debugfs fixes - HDMI updates - IPS fix - GPU reset fix - RGB quantization fixes - SMU 13.0.x fixes - MES updates - UserQ updates - UVD fix - Various bounds checks - DML fixes - DCN 6 updates - NBIO 7.11.5 support - Audio fixes - More display KUnit tests - SMU 15 updates - RAS updates - VCN 5.0.2 updates - JPEG 5.0.2 updates - DCN 4.2 updates - PSR fixes - Misc cleanups - PSP 15.0.8 updates - RAS BERT support - RAS CPER updates - vblank fixes - LSDMA updates - GC 12.1 updates - MMHUB 4.2 updates - NBIO 6.3.2 updates - SMU 15.0.8 updates - IP discovery updates - GPU spatial partitioning updates - HDMI 2.1 freesync support - HDMI 2.1 ALLM support - HDMI 2.1 VRR support - Require jobs for IBs - Enable FRL for HDMI - MES oversubscription fixes - IH 6-7 updates - GMC 11-12 fault handling updates - Fixed point cleanup - Backlight fixes - GPUVM cleanup - Devcoredump fixes - UALoE (UALink over Ethernet) Support - SDMA userq fixes - GC 8 fix amdkfd: - Various bounds checks - SVM fixes - GC 12.1 updates - MES updates - Trap handler fixes - Debugfs fixes drm: - Add gem callback for when handle count goes to 0 - Rust fix UAPI: - INFO IOCTL fix for 32 bit userspace on 64 bit kernel - Add syncobj_points to USERQ signal ioctl Proposed userspace: * radeonsi NV_timeline_semaphore https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37335 * RADV user queues https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40808 - Add UALink support IOCTLs Proposed userspace: https://github.com/ROCm/rocm-systems/blob/35959f8e1260c7cee3e51a740e320be3856ee4ff/projects/rocr-runtime/libhsakmt/src/memory.c#L971 https://github.com/ROCm/rocm-systems/blob/35959f8e1260c7cee3e51a740e320be3856ee4ff/projects/rocr-runtime/libhsakmt/src/memory.c#L1036 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260910213040.826425-1-alexander.deucher@amd.com
2026-09-10drm/amd/ras: Adjust second parameter of mp1_v13_0_eeprom_send_msg()Nathan Chancellor
When building with -Wincompatible-function-pointer-types-strict, a warning designed to catch kernel control flow integrity (kCFI) issues at build time, there is an instance around mp1_v13_0_eeprom_send_msg(): drivers/gpu/drm/amd/amdgpu/../ras/ras_mgr/amdgpu_ras_mp1_v13_0.c:157:25: error: incompatible function pointer types initializing 'int (*)(struct ras_core_context *, u32, uint32_t, uint32_t *)' (aka 'int (*)(struct ras_core_context *, unsigned int, unsigned int, unsigned int *)') with an expression of type 'int (struct ras_core_context *, enum ras_fw_eeprom_cmd, uint32_t, uint32_t *)' (aka 'int (struct ras_core_context *, enum ras_fw_eeprom_cmd, unsigned int, unsigned int *)') [-Werror,-Wincompatible-function-pointer-types-strict] 157 | .mp1_send_eeprom_msg = mp1_v13_0_eeprom_send_msg, | ^~~~~~~~~~~~~~~~~~~~~~~~~ While 'u32' and 'enum ras_fw_eeprom_cmd' are ABI compatible, hence no regular warning from -Wincompatible-function-pointer-types, the mismatch will trigger a kCFI violation when mp1_v13_0_eeprom_send_msg() is called indirectly. Update the second parameter of mp1_v13_0_eeprom_send_msg()' to be 'u32 msg_id' to match the prototype in 'struct ras_mp1_sys_func' (which was recently changed to support mp1_v15_0), clearing up the warning and kCFI violation. Fixes: 11a948c7817b ("drm/amd/ras: Support retrieving bad page info from mp1_v15_0") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-04treewide: refresh kmalloc_obj() conversionsKees Cook
This is another run of the Coccinelle script for converting kmalloc() family of allocations to kmalloc_obj() via the existing rules in scripts/coccinelle/api/kmalloc_objs.cocci This catches both the set of kmalloc() uses added since the first kmalloc_obj() conversions in v7.0 and adds a large group missed in the first pass due to Coccinelle not interacting well with the cleanup.h scoped_...() family of macros[1]. I worked around this with spatch's "--macro-file" argument to a file with all the scoped_...() macros mapped to Coccinelle's YACFE_ITERATOR[2] as that was the closest viable control flow indicator I could find. Build tested allmodconfig on x86, arm64, arm, loongarch, mips, powerpc, riscv, and s390 with no new warnings. Link: https://lore.kernel.org/lkml/202609021314.8A9C0B8@keescook/ [1] Link: https://github.com/coccinelle/coccinelle/blob/master/standard.h [2] Signed-off-by: Kees Cook <kees+treewide@kernel.org>
2026-09-02drm/amd/ras: take a log batch id only once there is something to logXiang Liu
The id is claimed before the banks are read, so a poll that ends up logging nothing still burns one and leaves a gap that every reader of the log then has to walk over. Claim it when the first record of the batch is about to go in. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/ras: report how far a CPER record query gotXiang Liu
The caller walks the log with cper_start_id and resumes at cper_start_id + real_cper_num, but the reply only counts the ids that held a record. A batch id that holds nothing therefore never moves the caller forward, and every such id makes it read the next populated batch one more time. Count the ids covered instead. The rewind to the last populated batch when the query starts at the end has the same effect once the caller has drained the log, and the latest id is already reported by the snapshot query, so drop it. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/ras: report the banks the scrubber loggedXiang Liu
A bank carrying the scrub bit was found by the background scrubber rather than by an access, which is worth telling apart from the rest when reading a log. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/ras: drop the ras_ prefix from the ACA v5 file namesXiang Liu
The prefix marks the files that back a hardware IP block. ACA is a bank format rather than an IP, and the rest of its files are named after it alone, so the v5 pair is the odd one out. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amd/ras: skip poison banks read through the UE channelXiang Liu
Outside of UMC a bank with the poison bit set describes the consumption of an error that was already reported, not a new uncorrectable one. Injecting an uncorrectable error while a workload is running therefore buries the real bank under a dump of GFX poison banks collected from every other device of the hive. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: add supported aca blocks mappingStanley.Yang
Add dacee_be, ucie_pcs, lsdma aca blocks mapping, add pcs_xgmi aca block info. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: record the fatal state on every device of the hiveXiang Liu
The fatal error interrupt is broadcast to every device of the hive and they all race for amdgpu_ras_global_ras_isr(), which hands -EBUSY to everyone but the winner. Treating that as a failure returns before the device is marked, so seven devices out of eight are left without their fatal and SRAM ECC state, the one that actually logged the error among them. KFD then tells the processes on those devices that the reset was a plain hang. -EBUSY only means the reset has already been asked for. Record the state anyway and leave the request to the winner. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: tell KFD the reset came from an ECC errorXiang Liu
kfd_signal_reset_event() picks between KFD_HW_EXCEPTION_ECC and KFD_HW_EXCEPTION_GPU_HANG from the SRAM ECC flag, and only delivers the memory exception event for the former. Nothing raises that flag on the RAS module paths, so a reset caused by an uncorrectable or a consumed poison error is reported to every process on the device as a plain hang and the runtime carries on instead of tearing the workload down. Raise it the way the per IP callbacks used to. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: drop the RAS module state when its sw init failsXiang Liu
The failure paths free the RAS manager but keep the flags that advertise it as the owner of RAS and of the RAS firmware load. Every entry point gated on those hits the NULL manager, hw_init turns that into -EINVAL and the whole probe fails. Clear both once the manager is gone, and route the allocation failure through the same place. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: tolerate an unsupported MCA debug mode controlXiang Liu
ras_mp1_set_debug_mode() reports -EOPNOTSUPP where the control does not exist, an SR-IOV guest among them. Treating that as fatal fails ras_core_sw_init() and takes RAS down on every VF. Nothing else in the MP1 block depends on it, so carry on. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: skip the RAS firmware reload when the block is downXiang Liu
A reset on init lowers the init level to the minimal XGMI set, which leaves out the RAS IP block, so its hw_init never runs and the PSP buffers stay unallocated. The resume that follows the reset tries to reload the RAS firmware into those buffers, fails with -ENOMEM and aborts the whole resume, taking every device of the hive down with it. There is nothing to reload in that case. Leave the block alone and let amdgpu_ras_resume_after_reset() bring it up, which is where it has to happen anyway: the RAS hardware init reads the EEPROM and so takes the reset domain lock for read, while the reset on init path still holds it for write, so doing it here deadlocks. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: use the per-ASIC reserved VRAM size for the bad page thresholdXiang Liu
The default bad page threshold is derived from the VRAM reserved for retirement, but ras_eeprom_i2c_config() hardcodes RAS_RESERVED_VRAM_SIZE_DEFAULT. amdgpu_ras_validate_threshold() instead derives it from con->reserved_pages_in_bytes, which amdgpu_ras_init_reserved_vram_size() doubles on MP0 v13.0.14. That part therefore ends up with a 128 bad page threshold where it should have 256, and reaches the limit after half as many retirements as intended. Reuse the value already computed for con->reserved_pages_in_bytes rather than deriving it again, so the two cannot drift apart. Fixes: c32092c39fa0 ("drm/amd/ras: Refactor EEPROM parameter config to support multiple ras EEPROMs") Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: request GFX RAS features through ras_mgrXiang Liu
psp_ras_enable_features() returns 0 without sending anything once the RAS TA is loaded by ras_mgr, and nothing on that path sends ENABLE_FEATURES either. GFX RAS features therefore end up enabled by no one, silently, because the helper still reports success. This is harmless at boot, where the TA is loaded with poison_mode_en set while GFX is freshly initialized. It is not harmless across a reset: a mode2 reset clears the GFX side, amdgpu_gfx_ras_late_init() re-runs from the reset handler but its enable request goes nowhere, and GFX stops raising SQ EDC_FED. The visible effect is that only the first poison injection after boot is ever consumed. Every later one creates the poison in HBM and is never reported, since the first injection triggers the reset that breaks reporting. Add ras_psp_enable_features() to send ENABLE_FEATURES/DISABLE_FEATURES to the TA owned by ras_mgr, and route amdgpu_ras_feature_enable() through it. Newer parts arm RAS features inside the TA and must not be toggled by the driver, so restrict the request to GFX IP versions below 12.1.0. Fixes: e21b4356a304 ("drm/amdgpu: add switch to select firmware loading path for RAS RL and TA") Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: fix CPER command record retrievalXiang Liu
The CPER command reports the next batch ID as the latest valid record and does not handle a request starting at the write pointer. Batch trace responses also copy only the ACA interpretation of the log union. Report the latest valid CPER ID, select the preceding record for a write pointer request, expose a bounded command transfer size, and copy the complete log body for batch trace records. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: assign BERT platform record ownershipXiang Liu
IA processor and Platform Memory BERT sections are system-wide records and must not be copied into every GPU RAS ring. Per-socket GPU records still need to be offered to each matching GPU. Assign platform sections to the first eligible RAS instance and claim each GPU socket before parsing its cached BERT data. Serialize ownership with the shared mutex and retain the state until the final RAS device exits. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: parse and route BERT sectionsXiang Liu
BERT may contain structured AMD crashdump, IA processor, Platform Memory, PCIe, and SMN sections. Replaying all sections for every GPU either duplicates GPU records or drops CPU and platform records when their topology IDs are compared with GPU OAM IDs. Parse the supported section formats in rascore. Route GPU records using the OAM identity and gate CPU and platform sections through an explicit owner selected by the operating-system integration layer. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: collect CPU MCE metadataXiang Liu
Processor CPER generation needs the APIC ID and bank number from the x86 machine-check record. CPU banks must also be logged by only one GPU to avoid duplicate processor records. Copy the APIC ID and bank number into the rascore ACA bank and route CPU banks through the first registered GPU. Keep GPU banks routed by their decoded socket ID. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: generate Platform Memory CPER recordsXiang Liu
Preserve standard Platform Memory sections recovered from BERT instead of wrapping them in the AMD crashdump format. Validate each boot section, copy its raw payload unchanged, align each complete record to a 32-bit boundary, and report the exact serialized size. Route Platform Memory records through a dedicated generator, independently of crashdump and processor records. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: generate processor CPER recordsXiang Liu
Encode runtime CPU machine checks with the standard IA Processor section, including APIC ID, machine-check status, bank MSR address, and SMCA register context. Also preserve IA Processor sections recovered from BERT as boot-notified records with their original context metadata and variable payload size. Route both forms through a processor-specific generator so they remain separate from AMD crashdump records. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: generate AMD crashdump CPER recordsXiang Liu
Populate the AMD crashdump common header and error information before serializing fatal and boot records. Validate that batched boot records share a section type, clamp the register context to the crashdump payload, and account for each record header when sizing the output. Keep AMD record dispatch in a dedicated helper so processor and Platform Memory generation can be added independently. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: define processor and memory CPER formatsXiang Liu
CPU machine-check and platform boot errors require standard processor and Platform Memory section definitions. The AMD crashdump format also uses a 64-byte common header followed by a common error information structure. Add the required GUIDs, validity fields, processor structures, and AMD crashdump wire layout so rascore can generate each record type. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: preserve CPU MCE context in the log ringXiang Liu
Processor CPER generation needs the APIC ID and machine-check bank number in addition to the ACA register values. Logging the full internal ACA bank also exceeds the stable fixed-size log body representation. Carry the APIC ID and bank number with incoming ACA banks and store CPU MCE events in a compact 128-byte log context for later CPER encoding. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: classify ACA v5 MCE statusXiang Liu
Machine-check records may not carry the hardware-maintained UMC error count expected by the normal polling path. As a result, valid deferred, uncorrected, and corrected MCE status values can remain unclassified. For MCE-originated banks, classify the error directly from the MCA status bits when normal UMC decoding does not produce an error count. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: allow waking RAS processing without an eventXiang Liu
GPU MCE handling queues bank data directly in the MCE FIFO and only needs to wake the RAS processing thread. Requiring a separate event request prevents this path from scheduling processing when no event object is available. Permit a NULL request to skip event queue insertion while still incrementing the interrupt request count and waking the processing thread. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: move BERT boot errors to BERT sw initXiang Liu
Keep BERT boot-error handling owned by the BERT module instead of letting the MCE notifier lifecycle drive BERT processing and cleanup. Group the cached boot-error state into a single structure so the related poll result, raw record data, per-socket write tracking, and lock are managed together. Expose only the standard BERT sw_init/sw_fini entry points. The RAS manager calls them around the existing MCE sw lifecycle, while the MCE code no longer includes BERT headers or calls BERT helpers directly. This lets BERT process cached boot records earlier in the RAS manager sw_init path and release its cached state independently during sw_fini. Signed-off-by: Xiang Liu <xiang.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: fix and improve bad page count calculationYiPeng Chai
Fix an issue where the saved bad page count is always zero. The cur_nps_valid_page_num field in the record already tracks the available bad page count, so use it directly to calculate the correct saved bad page number. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>