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authorDave Jiang <dave.jiang@intel.com>2026-10-09 14:11:10 -0700
committerDave Jiang <dave.jiang@intel.com>2026-10-09 14:11:10 -0700
commit91320b84095afcaf9e4f676eef5b05346d60eb79 (patch)
tree56b80b14d852082f122a3f04c43d1f3291cbffba /tools/perf/scripts/python
parent71392a644e88c6bb921cdf12cb2b00adec070fe4 (diff)
parent2658c66a5efb5f30f5ced708a5de831845b43f6d (diff)
downloadlinux-next-91320b84095afcaf9e4f676eef5b05346d60eb79.tar.gz
linux-next-91320b84095afcaf9e4f676eef5b05346d60eb79.zip
Merge branch 'for-7.4/cxl-fixes' into cxl-for-next
perf coordinates fixes: cxl/acpi: Convert QTG _DSM latencies to picoseconds cxl: Account for link width in latency calculation cxl/port: Convert PCIe link latency to nanoseconds GPF path fixes: cxl/pci: Update only the Port GPF timeout fields cxl/pci: Program the Port GPF timeouts before caching the DVSEC cxl/pci: Use the Device GPF DVSEC for restricted endpoints dport fixes: cxl/port: Attach endpoints to a dport under the lock that pins it cxl/core: Hold the dport host lock across dport lookup and use cxl/port: Clear cached dport pointers when a dport is removed
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