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authorKoichiro Den <den@valinux.co.jp>2026-10-09 13:54:52 +0900
committerDave Jiang <dave.jiang@intel.com>2026-10-09 14:10:35 -0700
commit2658c66a5efb5f30f5ced708a5de831845b43f6d (patch)
tree7cfe8b1f945770d88618a3c0797ab541cac775fc /tools/perf/scripts/python
parentdb4503d4575cdd2fad7e8a13a8a8ffcbc86d152d (diff)
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cxl/acpi: Convert QTG _DSM latencies to picoseconds
The QTG _DSM expects read and write latencies in picoseconds, as specified in CXL 3.0, Table 9-30. The code base originally kept the latencies passed to the QTG _DSM in picoseconds in effect. Commit 51293c565cf4 ("cxl: Fix incorrect region perf data calculation") normalized CDAT and host bridge latencies to nanoseconds, but did not add a conversion back to picoseconds when constructing the _DSM input. Firmware can therefore select QTG IDs using understated latencies. Convert the latencies to picoseconds when constructing the _DSM input package. Multiply in 64 bits and reject latencies that cannot fit in the DWORD inputs defined by the specification. Fixes: 51293c565cf4 ("cxl: Fix incorrect region perf data calculation") Cc: stable@vger.kernel.org Signed-off-by: Koichiro Den <den@valinux.co.jp> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20261009045452.1107921-4-den@valinux.co.jp Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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