Merge tag 'renesas-dts-for-v6.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.20 (take two)

  - Add cpufreq, thermal, GPIO IRQ, and CAN-FD support for the RZ/T2H
    and RZ/N2H SoCs and their EVK boards,
  - Add more serial (RSCI) and CAN-FD support for the RZ/V2H and RZ/V2N
    SoCs,
  - Drop unused .dtsi files,
  - Add I3C support for the RZ/G3E SMARC SoM,
  - Add GPIO support for the RZ/N1 SoC,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (27 commits)
  arm64: dts: renesas: rzt2h-rzn2h-evk: Reorder ADC nodes
  ARM: dts: r9a06g032: Add support for GPIO interrupts
  ARM: dts: r9a06g032: Add GPIO controllers
  arm64: dts: renesas: rzg3e-smarc-som: Enable I3C support
  arm64: dts: renesas: Use lowercase hex
  arm64: dts: renesas: Use hyphens in node names
  arm/arm64: dts: renesas: Drop unused .dtsi
  arm64: dts: renesas: rzt2h-n2h-evk-common: Use GPIO for SD0 write protect
  arm64: dts: renesas: r9a09g057: Add CANFD node
  arm64: dts: renesas: r9a09g056: Add CANFD node
  arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Enable CANFD
  arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable CANFD
  arm64: dts: renesas: r9a09g087: Add CANFD node
  arm64: dts: renesas: r9a09g077: Add CANFD node
  arm64: dts: renesas: r9a09g057: Add RSCI nodes
  arm64: dts: renesas: r9a09g056: Add RSCI nodes
  arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add GPIO keys
  arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add GPIO keys
  arm64: dts: renesas: r9a09g087: Add GPIO IRQ support
  arm64: dts: renesas: r9a09g077: Add GPIO IRQ support
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

3 files changed, 159 insertions, 114 deletions

diff --git a/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi b/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi
deleted file mode 100644
index 8d77579807ec..000000000000
--- a/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Device Tree Source for the GR-Peach audiocamera shield expansion board
- *
- * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
- */
-
-#include "r7s72100.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
-
-/ {
-	/* On-board camera clock. */
-	camera_clk: camera_clk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <27000000>;
-	};
-};
-
-&pinctrl {
-	i2c1_pins: i2c1 {
-		/* P1_2 as SCL; P1_3 as SDA */
-		pinmux = <RZA1_PINMUX(1, 2, 1)>, <RZA1_PINMUX(1, 3, 1)>;
-	};
-
-	vio_pins: vio {
-		/* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */
-		pinmux = <RZA1_PINMUX(1, 0, 5)>, /* VIO_VD */
-			 <RZA1_PINMUX(1, 1, 5)>, /* VIO_HD */
-			 <RZA1_PINMUX(2, 0, 7)>, /* VIO_D0 */
-			 <RZA1_PINMUX(2, 1, 7)>, /* VIO_D1 */
-			 <RZA1_PINMUX(2, 2, 7)>, /* VIO_D2 */
-			 <RZA1_PINMUX(2, 3, 7)>, /* VIO_D3 */
-			 <RZA1_PINMUX(2, 4, 7)>, /* VIO_D4 */
-			 <RZA1_PINMUX(2, 5, 7)>, /* VIO_D5 */
-			 <RZA1_PINMUX(2, 6, 7)>, /* VIO_D6 */
-			 <RZA1_PINMUX(2, 7, 7)>, /* VIO_D7 */
-			 <RZA1_PINMUX(10, 0, 6)>; /* VIO_CLK */
-	};
-};
-
-&i2c1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&i2c1_pins>;
-
-	status = "okay";
-	clock-frequency = <100000>;
-
-	camera@48 {
-		compatible = "aptina,mt9v111";
-		reg = <0x48>;
-
-		clocks = <&camera_clk>;
-
-		port {
-			mt9v111_out: endpoint {
-				remote-endpoint = <&ceu_in>;
-			};
-		};
-	};
-};
-
-&ceu {
-	pinctrl-names = "default";
-	pinctrl-0 = <&vio_pins>;
-
-	status = "okay";
-
-	port {
-		ceu_in: endpoint {
-			remote-endpoint = <&mt9v111_out>;
-		};
-	};
-};
diff --git a/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi b/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi
deleted file mode 100644
index 6e7589ea7562..000000000000
--- a/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Common file for the AA121TD01 panel connected to Renesas R-Car boards
- *
- * Copyright (C) 2015 Renesas Electronics Corp.
- */
-
-/ {
-	panel {
-		compatible = "mitsubishi,aa121td01", "panel-lvds";
-
-		width-mm = <261>;
-		height-mm = <163>;
-		data-mapping = "jeida-18";
-
-		panel-timing {
-			/* 1280x800 @60Hz */
-			clock-frequency = <71000000>;
-			hactive = <1280>;
-			vactive = <800>;
-			hsync-len = <70>;
-			hfront-porch = <20>;
-			hback-porch = <70>;
-			vsync-len = <5>;
-			vfront-porch = <3>;
-			vback-porch = <15>;
-		};
-
-		port {
-			panel_in: endpoint {
-				remote-endpoint = <&lvds_connector>;
-			};
-		};
-	};
-};
-
-&lvds_connector {
-	remote-endpoint = <&panel_in>;
-};
diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index 7c143bd5d7c9..f4f760aff28b 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -515,6 +515,165 @@
 				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
 
+		/*
+		 * The GPIO mapping to the corresponding pins is not obvious.
+		 * See the hardware documentation for details.
+		 */
+		gpio0: gpio@5000b000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x5000b000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&sysctrl R9A06G032_HCLK_GPIO0>;
+			clock-names = "bus";
+
+			/* GPIO0a[0]      connected to pin  GPIO0      */
+			/* GPIO0a[1..2]   connected to pins GPIO3..4   */
+			/* GPIO0a[3..4]   connected to pins GPIO9..10  */
+			/* GPIO0a[5]      connected to pin  GPIO12     */
+			/* GPIO0a[6..7]   connected to pins GPIO15..16 */
+			/* GPIO0a[8..9]   connected to pins GPIO21..22 */
+			/* GPIO0a[10]     connected to pin  GPIO24     */
+			/* GPIO0a[11..12] connected to pins GPIO27..28 */
+			/* GPIO0a[13..14] connected to pins GPIO33..34 */
+			/* GPIO0a[15]     connected to pin  GPIO36     */
+			/* GPIO0a[16..17] connected to pins GPIO39..40 */
+			/* GPIO0a[18..19] connected to pins GPIO45..46 */
+			/* GPIO0a[20]     connected to pin  GPIO48     */
+			/* GPIO0a[21..22] connected to pins GPIO51..52 */
+			/* GPIO0a[23..24] connected to pins GPIO57..58 */
+			/* GPIO0a[25..31] connected to pins GPIO62..68 */
+			gpio0a: gpio-port@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+
+				interrupt-controller;
+				interrupt-parent = <&gpioirqmux>;
+				interrupts = < 0  1  2  3  4  5  6  7
+					       8  9 10 11 12 13 14 15
+					      16 17 18 19 20 21 22 23
+					      24 25 26 27 28 29 30 31>;
+				#interrupt-cells = <2>;
+			};
+
+			/* GPIO0b[0..1]   connected to pins GPIO1..2   */
+			/* GPIO0b[2..5]   connected to pins GPIO5..8   */
+			/* GPIO0b[6]      connected to pin  GPIO11     */
+			/* GPIO0b[7..8]   connected to pins GPIO13..14 */
+			/* GPIO0b[9..12]  connected to pins GPIO17..20 */
+			/* GPIO0b[13]     connected to pin  GPIO23     */
+			/* GPIO0b[14..15] connected to pins GPIO25..26 */
+			/* GPIO0b[16..19] connected to pins GPIO29..32 */
+			/* GPIO0b[20]     connected to pin  GPIO35     */
+			/* GPIO0b[21..22] connected to pins GPIO37..38 */
+			/* GPIO0b[23..26] connected to pins GPIO41..44 */
+			/* GPIO0b[27]     connected to pin  GPIO47     */
+			/* GPIO0b[28..29] connected to pins GPIO49..50 */
+			/* GPIO0b[30..31] connected to pins GPIO53..54 */
+			gpio0b: gpio-port@1 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <1>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+			};
+		};
+
+		gpio1: gpio@5000c000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x5000c000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&sysctrl R9A06G032_HCLK_GPIO1>;
+			clock-names = "bus";
+
+			/* GPIO1a[0..4]  connected to pins GPIO69..73 */
+			/* GPIO1a[5..31] connected to pins GPIO95..121 */
+			gpio1a: gpio-port@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+
+				interrupt-controller;
+				interrupt-parent = <&gpioirqmux>;
+				interrupts = <32 33 34 35 36 37 38 39
+					      40 41 42 43 44 45 46 47
+					      48 49 50 51 52 53 54 55
+					      56 57 58 59 60 61 62 63>;
+				#interrupt-cells = <2>;
+			};
+
+			/* GPIO1b[0..1]   connected to pins GPIO55..56 */
+			/* GPIO1b[2..4]   connected to pins GPIO59..61 */
+			/* GPIO1b[5..25]  connected to pins GPIO74..94 */
+			/* GPIO1b[26..31] connected to pins GPIO150..155 */
+			gpio1b: gpio-port@1 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <1>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+			};
+		};
+
+		gpio2: gpio@5000d000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x5000d000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&sysctrl R9A06G032_HCLK_GPIO2>;
+			clock-names = "bus";
+
+			/* GPIO2a[0..27]  connected to pins GPIO122..149 */
+			/* GPIO2a[28..31] connected to pins GPIO156..159 */
+			gpio2a: gpio-port@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+
+				interrupt-controller;
+				interrupt-parent = <&gpioirqmux>;
+				interrupts = <64 65 66 67 68 69 70 71
+					      72 73 74 75 76 77 78 79
+					      80 81 82 83 84 85 86 87
+					      88 89 90 91 92 93 94 95>;
+				#interrupt-cells = <2>;
+			};
+
+			/* GPIO2b[0..9] connected to pins GPIO160..169 */
+			gpio2b: gpio-port@1 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <1>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <10>;
+			};
+		};
+
+		gpioirqmux: interrupt-controller@51000480 {
+			compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux";
+			reg = <0x51000480 0x20>;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			interrupt-map-mask = <0x7f>;
+
+			/*
+			 * Example mapping entry. Board DTs need to overwrite
+			 * 'interrupt-map' with their specific mapping. Check
+			 * the irqmux binding documentation for details.
+			 */
+			interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+		};
+
 		can0: can@52104000 {
 			compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
 			reg = <0x52104000 0x800>;