diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2026-01-26 15:36:27 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2026-01-26 15:36:28 +0100 |
| commit | ab8292d7021696dfd0faf9477b37b8c4b3b89adf (patch) | |
| tree | b7d02751b6a4b80d86dae20ea31049eb8cc2ec32 | |
| parent | 6e646eac67c6b77e2025239d2da2196ef7285c3c (diff) | |
| parent | 5979010bcc665e9bcf41b22f111b3fe7fc4eadb1 (diff) | |
| download | linux-next-ab8292d7021696dfd0faf9477b37b8c4b3b89adf.tar.gz linux-next-ab8292d7021696dfd0faf9477b37b8c4b3b89adf.zip | |
Merge tag 'renesas-dts-for-v6.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.20 (take two)
- Add cpufreq, thermal, GPIO IRQ, and CAN-FD support for the RZ/T2H
and RZ/N2H SoCs and their EVK boards,
- Add more serial (RSCI) and CAN-FD support for the RZ/V2H and RZ/V2N
SoCs,
- Drop unused .dtsi files,
- Add I3C support for the RZ/G3E SMARC SoM,
- Add GPIO support for the RZ/N1 SoC,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (27 commits)
arm64: dts: renesas: rzt2h-rzn2h-evk: Reorder ADC nodes
ARM: dts: r9a06g032: Add support for GPIO interrupts
ARM: dts: r9a06g032: Add GPIO controllers
arm64: dts: renesas: rzg3e-smarc-som: Enable I3C support
arm64: dts: renesas: Use lowercase hex
arm64: dts: renesas: Use hyphens in node names
arm/arm64: dts: renesas: Drop unused .dtsi
arm64: dts: renesas: rzt2h-n2h-evk-common: Use GPIO for SD0 write protect
arm64: dts: renesas: r9a09g057: Add CANFD node
arm64: dts: renesas: r9a09g056: Add CANFD node
arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Enable CANFD
arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable CANFD
arm64: dts: renesas: r9a09g087: Add CANFD node
arm64: dts: renesas: r9a09g077: Add CANFD node
arm64: dts: renesas: r9a09g057: Add RSCI nodes
arm64: dts: renesas: r9a09g056: Add RSCI nodes
arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add GPIO keys
arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add GPIO keys
arm64: dts: renesas: r9a09g087: Add GPIO IRQ support
arm64: dts: renesas: r9a09g077: Add GPIO IRQ support
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
47 files changed, 1426 insertions, 986 deletions
diff --git a/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi b/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi deleted file mode 100644 index 8d77579807ec..000000000000 --- a/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the GR-Peach audiocamera shield expansion board - * - * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org> - */ - -#include "r7s72100.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/r7s72100-pinctrl.h> - -/ { - /* On-board camera clock. */ - camera_clk: camera_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; -}; - -&pinctrl { - i2c1_pins: i2c1 { - /* P1_2 as SCL; P1_3 as SDA */ - pinmux = <RZA1_PINMUX(1, 2, 1)>, <RZA1_PINMUX(1, 3, 1)>; - }; - - vio_pins: vio { - /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */ - pinmux = <RZA1_PINMUX(1, 0, 5)>, /* VIO_VD */ - <RZA1_PINMUX(1, 1, 5)>, /* VIO_HD */ - <RZA1_PINMUX(2, 0, 7)>, /* VIO_D0 */ - <RZA1_PINMUX(2, 1, 7)>, /* VIO_D1 */ - <RZA1_PINMUX(2, 2, 7)>, /* VIO_D2 */ - <RZA1_PINMUX(2, 3, 7)>, /* VIO_D3 */ - <RZA1_PINMUX(2, 4, 7)>, /* VIO_D4 */ - <RZA1_PINMUX(2, 5, 7)>, /* VIO_D5 */ - <RZA1_PINMUX(2, 6, 7)>, /* VIO_D6 */ - <RZA1_PINMUX(2, 7, 7)>, /* VIO_D7 */ - <RZA1_PINMUX(10, 0, 6)>; /* VIO_CLK */ - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <100000>; - - camera@48 { - compatible = "aptina,mt9v111"; - reg = <0x48>; - - clocks = <&camera_clk>; - - port { - mt9v111_out: endpoint { - remote-endpoint = <&ceu_in>; - }; - }; - }; -}; - -&ceu { - pinctrl-names = "default"; - pinctrl-0 = <&vio_pins>; - - status = "okay"; - - port { - ceu_in: endpoint { - remote-endpoint = <&mt9v111_out>; - }; - }; -}; diff --git a/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi b/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi deleted file mode 100644 index 6e7589ea7562..000000000000 --- a/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for the AA121TD01 panel connected to Renesas R-Car boards - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -/ { - panel { - compatible = "mitsubishi,aa121td01", "panel-lvds"; - - width-mm = <261>; - height-mm = <163>; - data-mapping = "jeida-18"; - - panel-timing { - /* 1280x800 @60Hz */ - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hsync-len = <70>; - hfront-porch = <20>; - hback-porch = <70>; - vsync-len = <5>; - vfront-porch = <3>; - vback-porch = <15>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_connector>; - }; - }; - }; -}; - -&lvds_connector { - remote-endpoint = <&panel_in>; -}; diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 7c143bd5d7c9..f4f760aff28b 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -515,6 +515,165 @@ <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; }; + /* + * The GPIO mapping to the corresponding pins is not obvious. + * See the hardware documentation for details. + */ + gpio0: gpio@5000b000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000b000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sysctrl R9A06G032_HCLK_GPIO0>; + clock-names = "bus"; + + /* GPIO0a[0] connected to pin GPIO0 */ + /* GPIO0a[1..2] connected to pins GPIO3..4 */ + /* GPIO0a[3..4] connected to pins GPIO9..10 */ + /* GPIO0a[5] connected to pin GPIO12 */ + /* GPIO0a[6..7] connected to pins GPIO15..16 */ + /* GPIO0a[8..9] connected to pins GPIO21..22 */ + /* GPIO0a[10] connected to pin GPIO24 */ + /* GPIO0a[11..12] connected to pins GPIO27..28 */ + /* GPIO0a[13..14] connected to pins GPIO33..34 */ + /* GPIO0a[15] connected to pin GPIO36 */ + /* GPIO0a[16..17] connected to pins GPIO39..40 */ + /* GPIO0a[18..19] connected to pins GPIO45..46 */ + /* GPIO0a[20] connected to pin GPIO48 */ + /* GPIO0a[21..22] connected to pins GPIO51..52 */ + /* GPIO0a[23..24] connected to pins GPIO57..58 */ + /* GPIO0a[25..31] connected to pins GPIO62..68 */ + gpio0a: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + + interrupt-controller; + interrupt-parent = <&gpioirqmux>; + interrupts = < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31>; + #interrupt-cells = <2>; + }; + + /* GPIO0b[0..1] connected to pins GPIO1..2 */ + /* GPIO0b[2..5] connected to pins GPIO5..8 */ + /* GPIO0b[6] connected to pin GPIO11 */ + /* GPIO0b[7..8] connected to pins GPIO13..14 */ + /* GPIO0b[9..12] connected to pins GPIO17..20 */ + /* GPIO0b[13] connected to pin GPIO23 */ + /* GPIO0b[14..15] connected to pins GPIO25..26 */ + /* GPIO0b[16..19] connected to pins GPIO29..32 */ + /* GPIO0b[20] connected to pin GPIO35 */ + /* GPIO0b[21..22] connected to pins GPIO37..38 */ + /* GPIO0b[23..26] connected to pins GPIO41..44 */ + /* GPIO0b[27] connected to pin GPIO47 */ + /* GPIO0b[28..29] connected to pins GPIO49..50 */ + /* GPIO0b[30..31] connected to pins GPIO53..54 */ + gpio0b: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + }; + }; + + gpio1: gpio@5000c000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000c000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sysctrl R9A06G032_HCLK_GPIO1>; + clock-names = "bus"; + + /* GPIO1a[0..4] connected to pins GPIO69..73 */ + /* GPIO1a[5..31] connected to pins GPIO95..121 */ + gpio1a: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + + interrupt-controller; + interrupt-parent = <&gpioirqmux>; + interrupts = <32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63>; + #interrupt-cells = <2>; + }; + + /* GPIO1b[0..1] connected to pins GPIO55..56 */ + /* GPIO1b[2..4] connected to pins GPIO59..61 */ + /* GPIO1b[5..25] connected to pins GPIO74..94 */ + /* GPIO1b[26..31] connected to pins GPIO150..155 */ + gpio1b: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + }; + }; + + gpio2: gpio@5000d000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000d000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sysctrl R9A06G032_HCLK_GPIO2>; + clock-names = "bus"; + + /* GPIO2a[0..27] connected to pins GPIO122..149 */ + /* GPIO2a[28..31] connected to pins GPIO156..159 */ + gpio2a: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + + interrupt-controller; + interrupt-parent = <&gpioirqmux>; + interrupts = <64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95>; + #interrupt-cells = <2>; + }; + + /* GPIO2b[0..9] connected to pins GPIO160..169 */ + gpio2b: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <10>; + }; + }; + + gpioirqmux: interrupt-controller@51000480 { + compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux"; + reg = <0x51000480 0x20>; + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-map-mask = <0x7f>; + + /* + * Example mapping entry. Board DTs need to overwrite + * 'interrupt-map' with their specific mapping. Check + * the irqmux binding documentation for details. + */ + interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + can0: can@52104000 { compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; reg = <0x52104000 0x800>; diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index d40a7224f9c3..af6d15f90c65 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -158,7 +158,7 @@ reg = <0x51>; }; - versaclock5: versaclock_som@6a { + versaclock5: versaclock-som@6a { compatible = "idt,5p49v6965"; reg = <0x6a>; #clock-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi index 38d486e7b8c3..6b22cc0b05b1 100644 --- a/arch/arm64/boot/dts/renesas/condor-common.dtsi +++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi @@ -501,7 +501,7 @@ reg = <0x00040000 0x080000>; read-only; }; - cert_header_sa3@c0000 { + cert-header-sa3@c0000 { reg = <0x000c0000 0x080000>; read-only; }; @@ -509,7 +509,7 @@ reg = <0x00140000 0x040000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index 733a55f77cfb..c83c97d99113 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -660,7 +660,7 @@ reg = <0x00040000 0x140000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index adc4449b809a..692a2b12aa03 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -765,7 +765,7 @@ reg = <0x00040000 0x140000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi b/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi deleted file mode 100644 index e0930d1ba3aa..000000000000 --- a/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi +++ /dev/null @@ -1,332 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Ideas on Board <kieran.bingham@ideasonboard.com> - * Copyright (C) 2021 Jacopo Mondi <jacopo+renesas@jmondi.org> - * - * Device Tree Source (overlay) that describes GMSL camera connected to - * Fakra connectors for the Eagle V3M and Condor V3H (and compatible) boards. - * - * The following cameras are currently supported: RDACM20 and RDACM21. - * - * The board .dts file that include this has to select which cameras are in use - * by specifying the camera model with: - * - * #define GMSL_CAMERA_RDACM20 - * or - * #define GMSL_CAMERA_RDACM21 - * - * And which cameras are connected to the board by defining: - * for GMSL channel 0: - * #define GMSL_CAMERA_0 - * #define GMSL_CAMERA_1 - * #define GMSL_CAMERA_2 - * #define GMSL_CAMERA_3 - * - * for GMSL channel 1: - * #define GMSL_CAMERA_4 - * #define GMSL_CAMERA_5 - * #define GMSL_CAMERA_6 - * #define GMSL_CAMERA_7 - */ - -#include <dt-bindings/gpio/gpio.h> - -/* Validate the board file settings. */ -#if !defined(GMSL_CAMERA_RDACM20) && !defined(GMSL_CAMERA_RDACM21) -#error "Camera model should be defined by the board file" -#endif - -#if defined(GMSL_CAMERA_RDACM20) && defined(GMSL_CAMERA_RDACM21) -#error "A single camera model should be selected" -#endif - -#if !defined(GMSL_CAMERA_0) && !defined(GMSL_CAMERA_1) && \ - !defined(GMSL_CAMERA_2) && !defined(GMSL_CAMERA_3) && \ - !defined(GMSL_CAMERA_4) && !defined(GMSL_CAMERA_5) && \ - !defined(GMSL_CAMERA_6) && !defined(GMSL_CAMERA_7) -#error "At least one camera should be selected" -#endif - -/* Deduce from the enabled cameras which GMSL channels are active. */ -#if defined(GMSL_CAMERA_0) || defined(GMSL_CAMERA_1) || \ - defined(GMSL_CAMERA_2) || defined(GMSL_CAMERA_3) -#define GMSL_0 -#endif - -#if defined(GMSL_CAMERA_4) || defined(GMSL_CAMERA_5) || \ - defined(GMSL_CAMERA_6) || defined(GMSL_CAMERA_7) -#define GMSL_1 -#endif - -/* Deduce the camera model compatible string. */ -#if defined(GMSL_CAMERA_RDACM20) -#define GMSL_CAMERA_MODEL "imi,rdacm20" -#elif defined(GMSL_CAMERA_RDACM21) -#define GMSL_CAMERA_MODEL "imi,rdacm21" -#endif - -#ifdef GMSL_0 -&vin0 { - status = "okay"; -}; - -&vin1 { - status = "okay"; -}; - -&vin2 { - status = "okay"; -}; - -&vin3 { - status = "okay"; -}; - -&gmsl0 { - status = "okay"; - -#if defined(GMSL_CAMERA_RDACM21) - maxim,reverse-channel-microvolt = <100000>; -#endif - - ports { -#ifdef GMSL_CAMERA_0 - port@0 { - max9286_in0: endpoint { - remote-endpoint = <&fakra_con0>; - }; - }; -#endif - -#ifdef GMSL_CAMERA_1 - port@1 { - max9286_in1: endpoint { - remote-endpoint = <&fakra_con1>; - }; - - }; -#endif - -#ifdef GMSL_CAMERA_2 - port@2 { - max9286_in2: endpoint { - remote-endpoint = <&fakra_con2>; - }; - - }; -#endif - -#ifdef GMSL_CAMERA_3 - port@3 { - max9286_in3: endpoint { - remote-endpoint = <&fakra_con3>; - }; - - }; -#endif - }; - - i2c-mux { -#ifdef GMSL_CAMERA_0 - i2c@0 { - status = "okay"; - - camera@51 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x51>, <0x61>; - - port { - fakra_con0: endpoint { - remote-endpoint = <&max9286_in0>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_1 - i2c@1 { - status = "okay"; - - camera@52 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x52>, <0x62>; - - port { - fakra_con1: endpoint { - remote-endpoint = <&max9286_in1>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_2 - i2c@2 { - status = "okay"; - - camera@53 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x53>, <0x63>; - - port { - fakra_con2: endpoint { - remote-endpoint = <&max9286_in2>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_3 - i2c@3 { - status = "okay"; - - camera@54 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x54>, <0x64>; - - port { - fakra_con3: endpoint { - remote-endpoint = <&max9286_in3>; - }; - }; - }; - }; -#endif - }; -}; -#endif /* ifdef GMSL_0 */ - -#ifdef GMSL_1 -&vin4 { - status = "okay"; -}; - -&vin5 { - status = "okay"; -}; - -&vin6 { - status = "okay"; -}; - -&vin7 { - status = "okay"; -}; - -&gmsl1 { - status = "okay"; - -#if defined(GMSL_CAMERA_RDACM21) - maxim,reverse-channel-microvolt = <100000>; -#endif - - ports { -#ifdef GMSL_CAMERA_4 - port@0 { - max9286_in4: endpoint { - remote-endpoint = <&fakra_con4>; - }; - }; -#endif - -#ifdef GMSL_CAMERA_5 - port@1 { - max9286_in5: endpoint { - remote-endpoint = <&fakra_con5>; - }; - - }; -#endif - -#ifdef GMSL_CAMERA_6 - port@2 { - max9286_in6: endpoint { - remote-endpoint = <&fakra_con6>; - }; - - }; -#endif - -#ifdef GMSL_CAMERA_7 - port@3 { - max9286_in7: endpoint { - remote-endpoint = <&fakra_con7>; - }; - - }; -#endif - }; - - i2c-mux { -#ifdef GMSL_CAMERA_4 - i2c@0 { - status = "okay"; - - camera@55 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x55>, <0x65>; - - port { - fakra_con4: endpoint { - remote-endpoint = <&max9286_in4>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_5 - i2c@1 { - status = "okay"; - - camera@56 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x56>, <0x66>; - - port { - fakra_con5: endpoint { - remote-endpoint = <&max9286_in5>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_6 - i2c@2 { - status = "okay"; - - camera@57 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x57>, <0x67>; - - port { - fakra_con6: endpoint { - remote-endpoint = <&max9286_in6>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_7 - i2c@3 { - status = "okay"; - - camera@58 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x58>, <0x68>; - - port { - fakra_con7: endpoint { - remote-endpoint = <&max9286_in7>; - }; - }; - }; - }; -#endif - }; -}; -#endif /* ifdef GMSL_1 */ diff --git a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi index deb69c272775..8bfc66b8ef86 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi @@ -50,7 +50,7 @@ pinctrl-names = "default"; status = "okay"; - cs2000: clk_multiplier@4f { + cs2000: clk-multiplier@4f { #clock-cells = <0>; compatible = "cirrus,cs2000-cp"; reg = <0x4f>; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index f0729a482cef..36675f5bcdea 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1901,7 +1901,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1909,7 +1909,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -1921,7 +1921,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -1929,23 +1929,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -1957,27 +1957,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2001,15 +2001,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2021,19 +2021,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2065,7 +2065,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2077,19 +2077,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index c9857ea944ed..ceef0104f75e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1785,7 +1785,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1793,7 +1793,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -1805,7 +1805,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -1813,23 +1813,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -1841,27 +1841,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -1885,15 +1885,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -1905,19 +1905,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -1949,7 +1949,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -1961,19 +1961,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 52920a6bf592..9df5f1a42400 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1944,7 +1944,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1952,7 +1952,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -1964,7 +1964,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -1972,23 +1972,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -2000,27 +2000,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2044,15 +2044,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2064,19 +2064,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2108,7 +2108,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2120,19 +2120,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 9ad700bde4ba..607f62a448d8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2176,7 +2176,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -2184,7 +2184,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -2196,7 +2196,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -2204,23 +2204,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -2232,27 +2232,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2276,15 +2276,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2296,19 +2296,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2340,7 +2340,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2352,19 +2352,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index e03b1f7cbfd6..e64c7b1aebc4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2101,7 +2101,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -2109,7 +2109,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -2121,7 +2121,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -2129,23 +2129,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -2157,27 +2157,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2201,15 +2201,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2221,19 +2221,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2265,7 +2265,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2277,19 +2277,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 31b11bdab69b..89f6c052c5e0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1981,7 +1981,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1989,7 +1989,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -2001,7 +2001,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -2009,23 +2009,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -2037,27 +2037,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2081,15 +2081,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2101,19 +2101,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2145,7 +2145,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2157,19 +2157,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 4e730144e5fd..425561e658ca 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1911,7 +1911,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1919,7 +1919,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -1931,7 +1931,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -1939,23 +1939,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -1967,27 +1967,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2011,15 +2011,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2031,19 +2031,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2075,7 +2075,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2087,19 +2087,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index b7328f9f7d4b..b26c5a709777 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -364,7 +364,7 @@ reg = <0x00040000 0x080000>; read-only; }; - cert_header_sa3@c0000 { + cert-header-sa3@c0000 { reg = <0x000c0000 0x080000>; read-only; }; @@ -372,7 +372,7 @@ reg = <0x00140000 0x040000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index f18d26360610..343f9610f892 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -255,7 +255,7 @@ reg = <0x00040000 0x080000>; read-only; }; - cert_header_sa3@c0000 { + cert-header-sa3@c0000 { reg = <0x000c0000 0x080000>; read-only; }; @@ -263,7 +263,7 @@ reg = <0x00140000 0x040000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts index 87a9bb44cad6..e3725304fed0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -236,7 +236,7 @@ reg = <0x00040000 0x080000>; read-only; }; - cert_header_sa3@c0000 { + cert-header-sa3@c0000 { reg = <0x000c0000 0x080000>; read-only; }; @@ -244,7 +244,7 @@ reg = <0x00140000 0x040000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779m0.dtsi b/arch/arm64/boot/dts/renesas/r8a779m0.dtsi deleted file mode 100644 index 38978360e722..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m0.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car H3e (R8A779M0) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77951.dtsi" - -/ { - compatible = "renesas,r8a779m0", "renesas,r8a7795"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m2.dtsi b/arch/arm64/boot/dts/renesas/r8a779m2.dtsi deleted file mode 100644 index bced12764c69..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m2.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car M3e (R8A779M2) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77961.dtsi" - -/ { - compatible = "renesas,r8a779m2", "renesas,r8a77961"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m4.dtsi b/arch/arm64/boot/dts/renesas/r8a779m4.dtsi deleted file mode 100644 index ae8486056962..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m4.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car M3Ne (R8A779M4) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77965.dtsi" - -/ { - compatible = "renesas,r8a779m4", "renesas,r8a77965"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m6.dtsi b/arch/arm64/boot/dts/renesas/r8a779m6.dtsi deleted file mode 100644 index 94d6a6cf503e..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m6.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car E3e (R8A779M6) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77990.dtsi" - -/ { - compatible = "renesas,r8a779m6", "renesas,r8a77990"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m7.dtsi b/arch/arm64/boot/dts/renesas/r8a779m7.dtsi deleted file mode 100644 index 0580fa614034..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m7.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car D3e (R8A779M7) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77995.dtsi" - -/ { - compatible = "renesas,r8a779m7", "renesas,r8a77995"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m8.dtsi b/arch/arm64/boot/dts/renesas/r8a779m8.dtsi deleted file mode 100644 index dfccc080fb3e..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m8.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car H3Ne (R8A779M8) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77951.dtsi" - -/ { - compatible = "renesas,r8a779m8", "renesas,r8a7795"; -}; - -&cluster0_opp { - /delete-node/ opp-1600000000; - /delete-node/ opp-1700000000; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779mb.dtsi b/arch/arm64/boot/dts/renesas/r8a779mb.dtsi deleted file mode 100644 index 181b737c91cd..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779mb.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car H3Ne-1.7G (R8A779MB) SoC - * - * Copyright (C) 2022 Glider bv - */ - -#include "r8a77951.dtsi" - -/ { - compatible = "renesas,r8a779mb", "renesas,r8a7795"; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index bd52d60bafb9..29273da81995 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1371,7 +1371,7 @@ wdt1: watchdog@12800c00 { compatible = "renesas,r9a07g044-wdt", "renesas,rzg2l-wdt"; - reg = <0 0x12800C00 0 0x400>; + reg = <0 0x12800c00 0 0x400>; clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>, <&cpg CPG_MOD R9A07G044_WDT1_CLK>; clock-names = "pclk", "oscclk"; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi deleted file mode 100644 index 56a979e82c4f..000000000000 --- a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/G2LC R9A07G044C1 SoC specific parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r9a07g044.dtsi" - -/ { - compatible = "renesas,r9a07g044c1", "renesas,r9a07g044"; - - cpus { - /delete-node/ cpu-map; - /delete-node/ cpu@100; - }; -}; - -&soc { - /delete-node/ ssi@1004a800; - /delete-node/ serial@1004c800; - /delete-node/ adc@10059000; - /delete-node/ ethernet@11c30000; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi deleted file mode 100644 index 9cf27ca9f1d2..000000000000 --- a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/G2L R9A07G044L1 SoC specific parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r9a07g044.dtsi" - -/ { - compatible = "renesas,r9a07g044l1", "renesas,r9a07g044"; - - cpus { - /delete-node/ cpu-map; - /delete-node/ cpu@100; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 4e0256d3201d..0dee48c4f1e4 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1379,7 +1379,7 @@ wdt1: watchdog@12800c00 { compatible = "renesas,r9a07g054-wdt", "renesas,rzg2l-wdt"; - reg = <0 0x12800C00 0 0x400>; + reg = <0 0x12800c00 0 0x400>; clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>, <&cpg CPG_MOD R9A07G054_WDT1_CLK>; clock-names = "pclk", "oscclk"; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi deleted file mode 100644 index d85a6ac0f024..000000000000 --- a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/V2L R9A07G054L1 SoC specific parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r9a07g054.dtsi" - -/ { - compatible = "renesas,r9a07g054l1", "renesas,r9a07g054"; - - cpus { - /delete-node/ cpu-map; - /delete-node/ cpu@100; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi deleted file mode 100644 index e50d9159e832..000000000000 --- a/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/G3E R9A09G047E37 SoC specific parts - * - * Copyright (C) 2024 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r9a09g047.dtsi" - -/ { - compatible = "renesas,r9a09g047e37", "renesas,r9a09g047"; - - cpus { - /delete-node/ cpu@200; - /delete-node/ cpu@300; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index d942ac1f7865..9fb15ca24984 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -694,6 +694,66 @@ status = "disabled"; }; + canfd: can@12440000 { + compatible = "renesas,r9a09g056-canfd", "renesas,r9a09g047-canfd"; + reg = <0 0x12440000 0 0x40000>; + interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx", + "ch2_err", "ch2_rec", "ch2_trx", + "ch3_err", "ch3_rec", "ch3_trx", + "ch4_err", "ch4_rec", "ch4_trx", + "ch5_err", "ch5_rec", "ch5_trx"; + clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, + <&cpg CPG_MOD 0x9e>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_MOD 0x9e>; + assigned-clock-rates = <80000000>; + resets = <&cpg 0xa1>, <&cpg 0xa2>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + channel2 { + status = "disabled"; + }; + channel3 { + status = "disabled"; + }; + channel4 { + status = "disabled"; + }; + channel5 { + status = "disabled"; + }; + }; + rspi0: spi@12800000 { compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi"; reg = <0x0 0x12800000 0x0 0x400>; @@ -757,6 +817,226 @@ status = "disabled"; }; + rsci0: serial@12800c00 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12800c00 0 0x400>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>, + <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>, + <&cpg CPG_MOD 0x5f>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x81>, <&cpg 0x82>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci1: serial@12801000 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801000 0 0x400>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>, + <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>, + <&cpg CPG_MOD 0x64>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x83>, <&cpg 0x84>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci2: serial@12801400 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801400 0 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>, + <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>, + <&cpg CPG_MOD 0x69>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x85>, <&cpg 0x86>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci3: serial@12801800 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801800 0 0x400>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>, + <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>, + <&cpg CPG_MOD 0x6e>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x87>, <&cpg 0x88>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci4: serial@12801c00 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801c00 0 0x400>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>, + <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>, + <&cpg CPG_MOD 0x73>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x89>, <&cpg 0x8a>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci5: serial@12802000 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802000 0 0x400>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>, + <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>, + <&cpg CPG_MOD 0x78>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8b>, <&cpg 0x8c>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci6: serial@12802400 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802400 0 0x400>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>, + <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>, + <&cpg CPG_MOD 0x7d>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8d>, <&cpg 0x8e>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci7: serial@12802800 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802800 0 0x400>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>, + <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>, + <&cpg CPG_MOD 0x82>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8f>, <&cpg 0x90>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci8: serial@12802c00 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802c00 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>, + <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>, + <&cpg CPG_MOD 0x87>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x91>, <&cpg 0x92>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci9: serial@12803000 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12803000 0 0x400>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>, + <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>, + <&cpg CPG_MOD 0x8c>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x93>, <&cpg 0x94>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index a36961804494..80cba9fcfe7b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -690,6 +690,66 @@ status = "disabled"; }; + canfd: can@12440000 { + compatible = "renesas,r9a09g057-canfd", "renesas,r9a09g047-canfd"; + reg = <0 0x12440000 0 0x40000>; + interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx", + "ch2_err", "ch2_rec", "ch2_trx", + "ch3_err", "ch3_rec", "ch3_trx", + "ch4_err", "ch4_rec", "ch4_trx", + "ch5_err", "ch5_rec", "ch5_trx"; + clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, + <&cpg CPG_MOD 0x9e>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_MOD 0x9e>; + assigned-clock-rates = <80000000>; + resets = <&cpg 0xa1>, <&cpg 0xa2>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + channel2 { + status = "disabled"; + }; + channel3 { + status = "disabled"; + }; + channel4 { + status = "disabled"; + }; + channel5 { + status = "disabled"; + }; + }; + rspi0: spi@12800000 { compatible = "renesas,r9a09g057-rspi"; reg = <0x0 0x12800000 0x0 0x400>; @@ -753,6 +813,226 @@ status = "disabled"; }; + rsci0: serial@12800c00 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12800c00 0 0x400>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>, + <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>, + <&cpg CPG_MOD 0x5f>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x81>, <&cpg 0x82>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci1: serial@12801000 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801000 0 0x400>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>, + <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>, + <&cpg CPG_MOD 0x64>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x83>, <&cpg 0x84>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci2: serial@12801400 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801400 0 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>, + <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>, + <&cpg CPG_MOD 0x69>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x85>, <&cpg 0x86>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci3: serial@12801800 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801800 0 0x400>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>, + <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>, + <&cpg CPG_MOD 0x6e>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x87>, <&cpg 0x88>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci4: serial@12801c00 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801c00 0 0x400>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>, + <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>, + <&cpg CPG_MOD 0x73>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x89>, <&cpg 0x8a>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci5: serial@12802000 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802000 0 0x400>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>, + <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>, + <&cpg CPG_MOD 0x78>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8b>, <&cpg 0x8c>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci6: serial@12802400 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802400 0 0x400>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>, + <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>, + <&cpg CPG_MOD 0x7d>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8d>, <&cpg 0x8e>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci7: serial@12802800 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802800 0 0x400>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>, + <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>, + <&cpg CPG_MOD 0x82>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8f>, <&cpg 0x90>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci8: serial@12802c00 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802c00 0 0x400>; + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>, + <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>, + <&cpg CPG_MOD 0x87>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x91>, <&cpg 0x92>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci9: serial@12803000 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12803000 0 0x400>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>, + <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>, + <&cpg CPG_MOD 0x8c>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x93>, <&cpg 0x94>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 962a544fc50a..dc4577ebf2e9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -61,7 +61,7 @@ memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x1 0xF8000000>; + reg = <0x0 0x48000000 0x1 0xf8000000>; }; memory@240000000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts index e8523bb6705a..3028ed406306 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts @@ -27,7 +27,7 @@ memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x1 0xF8000000>; + reg = <0x0 0x48000000 0x1 0xf8000000>; }; reg_1p8v: regulator-1p8v { diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 2db5f5e94f7c..14d7fb6f8952 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -14,6 +14,17 @@ #size-cells = <2>; interrupt-parent = <&gic>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -24,6 +35,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C0>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -32,6 +46,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C1>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -40,6 +57,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C2>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -48,6 +68,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C3>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { @@ -237,6 +260,37 @@ status = "disabled"; }; + canfd: can@80040000 { + compatible = "renesas,r9a09g077-canfd"; + reg = <0 0x80040000 0 0x20000>; + interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R9A09G077_CLK_PCLKH>, + <&cpg CPG_CORE R9A09G077_PCLKCAN>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A09G077_PCLKCAN>; + assigned-clock-rates = <80000000>; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + }; + wdt0: watchdog@80082000 { compatible = "renesas,r9a09g077-wdt"; reg = <0 0x80082000 0 0x400>, @@ -297,6 +351,17 @@ status = "disabled"; }; + tsu: thermal@80086000 { + compatible = "renesas,r9a09g077-tsu"; + reg = <0 0x80086000 0 0x1000>; + interrupts = <GIC_SPI 713 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 307>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + }; + i2c0: i2c@80088000 { compatible = "renesas,riic-r9a09g077"; reg = <0 0x80088000 0 0x400>; @@ -1001,6 +1066,9 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl 0 0 288>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&icu>; power-domains = <&cpg>; }; @@ -1175,6 +1243,37 @@ snps,blen = <16 8 4 0 0 0 0>; }; + thermal-zones { + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 1>, <&cpu1 0 1>, + <&cpu2 0 1>, <&cpu3 0 1>; + contribution = <1024>; + }; + }; + + trips { + target: trip-point { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor_crit: sensor-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index d1474f1bd523..e9639bbb2d70 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include <dt-bindings/input/input.h> + #include "r9a09g077m44.dtsi" /* @@ -60,6 +62,37 @@ model = "Renesas RZ/T2H EVK Board based on r9a09g077m44"; compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077"; + keys { + compatible = "gpio-keys"; + +#if (!SD1_MICRO_SD) + /* SW2-3: OFF */ + key-1 { + interrupts-extended = <&pinctrl RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_1>; + label = "SW9"; + wakeup-source; + debounce-interval = <20>; + }; +#endif + + key-2 { + interrupts-extended = <&pinctrl RZT2H_GPIO(0, 3) IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_2>; + label = "SW10"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + interrupts-extended = <&pinctrl RZT2H_GPIO(8, 7) IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_3>; + label = "SW11"; + wakeup-source; + debounce-interval = <20>; + }; + }; + leds { compatible = "gpio-leds"; @@ -138,6 +171,44 @@ }; }; +&adc2 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; + + channel@4 { + reg = <0x4>; + }; + + channel@5 { + reg = <0x5>; + }; +}; + +&canfd { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; +}; + &i2c0 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; @@ -167,6 +238,17 @@ &pinctrl { /* + * CAN0 Pin Configuration: + * + * SW7[1] OFF; SW7[2] ON - Use P24_4 as CANTX0. + * SW7[3] OFF; SW7[4] ON - Use P24_3 as CANRX0. + */ + can0_pins: can0-pins { + pinmux = <RZT2H_PORT_PINMUX(24, 3, 0x19)>, /* CANRX0 */ + <RZT2H_PORT_PINMUX(24, 4, 0x19)>; /* CANTX0 */ + }; + + /* * GMAC2 Pin Configuration: * * SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 @@ -256,30 +338,3 @@ }; }; -&adc2 { - status = "okay"; - - channel@0 { - reg = <0x0>; - }; - - channel@1 { - reg = <0x1>; - }; - - channel@2 { - reg = <0x2>; - }; - - channel@3 { - reg = <0x3>; - }; - - channel@4 { - reg = <0x4>; - }; - - channel@5 { - reg = <0x5>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index f3225694b4cb..4a1339561332 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -14,6 +14,17 @@ #size-cells = <2>; interrupt-parent = <&gic>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -24,6 +35,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C0>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -32,6 +46,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C1>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -40,6 +57,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C2>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -48,6 +68,9 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C3>; + #cooling-cells = <2>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { @@ -237,6 +260,37 @@ status = "disabled"; }; + canfd: can@80040000 { + compatible = "renesas,r9a09g087-canfd", "renesas,r9a09g077-canfd"; + reg = <0 0x80040000 0 0x20000>; + interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R9A09G087_CLK_PCLKH>, + <&cpg CPG_CORE R9A09G087_PCLKCAN>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A09G087_PCLKCAN>; + assigned-clock-rates = <80000000>; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + }; + wdt0: watchdog@80082000 { compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; reg = <0 0x80082000 0 0x400>, @@ -297,6 +351,17 @@ status = "disabled"; }; + tsu: thermal@80086000 { + compatible = "renesas,r9a09g087-tsu", "renesas,r9a09g077-tsu"; + reg = <0 0x80086000 0 0x1000>; + interrupts = <GIC_SPI 713 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 307>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + }; + i2c0: i2c@80088000 { compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; reg = <0 0x80088000 0 0x400>; @@ -1004,6 +1069,9 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl 0 0 280>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&icu>; power-domains = <&cpg>; }; @@ -1178,6 +1246,37 @@ snps,blen = <16 8 4 0 0 0 0>; }; + thermal-zones { + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 1>, <&cpu1 0 1>, + <&cpu2 0 1>, <&cpu3 0 1>; + contribution = <1024>; + }; + }; + + trips { + target: trip-point { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor_crit: sensor-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index eaf73868783b..19f0a2c06753 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include <dt-bindings/input/input.h> + #include "r9a09g087m44.dtsi" /* @@ -28,6 +30,13 @@ #define SD0_SD (!SD0_EMMC) /* + * To enable CANFD interface disable both eMMC and SD card on SDHI0 by + * setting SD0_EMMC and SD0_SD macros to 0 as pins P12_0 and P12_1 + * will be used for CANFD interface. + */ +#define CANFD_ENABLE (!SD0_EMMC && !SD0_SD) + +/* * P17_4 = SD1_CD; DSW5[3] = ON; DSW19[1] = OFF; DSW19[2] = ON * P08_6 = SD1_IOVS; DSW5[3] = ON * To enable proper operation in 1.8V modes, JP21 must have pins 2 and 3 @@ -77,6 +86,34 @@ model = "Renesas RZ/N2H EVK Board based on r9a09g087m44"; compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087"; + keys { + compatible = "gpio-keys"; + + key-1 { + interrupts-extended = <&pinctrl RZT2H_GPIO(18, 2) IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_1>; + label = "SW2"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + interrupts-extended = <&pinctrl RZT2H_GPIO(0, 4) IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_2>; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + interrupts-extended = <&pinctrl RZT2H_GPIO(18, 7) IRQ_TYPE_EDGE_FALLING>; + linux,code = <KEY_3>; + label = "SW4"; + wakeup-source; + debounce-interval = <20>; + }; + }; + leds { compatible = "gpio-leds"; @@ -173,6 +210,82 @@ }; }; +&adc2 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; + + channel@4 { + reg = <0x4>; + }; + + channel@5 { + reg = <0x5>; + }; + + channel@6 { + reg = <0x6>; + }; + + channel@7 { + reg = <0x7>; + }; + + channel@8 { + reg = <0x8>; + }; + + channel@9 { + reg = <0x9>; + }; + + channel@a { + reg = <0xa>; + }; + + channel@b { + reg = <0xb>; + }; + + channel@c { + reg = <0xc>; + }; + + channel@d { + reg = <0xd>; + }; + + channel@e { + reg = <0xe>; + }; +}; + +#if CANFD_ENABLE +&canfd { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel1 { + status = "okay"; + }; +}; +#endif + #if I2C0 &i2c0 { pinctrl-0 = <&i2c0_pins>; @@ -210,6 +323,16 @@ &pinctrl { /* + * CAN1 Pin Configuration: + * + * DSW5[1] ON; DSW5[2] OFF - Use P12_0 and P12_1 for CAN1 interface. + */ + can1_pins: can1-pins { + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x19)>, /* CANRX1 */ + <RZT2H_PORT_PINMUX(12, 1, 0x19)>; /* CANTX1 */ + }; + + /* * GMAC2 Pin Configuration: * * DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 @@ -309,66 +432,3 @@ }; }; -&adc2 { - status = "okay"; - - channel@0 { - reg = <0x0>; - }; - - channel@1 { - reg = <0x1>; - }; - - channel@2 { - reg = <0x2>; - }; - - channel@3 { - reg = <0x3>; - }; - - channel@4 { - reg = <0x4>; - }; - - channel@5 { - reg = <0x5>; - }; - - channel@6 { - reg = <0x6>; - }; - - channel@7 { - reg = <0x7>; - }; - - channel@8 { - reg = <0x8>; - }; - - channel@9 { - reg = <0x9>; - }; - - channel@a { - reg = <0xa>; - }; - - channel@b { - reg = <0xb>; - }; - - channel@c { - reg = <0xc>; - }; - - channel@d { - reg = <0xd>; - }; - - channel@e { - reg = <0xe>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index eb0de21d6716..3b571c096752 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -126,6 +126,14 @@ }; }; +&i3c { + pinctrl-0 = <&i3c_pins>; + pinctrl-names = "default"; + i2c-scl-hz = <400000>; + i3c-scl-hz = <12500000>; + status = "okay"; +}; + &mdio0 { phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", @@ -223,6 +231,12 @@ <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */ }; + i3c_pins: i3c { + pinmux = <RZG3E_PORT_PINMUX(2, 0, 2)>, /* I3C0_SCL */ + <RZG3E_PORT_PINMUX(2, 1, 2)>; /* I3C0_SDA */ + drive-push-pull; + }; + rtc_irq_pin: rtc-irq { pins = "PS1"; bias-pull-up; diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 3eed1f3948e8..510399febf29 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -69,6 +69,85 @@ #endif }; +/* + * ADC0 AN000 can be connected to a potentiometer on the board or + * exposed on ADC header. + * + * T2H: + * SW17[1] = ON, SW17[2] = OFF - Potentiometer + * SW17[1] = OFF, SW17[2] = ON - CN41 header + * N2H: + * DSW6[1] = OFF, DSW6[2] = ON - Potentiometer + * DSW6[1] = ON, DSW6[2] = OFF - CN3 header + */ +&adc0 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; +}; + +/* + * ADC1 AN100 can be exposed on ADC header or on mikroBUS connector. + * + * T2H: + * SW18[1] = ON, SW18[2] = OFF - CN42 header + * SW18[1] = OFF, SW18[2] = ON - mikroBUS + * N2H: + * DSW6[3] = ON, DSW6[4] = OFF - CN4 header + * DSW6[3] = OFF, DSW6[4] = ON - mikroBUS + * + * ADC1 AN101 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[3] = ON, SW18[4] = OFF - CN42 header + * SW18[3] = OFF, SW18[4] = ON - Grove2 + * N2H: + * DSW6[5] = ON, DSW6[6] = OFF - CN4 header + * DSW6[5] = OFF, DSW6[6] = ON - Grove2 + * + * ADC1 AN102 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[5] = ON, SW18[6] = OFF - CN42 header + * SW18[5] = OFF, SW18[6] = ON - Grove2 + * N2H: + * DSW6[7] = ON, DSW6[8] = OFF - CN4 header + * DSW6[7] = OFF, DSW6[8] = ON - Grove2 + */ +&adc1 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; +}; + &ehci { dr_mode = "otg"; status = "okay"; @@ -224,8 +303,7 @@ ctrl-pins { pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */ <RZT2H_PORT_PINMUX(12, 1, 0x29)>, /* SD0_CMD */ - <RZT2H_PORT_PINMUX(22, 5, 0x29)>, /* SD0_CD */ - <RZT2H_PORT_PINMUX(22, 6, 0x29)>; /* SD0_WP */ + <RZT2H_PORT_PINMUX(22, 5, 0x29)>; /* SD0_CD */ }; }; @@ -282,6 +360,7 @@ pinctrl-names = "default", "state_uhs"; vmmc-supply = <®_3p3v>; vqmmc-supply = <&vqmmc_sdhi0>; + wp-gpios = <&pinctrl RZT2H_GPIO(22, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; sd-uhs-sdr50; sd-uhs-sdr104; @@ -315,81 +394,3 @@ timeout-sec = <60>; }; -/* - * ADC0 AN000 can be connected to a potentiometer on the board or - * exposed on ADC header. - * - * T2H: - * SW17[1] = ON, SW17[2] = OFF - Potentiometer - * SW17[1] = OFF, SW17[2] = ON - CN41 header - * N2H: - * DSW6[1] = OFF, DSW6[2] = ON - Potentiometer - * DSW6[1] = ON, DSW6[2] = OFF - CN3 header - */ -&adc0 { - status = "okay"; - - channel@0 { - reg = <0x0>; - }; - - channel@1 { - reg = <0x1>; - }; - - channel@2 { - reg = <0x2>; - }; - - channel@3 { - reg = <0x3>; - }; -}; - -/* - * ADC1 AN100 can be exposed on ADC header or on mikroBUS connector. - * - * T2H: - * SW18[1] = ON, SW18[2] = OFF - CN42 header - * SW18[1] = OFF, SW18[2] = ON - mikroBUS - * N2H: - * DSW6[3] = ON, DSW6[4] = OFF - CN4 header - * DSW6[3] = OFF, DSW6[4] = ON - mikroBUS - * - * ADC1 AN101 can be exposed on ADC header or on Grove2 connector. - * - * T2H: - * SW18[3] = ON, SW18[4] = OFF - CN42 header - * SW18[3] = OFF, SW18[4] = ON - Grove2 - * N2H: - * DSW6[5] = ON, DSW6[6] = OFF - CN4 header - * DSW6[5] = OFF, DSW6[6] = ON - Grove2 - * - * ADC1 AN102 can be exposed on ADC header or on Grove2 connector. - * - * T2H: - * SW18[5] = ON, SW18[6] = OFF - CN42 header - * SW18[5] = OFF, SW18[6] = ON - Grove2 - * N2H: - * DSW6[7] = ON, DSW6[8] = OFF - CN4 header - * DSW6[7] = OFF, DSW6[8] = ON - Grove2 - */ -&adc1 { - status = "okay"; - - channel@0 { - reg = <0x0>; - }; - - channel@1 { - reg = <0x1>; - }; - - channel@2 { - reg = <0x2>; - }; - - channel@3 { - reg = <0x3>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index fa8bfee07b3c..d4a921bed4c3 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -501,7 +501,7 @@ }; }; - cs2000: clk_multiplier@4f { + cs2000: clk-multiplier@4f { #clock-cells = <0>; compatible = "cirrus,cs2000-cp"; reg = <0x4f>; @@ -890,7 +890,7 @@ reg = <0x00040000 0x140000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index a9e53b36f1d9..241caf737abb 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -413,7 +413,7 @@ reg = <0x00040000 0x140000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index a8bcb26f4270..571de3cafa82 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -12,6 +12,8 @@ #include <arm64/renesas/r9a07g043.dtsi> / { + interrupt-parent = <&plic>; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -52,7 +54,6 @@ &soc { dma-noncoherent; - interrupt-parent = <&plic>; irqc: interrupt-controller@110a0000 { compatible = "renesas,r9a07g043f-irqc"; diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h index 2a805e06487b..c4863e444458 100644 --- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -31,5 +31,8 @@ #define R9A09G077_ETCLKC 19 #define R9A09G077_ETCLKD 20 #define R9A09G077_ETCLKE 21 +#define R9A09G077_XSPI_CLK0 22 +#define R9A09G077_XSPI_CLK1 23 +#define R9A09G077_PCLKCAN 24 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h index 09da0ad33be6..0d53f1e65077 100644 --- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h @@ -31,5 +31,8 @@ #define R9A09G087_ETCLKC 19 #define R9A09G087_ETCLKD 20 #define R9A09G087_ETCLKE 21 +#define R9A09G087_XSPI_CLK0 22 +#define R9A09G087_XSPI_CLK1 23 +#define R9A09G087_PCLKCAN 24 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */ |