diff options
Diffstat (limited to 'arch/arm')
142 files changed, 11733 insertions, 1220 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 202397be76d8..835b5f100e92 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -5,8 +5,11 @@ config ARM select ARCH_32BIT_OFF_T select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND select ARCH_HAS_BINFMT_FLAT + select ARCH_HAS_CACHE_LINE_SIZE if OF select ARCH_HAS_CPU_CACHE_ALIASING select ARCH_HAS_CPU_FINALIZE_INIT if MMU + select ARCH_HAS_CRC32 if KERNEL_MODE_NEON + select ARCH_HAS_CRC_T10DIF if KERNEL_MODE_NEON select ARCH_HAS_CURRENT_STACK_POINTER select ARCH_HAS_DEBUG_VIRTUAL if MMU select ARCH_HAS_DMA_ALLOC if MMU @@ -1751,5 +1754,3 @@ config ARCH_HIBERNATION_POSSIBLE default y if ARCH_SUSPEND_POSSIBLE endmenu - -source "arch/arm/Kconfig.assembler" diff --git a/arch/arm/Kconfig.assembler b/arch/arm/Kconfig.assembler deleted file mode 100644 index 5cb31aae1188..000000000000 --- a/arch/arm/Kconfig.assembler +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -config AS_VFP_VMRS_FPINST - def_bool $(as-instr,.fpu vfpv2\nvmrs r0$(comma)FPINST) - help - Supported by binutils >= 2.24 and LLVM integrated assembler. diff --git a/arch/arm/boot/dts/allwinner/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/allwinner/suniv-f1c100s-licheepi-nano.dts index 43896723a994..472ded0aafcf 100644 --- a/arch/arm/boot/dts/allwinner/suniv-f1c100s-licheepi-nano.dts +++ b/arch/arm/boot/dts/allwinner/suniv-f1c100s-licheepi-nano.dts @@ -62,6 +62,14 @@ status = "okay"; }; +&codec { + allwinner,audio-routing = + "Headphone", "HP", + "Headphone", "HPCOM", + "MIC", "Mic"; + status = "okay"; +}; + &usb_otg { dr_mode = "otg"; status = "okay"; diff --git a/arch/arm/boot/dts/allwinner/suniv-f1c100s.dtsi b/arch/arm/boot/dts/allwinner/suniv-f1c100s.dtsi index 3c61d59ab5f8..e4b41bc93852 100644 --- a/arch/arm/boot/dts/allwinner/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/allwinner/suniv-f1c100s.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/suniv-ccu-f1c100s.h> #include <dt-bindings/reset/suniv-ccu-f1c100s.h> +#include <dt-bindings/dma/sun4i-a10.h> / { #address-cells = <1>; @@ -159,6 +160,15 @@ status = "disabled"; }; + dma: dma-controller@1c02000 { + compatible = "allwinner,suniv-f1c100s-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <18>; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <2>; + }; + ccu: clock@1c20000 { compatible = "allwinner,suniv-f1c100s-ccu"; reg = <0x01c20000 0x400>; @@ -326,5 +336,19 @@ resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; + + codec: codec@1c23c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,suniv-f1c100s-codec"; + reg = <0x01c23c00 0x400>; + interrupts = <21>; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_CODEC>; + clock-names = "apb", "codec"; + dmas = <&dma SUN4I_DMA_NORMAL 12>, + <&dma SUN4I_DMA_NORMAL 12>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_CODEC>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi index 8cb0fc78b2af..28ec2c821cdc 100644 --- a/arch/arm/boot/dts/amlogic/meson.dtsi +++ b/arch/arm/boot/dts/amlogic/meson.dtsi @@ -255,8 +255,6 @@ usb0: usb@c9040000 { compatible = "snps,dwc2"; - #address-cells = <1>; - #size-cells = <0>; reg = <0xc9040000 0x40000>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb0_phy>; @@ -270,8 +268,6 @@ usb1: usb@c90c0000 { compatible = "snps,dwc2"; - #address-cells = <1>; - #size-cells = <0>; reg = <0xc90c0000 0x40000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb1_phy>; diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index c4f064e4b073..2e5f4833a073 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-amd-daytonax.dtb \ aspeed-bmc-amd-ethanolx.dtb \ aspeed-bmc-ampere-mtjade.dtb \ + aspeed-bmc-ampere-mtjefferson.dtb \ aspeed-bmc-ampere-mtmitchell.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-asrock-e3c246d4i.dtb \ @@ -40,6 +41,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-ibm-rainier.dtb \ aspeed-bmc-ibm-rainier-1s4u.dtb \ aspeed-bmc-ibm-rainier-4u.dtb \ + aspeed-bmc-ibm-sbp1.dtb \ aspeed-bmc-ibm-system1.dtb \ aspeed-bmc-intel-s2600wf.dtb \ aspeed-bmc-inspur-fp5280g2.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjefferson.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjefferson.dts new file mode 100644 index 000000000000..c435359a4bd9 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjefferson.dts @@ -0,0 +1,622 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright 2024 Ampere Computing LLC. + +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include <dt-bindings/i2c/i2c.h> +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "Ampere Mt. Jefferson BMC"; + compatible = "ampere,mtjefferson-bmc", "aspeed,ast2600"; + + aliases { + i2c20 = &i2c4_bus70_chn0; + i2c22 = &i2c4_bus70_chn2; + + /* + * I2C OCP alias port + */ + i2c30 = &ocpslot; + + /* + * I2C NVMe alias port + */ + i2c48 = &nvmeslot_0; + i2c49 = &nvmeslot_1; + i2c50 = &nvmeslot_2; + i2c51 = &nvmeslot_3; + i2c52 = &nvmeslot_4; + i2c53 = &nvmeslot_5; + i2c54 = &nvmeslot_6; + i2c55 = &nvmeslot_7; + i2c56 = &nvmeslot_8; + i2c57 = &nvmeslot_9; + i2c58 = &nvmeslot_10; + i2c59 = &nvmeslot_11; + }; + + chosen { + stdout-path = &uart5; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: video { + size = <0x04000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + vga_memory: region@bf000000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; + }; + + voltage_mon_reg: voltage-mon-regulator { + compatible = "regulator-fixed"; + regulator-name = "ltc2497_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + led-bmc-ready { + gpios = <&gpio0 ASPEED_GPIO(W, 5) (GPIO_ACTIVE_HIGH | GPIO_TRANSITORY)>; + }; + + led-sw-heartbeat { + gpios = <&gpio0 ASPEED_GPIO(N, 3) GPIO_ACTIVE_HIGH>; + }; + + led-identify { + gpios = <&gpio0 ASPEED_GPIO(S, 3) GPIO_ACTIVE_HIGH>; + }; + + led-fault { + gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, + <&adc_i2c_2 0>, <&adc_i2c_2 1>, + <&adc_i2c_2 2>, <&adc_i2c_2 3>, + <&adc_i2c_2 4>, <&adc_i2c_2 5>, + <&adc_i2c_2 6>, <&adc_i2c_2 7>, + <&adc_i2c_2 8>, <&adc_i2c_2 9>, + <&adc_i2c_2 10>, <&adc_i2c_2 11>, + <&adc_i2c_2 12>, <&adc_i2c_2 13>, + <&adc_i2c_2 14>, <&adc_i2c_2 15>, + <&adc_i2c_0 0>, <&adc_i2c_0 1>, + <&adc_i2c_0 2>, <&adc_i2c_0 3>, + <&adc_i2c_0 4>, <&adc_i2c_0 5>, + <&adc_i2c_0 6>, <&adc_i2c_0 7>, + <&adc_i2c_0 8>, <&adc_i2c_0 9>, + <&adc_i2c_0 10>, <&adc_i2c_0 11>, + <&adc_i2c_0 12>; + }; +}; + +&mdio0 { + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mac0 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default>; +}; + +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + use-ncsi; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <20000000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + bus-frequency = <1000000>; + multi-master; + mctp-controller; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; +}; + +&i2c4 { + status = "okay"; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c-mux@70 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c4_bus70_chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + eeprom@52 { + compatible = "atmel,24c256"; + reg = <0x52>; + pagesize = <32>; + }; + temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + temperature-sensor@4a{ + compatible = "ti,tmp75"; + reg = <0x4a>; + }; + temperature-sensor@4b { + compatible = "ti,tmp464"; + reg = <0x4b>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0x0>; + status = "disabled"; + }; + channel@1 { + reg = <0x1>; + status = "disabled"; + }; + channel@2 { + reg = <0x2>; + status = "disabled"; + }; + channel@3 { + reg = <0x3>; + status = "disabled"; + }; + channel@4 { + reg = <0x4>; + }; + }; + temperature-sensor@4d { + compatible = "ti,tmp75"; + reg = <0x4d>; + }; + temperature-sensor@4e { + compatible = "ti,tmp75"; + reg = <0x4e>; + }; + temperature-sensor@4f { + compatible = "ti,tmp75"; + reg = <0x4f>; + }; + temperature-sensor@28 { + compatible = "nuvoton,nct7802"; + reg = <0x28>; + + #address-cells = <1>; + #size-cells = <0>; + channel@1 { /* RTD1 */ + reg = <1>; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + }; + adc_i2c_0: adc@14 { + compatible = "lltc,ltc2497"; + reg = <0x14>; + vref-supply = <&voltage_mon_reg>; + #io-channel-cells = <1>; + }; + }; + + i2c4_bus70_chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + adc_i2c_2: adc@14 { + compatible = "lltc,ltc2497"; + reg = <0x14>; + vref-supply = <&voltage_mon_reg>; + #io-channel-cells = <1>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + nvmeslot_8: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_9: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_10: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_11: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + }; + + i2c-mux@72 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72>; + i2c-mux-idle-disconnect; + + nvmeslot_4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; + + i2c-mux@74 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c-mux-idle-disconnect; + + ocpslot: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + ocpslot_temp: temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0x0>; + status = "disabled"; + }; + channel@1 { + reg = <0x1>; + }; + }; + }; + + nvmeslot_0: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_1: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_2: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_3: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c7 { + status = "okay"; + + temperature-sensor@4f { + compatible = "ti,tmp75"; + reg = <0x4f>; + }; +}; + +&i2c8 { + status = "okay"; + + fan-controller@5c { + compatible = "onnn,adt7462"; + reg = <0x5c>; + }; +}; + +&i2c9 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + temperature-sensor@18 { + compatible = "jedec,jc-42.4-temp"; + reg = <0x18>; + }; + + temperature-sensor@1a { + compatible = "jedec,jc-42.4-temp"; + reg = <0x1a>; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; +}; + +&i2c14 { + status = "okay"; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + bmc_ast2600_cpu: temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; +}; + +&i2c15 { + status = "okay"; + gpio_expander1: gpio-expander@22 { + compatible = "nxp,pca9535"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "presence-ocp1","presence-ocp2", + "","", + "","", + "","", + "","", + "","", + "","", + "",""; + }; +}; + +&adc0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default>; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","cpu-type-detect","i2c2-reset-n","i2c6-reset-n","i2c5-reset-n", + /*B0-B7*/ "","","","","host0-sysreset-n","host0-pmin-n","fru-rd-complete", + "chassis-id-sel", + /*C0-C7*/ "s0-vrd-fault-n","","bmc-debug-mode","","cpld-3v3-irq-n","","vrd-sel", + "spd-sel", + /*D0-D7*/ "presence-ps0","presence-ps1","hsc-12vmain-alt2-n","ext-high-temp-n", + "","","","", + /*E0-E7*/ "eth-phy-rst-n","eth-phy-int-n","","","","","","", + /*F0-F7*/ "s0-pcp-oc-warn-n","","power-chassis-control", + "cpu-bios-recover","s0-heartbeat","hs-scout-proc-hot","s0-vr-hot-n","", + /*G0-G7*/ "","","hsc-12vmain-alt1-n","","","bp-cpld-program-en","led-fp-sta-gr", + "led-fp-sta-amb", + /*H0-H7*/ "jtag-program-sel","jtag-cmpl2","wd-disable-n","power-chassis-good","","", + "","", + /*I0-I7*/ "","","","","","","power-button","rtc-battery-voltage-read-enable", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","reset-button","","","", + /*M0-M7*/ "nmi-n","s0-ddr-save","soc-spi-nor-access","presence-cpu0","s0-rtc-lock", + "","","", + /*N0-N7*/ "hpm-fw-recovery","hpm-stby-rst-n","jtag-sel-s0","led-sw-hb", + "jtag-dbgr-prsnt-n","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "ps0-ac-loss-n","ps1-ac-loss-n","","","led-fault","user-mode","jtag-srst-n", + "led-bmc-hb", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","identify-button","led-identify","","spi-nor-access","host0-ready","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n", + "host0-reboot-ack-n","s0-fw-boot-ok","host0-shd-req-n", + "host0-shd-ack-n","s0-overtemp-n", + /*W0-W7*/ "ocp-aux-pwren","ocp-main-pwren","ocp-pgood","", + "bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","vrd-prg-en-n","","","","host0-special-boot", + /*Z0-Z7*/ "","ps0-pgood","ps1-pgood","","","","",""; + + ocp-aux-pwren-hog { + gpio-hog; + gpios = <ASPEED_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "ocp-aux-pwren"; + }; + +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","s0-soc-pgood","vga-ft-press-n","emmc-rst-n","s01-uart1-sel", + /*18C0-18C7*/ "uart1-mode0","uart1-mode1","uart2-mode0","uart2-mode1", + "","","","", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "","","",""; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts index 0295f5adcfbc..2b336aa0146d 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts @@ -677,6 +677,12 @@ #size-cells = <0>; #gpio-cells = <2>; + gpio-line-names = + "ext-vref-sel","","presence-hdd-bp5-n","presence-hdd-bp6-n", + "","bmc-riser-en-n","bmc-ocp1-en-n","bmc-ocp0-en-n", + "","","","", + "","","",""; + bmc-ocp0-en-hog { gpio-hog; gpios = <7 GPIO_ACTIVE_LOW>; @@ -684,6 +690,16 @@ line-name = "bmc-ocp0-en-n"; }; }; + + fan-controller0@20 { + compatible = "maxim,max31790"; + reg = <0x20>; + }; + + fan-controller1@2f { + compatible = "maxim,max31790"; + reg = <0x2f>; + }; }; &i2c9 { @@ -958,7 +974,7 @@ "fan-fault","psu-fault", "","", "","", - "","", + "gpi0","gpi1", "","", "","", "","", diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts index 82835e96317d..c151984289bc 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts @@ -50,14 +50,14 @@ i2c45 = &i2c0mux5ch1; i2c46 = &i2c0mux5ch2; i2c47 = &i2c0mux5ch3; - i2c48 = &i2c30mux0ch0; - i2c49 = &i2c30mux0ch1; - i2c50 = &i2c30mux0ch2; - i2c51 = &i2c30mux0ch3; - i2c52 = &i2c30mux0ch4; - i2c53 = &i2c30mux0ch5; - i2c54 = &i2c30mux0ch6; - i2c55 = &i2c30mux0ch7; + i2c48 = &i2c5mux0ch0; + i2c49 = &i2c5mux0ch1; + i2c50 = &i2c5mux0ch2; + i2c51 = &i2c5mux0ch3; + i2c52 = &i2c5mux0ch4; + i2c53 = &i2c5mux0ch5; + i2c54 = &i2c5mux0ch6; + i2c55 = &i2c5mux0ch7; }; chosen { @@ -153,6 +153,13 @@ status = "okay"; }; +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ncsi3_default>; + use-ncsi; +}; + &mac3 { status = "okay"; pinctrl-names = "default"; @@ -185,6 +192,7 @@ reg = <0x71>; #address-cells = <1>; #size-cells = <0>; + i2c-mux-idle-disconnect; i2c0mux0ch0: i2c@0 { #address-cells = <1>; @@ -213,6 +221,7 @@ reg = <0x72>; #address-cells = <1>; #size-cells = <0>; + i2c-mux-idle-disconnect; i2c0mux1ch0: i2c@0 { #address-cells = <1>; @@ -242,79 +251,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - i2c-mux@70 { - compatible = "nxp,pca9548"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - i2c30mux0ch0: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - i2c30mux0ch1: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - i2c30mux0ch2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - i2c30mux0ch3: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - i2c30mux0ch4: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - i2c30mux0ch5: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - i2c30mux0ch6: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - // HDD FRU EEPROM - eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - }; - }; - i2c30mux0ch7: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - - power-sensor@40 { - compatible = "ti,ina230"; - reg = <0x40>; - shunt-resistor = <2000>; - }; - power-sensor@41 { - compatible = "ti,ina230"; - reg = <0x41>; - shunt-resistor = <2000>; - }; - power-sensor@44 { - compatible = "ti,ina230"; - reg = <0x44>; - shunt-resistor = <2000>; - }; - power-sensor@45 { - compatible = "ti,ina230"; - reg = <0x45>; - shunt-resistor = <2000>; - }; - }; - }; }; i2c0mux1ch3: i2c@3 { #address-cells = <1>; @@ -328,6 +264,7 @@ reg = <0x73>; #address-cells = <1>; #size-cells = <0>; + i2c-mux-idle-disconnect; i2c0mux2ch0: i2c@0 { #address-cells = <1>; @@ -356,6 +293,7 @@ reg = <0x75>; #address-cells = <1>; #size-cells = <0>; + i2c-mux-idle-disconnect; i2c0mux3ch0: i2c@0 { #address-cells = <1>; @@ -384,6 +322,7 @@ reg = <0x76>; #address-cells = <1>; #size-cells = <0>; + i2c-mux-idle-disconnect; i2c0mux4ch0: i2c@0 { #address-cells = <1>; @@ -426,6 +365,7 @@ reg = <0x77>; #address-cells = <1>; #size-cells = <0>; + i2c-mux-idle-disconnect; i2c0mux5ch0: i2c@0 { #address-cells = <1>; @@ -512,12 +452,12 @@ power-monitor@42 { compatible = "lltc,ltc4287"; reg = <0x42>; - shunt-resistor-micro-ohms = <200>; + shunt-resistor-micro-ohms = <100>; }; power-monitor@43 { compatible = "lltc,ltc4287"; reg = <0x43>; - shunt-resistor-micro-ohms = <200>; + shunt-resistor-micro-ohms = <100>; }; }; i2c1mux0ch5: i2c@5 { @@ -593,8 +533,6 @@ reg = <0x20>; gpio-controller; #gpio-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <ASPEED_GPIO(B, 4) IRQ_TYPE_LEVEL_LOW>; }; // Module 1 IOEXP @@ -603,8 +541,6 @@ reg = <0x21>; gpio-controller; #gpio-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <ASPEED_GPIO(B, 4) IRQ_TYPE_LEVEL_LOW>; }; // HMC IOEXP @@ -613,8 +549,6 @@ reg = <0x27>; gpio-controller; #gpio-cells = <2>; - interrupt-parent = <&gpio0>; - interrupts = <ASPEED_GPIO(B, 4) IRQ_TYPE_LEVEL_LOW>; }; // Module 0 EEPROM @@ -640,6 +574,81 @@ &i2c5 { status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c5mux0ch0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + i2c5mux0ch1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c5mux0ch2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + i2c5mux0ch3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + i2c5mux0ch4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + i2c5mux0ch5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + i2c5mux0ch6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + // HDD FRU EEPROM + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + }; + i2c5mux0ch7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + power-sensor@41 { + compatible = "ti,ina230"; + reg = <0x41>; + shunt-resistor = <2000>; + }; + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + shunt-resistor = <2000>; + }; + power-sensor@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + }; + }; }; &i2c6 { @@ -834,9 +843,9 @@ }; // OCP NIC1 FRU EEPROM - eeprom@50 { + eeprom@52 { compatible = "atmel,24c64"; - reg = <0x50>; + reg = <0x52>; }; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts index cf3f807a38fe..9cb511a846e3 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts @@ -135,10 +135,6 @@ use-ncsi; }; -&rtc { - status = "okay"; -}; - &fmc { status = "okay"; @@ -397,12 +393,6 @@ reg = <0x31>; gpio-controller; #gpio-cells = <2>; - - gpio-line-names = - "","","","", - "","","presence-cmm","", - "","","","", - "","","",""; }; // PTTV FRU @@ -426,12 +416,6 @@ reg = <0x31>; gpio-controller; #gpio-cells = <2>; - - gpio-line-names = - "","","","", - "","","presence-cmm","", - "","","","", - "","","",""; }; // Aegis FRU @@ -506,6 +490,11 @@ #address-cells = <1>; #size-cells = <0>; reg = <3>; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; }; }; }; @@ -565,7 +554,7 @@ /*B0-B7*/ "","","","", "bmc-spi-mux-select-0","led-identify","","", /*C0-C7*/ "reset-cause-platrst","","","","", - "cpu0-err-alert","","", + "power-hsc-good","power-chassis-good","", /*D0-D7*/ "","","sol-uart-select","","","","","", /*E0-E7*/ "","","","","","","","", /*F0-F7*/ "","","","","","","","", @@ -584,14 +573,16 @@ /*O0-O7*/ "","","","","","","","", /*P0-P7*/ "power-button","power-host-control", "reset-button","","led-power","","","", - /*Q0-Q7*/ "","","","","","power-chassis-control","","", + /*Q0-Q7*/ + "","","","", + "","power-chassis-control","","uart-switch-button", /*R0-R7*/ "","","","","","","","", /*S0-S7*/ "","","","","","","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","led-identify-gate","", /*V0-V7*/ "","","","", "rtc-battery-voltage-read-enable","", - "power-chassis-good","", + "","", /*W0-W7*/ "","","","","","","","", /*X0-X7*/ "","","","","","","","", /*Y0-Y7*/ "","","","","","","","", @@ -672,7 +663,7 @@ "presence-asic-modules-0","rt-cpu0-p1-force-enable", "presence-asic-modules-1","bios-debug-msg-disable", "","uart-control-buffer-select", - "","ac-control-n", + "presence-cmm","ac-control-n", /*G0-G3 line 96-103*/ "FM_CPU_CORETYPE2","", "FM_CPU_CORETYPE1","", @@ -684,7 +675,7 @@ "FM_BOARD_REV_ID2","", "FM_BOARD_REV_ID1","", /*H0-H3 line 112-119*/ - "FM_BOARD_REV_ID0","", + "FM_BOARD_REV_ID0","reset-control-cmos-clear", "","","","","","", /*H4-H7 line 120-127*/ "","", @@ -699,7 +690,7 @@ /*I4-I7 line 136-143*/ "","","","","","","","", /*J0-J3 line 144-151*/ - "","","","","","","","", + "","","power-card-enable","","","","","", /*J4-J7 line 152-159*/ "SLOT_ID_BCB_0","", "SLOT_ID_BCB_1","", @@ -715,9 +706,15 @@ "cpu0-thermtrip-alert","", "reset-cause-pcie","", /*L4-L7 line 184-191*/ - "pvdd11-ocp-alert","","","","","","","", + "pvdd11-ocp-alert","", + "power-fault-n","", + "asic0-card-type-detection0-n","", + "asic0-card-type-detection1-n","", /*M0-M3 line 192-199*/ - "","","","","","","","", + "asic0-card-type-detection2-n","", + "uart-switch-lsb","", + "uart-switch-msb","", + "","", /*M4-M7 line 200-207*/ "","","","","","","","", /*N0-N3 line 208-215*/ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts index 41e2246cfbd1..ef96b17becb2 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts @@ -23,6 +23,32 @@ i2c19 = &imux19; i2c20 = &imux20; i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + i2c32 = &imux32; + i2c33 = &imux33; + i2c34 = &imux34; + i2c35 = &imux35; + i2c36 = &imux36; + i2c37 = &imux37; + i2c38 = &imux38; + i2c39 = &imux39; + i2c40 = &imux40; + i2c41 = &imux41; + i2c42 = &imux42; + i2c43 = &imux43; + i2c44 = &imux44; + i2c45 = &imux45; + i2c46 = &imux46; + i2c47 = &imux47; spi1 = &spi_gpio; }; @@ -75,6 +101,11 @@ gpios = <&leds_gpio 10 GPIO_ACTIVE_LOW>; default-state = "off"; }; + + led-5 { + label = "bmc_ready_noled"; + gpios = <&sgpiom0 141 (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>; + }; }; spi_gpio: spi { @@ -182,6 +213,63 @@ gpio-controller; #gpio-cells = <2>; }; + + gpio@11 { + compatible = "nxp,pca9555"; + reg = <0x11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <238 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "PWRGD_P24V_SMPWROK", "P1V5_PWROK", + "P3V3_PWROK", "P5V_PWROK", + "P12V_SCM_PWROK", "P12V_PWROK", + "P24V_PWROK", "P48V_HSC_PWROK", + "ERR_GPIO_IRQ", "TMP75_ALERT_N", + "BMC_PWROK", "P12V_INA230_ALERT_N", + "P24V_INA230_ALERT_N","", + "P48V_HSC_ALERT_N", "P1V05_PWROK"; + }; + + gpio@12 { + compatible = "nxp,pca9555"; + reg = <0x12>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <240 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "P1V05_PWR_FAIL", "P1V5_PWR_FAIL", + "P24V_PWR_FAIL", "P24V_SM_PWR_FAIL", + "IRQ_NW0/1/2_N", "IRQ_NW3/4/5_N", + "RTC_INT_N_R", "ERR_GPIO_IRQ", + "", "", + "", "", + "", "", + "", ""; + }; + + gpio@13 { + compatible = "nxp,pca9555"; + reg = <0x13>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <242 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "", "", + "", "", + "", "", + "", "", + "RACKMON_A_1", "RACKMON_A_2", + "RACKMON_B_1", "RACKMON_B_2", + "", "", + "", ""; + }; }; &i2c1 { @@ -213,10 +301,11 @@ #size-cells = <0>; i2c-mux-idle-disconnect; - imux16: i2c@0 { + // FCB 1 + imux16: i2c@1 { #address-cells = <1>; #size-cells = <0>; - reg = <0>; + reg = <1>; eeprom@50 { compatible = "atmel,24c128"; @@ -258,12 +347,88 @@ compatible = "ti,tmp75"; reg = <0x4b>; }; - }; - imux17: i2c@1 { + gpio@11 { + compatible = "nxp,pca9555"; + reg = <0x11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <218 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "P48V_FAN1_PWRGD_R", "P48V_FAN2_PWRGD_R", + "P48V_FAN3_PWRGD_R", "P48V_FAN4_PWRGD_R", + "FCB_1_P48V_ZONE0_PWRGD_R", "FCB_1_P48V_ZONE1_PWRGD_R", + "FCB_1_PWRGD_P3V3_R", "", + "", "", + "", "", + "", "", + "", ""; + }; + + gpio@12 { + compatible = "nxp,pca9555"; + reg = <0x12>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <218 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "INA238_FAN1_ALERT_N", "INA238_FAN2_ALERT_N", + "INA238_FAN3_ALERT_N", "INA238_FAN4_ALERT_N", + "FCB_1_TMP75_ALERT_N", "", + "", "", + "FAN1_PRSNT", "FAN2_PRSNT", + "FAN3_PRSNT", "FAN4_PRSNT", + "", "", + "", ""; + }; + + gpio@13 { + compatible = "nxp,pca9555"; + reg = <0x13>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <218 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "FAN1_IL_TACH_ALERT", "FAN1_OL_TACH_ALERT", + "FAN2_IL_TACH_ALERT", "FAN2_OL_TACH_ALERT", + "FAN3_IL_TACH_ALERT", "FAN3_OL_TACH_ALERT", + "FAN4_IL_TACH_ALERT", "FAN4_IL_TACH_ALERT", + "", "", + "", "", + "", "", + "", ""; + }; + + gpio@17 { + compatible = "nxp,pca9555"; + reg = <0x17>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <218 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "FCB_1_P1V0_POWER_FAIL", "FCB_1_P1V8_POWER_FAIL", + "FCB_1_P48V_ZONE0_POWER_FAIL", "FAN1_POWER_FAIL", + "FAN2_POWER_FAIL", "FAN3_POWER_FAIL", + "FAN4_POWER_FAIL", "", + "", "", + "", "", + "", "", + "", ""; + }; + }; + // FCB 2 + imux17: i2c@0 { #address-cells = <1>; #size-cells = <0>; - reg = <1>; + reg = <0>; eeprom@50 { compatible = "atmel,24c128"; @@ -305,12 +470,88 @@ compatible = "ti,tmp75"; reg = <0x4b>; }; - }; - imux18: i2c@2 { + gpio@11 { + compatible = "nxp,pca9555"; + reg = <0x11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <220 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "P48V_FAN5_PWRGD_R", "P48V_FAN6_PWRGD_R", + "P48V_FAN7_PWRGD_R", "P48V_FAN8_PWRGD_R", + "FCB_2_P48V_ZONE0_PWRGD_R", "FCB_2_P48V_ZONE1_PWRGD_R", + "FCB_2_PWRGD_P3V3_R", "", + "", "", + "", "", + "", "", + "", ""; + }; + + gpio@12 { + compatible = "nxp,pca9555"; + reg = <0x12>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <220 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "INA238_FAN5_ALERT_N", "INA238_FAN6_ALERT_N", + "INA238_FAN7_ALERT_N", "INA238_FAN8_ALERT_N", + "FCB_2_TMP75_ALERT_N", "", + "", "", + "FAN5_PRSNT", "FAN6_PRSNT", + "FAN7_PRSNT", "FAN8_PRSNT", + "", "", + "", ""; + }; + + gpio@13 { + compatible = "nxp,pca9555"; + reg = <0x13>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <220 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "FAN5_IL_TACH_ALERT", "FAN5_OL_TACH_ALERT", + "FAN6_IL_TACH_ALERT", "FAN6_OL_TACH_ALERT", + "FAN7_IL_TACH_ALERT", "FAN7_OL_TACH_ALERT", + "FAN8_IL_TACH_ALERT", "FAN8_IL_TACH_ALERT", + "", "", + "", "", + "", "", + "", ""; + }; + + gpio@17 { + compatible = "nxp,pca9555"; + reg = <0x17>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <220 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "FCB_2_P1V0_POWER_FAIL", "FCB_2_P1V8_POWER_FAIL", + "FCB_2_P48V_ZONE0_POWER_FAIL", "FAN5_POWER_FAIL", + "FAN6_POWER_FAIL", "FAN7_POWER_FAIL", + "FAN8_POWER_FAIL", "", + "", "", + "", "", + "", "", + "", ""; + }; + }; + // FCB 3 + imux18: i2c@3 { #address-cells = <1>; #size-cells = <0>; - reg = <2>; + reg = <3>; eeprom@50 { compatible = "atmel,24c128"; @@ -352,12 +593,88 @@ compatible = "ti,tmp75"; reg = <0x4b>; }; - }; - imux19: i2c@3 { + gpio@11 { + compatible = "nxp,pca9555"; + reg = <0x11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <230 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "P48V_FAN9_PWRGD_R", "P48V_FAN10_PWRGD_R", + "P48V_FAN11_PWRGD_R", "P48V_FAN12_PWRGD_R", + "FCB_3_P48V_ZONE0_PWRGD_R", "FCB_3_P48V_ZONE1_PWRGD_R", + "FCB_3_PWRGD_P3V3_R", "", + "", "", + "", "", + "", "", + "", ""; + }; + + gpio@12 { + compatible = "nxp,pca9555"; + reg = <0x12>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <230 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "INA238_FAN9_ALERT_N", "INA238_FAN10_ALERT_N", + "INA238_FAN11_ALERT_N", "INA238_FAN12_ALERT_N", + "FCB_3_TMP75_ALERT_N", "", + "", "", + "FAN9_PRSNT", "FAN10_PRSNT", + "FAN11_PRSNT", "FAN12_PRSNT", + "", "", + "", ""; + }; + + gpio@13 { + compatible = "nxp,pca9555"; + reg = <0x13>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <230 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "FAN9_IL_TACH_ALERT", "FAN9_OL_TACH_ALERT", + "FAN10_IL_TACH_ALERT", "FAN10_OL_TACH_ALERT", + "FAN11_IL_TACH_ALERT", "FAN11_OL_TACH_ALERT", + "FAN12_IL_TACH_ALERT", "FAN12_IL_TACH_ALERT", + "", "", + "", "", + "", "", + "", ""; + }; + + gpio@17 { + compatible = "nxp,pca9555"; + reg = <0x17>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <230 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "FCB_3_P1V0_POWER_FAIL", "FCB_3_P1V8_POWER_FAIL", + "FCB_3_P48V_ZONE0_POWER_FAIL", "FAN9_POWER_FAIL", + "FAN10_POWER_FAIL", "FAN11_POWER_FAIL", + "FAN12_POWER_FAIL", "", + "", "", + "", "", + "", "", + "", ""; + }; + }; + // FCB 4 + imux19: i2c@2 { #address-cells = <1>; #size-cells = <0>; - reg = <3>; + reg = <2>; eeprom@50 { compatible = "atmel,24c128"; @@ -399,9 +716,85 @@ compatible = "ti,tmp75"; reg = <0x4b>; }; - }; - imux20: i2c@5 { + gpio@11 { + compatible = "nxp,pca9555"; + reg = <0x11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <232 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "P48V_FAN13_PWRGD_R", "P48V_FAN14_PWRGD_R", + "P48V_FAN15_PWRGD_R", "P48V_FAN16_PWRGD_R", + "FCB_4_P48V_ZONE0_PWRGD_R", "FCB_4_P48V_ZONE1_PWRGD_R", + "FCB_4_PWRGD_P3V3_R", "", + "", "", + "", "", + "", "", + "", ""; + }; + + gpio@12 { + compatible = "nxp,pca9555"; + reg = <0x12>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <232 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "INA238_FAN13_ALERT_N", "INA238_FAN14_ALERT_N", + "INA238_FAN15_ALERT_N", "INA238_FAN16_ALERT_N", + "FCB_4_TMP75_ALERT_N", "", + "", "", + "FAN13_PRSNT", "FAN14_PRSNT", + "FAN15_PRSNT", "FAN16_PRSNT", + "", "", + "", ""; + }; + + gpio@13 { + compatible = "nxp,pca9555"; + reg = <0x13>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <232 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "FAN13_IL_TACH_ALERT", "FAN13_OL_TACH_ALERT", + "FAN14_IL_TACH_ALERT", "FAN14_OL_TACH_ALERT", + "FAN15_IL_TACH_ALERT", "FAN15_OL_TACH_ALERT", + "FAN16_IL_TACH_ALERT", "FAN16_IL_TACH_ALERT", + "", "", + "", "", + "", "", + "", ""; + }; + + gpio@17 { + compatible = "nxp,pca9555"; + reg = <0x17>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <232 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "FCB_4_P1V0_POWER_FAIL", "FCB_4_P1V8_POWER_FAIL", + "FCB_4_P48V_ZONE0_POWER_FAIL", "FAN13_POWER_FAIL", + "FAN14_POWER_FAIL", "FAN15_POWER_FAIL", + "FAN16_POWER_FAIL", "", + "", "", + "", "", + "", "", + "", ""; + }; + }; + // FCB 5 + imux20: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; @@ -445,9 +838,85 @@ compatible = "ti,tmp75"; reg = <0x4b>; }; - }; - imux21: i2c@4 { + gpio@11 { + compatible = "nxp,pca9555"; + reg = <0x11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <254 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "P48V_FAN20_PWRGD_R", "P48V_FAN19_PWRGD_R", + "P48V_FAN18_PWRGD_R", "P48V_FAN17_PWRGD_R", + "FCB_5_P48V_ZONE0_PWRGD_R", "FCB_5_P48V_ZONE1_PWRGD_R", + "FCB_5_PWRGD_P3V3_R", "", + "", "", + "", "", + "", "", + "", ""; + }; + + gpio@12 { + compatible = "nxp,pca9555"; + reg = <0x12>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <254 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "INA238_FAN20_ALERT_N", "INA238_FAN19_ALERT_N", + "INA238_FAN18_ALERT_N", "INA238_FAN17_ALERT_N", + "FCB_5_TMP75_ALERT_N", "", + "", "", + "FAN20_PRSNT", "FAN19_PRSNT", + "FAN18_PRSNT", "FAN17_PRSNT", + "", "", + "", ""; + }; + + gpio@13 { + compatible = "nxp,pca9555"; + reg = <0x13>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <254 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "FAN20_IL_TACH_ALERT", "FAN20_OL_TACH_ALERT", + "FAN19_IL_TACH_ALERT", "FAN19_OL_TACH_ALERT", + "FAN18_IL_TACH_ALERT", "FAN18_OL_TACH_ALERT", + "FAN17_IL_TACH_ALERT", "FAN17_OL_TACH_ALERT", + "", "", + "", "", + "", "", + "", ""; + }; + + gpio@17 { + compatible = "nxp,pca9555"; + reg = <0x17>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <254 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "FCB_5_P1V0_POWER_FAIL", "FCB_5_P1V8_POWER_FAIL", + "FCB_5_P48V_ZONE0_POWER_FAIL", "FAN20_POWER_FAIL", + "FAN19_POWER_FAIL", "FAN18_POWER_FAIL", + "FAN17_POWER_FAIL", "", + "", "", + "", "", + "", "", + "", ""; + }; + }; + // FCB 6 + imux21: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; @@ -491,24 +960,316 @@ compatible = "ti,tmp75"; reg = <0x4b>; }; + + gpio@11 { + compatible = "nxp,pca9555"; + reg = <0x11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <252 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "P48V_FAN24_PWRGD_R", "P48V_FAN23_PWRGD_R", + "P48V_FAN22_PWRGD_R", "P48V_FAN21_PWRGD_R", + "FCB_6_P48V_ZONE0_PWRGD_R", "FCB_6_P48V_ZONE1_PWRGD_R", + "FCB_6_PWRGD_P3V3_R", "", + "", "", + "", "", + "", "", + "", ""; + }; + + gpio@12 { + compatible = "nxp,pca9555"; + reg = <0x12>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <252 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "INA238_FAN24_ALERT_N", "INA238_FAN23_ALERT_N", + "INA238_FAN22_ALERT_N", "INA238_FAN21_ALERT_N", + "FCB_6_TMP75_ALERT_N", "", + "", "", + "FAN24_PRSNT", "FAN23_PRSNT", + "FAN22_PRSNT", "FAN21_PRSNT", + "", "", + "", ""; + }; + + gpio@13 { + compatible = "nxp,pca9555"; + reg = <0x13>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <252 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "FAN24_IL_TACH_ALERT", "FAN24_OL_TACH_ALERT", + "FAN23_IL_TACH_ALERT", "FAN23_OL_TACH_ALERT", + "FAN22_IL_TACH_ALERT", "FAN22_OL_TACH_ALERT", + "FAN21_IL_TACH_ALERT", "FAN21_OL_TACH_ALERT", + "", "", + "", "", + "", "", + "", ""; + }; + + gpio@17 { + compatible = "nxp,pca9555"; + reg = <0x17>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&sgpiom0>; + interrupts = <252 IRQ_TYPE_LEVEL_LOW>; + + gpio-line-names = + "FCB_6_P1V0_POWER_FAIL", "FCB_6_P1V8_POWER_FAIL", + "FCB_6_P48V_ZONE0_POWER_FAIL", "FAN24_POWER_FAIL", + "FAN23_POWER_FAIL", "FAN22_POWER_FAIL", + "FAN21_POWER_FAIL", "", + "", "", + "", "", + "", "", + "", ""; + }; + }; + + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; }; }; }; &i2c3 { status = "okay"; + + i2c-mux@72 { + compatible = "nxp,pca9545"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + }; }; &i2c4 { status = "okay"; + + i2c-mux@72 { + compatible = "nxp,pca9545"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + + imux28: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux29: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux30: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux31: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + }; }; &i2c5 { status = "okay"; + + i2c-mux@72 { + compatible = "nxp,pca9545"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + + imux32: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux33: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux34: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux35: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + }; }; &i2c6 { status = "okay"; + + i2c-mux@72 { + compatible = "nxp,pca9545"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + + imux36: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux37: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux38: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux39: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + }; }; &i2c7 { @@ -531,14 +1292,111 @@ compatible = "nxp,pcf8563"; reg = <0x51>; }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; }; &i2c12 { status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9545"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + imux40: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux41: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux42: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux43: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; }; &i2c13 { status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9545"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + imux44: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux45: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux46: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + imux47: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; }; &i2c14 { @@ -627,7 +1485,6 @@ gpio-line-names = /*"input pin","output pin"*/ /*A0 - A7*/ - "PRSNT_MTIA_BLADE0_N","PWREN_MTIA_BLADE0_EN_N", "PRSNT_MTIA_BLADE1_N","PWREN_MTIA_BLADE1_EN_N", "PRSNT_MTIA_BLADE2_N","PWREN_MTIA_BLADE2_EN_N", "PRSNT_MTIA_BLADE3_N","PWREN_MTIA_BLADE3_EN_N", @@ -635,8 +1492,8 @@ "PRSNT_MTIA_BLADE5_N","PWREN_MTIA_BLADE5_EN_N", "PRSNT_MTIA_BLADE6_N","PWREN_MTIA_BLADE6_EN_N", "PRSNT_MTIA_BLADE7_N","PWREN_MTIA_BLADE7_EN_N", - /*B0 - B7*/ "PRSNT_MTIA_BLADE8_N","PWREN_MTIA_BLADE8_EN_N", + /*B0 - B7*/ "PRSNT_MTIA_BLADE9_N","PWREN_MTIA_BLADE9_EN_N", "PRSNT_MTIA_BLADE10_N","PWREN_MTIA_BLADE10_EN_N", "PRSNT_MTIA_BLADE11_N","PWREN_MTIA_BLADE11_EN_N", @@ -644,80 +1501,80 @@ "PRSNT_MTIA_BLADE13_N","PWREN_MTIA_BLADE13_EN_N", "PRSNT_MTIA_BLADE14_N","PWREN_MTIA_BLADE14_EN_N", "PRSNT_MTIA_BLADE15_N","PWREN_MTIA_BLADE15_EN_N", + "PRSNT_MTIA_BLADE16_N","PWREN_MTIA_BLADE16_EN_N", /*C0 - C7*/ - "PRSNT_NW_BLADE0_N","PWREN_NW_BLADE0_EN_N", "PRSNT_NW_BLADE1_N","PWREN_NW_BLADE1_EN_N", "PRSNT_NW_BLADE2_N","PWREN_NW_BLADE2_EN_N", "PRSNT_NW_BLADE3_N","PWREN_NW_BLADE3_EN_N", "PRSNT_NW_BLADE4_N","PWREN_NW_BLADE4_EN_N", "PRSNT_NW_BLADE5_N","PWREN_NW_BLADE5_EN_N", - "PRSNT_FCB_TOP_0_N","PWREN_MTIA_BLADE0_HSC_EN_N", - "PRSNT_FCB_TOP_1_N","PWREN_MTIA_BLADE1_HSC_EN_N", + "PRSNT_NW_BLADE6_N","PWREN_NW_BLADE6_EN_N", + "PRSNT_FCB_1_N","PWREN_MTIA_BLADE1_HSC_EN_N", + "PRSNT_FCB_2_N","PWREN_MTIA_BLADE2_HSC_EN_N", /*D0 - D7*/ - "PRSNT_FCB_MIDDLE_0_N","PWREN_MTIA_BLADE2_HSC_EN_N", - "PRSNT_FCB_MIDDLE_1_N","PWREN_MTIA_BLADE3_HSC_EN_N", - "PRSNT_FCB_BOTTOM_1_N","PWREN_MTIA_BLADE4_HSC_EN_N", - "PRSNT_FCB_BOTTOM_0_N","PWREN_MTIA_BLADE5_HSC_EN_N", - "PWRGD_MTIA_BLADE0_PWROK_N","PWREN_MTIA_BLADE6_HSC_EN_N", + "PRSNT_FCB_3_N","PWREN_MTIA_BLADE3_HSC_EN_N", + "PRSNT_FCB_4_N","PWREN_MTIA_BLADE4_HSC_EN_N", + "PRSNT_FCB_6_N","PWREN_MTIA_BLADE5_HSC_EN_N", + "PRSNT_FCB_5_N","PWREN_MTIA_BLADE6_HSC_EN_N", "PWRGD_MTIA_BLADE1_PWROK_N","PWREN_MTIA_BLADE7_HSC_EN_N", "PWRGD_MTIA_BLADE2_PWROK_N","PWREN_MTIA_BLADE8_HSC_EN_N", "PWRGD_MTIA_BLADE3_PWROK_N","PWREN_MTIA_BLADE9_HSC_EN_N", - /*E0 - E7*/ "PWRGD_MTIA_BLADE4_PWROK_N","PWREN_MTIA_BLADE10_HSC_EN_N", + /*E0 - E7*/ "PWRGD_MTIA_BLADE5_PWROK_N","PWREN_MTIA_BLADE11_HSC_EN_N", "PWRGD_MTIA_BLADE6_PWROK_N","PWREN_MTIA_BLADE12_HSC_EN_N", "PWRGD_MTIA_BLADE7_PWROK_N","PWREN_MTIA_BLADE13_HSC_EN_N", "PWRGD_MTIA_BLADE8_PWROK_N","PWREN_MTIA_BLADE14_HSC_EN_N", "PWRGD_MTIA_BLADE9_PWROK_N","PWREN_MTIA_BLADE15_HSC_EN_N", - "PWRGD_MTIA_BLADE10_PWROK_N","PWREN_NW_BLADE0_HSC_EN_N", + "PWRGD_MTIA_BLADE10_PWROK_N","PWREN_MTIA_BLADE16_HSC_EN_N", "PWRGD_MTIA_BLADE11_PWROK_N","PWREN_NW_BLADE1_HSC_EN_N", - /*F0 - F7*/ "PWRGD_MTIA_BLADE12_PWROK_N","PWREN_NW_BLADE2_HSC_EN_N", + /*F0 - F7*/ "PWRGD_MTIA_BLADE13_PWROK_N","PWREN_NW_BLADE3_HSC_EN_N", "PWRGD_MTIA_BLADE14_PWROK_N","PWREN_NW_BLADE4_HSC_EN_N", "PWRGD_MTIA_BLADE15_PWROK_N","PWREN_NW_BLADE5_HSC_EN_N", - "PWRGD_NW_BLADE0_PWROK_N","PWREN_FCB_TOP_0_EN_N", - "PWRGD_NW_BLADE1_PWROK_N","PWREN_FCB_TOP_1_EN_N", - "PWRGD_NW_BLADE2_PWROK_N","PWREN_FCB_MIDDLE_0_EN_N", - "PWRGD_NW_BLADE3_PWROK_N","PWREN_FCB_MIDDLE_1_EN_N", + "PWRGD_MTIA_BLADE16_PWROK_N","PWREN_NW_BLADE6_HSC_EN_N", + "PWRGD_NW_BLADE1_PWROK_N","PWREN_SGPIO_FCB_2_EN_N", + "PWRGD_NW_BLADE2_PWROK_N","PWREN_SGPIO_FCB_1_EN_N", + "PWRGD_NW_BLADE3_PWROK_N","PWREN_SGPIO_FCB_4_EN_N", + "PWRGD_NW_BLADE4_PWROK_N","PWREN_SGPIO_FCB_3_EN_N", /*G0 - G7*/ - "PWRGD_NW_BLADE4_PWROK_N","PWREN_FCB_BOTTOM_1_EN_N", - "PWRGD_NW_BLADE5_PWROK_N","PWREN_FCB_BOTTOM_0_EN_N", - "PWRGD_FCB_TOP_0_PWROK_N","FM_CMM_AC_CYCLE_N", - "PWRGD_FCB_TOP_1_PWROK_N","MGMT_SFP_TX_DIS", - "PWRGD_FCB_MIDDLE_0_PWROK_N","FM_MDIO_SW_SEL", - "PWRGD_FCB_MIDDLE_1_PWROK_N","FM_P24V_SMPWR_EN", - "PWRGD_FCB_BOTTOM_1_PWROK_N","", - "PWRGD_FCB_BOTTOM_0_PWROK_N","", + "PWRGD_NW_BLADE5_PWROK_N","PWREN_SGPIO_FCB_5_EN_N", + "PWRGD_NW_BLADE6_PWROK_N","PWREN_SGPIO_FCB_6_EN_N", + "PWRGD_FCB_1","FM_BMC_RST_RTCRST_R", + "PWRGD_FCB_2","", + "PWRGD_FCB_3","FM_MDIO_SW_SEL", + "PWRGD_FCB_4","FM_P24V_SMPWR_EN", + "PWRGD_FCB_6","", + "PWRGD_FCB_5","", /*H0 - H7*/ - "LEAK_DETECT_MTIA_BLADE0_N","", "LEAK_DETECT_MTIA_BLADE1_N","", "LEAK_DETECT_MTIA_BLADE2_N","", "LEAK_DETECT_MTIA_BLADE3_N","", "LEAK_DETECT_MTIA_BLADE4_N","", "LEAK_DETECT_MTIA_BLADE5_N","", "LEAK_DETECT_MTIA_BLADE6_N","", - "LEAK_DETECT_MTIA_BLADE7_N","", + "LEAK_DETECT_MTIA_BLADE7_N","ERR_INJECT_CMM_PWR_FAIL_N", + "LEAK_DETECT_MTIA_BLADE8_N","", /*I0 - I7*/ - "LEAK_DETECT_MTIA_BLADE8_N","RST_I2CRST_FCB_BOTTOM_1_N", - "LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_BOTTOM_0_N", - "LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_MIDDLE_0_N", - "LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_MIDDLE_1_N", - "LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_TOP_0_N", - "LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_TOP_1_N", - "LEAK_DETECT_MTIA_BLADE14_N","BMC_READY", - "LEAK_DETECT_MTIA_BLADE15_N","FM_88E6393X_BIN_UPDATE_EN_N", + "LEAK_DETECT_MTIA_BLADE9_N","RST_I2CRST_FCB_5_N", + "LEAK_DETECT_MTIA_BLADE10_N","RST_I2CRST_FCB_6_N", + "LEAK_DETECT_MTIA_BLADE11_N","RST_I2CRST_FCB_4_N", + "LEAK_DETECT_MTIA_BLADE12_N","RST_I2CRST_FCB_3_N", + "LEAK_DETECT_MTIA_BLADE13_N","RST_I2CRST_FCB_2_N", + "LEAK_DETECT_MTIA_BLADE14_N","RST_I2CRST_FCB_1_N", + "LEAK_DETECT_MTIA_BLADE15_N","BMC_READY", + "LEAK_DETECT_MTIA_BLADE16_N","FM_88E6393X_BIN_UPDATE_EN_N", /*J0 - J7*/ - "LEAK_DETECT_NW_BLADE0_N","WATER_VALVE_CLOSED_N", - "LEAK_DETECT_NW_BLADE1_N","", + "LEAK_DETECT_NW_BLADE1_N","WATER_VALVE_CLOSED_N", "LEAK_DETECT_NW_BLADE2_N","", "LEAK_DETECT_NW_BLADE3_N","", "LEAK_DETECT_NW_BLADE4_N","", "LEAK_DETECT_NW_BLADE5_N","", - "PWRGD_MTIA_BLADE0_HSC_PWROK_N","", + "LEAK_DETECT_NW_BLADE6_N","", "PWRGD_MTIA_BLADE1_HSC_PWROK_N","", - /*K0 - K7*/ "PWRGD_MTIA_BLADE2_HSC_PWROK_N","", + /*K0 - K7*/ "PWRGD_MTIA_BLADE3_HSC_PWROK_N","", "PWRGD_MTIA_BLADE4_HSC_PWROK_N","", "PWRGD_MTIA_BLADE5_HSC_PWROK_N","", @@ -725,49 +1582,50 @@ "PWRGD_MTIA_BLADE7_HSC_PWROK_N","", "PWRGD_MTIA_BLADE8_HSC_PWROK_N","", "PWRGD_MTIA_BLADE9_HSC_PWROK_N","", - /*L0 - L7*/ "PWRGD_MTIA_BLADE10_HSC_PWROK_N","", + /*L0 - L7*/ "PWRGD_MTIA_BLADE11_HSC_PWROK_N","", "PWRGD_MTIA_BLADE12_HSC_PWROK_N","", "PWRGD_MTIA_BLADE13_HSC_PWROK_N","", "PWRGD_MTIA_BLADE14_HSC_PWROK_N","", "PWRGD_MTIA_BLADE15_HSC_PWROK_N","", - "PWRGD_NW_BLADE0_HSC_PWROK_N","", + "PWRGD_MTIA_BLADE16_HSC_PWROK_N","", "PWRGD_NW_BLADE1_HSC_PWROK_N","", - /*M0 - M7*/ "PWRGD_NW_BLADE2_HSC_PWROK_N","", + /*M0 - M7*/ "PWRGD_NW_BLADE3_HSC_PWROK_N","", "PWRGD_NW_BLADE4_HSC_PWROK_N","", "PWRGD_NW_BLADE5_HSC_PWROK_N","", + "PWRGD_NW_BLADE6_HSC_PWROK_N","", "RPU_READY","", "IT_GEAR_RPU_LINK_N","", "IT_GEAR_LEAK","", "WATER_VALVE_CLOSED_N","", /*N0 - N7*/ - "VALVE_STS0","", - "VALVE_STS1","", - "PCA9555_IRQ0_N","", + "VALVE_STATUS_0","", + "VALVE_STATUS_1","", "PCA9555_IRQ1_N","", + "PCA9555_IRQ2_N","", "CR_TOGGLE_BOOT_N","", - "IRQ_FCB_TOP0_N","", - "IRQ_FCB_TOP1_N","", + "IRQ_FCB_1_N","", + "IRQ_FCB_2_N","", "CMM_CABLE_CARTRIDGE_PRSNT_BOT_N","", /*O0 - O7*/ "CMM_CABLE_CARTRIDGE_PRSNT_TOP_N","", "BOT_BCB_CABLE_PRSNT_N","", "TOP_BCB_CABLE_PRSNT_N","", - "IRQ_FCB_MID0_N","", - "IRQ_FCB_MID1_N","", + "IRQ_FCB_3_N","", + "IRQ_FCB_4_N","", "CHASSIS_LEAK0_DETECT_N","", "CHASSIS_LEAK1_DETECT_N","", - "VALVE_RMON_A_1","", + "PCA9555_IRQ3_N","", /*P0 - P7*/ - "VALVE_RMON_A_2","", - "VALVE_RMON_B_1","", - "VALVE_RMON_B_2","", + "PCA9555_IRQ4_N","", + "PCA9555_IRQ5_N","", + "CMM_AC_PWR_BTN_N","", "RPU_READY_SPARE","", "IT_GEAR_LEAK_SPARE","", "IT_GEAR_RPU_LINK_SPARE_N","", - "IRQ_FCB_BOT0_N","", - "IRQ_FCB_BOT0_N",""; + "IRQ_FCB_6_N","", + "IRQ_FCB_5_N",""; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts index 98477792aa00..29f224bccd63 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts @@ -17,6 +17,27 @@ serial6 = &uart7; serial7 = &uart8; serial8 = &uart9; + + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + i2c32 = &imux32; + i2c33 = &imux33; + i2c34 = &imux34; + i2c35 = &imux35; }; chosen { @@ -32,7 +53,25 @@ compatible = "iio-hwmon"; io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, - <&adc1 0>, <&adc1 1>; + <&adc1 0>, <&adc1 1>, <&adc1 7>; + }; + + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <33000000>; + }; }; }; @@ -83,6 +122,13 @@ aspeed,ext-pulse-duration = <256>; }; +&wdt2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst2_default>; + aspeed,reset-type = "system"; +}; + &mac2 { status = "okay"; pinctrl-names = "default"; @@ -105,15 +151,17 @@ status = "okay"; m25p,fast-read; label = "bmc"; - spi-rx-bus-width = <4>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-64.dtsi" +#include "openbmc-flash-layout-128.dtsi" }; flash@1 { status = "okay"; m25p,fast-read; - label = "bmc2"; - spi-rx-bus-width = <4>; + label = "alt-bmc"; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; spi-max-frequency = <50000000>; }; }; @@ -129,9 +177,38 @@ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; }; + gpio@21 { + compatible = "nxp,pca9506"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@22 { + compatible = "nxp,pca9506"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@23 { + compatible = "nxp,pca9506"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@24 { + compatible = "nxp,pca9506"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + power-sensor@40 { - compatible = "adi,adm1278"; + compatible = "adi,adm1281"; reg = <0x40>; + shunt-resistor-micro-ohms = <500>; }; }; @@ -146,9 +223,38 @@ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; }; + gpio@21 { + compatible = "nxp,pca9506"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@22 { + compatible = "nxp,pca9506"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@23 { + compatible = "nxp,pca9506"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@24 { + compatible = "nxp,pca9506"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + power-sensor@40 { - compatible = "adi,adm1278"; + compatible = "adi,adm1281"; reg = <0x40>; + shunt-resistor-micro-ohms = <500>; }; }; @@ -163,9 +269,38 @@ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; }; + gpio@21 { + compatible = "nxp,pca9506"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@22 { + compatible = "nxp,pca9506"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@23 { + compatible = "nxp,pca9506"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@24 { + compatible = "nxp,pca9506"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + power-sensor@40 { - compatible = "adi,adm1278"; + compatible = "adi,adm1281"; reg = <0x40>; + shunt-resistor-micro-ohms = <500>; }; }; @@ -180,9 +315,38 @@ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; }; + gpio@21 { + compatible = "nxp,pca9506"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@22 { + compatible = "nxp,pca9506"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@23 { + compatible = "nxp,pca9506"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@24 { + compatible = "nxp,pca9506"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + power-sensor@40 { - compatible = "adi,adm1278"; + compatible = "adi,adm1281"; reg = <0x40>; + shunt-resistor-micro-ohms = <500>; }; }; @@ -197,9 +361,38 @@ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; }; + gpio@21 { + compatible = "nxp,pca9506"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@22 { + compatible = "nxp,pca9506"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@23 { + compatible = "nxp,pca9506"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@24 { + compatible = "nxp,pca9506"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + power-sensor@40 { - compatible = "adi,adm1278"; + compatible = "adi,adm1281"; reg = <0x40>; + shunt-resistor-micro-ohms = <500>; }; }; @@ -214,9 +407,38 @@ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; }; + gpio@21 { + compatible = "nxp,pca9506"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@22 { + compatible = "nxp,pca9506"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@23 { + compatible = "nxp,pca9506"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@24 { + compatible = "nxp,pca9506"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + power-sensor@40 { - compatible = "adi,adm1278"; + compatible = "adi,adm1281"; reg = <0x40>; + shunt-resistor-micro-ohms = <500>; }; }; @@ -231,9 +453,38 @@ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; }; + gpio@21 { + compatible = "nxp,pca9506"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@22 { + compatible = "nxp,pca9506"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@23 { + compatible = "nxp,pca9506"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@24 { + compatible = "nxp,pca9506"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + power-sensor@40 { - compatible = "adi,adm1278"; + compatible = "adi,adm1281"; reg = <0x40>; + shunt-resistor-micro-ohms = <500>; }; }; @@ -248,48 +499,363 @@ reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; }; + gpio@21 { + compatible = "nxp,pca9506"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@22 { + compatible = "nxp,pca9506"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@23 { + compatible = "nxp,pca9506"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@24 { + compatible = "nxp,pca9506"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; + power-sensor@40 { - compatible = "adi,adm1278"; + compatible = "adi,adm1281"; reg = <0x40>; + shunt-resistor-micro-ohms = <500>; }; }; &i2c8 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; bus-frequency = <400000>; i2c-mux@70 { compatible = "nxp,pca9544"; - idle-state = <0>; - i2c-mux-idle-disconnect; reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + imux16: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + gpio@49 { + compatible = "nxp,pca9537"; + reg = <0x49>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; + }; + + imux17: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + gpio@49 { + compatible = "nxp,pca9537"; + reg = <0x49>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; + }; + + imux18: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + gpio@49 { + compatible = "nxp,pca9537"; + reg = <0x49>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; + }; + + imux19: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + gpio@49 { + compatible = "nxp,pca9537"; + reg = <0x49>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; + }; }; }; &i2c9 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; bus-frequency = <400000>; i2c-mux@71 { compatible = "nxp,pca9544"; - idle-state = <0>; - i2c-mux-idle-disconnect; reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + imux20: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + gpio@49 { + compatible = "nxp,pca9537"; + reg = <0x49>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; + }; + + imux21: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + gpio@49 { + compatible = "nxp,pca9537"; + reg = <0x49>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; + }; + + imux22: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + gpio@49 { + compatible = "nxp,pca9537"; + reg = <0x49>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; + }; + + imux23: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + gpio@49 { + compatible = "nxp,pca9537"; + reg = <0x49>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; + }; }; }; &i2c10 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; bus-frequency = <400000>; + i2c-mux@74 { + compatible = "nxp,pca9544"; + reg = <0x74>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + imux28: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@20 { + compatible = "nxp,pca9506"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@21 { + compatible = "nxp,pca9506"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@22 { + compatible = "nxp,pca9506"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@23 { + compatible = "nxp,pca9506"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@24 { + compatible = "nxp,pca9506"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "","","","", + "NIC0_MAIN_PWR_EN", + "NIC1_MAIN_PWR_EN", + "NIC2_MAIN_PWR_EN", + "NIC3_MAIN_PWR_EN", + "","","","","","","","", + "","","","","","","","", + "","","","","","","",""; + }; + }; + + imux29: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; &i2c11 { status = "okay"; power-sensor@10 { - compatible = "adi, adm1272"; + compatible = "adi,adm1272"; reg = <0x10>; }; power-sensor@12 { - compatible = "adi, adm1272"; + compatible = "adi,adm1272"; reg = <0x12>; }; @@ -298,6 +864,20 @@ reg = <0x20>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <98 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "P48V_OCP_GPIO1", "P48V_OCP_GPIO2", + "P48V_OCP_GPIO3", "FAN_BOARD_0_REVISION_0_R", + "FAN_BOARD_0_REVISION_1_R", + "FAN_BOARD_1_REVISION_0_R", + "FAN_BOARD_1_REVISION_1_R", "RST_MUX_R_N", + "RST_LED_CONTROL_FAN_BOARD_0_N", + "RST_LED_CONTROL_FAN_BOARD_1_N", + "RST_IOEXP_FAN_BOARD_0_N", + "RST_IOEXP_FAN_BOARD_1_N", + "PWRGD_LOAD_SWITCH_FAN_BOARD_0_R", + "PWRGD_LOAD_SWITCH_FAN_BOARD_1_R", + "", ""; }; gpio@21 { @@ -305,6 +885,19 @@ reg = <0x21>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <98 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "HSC_OCP_SLOT_ODD_GPIO1", + "HSC_OCP_SLOT_ODD_GPIO2", + "HSC_OCP_SLOT_ODD_GPIO3", + "HSC_OCP_SLOT_EVEN_GPIO1", + "HSC_OCP_SLOT_EVEN_GPIO2", + "HSC_OCP_SLOT_EVEN_GPIO3", + "ADC_TYPE_0_R", "ADC_TYPE_1_R", + "MEDUSA_BOARD_REV_0", "MEDUSA_BOARD_REV_1", + "MEDUSA_BOARD_REV_2", "MEDUSA_BOARD_TYPE", + "DELTA_MODULE_TYPE", "P12V_HSC_TYPE", + "", ""; }; gpio@22 { @@ -312,6 +905,16 @@ reg = <0x22>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <98 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "CARD_TYPE_SLOT1", "CARD_TYPE_SLOT2", + "CARD_TYPE_SLOT3", "CARD_TYPE_SLOT4", + "CARD_TYPE_SLOT5", "CARD_TYPE_SLOT6", + "CARD_TYPE_SLOT7", "CARD_TYPE_SLOT8", + "OC_P48V_HSC_0_N", "FLT_P48V_HSC_0_N", + "OC_P48V_HSC_1_N", "FLT_P48V_HSC_1_N", + "EN_P48V_AUX_0", "EN_P48V_AUX_1", + "PWRGD_P12V_AUX_0", "PWRGD_P12V_AUX_1"; }; gpio@23 { @@ -319,6 +922,16 @@ reg = <0x23>; gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <98 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "HSC1_ALERT1_R_N", "HSC2_ALERT1_R_N", + "HSC3_ALERT1_R_N", "HSC4_ALERT1_R_N", + "HSC5_ALERT1_R_N", "HSC6_ALERT1_R_N", + "HSC7_ALERT1_R_N", "HSC8_ALERT1_R_N", + "HSC1_ALERT2_R_N", "HSC2_ALERT2_R_N", + "HSC3_ALERT2_R_N", "HSC4_ALERT2_R_N", + "HSC5_ALERT2_R_N", "HSC6_ALERT2_R_N", + "HSC7_ALERT2_R_N", "HSC8_ALERT2_R_N"; }; temperature-sensor@48 { @@ -331,39 +944,84 @@ reg = <0x49>; }; - temperature-sensor@4a { - compatible = "ti,tmp75"; - reg = <0x4a>; - }; - - temperature-sensor@4b { - compatible = "ti,tmp75"; - reg = <0x4b>; - }; - eeprom@54 { - compatible = "atmel,24c256"; + compatible = "atmel,24c128"; reg = <0x54>; }; }; &i2c12 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; bus-frequency = <400000>; - temperature-sensor@48 { - compatible = "ti,tmp75"; - reg = <0x48>; - }; + i2c-mux@70 { + compatible = "nxp,pca9544"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; + imux34: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; + + rtc@6f { + compatible = "nuvoton,nct3018y"; + reg = <0x6f>; + }; - rtc@6f { - compatible = "nuvoton,nct3018y"; - reg = <0x6f>; + gpio@20 { + compatible = "nxp,pca9506"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@21 { + compatible = "nxp,pca9506"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@22 { + compatible = "nxp,pca9506"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@23 { + compatible = "nxp,pca9506"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + imux35: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; }; }; @@ -380,24 +1038,26 @@ }; &i2c14 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; bus-frequency = <400000>; adc@1d { compatible = "ti,adc128d818"; reg = <0x1d>; - ti,mode = /bits/ 8 <2>; + ti,mode = /bits/ 8 <1>; }; - adc@35 { + adc@36 { compatible = "ti,adc128d818"; - reg = <0x35>; - ti,mode = /bits/ 8 <2>; + reg = <0x36>; + ti,mode = /bits/ 8 <1>; }; adc@37 { compatible = "ti,adc128d818"; reg = <0x37>; - ti,mode = /bits/ 8 <2>; + ti,mode = /bits/ 8 <1>; }; power-sensor@40 { @@ -440,43 +1100,67 @@ reg = <0x51>; }; - i2c-mux@71 { - compatible = "nxp,pca9846"; + i2c-mux@73 { + compatible = "nxp,pca9544"; + reg = <0x73>; #address-cells = <1>; #size-cells = <0>; - - idle-state = <0>; i2c-mux-idle-disconnect; - reg = <0x71>; - i2c@0 { + imux32: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + adc@35 { + compatible = "maxim,max11617"; + reg = <0x35>; + }; + }; + + imux33: i2c@1 { + reg = <1>; #address-cells = <1>; #size-cells = <0>; + adc@35 { + compatible = "maxim,max11617"; + reg = <0x35>; + }; + }; + }; + + i2c-mux@74 { + compatible = "nxp,pca9546"; + reg = <0x74>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + imux30: i2c@0 { reg = <0>; + #address-cells = <1>; + #size-cells = <0>; adc@1f { compatible = "ti,adc128d818"; reg = <0x1f>; - ti,mode = /bits/ 8 <2>; + ti,mode = /bits/ 8 <1>; }; pwm@20{ - compatible = "max31790"; + compatible = "maxim,max31790"; reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; }; gpio@22{ compatible = "ti,tca6424"; reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; }; - pwm@23{ - compatible = "max31790"; - reg = <0x23>; - #address-cells = <1>; - #size-cells = <0>; + pwm@2f{ + compatible = "maxim,max31790"; + reg = <0x2f>; }; adc@33 { @@ -499,34 +1183,32 @@ }; }; - i2c@1 { + imux31: i2c@1 { + reg = <1>; #address-cells = <1>; #size-cells = <0>; - reg = <0>; adc@1f { compatible = "ti,adc128d818"; reg = <0x1f>; - ti,mode = /bits/ 8 <2>; + ti,mode = /bits/ 8 <1>; }; pwm@20{ - compatible = "max31790"; + compatible = "maxim,max31790"; reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; }; gpio@22{ compatible = "ti,tca6424"; reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; }; - pwm@23{ - compatible = "max31790"; - reg = <0x23>; - #address-cells = <1>; - #size-cells = <0>; + pwm@2f{ + compatible = "maxim,max31790"; + reg = <0x2f>; }; adc@33 { @@ -549,56 +1231,89 @@ }; }; }; +}; - i2c-mux@73 { +&i2c15 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + multi-master; + bus-frequency = <400000>; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@72 { compatible = "nxp,pca9544"; + reg = <0x72>; #address-cells = <1>; #size-cells = <0>; - idle-state = <0>; - i2c-mux-idle-disconnect; - reg = <0x73>; - - i2c@0 { + imux24: i2c@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; - reg = <0>; + mctp-controller; + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; - adc@35 { - compatible = "maxim,max11617"; - reg = <0x35>; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; }; }; - i2c@1 { + imux25: i2c@1 { + reg = <1>; #address-cells = <1>; #size-cells = <0>; - reg = <0>; + mctp-controller; + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; - adc@35 { - compatible = "maxim,max11617"; - reg = <0x35>; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; }; }; - }; -}; -&i2c15 { - status = "okay"; - mctp-controller; - multi-master; - bus-frequency = <400000>; + imux26: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + mctp-controller; + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; - mctp@10 { - compatible = "mctp-i2c-controller"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - }; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; - i2c-mux@72 { - compatible = "nxp,pca9544"; - idle-state = <0>; - i2c-mux-idle-disconnect; - reg = <0x72>; + imux27: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + mctp-controller; + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; }; }; @@ -612,10 +1327,10 @@ &adc1 { status = "okay"; - pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default>; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc15_default>; }; - &ehci0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts index dfe5cc3edb52..bc4c46235421 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-blueridge.dts @@ -207,7 +207,8 @@ /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","", "factory-reset-toggle","", /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","bmc-ingraham0","rear-enc-id0","rear-enc-fault0","","","","", + /*H0-H7*/ "","led-bmc-ingraham0","led-rear-enc-id0","led-rear-enc-fault0","","","", + "", /*I0-I7*/ "","","","","","","bmc-secure-boot","", /*J0-J7*/ "","","","","","","","", /*K0-K7*/ "","","","","","","","", @@ -215,7 +216,7 @@ /*M0-M7*/ "","","","","","","","", /*N0-N7*/ "","","","","","","","", /*O0-O7*/ "","","","usb-power","","","","", - /*P0-P7*/ "","","","","pcieslot-power","","","", + /*P0-P7*/ "","","","","led-pcieslot-power","","","", /*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","", /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","", "", @@ -739,7 +740,7 @@ type = <PCA955X_TYPE_LED>; }; - led@10 { + led@a { reg = <10>; default-state = "keep"; label = "ddimm10"; @@ -747,7 +748,7 @@ type = <PCA955X_TYPE_LED>; }; - led@11 { + led@b { reg = <11>; default-state = "keep"; label = "ddimm11"; @@ -755,7 +756,7 @@ type = <PCA955X_TYPE_LED>; }; - led@12 { + led@c { reg = <12>; default-state = "keep"; label = "ddimm12"; @@ -763,7 +764,7 @@ type = <PCA955X_TYPE_LED>; }; - led@13 { + led@d { reg = <13>; default-state = "keep"; label = "ddimm13"; @@ -771,7 +772,7 @@ type = <PCA955X_TYPE_LED>; }; - led@14 { + led@e { reg = <14>; default-state = "keep"; label = "ddimm14"; @@ -779,7 +780,7 @@ type = <PCA955X_TYPE_LED>; }; - led@15 { + led@f { reg = <15>; default-state = "keep"; label = "ddimm15"; @@ -876,7 +877,7 @@ type = <PCA955X_TYPE_LED>; }; - led@10 { + led@a { reg = <10>; default-state = "keep"; label = "ddimm26"; @@ -884,7 +885,7 @@ type = <PCA955X_TYPE_LED>; }; - led@11 { + led@b { reg = <11>; default-state = "keep"; label = "ddimm27"; @@ -892,7 +893,7 @@ type = <PCA955X_TYPE_LED>; }; - led@12 { + led@c { reg = <12>; default-state = "keep"; label = "ddimm28"; @@ -900,7 +901,7 @@ type = <PCA955X_TYPE_LED>; }; - led@13 { + led@d { reg = <13>; default-state = "keep"; label = "ddimm29"; @@ -908,7 +909,7 @@ type = <PCA955X_TYPE_LED>; }; - led@14 { + led@e { reg = <14>; default-state = "keep"; label = "ddimm30"; @@ -916,7 +917,7 @@ type = <PCA955X_TYPE_LED>; }; - led@15 { + led@f { reg = <15>; default-state = "keep"; label = "ddimm31"; @@ -1005,7 +1006,7 @@ type = <PCA955X_TYPE_LED>; }; - led@10 { + led@a { reg = <10>; default-state = "keep"; label = "pcieslot7"; @@ -1013,7 +1014,7 @@ type = <PCA955X_TYPE_LED>; }; - led@11 { + led@b { reg = <11>; default-state = "keep"; label = "pcieslot8"; @@ -1021,7 +1022,7 @@ type = <PCA955X_TYPE_LED>; }; - led@12 { + led@c { reg = <12>; default-state = "keep"; label = "pcieslot9"; @@ -1029,7 +1030,7 @@ type = <PCA955X_TYPE_LED>; }; - led@13 { + led@d { reg = <13>; default-state = "keep"; label = "pcieslot10"; @@ -1037,7 +1038,7 @@ type = <PCA955X_TYPE_LED>; }; - led@14 { + led@e { reg = <14>; default-state = "keep"; label = "pcieslot11"; @@ -1045,7 +1046,7 @@ type = <PCA955X_TYPE_LED>; }; - led@15 { + led@f { reg = <15>; default-state = "keep"; label = "tpm-wilson"; @@ -1231,8 +1232,9 @@ #gpio-cells = <2>; gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "power-config-full-load", ""; + "", "", "", "", "", "", "P10_DCM0_PRES", "P10_DCM1_PRES", + "", "", "", "", "PRESENT_VRM_DCM0_N", "PRESENT_VRM_DCM1_N", + "power-config-full-load", ""; }; led-controller@61 { diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts index 513077a1f4be..9961508ee872 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts @@ -353,6 +353,33 @@ "presence-base-op", ""; }; + + led-controller@63 { + compatible = "nxp,pca9552"; + reg = <0x63>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-vrm-c12", + "presence-vrm-c13", + "presence-vrm-c15", + "presence-vrm-c16", + "presence-vrm-c17", + "presence-vrm-c18", + "presence-vrm-c20", + "presence-vrm-c21", + "presence-vrm-c54", + "presence-vrm-c55", + "presence-vrm-c57", + "presence-vrm-c58", + "presence-vrm-c59", + "presence-vrm-c60", + "presence-vrm-c62", + "presence-vrm-c63"; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts index c24e464e5faa..9a43fc7bcebe 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-fuji.dts @@ -355,6 +355,33 @@ "presence-base-op", ""; }; + + led-controller@63 { + compatible = "nxp,pca9552"; + reg = <0x63>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "presence-vrm-c12", + "presence-vrm-c13", + "presence-vrm-c15", + "presence-vrm-c16", + "presence-vrm-c17", + "presence-vrm-c18", + "presence-vrm-c20", + "presence-vrm-c21", + "presence-vrm-c54", + "presence-vrm-c55", + "presence-vrm-c57", + "presence-vrm-c58", + "presence-vrm-c59", + "presence-vrm-c60", + "presence-vrm-c62", + "presence-vrm-c63"; + }; }; &i2c1 { @@ -949,7 +976,7 @@ type = <PCA955X_TYPE_LED>; }; - led@10 { + led@a { reg = <10>; default-state = "keep"; label = "pcieslot-c10"; @@ -957,7 +984,7 @@ type = <PCA955X_TYPE_LED>; }; - led@11 { + led@b { reg = <11>; default-state = "keep"; label = "pcieslot-c11"; @@ -1058,7 +1085,7 @@ type = <PCA955X_TYPE_LED>; }; - led@10 { + led@a { reg = <10>; default-state = "keep"; label = "ddimm10"; @@ -1066,7 +1093,7 @@ type = <PCA955X_TYPE_LED>; }; - led@11 { + led@b { reg = <11>; default-state = "keep"; label = "ddimm11"; @@ -1074,7 +1101,7 @@ type = <PCA955X_TYPE_LED>; }; - led@12 { + led@c { reg = <12>; default-state = "keep"; label = "ddimm12"; @@ -1082,7 +1109,7 @@ type = <PCA955X_TYPE_LED>; }; - led@13 { + led@d { reg = <13>; default-state = "keep"; label = "ddimm13"; @@ -1090,7 +1117,7 @@ type = <PCA955X_TYPE_LED>; }; - led@14 { + led@e { reg = <14>; default-state = "keep"; label = "ddimm14"; @@ -1098,7 +1125,7 @@ type = <PCA955X_TYPE_LED>; }; - led@15 { + led@f { reg = <15>; default-state = "keep"; label = "ddimm15"; @@ -1195,7 +1222,7 @@ type = <PCA955X_TYPE_LED>; }; - led@10 { + led@a { reg = <10>; default-state = "keep"; label = "ddimm26"; @@ -1203,7 +1230,7 @@ type = <PCA955X_TYPE_LED>; }; - led@11 { + led@b { reg = <11>; default-state = "keep"; label = "ddimm27"; @@ -1211,7 +1238,7 @@ type = <PCA955X_TYPE_LED>; }; - led@12 { + led@c { reg = <12>; default-state = "keep"; label = "ddimm28"; @@ -1219,7 +1246,7 @@ type = <PCA955X_TYPE_LED>; }; - led@13 { + led@d { reg = <13>; default-state = "keep"; label = "ddimm29"; @@ -1227,7 +1254,7 @@ type = <PCA955X_TYPE_LED>; }; - led@14 { + led@e { reg = <14>; default-state = "keep"; label = "ddimm30"; @@ -1235,7 +1262,7 @@ type = <PCA955X_TYPE_LED>; }; - led@15 { + led@f { reg = <15>; default-state = "keep"; label = "ddimm31"; @@ -1332,7 +1359,7 @@ type = <PCA955X_TYPE_LED>; }; - led@10 { + led@a { reg = <10>; default-state = "keep"; label = "ddimm42"; @@ -1340,7 +1367,7 @@ type = <PCA955X_TYPE_LED>; }; - led@11 { + led@b { reg = <11>; default-state = "keep"; label = "ddimm43"; @@ -1348,7 +1375,7 @@ type = <PCA955X_TYPE_LED>; }; - led@12 { + led@c { reg = <12>; default-state = "keep"; label = "ddimm44"; @@ -1356,7 +1383,7 @@ type = <PCA955X_TYPE_LED>; }; - led@13 { + led@d { reg = <13>; default-state = "keep"; label = "ddimm45"; @@ -1364,7 +1391,7 @@ type = <PCA955X_TYPE_LED>; }; - led@14 { + led@e { reg = <14>; default-state = "keep"; label = "ddimm46"; @@ -1372,7 +1399,7 @@ type = <PCA955X_TYPE_LED>; }; - led@15 { + led@f { reg = <15>; default-state = "keep"; label = "ddimm47"; @@ -1469,7 +1496,7 @@ type = <PCA955X_TYPE_LED>; }; - led@10 { + led@a { reg = <10>; default-state = "keep"; label = "ddimm58"; @@ -1477,7 +1504,7 @@ type = <PCA955X_TYPE_LED>; }; - led@11 { + led@b { reg = <11>; default-state = "keep"; label = "ddimm59"; @@ -1485,7 +1512,7 @@ type = <PCA955X_TYPE_LED>; }; - led@12 { + led@c { reg = <12>; default-state = "keep"; label = "ddimm60"; @@ -1493,7 +1520,7 @@ type = <PCA955X_TYPE_LED>; }; - led@13 { + led@d { reg = <13>; default-state = "keep"; label = "ddimm61"; @@ -1501,7 +1528,7 @@ type = <PCA955X_TYPE_LED>; }; - led@14 { + led@e { reg = <14>; default-state = "keep"; label = "ddimm62"; @@ -1509,7 +1536,7 @@ type = <PCA955X_TYPE_LED>; }; - led@15 { + led@f { reg = <15>; default-state = "keep"; label = "ddimm63"; @@ -1598,7 +1625,7 @@ type = <PCA955X_TYPE_LED>; }; - led@10 { + led@a { reg = <10>; default-state = "keep"; label = "vrm6"; @@ -1606,7 +1633,7 @@ type = <PCA955X_TYPE_LED>; }; - led@11 { + led@b { reg = <11>; default-state = "keep"; label = "vrm7"; @@ -1614,7 +1641,7 @@ type = <PCA955X_TYPE_LED>; }; - led@12 { + led@c { reg = <12>; default-state = "keep"; label = "vrm12"; @@ -1622,7 +1649,7 @@ type = <PCA955X_TYPE_LED>; }; - led@13 { + led@d { reg = <13>; default-state = "keep"; label = "vrm13"; @@ -1630,7 +1657,7 @@ type = <PCA955X_TYPE_LED>; }; - led@14 { + led@e { reg = <14>; default-state = "keep"; label = "vrm14"; @@ -1638,7 +1665,7 @@ type = <PCA955X_TYPE_LED>; }; - led@15 { + led@f { reg = <15>; default-state = "keep"; label = "vrm15"; @@ -1727,7 +1754,7 @@ type = <PCA955X_TYPE_LED>; }; - led@10 { + led@a { reg = <10>; default-state = "keep"; label = "vrm2"; @@ -1735,7 +1762,7 @@ type = <PCA955X_TYPE_LED>; }; - led@11 { + led@b { reg = <11>; default-state = "keep"; label = "vrm3"; @@ -1743,7 +1770,7 @@ type = <PCA955X_TYPE_LED>; }; - led@12 { + led@c { reg = <12>; default-state = "keep"; label = "vrm8"; @@ -1751,7 +1778,7 @@ type = <PCA955X_TYPE_LED>; }; - led@13 { + led@d { reg = <13>; default-state = "keep"; label = "vrm9"; @@ -1759,7 +1786,7 @@ type = <PCA955X_TYPE_LED>; }; - led@14 { + led@e { reg = <14>; default-state = "keep"; label = "vrm10"; @@ -1767,7 +1794,7 @@ type = <PCA955X_TYPE_LED>; }; - led@15 { + led@f { reg = <15>; default-state = "keep"; label = "vrm11"; @@ -2118,7 +2145,7 @@ type = <PCA955X_TYPE_LED>; }; - led@10 { + led@a { reg = <10>; default-state = "keep"; label = "fan0"; @@ -2126,7 +2153,7 @@ type = <PCA955X_TYPE_LED>; }; - led@11 { + led@b { reg = <11>; default-state = "keep"; label = "fan1"; @@ -2134,7 +2161,7 @@ type = <PCA955X_TYPE_LED>; }; - led@12 { + led@c { reg = <12>; default-state = "keep"; label = "fan2"; @@ -2142,7 +2169,7 @@ type = <PCA955X_TYPE_LED>; }; - led@13 { + led@d { reg = <13>; default-state = "keep"; label = "fan3"; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts index 0776b72c2199..638a2c1c7892 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts @@ -109,22 +109,22 @@ compatible = "gpio-leds"; /* BMC Card fault LED at the back */ - bmc-ingraham0 { + led-bmc-ingraham0 { gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>; }; /* Enclosure ID LED at the back */ - rear-enc-id0 { + led-rear-enc-id0 { gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; }; /* Enclosure fault LED at the back */ - rear-enc-fault0 { + led-rear-enc-fault0 { gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; }; /* PCIE slot power LED */ - pcieslot-power { + led-pcieslot-power { gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>; }; }; @@ -203,7 +203,7 @@ /*E0-E7*/ "","","","","","","","", /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","factory-reset-toggle","", /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","bmc-ingraham0","rear-enc-id0","rear-enc-fault0","","","","", + /*H0-H7*/ "","led-bmc-ingraham0","led-rear-enc-id0","led-rear-enc-fault0","","","","", /*I0-I7*/ "","","","","","","bmc-secure-boot","", /*J0-J7*/ "","","","","","","","", /*K0-K7*/ "","","","","","","","", @@ -211,7 +211,7 @@ /*M0-M7*/ "","","","","","","","", /*N0-N7*/ "","","","","","","","", /*O0-O7*/ "","","","usb-power","","","","", - /*P0-P7*/ "","","","","pcieslot-power","","","", + /*P0-P7*/ "","","","","led-pcieslot-power","","","", /*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","", /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","", /*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3", @@ -1280,8 +1280,9 @@ #gpio-cells = <2>; gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "power-config-full-load", ""; + "", "", "", "", "", "", "P10_DCM0_PRES", "P10_DCM1_PRES", + "", "", "", "", "PRESENT_VRM_DCM0_N", "PRESENT_VRM_DCM1_N", + "power-config-full-load", ""; }; pca_pres2: pca9552@61 { diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-sbp1.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-sbp1.dts new file mode 100644 index 000000000000..8d98be3d5f2e --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-sbp1.dts @@ -0,0 +1,6086 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2024 IBM Corp. +/dts-v1/; +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/i2c/i2c.h> +#include "aspeed-g6.dtsi" + +/ { + model = "IBM SBP1"; + compatible = "ibm,sbp1-bmc", "aspeed,ast2600"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + label = "LED_BMC_READY"; + gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + retain-state-suspended; + panic-indicator; + }; + + led-id-tpm { + label = "LED_ID_TPM"; + gpios = <&smb_pex_vr_ctrl 12 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-bat { + label = "LED_ID_BAT"; + gpios = <&smb_pex_vr_ctrl 16 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-mgmt-port2 { + label = "LED_ID_MGMT_PORT2"; + gpios = <&smb_pex_vr_ctrl 17 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-mgmt-port1 { + label = "LED_ID_MGMT_PORT1"; + gpios = <&smb_pex_vr_ctrl 18 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-nic1-port1 { + label = "LED_ID_NIC1_PORT1"; + gpios = <&smb_pex_vr_ctrl 22 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-nic1-port2 { + label = "LED_ID_NIC1_PORT2"; + gpios = <&smb_pex_vr_ctrl 23 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-nic2-port1 { + label = "LED_ID_NIC2_PORT1"; + gpios = <&smb_pex_vr_ctrl 24 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-nic2-port2 { + label = "LED_ID_NIC2_PORT2"; + gpios = <&smb_pex_vr_ctrl 25 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-m2-ssd2 { + label = "LED_ID_M2_SSD2"; + gpios = <&smb_pex_vr_ctrl 36 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-m2-ssd1 { + label = "LED_ID_M2_SSD1"; + gpios = <&smb_pex_vr_ctrl 37 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dwr-frnt-p { + label = "LED_ID_DWR_FRNT_P"; + gpios = <&smb_svc_pex_cpu3_led 37 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_BLUE>; + + default-state = "on"; + retain-state-suspended; + retain-state-shutdown; + }; + + led-pwr-dwr-frnt { + label = "LED_PWR_DWR_FRNT"; + gpios = <&smb_svc_pex_cpu3_led 36 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_GREEN>; + + retain-state-suspended; + retain-state-shutdown; + }; + + led-pwr-dwr-back { + label = "LED_PWR_DWR_BACK"; + gpios = <&smb_pex_vr_ctrl 34 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_GREEN>; + + retain-state-suspended; + retain-state-shutdown; + }; + + led-id-dwr-back-p { + label = "LED_ID_DWR_BACK_P"; + gpios = <&smb_pex_vr_ctrl 35 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_BLUE>; + + default-state = "on"; + retain-state-suspended; + retain-state-shutdown; + }; + + led-id-cpu0 { + label = "LED_ID_CPU0"; + gpios = <&smb_svc_pex_cpu0_led 39 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-cpu1 { + label = "LED_ID_CPU1"; + gpios = <&smb_svc_pex_cpu1_led 39 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-cpu2 { + label = "LED_ID_CPU2"; + gpios = <&smb_svc_pex_cpu2_led 39 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-cpu3 { + label = "LED_ID_CPU3"; + gpios = <&smb_svc_pex_cpu3_led 39 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0e2 { + label = "LED_ID_DIMM_C0E2"; + gpios = <&smb_svc_pex_cpu0_led 20 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0e1 { + label = "LED_ID_DIMM_C0E1"; + gpios = <&smb_svc_pex_cpu0_led 21 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0f2 { + label = "LED_ID_DIMM_C0F2"; + gpios = <&smb_svc_pex_cpu0_led 22 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0f1 { + label = "LED_ID_DIMM_C0F1"; + gpios = <&smb_svc_pex_cpu0_led 23 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0g2 { + label = "LED_ID_DIMM_C0G2"; + gpios = <&smb_svc_pex_cpu0_led 24 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0g1 { + label = "LED_ID_DIMM_C0G1"; + gpios = <&smb_svc_pex_cpu0_led 25 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0h2 { + label = "LED_ID_DIMM_C0H2"; + gpios = <&smb_svc_pex_cpu0_led 26 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0h1 { + label = "LED_ID_DIMM_C0H1"; + gpios = <&smb_svc_pex_cpu0_led 27 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0a2 { + label = "LED_ID_DIMM_C0A2"; + gpios = <&smb_svc_pex_cpu0_led 28 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0a1 { + label = "LED_ID_DIMM_C0A1"; + gpios = <&smb_svc_pex_cpu0_led 29 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0b2 { + label = "LED_ID_DIMM_C0B2"; + gpios = <&smb_svc_pex_cpu0_led 30 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0b1 { + label = "LED_ID_DIMM_C0B1"; + gpios = <&smb_svc_pex_cpu0_led 31 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0c2 { + label = "LED_ID_DIMM_C0C2"; + gpios = <&smb_svc_pex_cpu0_led 32 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0c1 { + label = "LED_ID_DIMM_C0C1"; + gpios = <&smb_svc_pex_cpu0_led 33 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0d2 { + label = "LED_ID_DIMM_C0D2"; + gpios = <&smb_svc_pex_cpu0_led 34 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c0d1 { + label = "LED_ID_DIMM_C0D1"; + gpios = <&smb_svc_pex_cpu0_led 35 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1e2 { + label = "LED_ID_DIMM_C1E2"; + gpios = <&smb_svc_pex_cpu1_led 20 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1e1 { + label = "LED_ID_DIMM_C1E1"; + gpios = <&smb_svc_pex_cpu1_led 21 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1f2 { + label = "LED_ID_DIMM_C1F2"; + gpios = <&smb_svc_pex_cpu1_led 22 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1f1 { + label = "LED_ID_DIMM_C1F1"; + gpios = <&smb_svc_pex_cpu1_led 23 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1g2 { + label = "LED_ID_DIMM_C1G2"; + gpios = <&smb_svc_pex_cpu1_led 24 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1g1 { + label = "LED_ID_DIMM_C1G1"; + gpios = <&smb_svc_pex_cpu1_led 25 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1h2 { + label = "LED_ID_DIMM_C1H2"; + gpios = <&smb_svc_pex_cpu1_led 26 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1h1 { + label = "LED_ID_DIMM_C1H1"; + gpios = <&smb_svc_pex_cpu1_led 27 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1a2 { + label = "LED_ID_DIMM_C1A2"; + gpios = <&smb_svc_pex_cpu1_led 28 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1a1 { + label = "LED_ID_DIMM_C1A1"; + gpios = <&smb_svc_pex_cpu1_led 29 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1b2 { + label = "LED_ID_DIMM_C1B2"; + gpios = <&smb_svc_pex_cpu1_led 30 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1b1 { + label = "LED_ID_DIMM_C1B1"; + gpios = <&smb_svc_pex_cpu1_led 31 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1c2 { + label = "LED_ID_DIMM_C1C2"; + gpios = <&smb_svc_pex_cpu1_led 32 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1c1 { + label = "LED_ID_DIMM_C1C1"; + gpios = <&smb_svc_pex_cpu1_led 33 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1d2 { + label = "LED_ID_DIMM_C1D2"; + gpios = <&smb_svc_pex_cpu1_led 34 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c1d1 { + label = "LED_ID_DIMM_C1D1"; + gpios = <&smb_svc_pex_cpu1_led 35 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2e2 { + label = "LED_ID_DIMM_C2E2"; + gpios = <&smb_svc_pex_cpu2_led 20 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2e1 { + label = "LED_ID_DIMM_C2E1"; + gpios = <&smb_svc_pex_cpu2_led 21 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2f2 { + label = "LED_ID_DIMM_C2F2"; + gpios = <&smb_svc_pex_cpu2_led 22 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2f1 { + label = "LED_ID_DIMM_C2F1"; + gpios = <&smb_svc_pex_cpu2_led 23 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2g2 { + label = "LED_ID_DIMM_C2G2"; + gpios = <&smb_svc_pex_cpu2_led 24 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2g1 { + label = "LED_ID_DIMM_C2G1"; + gpios = <&smb_svc_pex_cpu2_led 25 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2h2 { + label = "LED_ID_DIMM_C2H2"; + gpios = <&smb_svc_pex_cpu2_led 26 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2h1 { + label = "LED_ID_DIMM_C2H1"; + gpios = <&smb_svc_pex_cpu2_led 27 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2a2 { + label = "LED_ID_DIMM_C2A2"; + gpios = <&smb_svc_pex_cpu2_led 28 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2a1 { + label = "LED_ID_DIMM_C2A1"; + gpios = <&smb_svc_pex_cpu2_led 29 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2b2 { + label = "LED_ID_DIMM_C2B2"; + gpios = <&smb_svc_pex_cpu2_led 30 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2b1 { + label = "LED_ID_DIMM_C2B1"; + gpios = <&smb_svc_pex_cpu2_led 31 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2c2 { + label = "LED_ID_DIMM_C2C2"; + gpios = <&smb_svc_pex_cpu2_led 32 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2c1 { + label = "LED_ID_DIMM_C2C1"; + gpios = <&smb_svc_pex_cpu2_led 33 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2d2 { + label = "LED_ID_DIMM_C2D2"; + gpios = <&smb_svc_pex_cpu2_led 34 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c2d1 { + label = "LED_ID_DIMM_C2D1"; + gpios = <&smb_svc_pex_cpu2_led 35 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3e2 { + label = "LED_ID_DIMM_C3E2"; + gpios = <&smb_svc_pex_cpu3_led 20 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3e1 { + label = "LED_ID_DIMM_C3E1"; + gpios = <&smb_svc_pex_cpu3_led 21 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3f2 { + label = "LED_ID_DIMM_C3F2"; + gpios = <&smb_svc_pex_cpu3_led 22 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3f1 { + label = "LED_ID_DIMM_C3F1"; + gpios = <&smb_svc_pex_cpu3_led 23 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3g2 { + label = "LED_ID_DIMM_C3G2"; + gpios = <&smb_svc_pex_cpu3_led 24 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3g1 { + label = "LED_ID_DIMM_C3G1"; + gpios = <&smb_svc_pex_cpu3_led 25 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3h2 { + label = "LED_ID_DIMM_C3H2"; + gpios = <&smb_svc_pex_cpu3_led 26 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3h1 { + label = "LED_ID_DIMM_C3H1"; + gpios = <&smb_svc_pex_cpu3_led 27 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3a2 { + label = "LED_ID_DIMM_C3A2"; + gpios = <&smb_svc_pex_cpu3_led 28 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3a1 { + label = "LED_ID_DIMM_C3A1"; + gpios = <&smb_svc_pex_cpu3_led 29 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3b2 { + label = "LED_ID_DIMM_C3B2"; + gpios = <&smb_svc_pex_cpu3_led 30 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3b1 { + label = "LED_ID_DIMM_C3B1"; + gpios = <&smb_svc_pex_cpu3_led 31 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3c2 { + label = "LED_ID_DIMM_C3C2"; + gpios = <&smb_svc_pex_cpu3_led 32 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3c1 { + label = "LED_ID_DIMM_C3C1"; + gpios = <&smb_svc_pex_cpu3_led 33 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3d2 { + label = "LED_ID_DIMM_C3D2"; + gpios = <&smb_svc_pex_cpu3_led 34 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-c3d1 { + label = "LED_ID_DIMM_C3D1"; + gpios = <&smb_svc_pex_cpu3_led 35 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd01 { + label = "LED_ID_RSSD01"; + gpios = <&smb_svc_pex_rssd01_16 0 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd02 { + label = "LED_ID_RSSD02"; + gpios = <&smb_svc_pex_rssd01_16 1 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd03 { + label = "LED_ID_RSSD03"; + gpios = <&smb_svc_pex_rssd01_16 2 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd04 { + label = "LED_ID_RSSD04"; + gpios = <&smb_svc_pex_rssd01_16 3 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd05 { + label = "LED_ID_RSSD05"; + gpios = <&smb_svc_pex_rssd01_16 4 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd06 { + label = "LED_ID_RSSD06"; + gpios = <&smb_svc_pex_rssd01_16 5 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd07 { + label = "LED_ID_RSSD07"; + gpios = <&smb_svc_pex_rssd01_16 6 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd08 { + label = "LED_ID_RSSD08"; + gpios = <&smb_svc_pex_rssd01_16 7 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd09 { + label = "LED_ID_RSSD09"; + gpios = <&smb_svc_pex_rssd01_16 8 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd10 { + label = "LED_ID_RSSD10"; + gpios = <&smb_svc_pex_rssd01_16 9 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd11 { + label = "LED_ID_RSSD11"; + gpios = <&smb_svc_pex_rssd01_16 10 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd12 { + label = "LED_ID_RSSD12"; + gpios = <&smb_svc_pex_rssd01_16 11 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd13 { + label = "LED_ID_RSSD13"; + gpios = <&smb_svc_pex_rssd01_16 12 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd14 { + label = "LED_ID_RSSD14"; + gpios = <&smb_svc_pex_rssd01_16 13 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd15 { + label = "LED_ID_RSSD15"; + gpios = <&smb_svc_pex_rssd01_16 14 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd16 { + label = "LED_ID_RSSD16"; + gpios = <&smb_svc_pex_rssd01_16 15 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd17 { + label = "LED_ID_RSSD17"; + gpios = <&smb_svc_pex_rssd17_32 0 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd18 { + label = "LED_ID_RSSD18"; + gpios = <&smb_svc_pex_rssd17_32 1 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd19 { + label = "LED_ID_RSSD19"; + gpios = <&smb_svc_pex_rssd17_32 2 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd20 { + label = "LED_ID_RSSD20"; + gpios = <&smb_svc_pex_rssd17_32 3 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd21 { + label = "LED_ID_RSSD21"; + gpios = <&smb_svc_pex_rssd17_32 4 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd22 { + label = "LED_ID_RSSD22"; + gpios = <&smb_svc_pex_rssd17_32 5 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd23 { + label = "LED_ID_RSSD23"; + gpios = <&smb_svc_pex_rssd17_32 6 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd24 { + label = "LED_ID_RSSD24"; + gpios = <&smb_svc_pex_rssd17_32 7 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd25 { + label = "LED_ID_RSSD25"; + gpios = <&smb_svc_pex_rssd17_32 8 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd26 { + label = "LED_ID_RSSD26"; + gpios = <&smb_svc_pex_rssd17_32 9 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd27 { + label = "LED_ID_RSSD27"; + gpios = <&smb_svc_pex_rssd17_32 10 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd28 { + label = "LED_ID_RSSD28"; + gpios = <&smb_svc_pex_rssd17_32 11 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd29 { + label = "LED_ID_RSSD29"; + gpios = <&smb_svc_pex_rssd17_32 12 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd30 { + label = "LED_ID_RSSD30"; + gpios = <&smb_svc_pex_rssd17_32 13 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd31 { + label = "LED_ID_RSSD31"; + gpios = <&smb_svc_pex_rssd17_32 14 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-dimm-rssd32 { + label = "LED_ID_RSSD32"; + gpios = <&smb_svc_pex_rssd17_32 15 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-fan-asm01 { + label = "LED_ID_FAN_ASM01"; + gpios = <&smb_svc_pex_rssd01_16 32 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-fan-asm02 { + label = "LED_ID_FAN_ASM02"; + gpios = <&smb_svc_pex_rssd01_16 33 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-fan-asm03 { + label = "LED_ID_FAN_ASM03"; + gpios = <&smb_svc_pex_rssd01_16 34 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-fan-asm04 { + label = "LED_ID_FAN_ASM04"; + gpios = <&smb_svc_pex_rssd01_16 35 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-fan-asm05 { + label = "LED_ID_FAN_ASM05"; + gpios = <&smb_svc_pex_rssd01_16 36 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-fan-asm06 { + label = "LED_ID_FAN_ASM06"; + gpios = <&smb_svc_pex_rssd01_16 37 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-fan-asm07 { + label = "LED_ID_FAN_ASM07"; + gpios = <&smb_svc_pex_rssd17_32 32 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-fan-asm08 { + label = "LED_ID_FAN_ASM08"; + gpios = <&smb_svc_pex_rssd17_32 33 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-fan-asm09 { + label = "LED_ID_FAN_ASM09"; + gpios = <&smb_svc_pex_rssd17_32 34 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-fan-asm10 { + label = "LED_ID_FAN_ASM10"; + gpios = <&smb_svc_pex_rssd17_32 35 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-fan-asm11 { + label = "LED_ID_FAN_ASM11"; + gpios = <&smb_svc_pex_rssd17_32 36 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + + led-id-fan-asm12 { + label = "LED_ID_FAN_ASM12"; + gpios = <&smb_svc_pex_rssd17_32 37 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_YELLOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&p12v_vd 0>, <&p5v_aux_vd 0>, <&p5v_bmc_aux_vd 0>, <&p3v3_aux_vd 0>, + <&p3v3_bmc_aux_vd 0>, <&p1v8_bmc_aux_vd 0>, <&adc1 4>, <&adc0 2>, <&adc1 0>, + <&p2V5_aux_vd 0>, <&p3v3_rtc_vd 0>; + }; + + p12v_vd: voltage-divider1 { + compatible = "voltage-divider"; + io-channels = <&adc1 3>; + #io-channel-cells = <1>; + + /* + * Scale the system voltage by 1127/127 to fit the ADC range. + * Use small nominator to prevent integer overflow. + */ + output-ohms = <15>; + full-ohms = <133>; + }; + + p5v_aux_vd: voltage-divider2 { + compatible = "voltage-divider"; + io-channels = <&adc1 5>; + #io-channel-cells = <1>; + + /* + * Scale the system voltage by 1365/365 to fit the ADC range. + * Use small nominator to prevent integer overflow. + */ + output-ohms = <50>; + full-ohms = <187>; + }; + + p5v_bmc_aux_vd: voltage-divider3 { + compatible = "voltage-divider"; + io-channels = <&adc0 3>; + #io-channel-cells = <1>; + + /* + * Scale the system voltage by 1365/365 to fit the ADC range. + * Use small nominator to prevent integer overflow. + */ + output-ohms = <50>; + full-ohms = <187>; + }; + + p3v3_aux_vd: voltage-divider4 { + compatible = "voltage-divider"; + io-channels = <&adc1 2>; + #io-channel-cells = <1>; + + /* + * Scale the system voltage by 1698/698 to fit the ADC range. + * Use small nominator to prevent integer overflow. + */ + output-ohms = <14>; + full-ohms = <34>; + }; + + p3v3_bmc_aux_vd: voltage-divider5 { + compatible = "voltage-divider"; + io-channels = <&adc0 7>; + #io-channel-cells = <1>; + + /* + * Scale the system voltage by 1698/698 to fit the ADC range. + * Use small nominator to prevent integer overflow. + */ + output-ohms = <14>; + full-ohms = <34>; + }; + + p1v8_bmc_aux_vd: voltage-divider6 { + compatible = "voltage-divider"; + io-channels = <&adc0 6>; + #io-channel-cells = <1>; + + /* + * Scale the system voltage by 4000/3000 to fit the ADC range. + * Use small nominator to prevent integer overflow. + */ + output-ohms = <3>; + full-ohms = <4>; + }; + + p2V5_aux_vd: voltage-divider7 { + compatible = "voltage-divider"; + io-channels = <&adc1 1>; + #io-channel-cells = <1>; + + /* + * Scale the system voltage by 2100/1100 to fit the ADC range. + * Use small nominator to prevent integer overflow. + */ + output-ohms = <11>; + full-ohms = <21>; + }; + + p3v3_rtc_vd: voltage-divider8 { + compatible = "voltage-divider"; + io-channels = <&adc1 7>; + #io-channel-cells = <1>; + + /* + * Scale the system voltage by 231000/100000 to fit the ADC range. + * Use small nominator to prevent integer overflow. + */ + output-ohms = <100>; + full-ohms = <231>; + }; + + thermistor0: thermistor-0 { + compatible = "epcos,b57891s0103"; + pullup-uv = <3300000>; + pullup-ohm = <10000>; + pulldown-ohm = <0>; + io-channels = <&adc0 0>; + #thermal-sensor-cells = <0>; + }; + + thermistor1: thermistor-1 { + compatible = "epcos,b57891s0103"; + pullup-uv = <3300000>; + pullup-ohm = <10000>; + pulldown-ohm = <0>; + io-channels = <&adc0 1>; + #thermal-sensor-cells = <0>; + }; + + thermistor2: thermistor-2 { + compatible = "epcos,b57891s0103"; + pullup-uv = <3300000>; + pullup-ohm = <10000>; + pulldown-ohm = <0>; + io-channels = <&adc0 4>; + #thermal-sensor-cells = <0>; + }; + + thermistor3: thermistor-3 { + compatible = "epcos,b57891s0103"; + pullup-uv = <3300000>; + pullup-ohm = <10000>; + pulldown-ohm = <0>; + io-channels = <&adc0 5>; + #thermal-sensor-cells = <0>; + }; + + p12v: fixedregulator-p12v { + compatible = "regulator-fixed"; + regulator-name = "p12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + p3v3_bmc_aux: fixedregulator-p3v3-bmc-aux { + compatible = "regulator-fixed"; + regulator-name = "p3v3_bmc_aux"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + p1v8_bmc_aux: fixedregulator-p1v8-bmc-aux { + compatible = "regulator-fixed"; + regulator-name = "p1v8_bmc_aux"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + p1v2_bmc_aux: fixedregulator-p1v2-bmc-aux { + compatible = "regulator-fixed"; + regulator-name = "p1v2_bmc_aux"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + p12v-a-consumer { + compatible = "regulator-output"; + vout-supply = <&p12v_a>; + }; + + p12v-b-consumer { + compatible = "regulator-output"; + vout-supply = <&p12v_b>; + }; + + p12v-c-consumer { + compatible = "regulator-output"; + vout-supply = <&p12v_c>; + }; + + p12v-d-consumer { + compatible = "regulator-output"; + vout-supply = <&p12v_d>; + }; + + pvccinfaon-cpu0-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccinfaon_cpu0>; + }; + + pvccfa-ehv-cpu0-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccfa_ehv_cpu0>; + }; + + pvnn-main-cpu0-consumer { + compatible = "regulator-output"; + vout-supply = <&pvnn_main_cpu0>; + }; + + pvccin-cpu0-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccin_cpu0>; + }; + + pvccfa-ehv-fivra-cpu0-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccfa_ehv_fivra_cpu0>; + }; + + pvccd-hv-cpu0-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccd_hv_cpu0>; + }; + + pvpp-hbm-cpu0-consumer { + compatible = "regulator-output"; + vout-supply = <&pvpp_hbm_cpu0>; + }; + + pvccinfaon-cpu1-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccinfaon_cpu1>; + }; + + pvccfa-ehv-cpu1-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccfa_ehv_cpu1>; + }; + + pvnn-main-cpu1-consumer { + compatible = "regulator-output"; + vout-supply = <&pvnn_main_cpu1>; + }; + + pvccin-cpu1-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccin_cpu1>; + }; + + pvccfa-ehv-fivra-cpu1-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccfa_ehv_fivra_cpu1>; + }; + + pvccd-hv-cpu1-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccd_hv_cpu1>; + }; + + pvpp-hbm-cpu1-consumer { + compatible = "regulator-output"; + vout-supply = <&pvpp_hbm_cpu1>; + }; + + pvccinfaon-cpu2-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccinfaon_cpu2>; + }; + + pvccfa-ehv-cpu2-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccfa_ehv_cpu2>; + }; + + pvnn-main-cpu2-consumer { + compatible = "regulator-output"; + vout-supply = <&pvnn_main_cpu2>; + }; + + pvccin-cpu2-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccin_cpu2>; + }; + + pvccfa-ehv-fivra-cpu2-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccfa_ehv_fivra_cpu2>; + }; + + pvccd-hv-cpu2-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccd_hv_cpu2>; + }; + + pvpp-hbm-cpu2-consumer { + compatible = "regulator-output"; + vout-supply = <&pvpp_hbm_cpu2>; + }; + + pvccinfaon-cpu3-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccinfaon_cpu3>; + }; + + pvccfa-ehv-cpu3-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccfa_ehv_cpu3>; + }; + + pvnn-main-cpu3-consumer { + compatible = "regulator-output"; + vout-supply = <&pvnn_main_cpu3>; + }; + + pvccin-cpu3-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccin_cpu3>; + }; + + pvccfa-ehv-fivra-cpu3-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccfa_ehv_fivra_cpu3>; + }; + + pvccd-hv-cpu3-consumer { + compatible = "regulator-output"; + vout-supply = <&pvccd_hv_cpu3>; + }; + + pvpp-hbm-cpu3-consumer { + compatible = "regulator-output"; + vout-supply = <&pvpp_hbm_cpu3>; + }; + + p1v05-pch-aux-consumer { + compatible = "regulator-output"; + vout-supply = <&p1v05_pch_aux>; + }; + + p1v8-pch-aux-consumer { + compatible = "regulator-output"; + vout-supply = <&p1v8_pch_aux>; + }; + + p3v3-pch-consumer { + compatible = "regulator-output"; + vout-supply = <&p3v3_pch>; + }; + + p5v-consumer { + compatible = "regulator-output"; + vout-supply = <&p5v>; + }; + + smb-m2-ssb-ssd2 { + compatible = "regulator-output"; + vout-supply = <&sw0_smb_m2_ssb_ssd2>; + }; + + smb-m2-ssb-ssd1 { + compatible = "regulator-output"; + vout-supply = <&sw0_smb_m2_ssb_ssd1>; + }; + + ssb-rssd01-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd01>; + }; + + ssb-rssd01-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd01>; + }; + + ssb-rssd02-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd02>; + }; + + ssb-rssd02-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd02>; + }; + + ssb-rssd03-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd03>; + }; + + ssb-rssd03-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd03>; + }; + + ssb-rssd04-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd04>; + }; + + ssb-rssd04-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd04>; + }; + + ssb-rssd05-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd05>; + }; + + ssb-rssd05-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd05>; + }; + + ssb-rssd06-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd06>; + }; + + ssb-rssd06-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd06>; + }; + + ssb-rssd07-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd07>; + }; + + ssb-rssd07-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd07>; + }; + + ssb-rssd08-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd08>; + }; + + ssb-rssd08-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd08>; + }; + + ssb-rssd09-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd09>; + }; + + ssb-rssd09-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd09>; + }; + + ssb-rssd10-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd10>; + }; + + ssb-rssd10-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd10>; + }; + + ssb-rssd11-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd11>; + }; + + ssb-rssd11-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd11>; + }; + + ssb-rssd12-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd12>; + }; + + ssb-rssd12-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd12>; + }; + + ssb-rssd13-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd13>; + }; + + ssb-rssd13-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd13>; + }; + + ssb-rssd14-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd14>; + }; + + ssb-rssd14-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd14>; + }; + + ssb-rssd15-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd15>; + }; + + ssb-rssd15-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd15>; + }; + + ssb-rssd16-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd16>; + }; + + ssb-rssd16-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd16>; + }; + + ssb-rssd17-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd17>; + }; + + ssb-rssd17-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd17>; + }; + + ssb-rssd18-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd18>; + }; + + ssb-rssd18-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd18>; + }; + + ssb-rssd19-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd19>; + }; + + ssb-rssd19-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd19>; + }; + + ssb-rssd20-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd20>; + }; + + ssb-rssd20-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd20>; + }; + + ssb-rssd21-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd21>; + }; + + ssb-rssd21-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd21>; + }; + + ssb-rssd22-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd22>; + }; + + ssb-rssd22-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd22>; + }; + + ssb-rssd23-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd23>; + }; + + ssb-rssd23-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd23>; + }; + + ssb-rssd24-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd24>; + }; + + ssb-rssd24-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd24>; + }; + + ssb-rssd25-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd25>; + }; + + ssb-rssd25-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd25>; + }; + + ssb-rssd26-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd26>; + }; + + ssb-rssd26-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd26>; + }; + + ssb-rssd27-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd27>; + }; + + ssb-rssd27-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd27>; + }; + + ssb-rssd28-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd28>; + }; + + ssb-rssd28-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd28>; + }; + + ssb-rssd29-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd29>; + }; + + ssb-rssd29-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd29>; + }; + + ssb-rssd30-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd30>; + }; + + ssb-rssd30-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd30>; + }; + + ssb-rssd31-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd31>; + }; + + ssb-rssd31-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd31>; + }; + + ssb-rssd32-sw0 { + compatible = "regulator-output"; + vout-supply = <&sw0_ssb_rssd32>; + }; + + ssb-rssd32-sw1 { + compatible = "regulator-output"; + vout-supply = <&sw1_ssb_rssd32>; + }; + + p3v3-nic-consumer { + compatible = "regulator-output"; + vout-supply = <&p3v3_nic>; + }; + + p1v8-nic-consumer { + compatible = "regulator-output"; + vout-supply = <&p1v8_nic>; + }; + + p1v2-nic-consumer { + compatible = "regulator-output"; + vout-supply = <&p1v2_nic>; + }; + + pvcore-nic1-consumer { + compatible = "regulator-output"; + vout-supply = <&pvcore_nic1>; + }; + + pvcore-nic2-consumer { + compatible = "regulator-output"; + vout-supply = <&pvcore_nic2>; + }; +}; + +&peci0 { + status = "okay"; +}; + +&vuart1 { + status = "okay"; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>, <0x81>; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; +#include "openbmc-flash-layout-64.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + status = "disabled"; +}; + +&gpio1 { + status = "disabled"; +}; + +&video { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default>; +}; + +&mdio2 { + status = "okay"; + + ethphy2: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio0 ASPEED_GPIO(V, 7) GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; +}; + +&mdio3 { + status = "okay"; + + ethphy3: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio0 ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; +}; + +&mac2 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; +}; + +&mac3 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; +}; + +&adc0 { + status = "okay"; + vref-supply = <&p1v8_bmc_aux>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default>; +}; + +&adc1 { + status = "okay"; + vref-supply = <&p1v8_bmc_aux>; + aspeed,battery-sensing; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc15_default>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&gpio0 { + status = "okay"; + gpio-line-names = + /* A0 - A7 */ + "", "", "", "", "", "", "", "", + /* B0 - B7 */ + "", "", "FM_ADR_TRIGGER_R_N", "RST_PLTRST_BUF_N", "BMC_TPM_RESET_N", "BMC_TPM_IRQ_N", + "PCH_TPM_RESET_N", "PCH_TPM_IRQ_N", + /* C0 - C7 */ + "", "", "", "", "", "", "", "", + /* D0 - D7 */ + "", "", "", "", "", "", "", "", + /* E0 - E7 */ + "", "", "", "", "", "", "", "", + /* F0 - F7 */ + "", "", "", "BMC_MUX_CPU1_RST_INT_N", "BMC_MUX_CPU2_RST_INT_N", "", "", "", + /* G0 - G7 */ + "FM_SSD_CLK_DRVR1_EN", "FM_CK440Q_DEV_EN", "BMC_MAC1_RESET_N", "FM_DB2000_DEV_EN", + "FM_CPU_RMCA_LVT3_N", "FM_CPU_CATERR_LVT3_N", "FM_DBP_PRESENT_N", "", + /* H0 - H7 */ + "SMB_SVC_PEX_RSSD17_32_INT", "LED_BMC_RDY", "RST_DBP_N", "", "", "", "", "", + /* I0 - I7 */ + "JTAG_MUX_MODE_SEL", "JTAG_MUX_TRANS_ENBL", "JTAG_MUX_LSP_SEL5", "JTAG_MUX_MSTR_SEL", + "JTAG_MUX_LSP_SEL3", "", "JTAG_MUX_ENBL_N", "JTAG_MUX_RST_N", + /* J0 - J7 */ + "", "", "", "", "", "", "", "", + /* K0 - K7 */ + "", "", "", "", "", "", "", "", + /* L0 - L7 */ + "", "", "", "", "RST_RTCRST_N", "RST_SRTCRST_N", "", "", + /* M0 - M7 */ + "BMC_UART1_CTS_N", "BMC_UART1_DCD_N", "BMC_UART1_DSR_N", "BMC_UART1_RI_N", + "BMC_UART1_DTR_N", "BMC_UART1_RTS_N", "", "", + /* N0 - N7 */ + "IRQ_BMC_PCH_NMI", "", "FM_PCH_BMC_THERMTRIP_N", "FM_BIOS_POST_CMPLT_N", "RST_PLTRST_N", + "FM_FLASH_SEC_OVRD", "FM_SMI_ACTIVE_N", "PWRGD_DBP", + /* O0 - O7 */ + "CATERR_CPU2_EN", "H_LVT1_THERMTRIP_N", "CATERR_CPU3_EN", "SMB_SVC_PEX_CPU0_LED_INT", + "H_LVT1_MEMTRIP_N", "", "CATERR_CPU1_EN", "FM_PCH_ADR_COMPLETE_N", + /* P0 - P7 */ + "PWRGD_SYS_PWROK", "PWRGD_PCH_PWROK", "BMC_MUX_CPU3_RST_INT_N", "BMC_MUX_SVC_RSSD_INT", + "FM_SLPS4_N", "IRQ_SML0_ALERT_N", "FM_SLPS3_N", "LED_BMC_HB", + /* Q0 - Q7 */ + "", "PEX_BMC_RST", "PEX_VR_CTRL_RST", "PEX_NIC_RST", "PEX_CPU0_LED_RST", "PEX_CPU1_LED_RST", + "PEX_CPU2_LED_RST", "PEX_CPU3_LED_RST", + /* R0 - R7 */ + "BMC_MUX_FANSSB_RSSD17_32_RST_INT_N", "BMC_MUX_FANPWM_RSSD01_16_RST_INT_N", + "BMC_MUX_SVC_VR_RST_INT_N", "BMC_MUX_NIC_RST_INT_N", "BMC_MUX_SVC_EXP_RST_INT_N", + "FM_CPU_ERR2_LVT3_N", "BMC_MUX_CPU0_RST_INT_N", "BMC_MUX_M2_RST_INT_N", + /* S0 - S7 */ + "SMB_SVC_PEX_RSSD01_16_INT", "RST_PCH_RSMRST_R_N", "", "", "BMC_ROT_FPGA_RESET_N", + "FM_SSD_CLK_DRVR0_EN", "", "", + /* T0 - T7 */ + "", "", "", "", "", "", "", "", + /* U0 - U7 */ + "", "", "", "", "", "", "", "", + /* V0 - V7 */ + "BMC_PEX_IRQ_INT", "RTC_BATT_TEST", "SMB_PEX_VR_CTRL_INT", "SMB_SVC_PEX_CPU3_LED_INT", + "PWRGD_CPUPWRGD", "SMB_SVC_PEX_CPU2_LED_INT", "SMB_SVC_PEX_CPU1_LED_INT", + "BMC_MAC0_RESET_N", + /* W0 - W7 */ + "", "", "", "", "", "", "", "", + /* X0 - X7 */ + "", "", "", "", "", "", "", "", + /* Y0 - Y7 */ + "FM_THROTTLE_N", "FM_PASSWORD_CLEAR_N", "H_LVT3_CATERR_DLY_N", "FM_CPU_OL_INT_R_N", "", "", + "", "", + /* Z0 - Z7 */ + "FM_CPU_ERR0_LVT3_N", "FM_CPU_ERR1_LVT3_N", "BMC_MUX_VR_PCH_CPU_RST_INT_N", + "JTAG_MUX_LSP_SEL1", "", "JTAG_MUX_LSP_SEL4", "JTAG_MUX_LSP_SEL2", ""; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_unbiased_default>; +}; + +&pinctrl { + pinctrl_gpio0_unbiased_default: gpio_default { + pins = "AB15", "AD14", "R23", "A18", "AD24", "AD15", "AE14", "AC15", "U25", "AA24", + "V24", "W26", "AA23", "V26", "U24", "V25", "AE15", "C15", "F15"; + bias-disable; + }; +}; + +&i2c1 { + status = "okay"; + + bmc_mux_nic: mux@77 { + compatible = "maxim,max7357"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio0 ASPEED_GPIO(R, 3) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + smb_pex_nic: pinctrl@20 { + compatible = "cypress,cy8c9540"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&smb_pex_vr_ctrl>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + vdd-supply = <&p3v3_aux>; + reset-gpios = <&gpio0 ASPEED_GPIO(Q, 3) GPIO_ACTIVE_HIGH>; + + gpio-reserved-ranges = <19 1>, <22 6>, <30 6>, <38 2>; + + gpio-line-names = + /* GPORT0 */ + "IRQ_NIC2_OVT_WRNG", "FM_NIC2_ALLSTANDBY_N", "IRQ_NIC2_OVT_SHTDN", + "SMB_VR_PVCORE_NIC2_ALERT_N", "FM_NIC2_PERST1_N", + "SMB_NIC2_ALERT_N", "FM_NIC2_PERST3_N", "FM_NIC2_PERST2_N", + /* GPORT1 */ + "FM_NIC1_RST_N", "FM_NIC1_PERST0_N", "FM_NIC1_PERST2_N", + "FM_NIC1_PERST3_N", "SMB_NIC1_ALERT_N", "FM_NIC1_PERST1_N", + "SMB_VR_PVCORE_NIC1_ALERT_N", "IRQ_NIC1_OVT_SHTDN", + /* GPORT2 */ + "SMB_VR_P3V3_NIC_ALERT_N", "FM_NIC2_FLASH_PRSNT", + "FM_NIC1_FLASH_PRSNT", "", + /* GPORT3 */ + "FM_NIC2_PERST0_N", "FM_NIC2_RST_N", "", "", "", "", "", "", + /* GPORT4 */ + "FM_NIC1_ALLSTANDBY_N", "IRQ_NIC1_OVT_WRNG", "", "", "", "", "", "", + /* GPORT5 */ + "SMB_VR_P1V8_NIC_ALERT_N", "SMB_VR_P1V2_NIC_ALERT_N", "", ""; + + pinctrl-0 = <&U62160_pins>; + pinctrl-names = "default"; + U62160_pins: cfg-pins { + pins = "gp03", "gp16", "gp20", "gp50", "gp51"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pvcore_nic2: ir38263-pvcore-nic2@40 { + compatible = "infineon,ir38263"; + reg = <0x40>; + + regulator-name = "pvcore_nic2"; + regulator-enable-ramp-delay = <2000>; + vin-supply = <&p12v>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + pvcore_nic1: ir38263-pvcore-nic1@40 { + compatible = "infineon,ir38263"; + reg = <0x40>; + + regulator-name = "pvcore_nic1"; + regulator-enable-ramp-delay = <2000>; + vin-supply = <&p12v>; + }; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + p3v3_nic: ir38263-p3v3-nic@40 { + compatible = "infineon,ir38263"; + reg = <0x40>; + + regulator-name = "p3v3_nic"; + regulator-enable-ramp-delay = <2000>; + vin-supply = <&p12v>; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + p1v2_nic: ir38263-p1v2-nic@40 { + compatible = "infineon,ir38263"; + reg = <0x40>; + + regulator-name = "p1v2_nic"; + regulator-enable-ramp-delay = <2000>; + vin-supply = <&p12v>; + }; + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + p1v8_nic: ir38263-p1v8-nic@40 { + compatible = "infineon,ir38263"; + reg = <0x40>; + + regulator-name = "p1v8_nic"; + regulator-enable-ramp-delay = <2000>; + vin-supply = <&p12v>; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + i2cmux1: mux@77 { + compatible = "maxim,max7357"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio0 ASPEED_GPIO(R, 7) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + smb_m2_ssb_ssd1: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p3v3_aux>; + + interrupt-parent = <&smb_pex_vr_ctrl>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "m2_ssb_ssd1:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_smb_m2_ssb_ssd1: sw0 { + shunt-resistor-micro-ohms = <12000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <2800000>; + regulator-name = "p3v3_m2_ssd1"; + regulator-enable-ramp-delay = <10000>; + }; + }; + }; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + smb_m2_ssb_ssd2: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + + interrupt-parent = <&smb_pex_vr_ctrl>; + interrupts = <39 IRQ_TYPE_LEVEL_LOW>; + vss1-supply = <&p3v3_aux>; + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "m2_ssb_ssd2:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_smb_m2_ssb_ssd2: sw0 { + shunt-resistor-micro-ohms = <12000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <2800000>; + regulator-name = "p3v3_m2_ssd2"; + regulator-enable-ramp-delay = <10000>; + }; + }; + }; + }; + + i2c@6 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@7 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c4 { + status = "okay"; + multi-master; + bus-frequency = <1000000>; + + bmc-slave@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + + i2c-protocol; + }; +}; + +&i2c5 { + status = "okay"; + + i2cmux2: mux@77 { + compatible = "maxim,max7357"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio0 ASPEED_GPIO(Z, 2) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + p1v05_pch_aux: ir38263-p1v05-pch-aux@40 { + compatible = "infineon,ir38263"; + reg = <0x40>; + + regulator-name = "p1v05_pch_aux"; + regulator-enable-ramp-delay = <2000>; + vin-supply = <&p12v>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + p1v8_pch_aux: ir38060-p1v8-pch-aux@40 { + compatible = "infineon,ir38060"; + reg = <0x40>; + + regulator-name = "p1v8_pch_aux"; + regulator-enable-ramp-delay = <2000>; + vin-supply = <&p12v>; + }; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c14 { + status = "okay"; + + i2cmux13: mux@77 { + compatible = "maxim,max7357"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio0 ASPEED_GPIO(R, 6) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + smb_pex_cpu0_event: pinctrl@20 { + compatible = "cypress,cy8c9540"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&smb_pex_vr_ctrl>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + vdd-supply = <&p3v3_aux>; + reset-gpios = <&smb_svc_pex_cpu0_led 16 GPIO_ACTIVE_HIGH>; + + gpio-reserved-ranges = <14 2>, <21 1>, <25 3>, <33 1>; + + gpio-line-names = + /* GPORT0 */ + "PWRGD_CHD_CPU0", "PWRGD_CHC_CPU0", + "PWRGD_CHB_CPU0", "PWRGD_CHA_CPU0", + "PWRGD_CHE_CPU0", "PWRGD_CHF_CPU0", + "PWRGD_CHG_CPU0", "PWRGD_CHH_CPU0", + /* GPORT1 */ + "SMB_VR_PVPP_HBM_CPU0_ALERT_N", "SMB_VR_PVCCINFAON_CPU0_ALERT_N", + "SMB_VR_PVNN_MAIN_CPU0_ALERT_N", "SMB_VR_PVCCD_HV_CPU0_ALERT_N", + "SMB_VR_PVCCIN_CPU0_ALERT_N", "SEL_SMB_DIMM_CPU0", + "", "", + /* GPORT2 */ + "PWRGD_LVC3_CPU0_AB_DRAM_G", "PWRGD_LVC3_CPU0_CD_DRAM_G", + "PWRGD_LVC3_CPU0_EF_DRAM_G", "PWRGD_LVC3_CPU0_GH_DRAM_G", + /* GPORT3 */ + "FM_CPU0_DISABLE_COD_N", "", + "RST_LVC3_CPU0_RESET_N", "PWRGD_LVC3_CPU0_PWRGOOD", + "PWRGD_PLT_AUX_CPU0_LVT3", "", + "", "", + /* GPORT4 */ + "H_LVT3_CPU0_PROCHOT_N", "H_LVT3_CPU0_MEMHOT_IN_N", + "H_LVT3_CPU0_MEMHOT_OUT_N", "H_LVT3_CPU0_MEMTRIP_OUT_N", + "H_LVT3_CPU0_THERMTRIP_OUT_N", "", + "H_LVT3_CPU0_NMI", "FM_S3M_CPU0_CD_INIT_ERROR", + /* GPORT5 */ + "FM_CPU0_PKG_ID0", "FM_CPU0_PKG_ID1", + "FM_CPU0_PROC_ID0", "FM_CPU0_PROC_ID1"; + + pinctrl-0 = <&U62080_pins>; + pinctrl-names = "default"; + U62080_pins: cfg-pins { + pins = "gp10", "gp11", "gp12", "gp13", "gp14"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pvccinfaon-pvccfa-cpu0@58 { + compatible = "mps,mp2971"; + reg = <0x58>; + interrupt-parent = <&smb_pex_cpu0_event>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvccinfaon_cpu0: vout0 { + regulator-name = "pvccinfaon_cpu0"; + regulator-enable-ramp-delay = <200>; + }; + pvccfa_ehv_cpu0: vout1 { + regulator-name = "pvccfa_ehv_cpu0"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + tda38640-pvnn-main-cpu0@40 { + compatible = "infineon,tda38640"; + reg = <0x40>; + interrupt-parent = <&smb_pex_cpu0_event>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvnn_main_cpu0: vout { + regulator-name = "pvnn_main_cpu0"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + mp2973-pvccin-pvccfa-cpu0@58 { + compatible = "mps,mp2973"; + reg = <0x58>; + interrupt-parent = <&smb_pex_cpu0_event>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvccin_cpu0: vout0 { + regulator-name = "pvccin_cpu0"; + regulator-enable-ramp-delay = <200>; + }; + pvccfa_ehv_fivra_cpu0: vout1 { + regulator-name = "pvccfa_ehv_fivra_cpu0"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + tda38640-pvccd-hv-cpu0@40 { + compatible = "infineon,tda38640"; + reg = <0x40>; + interrupt-parent = <&smb_pex_cpu0_event>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + infineon,en-pin-fixed-level; + + regulators { + pvccd_hv_cpu0: vout { + regulator-name = "pvccd_hv_cpu0"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + tda38640-pvpp-hbm-cpu0@40 { + compatible = "infineon,tda38640"; + reg = <0x40>; + interrupt-parent = <&smb_pex_cpu0_event>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvpp_hbm_cpu0: vout { + regulator-name = "pvpp_hbm_cpu0"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c7 { + status = "okay"; + + i2cmux4: mux@77 { + compatible = "maxim,max7357"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio0 ASPEED_GPIO(F, 3) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + smb_pex_cpu1_event: pinctrl@20 { + compatible = "cypress,cy8c9540"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&smb_pex_vr_ctrl>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + vdd-supply = <&p3v3_aux>; + reset-gpios = <&smb_svc_pex_cpu1_led 16 GPIO_ACTIVE_HIGH>; + + gpio-reserved-ranges = <14 2>, <21 1>, <25 3>, <33 1>; + + gpio-line-names = + /* GPORT0 */ + "PWRGD_CHD_CPU1", "PWRGD_CHC_CPU1", + "PWRGD_CHB_CPU1", "PWRGD_CHA_CPU1", + "PWRGD_CHE_CPU1", "PWRGD_CHF_CPU1", + "PWRGD_CHG_CPU1", "PWRGD_CHH_CPU1", + /* GPORT1 */ + "SMB_VR_PVPP_HBM_CPU1_ALERT_N", "SMB_VR_PVCCINFAON_CPU1_ALERT_N", + "SMB_VR_PVNN_MAIN_CPU1_ALERT_N", "SMB_VR_PVCCD_HV_CPU1_ALERT_N", + "SMB_VR_PVCCIN_CPU1_ALERT_N", "SEL_SMB_DIMM_CPU1", + "", "", + /* GPORT2 */ + "PWRGD_LVC3_CPU1_AB_DRAM_G", "PWRGD_LVC3_CPU1_CD_DRAM_G", + "PWRGD_LVC3_CPU1_EF_DRAM_G", "PWRGD_LVC3_CPU1_GH_DRAM_G", + /* GPORT3 */ + "FM_CPU1_DISABLE_COD_N", "", + "RST_LVC3_CPU1_RESET_N", "PWRGD_LVC3_CPU1_PWRGOOD", + "PWRGD_PLT_AUX_CPU1_LVT3", "", + "", "", + /* GPORT4 */ + "H_LVT3_CPU1_PROCHOT_N", "H_LVT3_CPU1_MEMHOT_IN_N", + "H_LVT3_CPU1_MEMHOT_OUT_N", "H_LVT3_CPU1_MEMTRIP_OUT_N", + "H_LVT3_CPU1_THERMTRIP_OUT_N", "", + "H_LVT3_CPU1_NMI", "FM_S3M_CPU1_CD_INIT_ERROR", + /* GPORT5 */ + "FM_CPU1_PKG_ID0", "FM_CPU1_PKG_ID1", + "FM_CPU1_PROC_ID0", "FM_CPU1_PROC_ID1"; + + pinctrl-0 = <&U62090_pins>; + pinctrl-names = "default"; + U62090_pins: cfg-pins { + pins = "gp10", "gp11", "gp12", "gp13", "gp14"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pvccinfaon-pvccfa-cpu1@58 { + compatible = "mps,mp2971"; + reg = <0x58>; + interrupt-parent = <&smb_pex_cpu1_event>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvccinfaon_cpu1: vout0 { + regulator-name = "pvccinfaon_cpu1"; + regulator-enable-ramp-delay = <200>; + }; + pvccfa_ehv_cpu1: vout1 { + regulator-name = "pvccfa_ehv_cpu1"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + tda38640-pvnn-main-cpu1@40 { + compatible = "infineon,tda38640"; + reg = <0x40>; + interrupt-parent = <&smb_pex_cpu1_event>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvnn_main_cpu1: vout { + regulator-name = "pvnn_main_cpu1"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + mp2973-pvccin-pvccfa-cpu1@58 { + compatible = "mps,mp2973"; + reg = <0x58>; + interrupt-parent = <&smb_pex_cpu1_event>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvccin_cpu1: vout0 { + regulator-name = "pvccin_cpu1"; + regulator-enable-ramp-delay = <200>; + }; + pvccfa_ehv_fivra_cpu1: vout1 { + regulator-name = "pvccfa_ehv_fivra_cpu1"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + tda38640-pvccd-hv-cpu1@40 { + compatible = "infineon,tda38640"; + reg = <0x40>; + interrupt-parent = <&smb_pex_cpu1_event>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + infineon,en-pin-fixed-level; + + regulators { + pvccd_hv_cpu1: vout { + regulator-name = "pvccd_hv_cpu1"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + tda38640-pvpp-hbm-cpu1@40 { + compatible = "infineon,tda38640"; + reg = <0x40>; + interrupt-parent = <&smb_pex_cpu1_event>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvpp_hbm_cpu1: vout { + regulator-name = "pvpp_hbm_cpu1"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c6 { + status = "okay"; + + i2cmux3: mux@77 { + compatible = "maxim,max7357"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&p3v3_aux>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + smb_pex_cpu2_event: pinctrl@20 { + compatible = "cypress,cy8c9540"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&smb_pex_vr_ctrl>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + vdd-supply = <&p3v3_aux>; + reset-gpios = <&smb_svc_pex_cpu2_led 16 GPIO_ACTIVE_HIGH>; + + gpio-reserved-ranges = <14 2>, <21 1>, <25 3>, <33 1>; + + gpio-line-names = + /* GPORT0 */ + "PWRGD_CHD_CPU2", "PWRGD_CHC_CPU2", + "PWRGD_CHB_CPU2", "PWRGD_CHA_CPU2", + "PWRGD_CHE_CPU2", "PWRGD_CHF_CPU2", + "PWRGD_CHG_CPU2", "PWRGD_CHH_CPU2", + /* GPORT1 */ + "SMB_VR_PVPP_HBM_CPU2_ALERT_N", "SMB_VR_PVCCINFAON_CPU2_ALERT_N", + "SMB_VR_PVNN_MAIN_CPU2_ALERT_N", "SMB_VR_PVCCD_HV_CPU2_ALERT_N", + "SMB_VR_PVCCIN_CPU2_ALERT_N", "SEL_SMB_DIMM_CPU2", + "", "", + /* GPORT2 */ + "PWRGD_LVC3_CPU2_AB_DRAM_G", "PWRGD_LVC3_CPU2_CD_DRAM_G", + "PWRGD_LVC3_CPU2_EF_DRAM_G", "PWRGD_LVC3_CPU2_GH_DRAM_G", + /* GPORT3 */ + "FM_CPU2_DISABLE_COD_N", "", + "RST_LVC3_CPU2_RESET_N", "PWRGD_LVC3_CPU2_PWRGOOD", + "PWRGD_PLT_AUX_CPU2_LVT3", "", + "", "", + /* GPORT4 */ + "H_LVT3_CPU2_PROCHOT_N", "H_LVT3_CPU2_MEMHOT_IN_N", + "H_LVT3_CPU2_MEMHOT_OUT_N", "H_LVT3_CPU2_MEMTRIP_OUT_N", + "H_LVT3_CPU2_THERMTRIP_OUT_N", "", + "H_LVT3_CPU2_NMI", "FM_S3M_CPU2_CD_INIT_ERROR", + /* GPORT5 */ + "FM_CPU2_PKG_ID0", "FM_CPU2_PKG_ID1", + "FM_CPU2_PROC_ID0", "FM_CPU2_PROC_ID1"; + + pinctrl-0 = <&U62100_pins>; + pinctrl-names = "default"; + U62100_pins: cfg-pins { + pins = "gp10", "gp11", "gp12", "gp13", "gp14"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pvccinfaon-pvccfa-cpu2@58 { + compatible = "mps,mp2971"; + reg = <0x58>; + interrupt-parent = <&smb_pex_cpu2_event>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvccinfaon_cpu2: vout0 { + regulator-name = "pvccinfaon_cpu2"; + regulator-enable-ramp-delay = <200>; + }; + pvccfa_ehv_cpu2: vout1 { + regulator-name = "pvccfa_ehv_cpu2"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + tda38640-pvnn-main-cpu2@40 { + compatible = "infineon,tda38640"; + reg = <0x40>; + interrupt-parent = <&smb_pex_cpu2_event>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvnn_main_cpu2: vout { + regulator-name = "pvnn_main_cpu2"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + mp2973-pvccin-pvccfa-cpu2@58 { + compatible = "mps,mp2973"; + reg = <0x58>; + interrupt-parent = <&smb_pex_cpu2_event>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvccin_cpu2: vout0 { + regulator-name = "pvccin_cpu2"; + regulator-enable-ramp-delay = <200>; + }; + pvccfa_ehv_fivra_cpu2: vout1 { + regulator-name = "pvccfa_ehv_fivra_cpu2"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + tda38640-pvccd-hv-cpu2@40 { + compatible = "infineon,tda38640"; + reg = <0x40>; + interrupt-parent = <&smb_pex_cpu2_event>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + infineon,en-pin-fixed-level; + + regulators { + pvccd_hv_cpu2: vout { + regulator-name = "pvccd_hv_cpu2"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + tda38640-pvpp-hbm-cpu2@40 { + compatible = "infineon,tda38640"; + reg = <0x40>; + interrupt-parent = <&smb_pex_cpu2_event>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvpp_hbm_cpu2: vout { + regulator-name = "pvpp_hbm_cpu2"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c12 { + status = "okay"; + + i2cmux22: mux@77 { + compatible = "maxim,max7357"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio0 ASPEED_GPIO(P, 2) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + smb_pex_cpu3_event: pinctrl@20 { + compatible = "cypress,cy8c9540"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&smb_pex_vr_ctrl>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + vdd-supply = <&p3v3_aux>; + reset-gpios = <&smb_svc_pex_cpu3_led 16 GPIO_ACTIVE_HIGH>; + + gpio-reserved-ranges = <14 2>, <21 1>, <25 3>, <33 1>; + + gpio-line-names = + /* GPORT0 */ + "PWRGD_CHD_CPU3", "PWRGD_CHC_CPU3", + "PWRGD_CHB_CPU3", "PWRGD_CHA_CPU3", + "PWRGD_CHE_CPU3", "PWRGD_CHF_CPU3", + "PWRGD_CHG_CPU3", "PWRGD_CHH_CPU3", + /* GPORT1 */ + "SMB_VR_PVPP_HBM_CPU3_ALERT_N", "SMB_VR_PVCCINFAON_CPU3_ALERT_N", + "SMB_VR_PVNN_MAIN_CPU3_ALERT_N", "SMB_VR_PVCCD_HV_CPU3_ALERT_N", + "SMB_VR_PVCCIN_CPU3_ALERT_N", "SEL_SMB_DIMM_CPU3", + "", "", + /* GPORT2 */ + "PWRGD_LVC3_CPU3_AB_DRAM_G", "PWRGD_LVC3_CPU3_CD_DRAM_G", + "PWRGD_LVC3_CPU3_EF_DRAM_G", "PWRGD_LVC3_CPU3_GH_DRAM_G", + /* GPORT3 */ + "FM_CPU3_DISABLE_COD_N", "", + "RST_LVC3_CPU3_RESET_N", "PWRGD_LVC3_CPU3_PWRGOOD", + "PWRGD_PLT_AUX_CPU3_LVT3", "", + "", "", + /* GPORT4 */ + "H_LVT3_CPU3_PROCHOT_N", "H_LVT3_CPU3_MEMHOT_IN_N", + "H_LVT3_CPU3_MEMHOT_OUT_N", "H_LVT3_CPU3_MEMTRIP_OUT_N", + "H_LVT3_CPU3_THERMTRIP_OUT_N", "", + "H_LVT3_CPU3_NMI", "FM_S3M_CPU3_CD_INIT_ERROR", + /* GPORT5 */ + "FM_CPU3_PKG_ID0", "FM_CPU3_PKG_ID1", + "FM_CPU3_PROC_ID0", "FM_CPU3_PROC_ID1"; + + pinctrl-0 = <&U62110_pins>; + pinctrl-names = "default"; + U62110_pins: cfg-pins { + pins = "gp10", "gp11", "gp12", "gp13", "gp14"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pvccinfaon-pvccfa-cpu3@58 { + compatible = "mps,mp2971"; + reg = <0x58>; + interrupt-parent = <&smb_pex_cpu3_event>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvccinfaon_cpu3: vout0 { + regulator-name = "pvccinfaon_cpu3"; + regulator-enable-ramp-delay = <200>; + }; + pvccfa_ehv_cpu3: vout1 { + regulator-name = "pvccfa_ehv_cpu3"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + tda38640-pvnn-main-cpu3@40 { + compatible = "infineon,tda38640"; + reg = <0x40>; + interrupt-parent = <&smb_pex_cpu3_event>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvnn_main_cpu3: vout { + regulator-name = "pvnn_main_cpu3"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + mp2973-pvccin-pvccfa-cpu3@58 { + compatible = "mps,mp2973"; + reg = <0x58>; + interrupt-parent = <&smb_pex_cpu3_event>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvccin_cpu3: vout0 { + regulator-name = "pvccin_cpu3"; + regulator-enable-ramp-delay = <200>; + }; + pvccfa_ehv_fivra_cpu3: vout1 { + regulator-name = "pvccfa_ehv_fivra_cpu3"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + tda38640-pvccd-hv-cpu3@40 { + compatible = "infineon,tda38640"; + reg = <0x40>; + interrupt-parent = <&smb_pex_cpu3_event>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + infineon,en-pin-fixed-level; + + regulators { + pvccd_hv_cpu3: vout { + regulator-name = "pvccd_hv_cpu3"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + tda38640-pvpp-hbm-cpu3@40 { + compatible = "infineon,tda38640"; + reg = <0x40>; + interrupt-parent = <&smb_pex_cpu3_event>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + pvpp_hbm_cpu3: vout { + regulator-name = "pvpp_hbm_cpu3"; + regulator-enable-ramp-delay = <200>; + }; + }; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c15 { + status = "okay"; + + i2cmux14: mux@77 { + compatible = "maxim,max7357"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio0 ASPEED_GPIO(R, 1) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux15: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 11 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux16: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 2 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux17: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 0 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux18: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 3 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + }; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux19: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 9 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + }; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + smb_pex_rssd17_32: pinctrl@20 { + compatible = "cypress,cy8c9560"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&bmc_pex_irq>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + vdd-supply = <&p3v3_aux>; + reset-gpios = <&bmc_pex_irq 19 GPIO_ACTIVE_HIGH>; + + gpio-reserved-ranges = <48 12>; + + gpio-line-names = + /* GPORT0 */ + "RSSD17_SMBRST_N", "RSSD18_SMBRST_N", + "RSSD19_SMBRST_N", "RSSD20_SMBRST_N", + "RSSD21_SMBRST_N", "RSSD22_SMBRST_N", + "RSSD23_SMBRST_N", "RSSD24_SMBRST_N", + /* GPORT1 */ + "RSSD25_SMBRST_N", "RSSD26_SMBRST_N", + "RSSD27_SMBRST_N", "RSSD28_SMBRST_N", + "RSSD29_SMBRST_N", "RSSD30_SMBRST_N", + "RSSD31_SMBRST_N", "RSSD32_SMBRST_N", + /* GPORT2 */ + "RSSD17_PWRDIS", "RSSD18_PWRDIS", + "RSSD19_PWRDIS", "RSSD20_PWRDIS", + /* GPORT3 */ + "RSSD21_PWRDIS", "RSSD22_PWRDIS", + "RSSD23_PWRDIS", "RSSD24_PWRDIS", + "RSSD25_PWRDIS", "RSSD26_PWRDIS", + "RSSD27_PWRDIS", "RSSD28_PWRDIS", + /* GPORT4 */ + "RSSD29_PWRDIS", "RSSD30_PWRDIS", + "RSSD31_PWRDIS", "RSSD32_PWRDIS", + "RSSD17_RESET_N", "RSSD18_RESET_N", + "RSSD19_RESET_N", "RSSD20_RESET_N", + /* GPORT5 */ + "RSSD21_RESET_N", "RSSD22_RESET_N", + "RSSD23_RESET_N", "RSSD24_RESET_N", + "RSSD25_RESET_N", "RSSD26_RESET_N", + "RSSD27_RESET_N", "RSSD28_RESET_N", + /* GPORT6 */ + "RSSD29_RESET_N", "RSSD30_RESET_N", + "RSSD31_RESET_N", "RSSD32_RESET_N", + "", "", + "", "", + /* GPORT7 */ + "", "", + "", "", + "", "", + "", ""; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux20: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 4 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux21: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 5 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; + +&i2c8 { + status = "okay"; + + i2cmux5: mux@77 { + compatible = "maxim,max7357"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio0 ASPEED_GPIO(R, 0) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux6: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + }; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux7: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux8: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 1 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux9: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + }; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux10: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + }; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + smb_pex_rssd_01_16: pinctrl@20 { + compatible = "cypress,cy8c9560"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&bmc_pex_irq>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + vdd-supply = <&p3v3_aux>; + reset-gpios = <&bmc_pex_irq 18 GPIO_ACTIVE_HIGH>; + + gpio-reserved-ranges = <48 12>; + + gpio-line-names = + /* GPORT0 */ + "RSSD01_SMBRST_N", "RSSD02_SMBRST_N", + "RSSD03_SMBRST_N", "RSSD04_SMBRST_N", + "RSSD05_SMBRST_N", "RSSD06_SMBRST_N", + "RSSD07_SMBRST_N", "RSSD08_SMBRST_N", + /* GPORT1 */ + "RSSD09_SMBRST_N", "RSSD10_SMBRST_N", + "RSSD11_SMBRST_N", "RSSD12_SMBRST_N", + "RSSD13_SMBRST_N", "RSSD14_SMBRST_N", + "RSSD15_SMBRST_N", "RSSD16_SMBRST_N", + /* GPORT2 */ + "RSSD01_PWRDIS", "RSSD02_PWRDIS", + "RSSD03_PWRDIS", "RSSD04_PWRDIS", + /* GPORT3 */ + "RSSD05_PWRDIS", "RSSD06_PWRDIS", + "RSSD07_PWRDIS", "RSSD08_PWRDIS", + "RSSD09_PWRDIS", "RSSD10_PWRDIS", + "RSSD11_PWRDIS", "RSSD12_PWRDIS", + /* GPORT4 */ + "RSSD13_PWRDIS", "RSSD14_PWRDIS", + "RSSD15_PWRDIS", "RSSD16_PWRDIS", + "RSSD01_RESET_N", "RSSD02_RESET_N", + "RSSD03_RESET_N", "RSSD04_RESET_N", + /* GPORT5 */ + "RSSD05_RESET_N", "RSSD06_RESET_N", + "RSSD07_RESET_N", "RSSD08_RESET_N", + "RSSD09_RESET_N", "RSSD10_RESET_N", + "RSSD11_RESET_N", "RSSD12_RESET_N", + /* GPORT6 */ + "RSSD13_RESET_N", "RSSD14_RESET_N", + "RSSD15_RESET_N", "RSSD16_RESET_N", + "", "", + "", "", + /* GPORT7 */ + "", "", + "", "", + "", "", + "", ""; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux11: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 12 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmux12: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&bmc_pex_irq 14 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_aux>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; +}; + +&i2c13 { + status = "okay"; + + i2cmux23: mux@77 { + compatible = "maxim,max7357"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio0 ASPEED_GPIO(R, 4) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_bmc_aux>; + }; +}; + +&i2cmux23 { + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + smb_pex_vr_ctrl: pinctrl@20 { + compatible = "cypress,cy8c9540"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(V, 2) IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + vdd-supply = <&p3v3_bmc_aux>; + reset-gpios = <&gpio0 ASPEED_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; + gpio-line-names = + /* GPORT0 */ + "BCM0_INPUT_DISABLE_N", "SMB_VR_P3V3_AUX_ALERT_N", + "SMB_PEX_CPU1_EVENT_INT", "SMB_PEX_CPU2_EVENT_INT", + "DPIC0_VOLTAGE_DETECTB_N", "DPIC0_VOLTAGE_DETECTA_N", + "DPIC1_VOLTAGE_DETECTA_N", "DPIC1_VOLTAGE_DETECTB_N", + /* GPORT1 */ + "SMB_PEX_NIC_INT", "SMB_VR_P1V05_PCH_AUX_ALERT_N", + "SMB_PEX_CPU0_EVENT_INT", "SMB_PEX_CPU3_EVENT_INT", + "LED_ID_TPM", "PLUG_DETECT_TPM", + "PLUG_DETECT_M2_SSD_CARRIER1", "RST_M2_SSD1_PERST_N", + /* GPORT2 */ + "LED_ID_BAT", "LED_ID_MGMT_PORT2", + "LED_ID_MGMT_PORT1", "SMB_VR_P5V_AUX_ALERT_N", + /* GPORT3 */ + "SMB_VR_AUX_SSB_ALERT_N", "BCM1_INPUT_DISABLE_N", + "LED_ID_NIC1_PORT1", "LED_ID_NIC1_PORT2", + "LED_ID_NIC2_PORT1", "LED_ID_NIC2_PORT2", + "RST_M2_SSD2_PERST_N", "PLUG_DETECT_M2_SSD2", + /* GPORT4 */ + "PLUG_DETECT_BAT", "PLUG_DETECT_M2_SSD1", + "M2_SSD1_SSB_ALERT_N", "BCM2_INPUT_DISABLE_N", + "SMB_VR_P1V8_PCH_AUX_ALERT_N", "BCM3_INPUT_DISABLE_N", + "LED_PWR_DWR_BACK", "LED_ID_DWR_BACK_P", + /* GPORT5 */ + "LED_ID_M2_SSD2", "LED_ID_M2_SSD1", + "PLUG_DETECT_M2_SSD_CARRIER2", "M2_SSD2_SSB_ALERT_N"; + + pinctrl-0 = <&U62120_input &U62120_input_pullup>; + pinctrl-names = "default"; + U62120_input: input-pins { + pins = "gp10"; + function = "gpio"; + input-enable; + bias-disable; + }; + U62120_input_pullup: input-pullup-pins { + pins = "gp01", "gp02", "gp03", "gp11", "gp12", "gp13", + "gp23", "gp30", "gp40", "gp42", "gp44", "gp53"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + }; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + bmc_pex_irq: pinctrl@20 { + compatible = "cypress,cy8c9520"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(V, 0) IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + vdd-supply = <&p3v3_aux>; + reset-gpios = <&gpio0 ASPEED_GPIO(Q, 1) GPIO_ACTIVE_HIGH>; + gpio-line-names = + /* GPORT0 */ + "SMB_MUX_PWM_FANGRP2_RST_INT_N", "SMB_MUX_SSB_FANGRP2_RST_INT_N", + "SMB_MUX_PWM_FANGRP1_RST_INT_N", "SMB_MUX_SSB_RSSD01_08_RST_INT_N", + "SMB_MUX_RSSD01_08_RST_INT_N", "SMB_MUX_RSSD09_16_RST_INT_N", + "SMB_PEX_RSSD01_16_INT", "SMB_MUX_SSB_FANGRP1_RST_INT_N", + /* GPORT1 */ + "SMB_SVC_PEX_FAN_ALERT_INT", "SMB_MUX_SSB_RSSD09_16_RST_INT_N", + "SMB_MUX_SSB_RSSD17_24_RST_INT_N", "SMB_MUX_PWM_FANGRP0_RST_INT_N", + "SMB_MUX_RSSD17_24_RST_INT_N", "SMB_PEX_RSSD17_32_INT", + "SMB_MUX_RSSD25_32_RST_INT_N", "SMB_MUX_SSB_RSSD25_32_RST_INT_N", + /* GPORT2 */ + "SMB_MUX_SSB_FANGRP0_RST_INT_N", "PEX_FAN_ALERT_RST", + "PEX_RSSD01_16_RST", "PEX_RSSD17_32_RST"; + pinctrl-0 = <&U60000_pins>; + pinctrl-names = "default"; + U60000_pins: cfg-pins { + pins = "gp06", "gp10", "gp15"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + i2cmux24: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&p3v3_bmc_aux>; + }; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + vcc-supply = <&p3v3_bmc_aux>; + }; + }; + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + i2cmux25: mux@70 { + compatible = "maxim,max7357"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2cmux25 { + reset-gpios = <&gpio0 ASPEED_GPIO(R, 2) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + vdd-supply = <&p3v3_bmc_aux>; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + p5v_aux: ir38263-p5v-aux@40 { + compatible = "infineon,ir38263"; + reg = <0x40>; + + regulator-name = "p5v_aux"; + regulator-enable-ramp-delay = <2000>; + vin-supply = <&p12v>; + vbus-supply = <&p3v3_bmc_aux>; + regulator-always-on; + regulator-boot-on; + }; + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + p3v3_aux: ir38263-p3v3-aux@40 { + compatible = "infineon,ir38263"; + reg = <0x40>; + + vin-supply = <&p12v>; + regulator-name = "p3v3_aux"; + /* + * 2msec for regulator + 18msec for board capacitance + * Note: Every IC has a PTC which slowly charges the bypass + * cap. + */ + regulator-enable-ramp-delay = <200000>; + }; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + aux_ssb: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_pex_vr_ctrl>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + vss1-supply = <&p5v_aux>; + vss2-supply = <&p3v3_aux>; + regulators { + p5v: sw0 { + regulator-name = "p5v"; + shunt-resistor-micro-ohms = <12000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <100000>; + }; + p3v3_pch: sw1 { + regulator-name = "p3v3_pch"; + shunt-resistor-micro-ohms = <12000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <100000>; + }; + }; + }; + }; + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + pli1209bc_p12v_a: regulator@5f { + compatible = "vicor,pli1209bc"; + reg = <0x5f>; + regulators { + p12v_a: vout2 { + regulator-name = "bcm0"; + regulator-boot-on; + }; + }; + }; + }; + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + pli1209bc_p12v_b: regulator@5f { + compatible = "vicor,pli1209bc"; + reg = <0x5f>; + regulators { + p12v_b: vout2 { + regulator-name = "bcm1"; + regulator-boot-on; + }; + }; + }; + }; + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + pli1209bc_p12v_c: regulator@5f { + compatible = "vicor,pli1209bc"; + reg = <0x5f>; + regulators { + p12v_c: vout2 { + regulator-name = "bcm2"; + regulator-boot-on; + }; + }; + }; + }; + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + pli1209bc_p12v_d: regulator@5f { + compatible = "vicor,pli1209bc"; + reg = <0x5f>; + regulators { + p12v_d: vout2 { + regulator-name = "bcm3"; + regulator-boot-on; + }; + }; + }; + }; +}; + +&i2cmux24 { + + reset-gpios = <&gpio0 ASPEED_GPIO(P, 3) (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + smb_svc_pex_rssd01_16: pinctrl@20 { + compatible = "cypress,cy8c9560"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + vdd-supply = <&p3v3_bmc_aux>; + reset-gpios = <&smb_svc_pex_cpu0_led 17 GPIO_ACTIVE_HIGH>; + gpio-line-names = + /* GPORT0 */ + "LED_ID_RSSD01", "LED_ID_RSSD02", + "LED_ID_RSSD03", "LED_ID_RSSD04", + "LED_ID_RSSD05", "LED_ID_RSSD06", + "LED_ID_RSSD07", "LED_ID_RSSD08", + /* GPORT1 */ + "LED_ID_RSSD09", "LED_ID_RSSD10", + "LED_ID_RSSD11", "LED_ID_RSSD12", + "LED_ID_RSSD13", "LED_ID_RSSD14", + "LED_ID_RSSD15", "LED_ID_RSSD16", + /* GPORT2 */ + "RSSD01_PRESENT_N", "RSSD02_PRESENT_N", + "RSSD03_PRESENT_N", "RSSD04_PRESENT_N", + /* GPORT3 */ + "RSSD05_PRESENT_N", "RSSD06_PRESENT_N", + "RSSD07_PRESENT_N", "RSSD08_PRESENT_N", + "RSSD09_PRESENT_N", "RSSD10_PRESENT_N", + "RSSD11_PRESENT_N", "RSSD12_PRESENT_N", + /* GPORT4 */ + "RSSD13_PRESENT_N", "RSSD14_PRESENT_N", + "RSSD15_PRESENT_N", "RSSD16_PRESENT_N", + "LED_ID_FAN_ASM01", "LED_ID_FAN_ASM02", + "LED_ID_FAN_ASM03", "LED_ID_FAN_ASM04", + /* GPORT5 */ + "LED_ID_FAN_ASM05", "LED_ID_FAN_ASM06", + "PLUG_DETECT_FAN_ASM01", "PLUG_DETECT_FAN_ASM02", + "PLUG_DETECT_FAN_ASM03", "PLUG_DETECT_FAN_ASM04", + "PLUG_DETECT_FAN_ASM05", "PLUG_DETECT_FAN_ASM06", + /* GPORT6 */ + "SSB_RSSD01_ALERT_N", "SSB_RSSD02_ALERT_N", + "SSB_RSSD03_ALERT_N", "SSB_RSSD04_ALERT_N", + "SSB_RSSD05_ALERT_N", "SSB_RSSD06_ALERT_N", + "SSB_RSSD07_ALERT_N", "SSB_RSSD08_ALERT_N", + /* GPORT7 */ + "SSB_RSSD09_ALERT_N", "SSB_RSSD10_ALERT_N", + "SSB_RSSD11_ALERT_N", "SSB_RSSD12_ALERT_N", + "SSB_RSSD13_ALERT_N", "SSB_RSSD14_ALERT_N", + "SSB_RSSD15_ALERT_N", "SSB_RSSD16_ALERT_N"; + pinctrl-0 = <&U65200_pins>; + pinctrl-names = "default"; + U65200_pins: cfg-pins { + pins = "gp60", "gp61", "gp62", + "gp63", "gp64", "gp65", "gp66", + "gp67", "gp70", "gp71", "gp72", + "gp73", "gp74", "gp75", "gp76", "gp77"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + }; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + smb_svc_pex_rssd17_32: pinctrl@20 { + compatible = "cypress,cy8c9560"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(H, 0) IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + vdd-supply = <&p3v3_bmc_aux>; + reset-gpios = <&smb_svc_pex_cpu1_led 17 GPIO_ACTIVE_HIGH>; + gpio-line-names = + /* GPORT0 */ + "LED_ID_RSSD17", "LED_ID_RSSD18", + "LED_ID_RSSD19", "LED_ID_RSSD20", + "LED_ID_RSSD21", "LED_ID_RSSD22", + "LED_ID_RSSD23", "LED_ID_RSSD24", + /* GPORT1 */ + "LED_ID_RSSD25", "LED_ID_RSSD26", + "LED_ID_RSSD27", "LED_ID_RSSD28", + "LED_ID_RSSD29", "LED_ID_RSSD30", + "LED_ID_RSSD31", "LED_ID_RSSD32", + /* GPORT2 */ + "RSSD17_PRESENT_N", "RSSD18_PRESENT_N", + "RSSD19_PRESENT_N", "RSSD20_PRESENT_N", + /* GPORT3 */ + "RSSD21_PRESENT_N", "RSSD22_PRESENT_N", + "RSSD23_PRESENT_N", "RSSD24_PRESENT_N", + "RSSD25_PRESENT_N", "RSSD26_PRESENT_N", + "RSSD27_PRESENT_N", "RSSD28_PRESENT_N", + /* GPORT4 */ + "RSSD29_PRESENT_N", "RSSD30_PRESENT_N", + "RSSD31_PRESENT_N", "RSSD32_PRESENT_N", + "LED_ID_FAN_ASM07", "LED_ID_FAN_ASM08", + "LED_ID_FAN_ASM09", "LED_ID_FAN_ASM10", + /* GPORT5 */ + "LED_ID_FAN_ASM11", "LED_ID_FAN_ASM12", + "PLUG_DETECT_FAN_ASM07", "PLUG_DETECT_FAN_ASM08", + "PLUG_DETECT_FAN_ASM09", "PLUG_DETECT_FAN_ASM10", + "PLUG_DETECT_FAN_ASM11", "PLUG_DETECT_FAN_ASM12", + /* GPORT6 */ + "SSB_RSSD17_ALERT_N", "SSB_RSSD18_ALERT_N", + "SSB_RSSD19_ALERT_N", "SSB_RSSD20_ALERT_N", + "SSB_RSSD21_ALERT_N", "SSB_RSSD22_ALERT_N", + "SSB_RSSD23_ALERT_N", "SSB_RSSD24_ALERT_N", + /* GPORT7 */ + "SSB_RSSD25_ALERT_N", "SSB_RSSD26_ALERT_N", + "SSB_RSSD27_ALERT_N", "SSB_RSSD28_ALERT_N", + "SSB_RSSD29_ALERT_N", "SSB_RSSD30_ALERT_N", + "SSB_RSSD31_ALERT_N", "SSB_RSSD32_ALERT_N"; + pinctrl-0 = <&U65300_pins>; + pinctrl-names = "default"; + U65300_pins: cfg-pins { + pins = "gp60", "gp61", "gp62", + "gp63", "gp64", "gp65", "gp66", + "gp67", "gp70", "gp71", "gp72", + "gp73", "gp74", "gp75", "gp76", + "gp77"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + smb_svc_pex_cpu1_led: pinctrl@20 { + compatible = "cypress,cy8c9540"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(V, 6) IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + vdd-supply = <&p3v3_bmc_aux>; + reset-gpios = <&gpio0 ASPEED_GPIO(Q, 5) GPIO_ACTIVE_HIGH>; + gpio-reserved-ranges = <18 2>, <36 2>; + gpio-line-names = + /* GPORT0 */ + "PLUG_DETECT_DIMM_C1E2", "PLUG_DETECT_DIMM_C1E1", + "PLUG_DETECT_DIMM_C1F2", "PLUG_DETECT_DIMM_C1F1", + "PLUG_DETECT_DIMM_C1G2", "PLUG_DETECT_DIMM_C1G1", + "PLUG_DETECT_DIMM_C1H2", "PLUG_DETECT_DIMM_C1H1", + /* GPORT1 */ + "PLUG_DETECT_DIMM_C1D1", "PLUG_DETECT_DIMM_C1D2", + "PLUG_DETECT_DIMM_C1C1", "PLUG_DETECT_DIMM_C1C2", + "PLUG_DETECT_DIMM_C1B1", "PLUG_DETECT_DIMM_C1B2", + "PLUG_DETECT_DIMM_C1A1", "PLUG_DETECT_DIMM_C1A2", + /* GPORT2 */ + "PEX_CPU1_EVENT_RST", "SVC_PEX_RSSD17_32_RST", + "", "", + /* GPORT3 */ + "LED_ID_DIMM_C1E2", "LED_ID_DIMM_C1E1", + "LED_ID_DIMM_C1F2", "LED_ID_DIMM_C1F1", + "LED_ID_DIMM_C1G2", "LED_ID_DIMM_C1G1", + "LED_ID_DIMM_C1H2", "LED_ID_DIMM_C1H1", + /* GPORT4 */ + "LED_ID_DIMM_C1A2", "LED_ID_DIMM_C1A1", + "LED_ID_DIMM_C1B2", "LED_ID_DIMM_C1B1", + "LED_ID_DIMM_C1C2", "LED_ID_DIMM_C1C1", + "LED_ID_DIMM_C1D2", "LED_ID_DIMM_C1D1", + /* GPORT5 */ + "", "", + "FM_CPU1_SKTOCC_N", "LED_ID_CPU1"; + }; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + smb_svc_pex_fan_alert: pinctrl@20 { + compatible = "cypress,cy8c9560"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&bmc_pex_irq>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + vdd-supply = <&p3v3_aux>; + reset-gpios = <&bmc_pex_irq 17 GPIO_ACTIVE_HIGH>; + gpio-reserved-ranges = <24 3>, <51 9>; + gpio-line-names = + /* GPORT0 */ + "FAN01_SSB_ALERT_N", "FAN02_SSB_ALERT_N", + "FAN03_SSB_ALERT_N", "FAN04_SSB_ALERT_N", + "FAN05_SSB_ALERT_N", "FAN06_SSB_ALERT_N", + "FAN07_SSB_ALERT_N", "FAN08_SSB_ALERT_N", + /* GPORT1 */ + "FAN09_SSB_ALERT_N", "FAN10_SSB_ALERT_N", + "FAN11_SSB_ALERT_N", "FAN12_SSB_ALERT_N", + "FAN13_SSB_ALERT_N", "FAN14_SSB_ALERT_N", + "FAN15_SSB_ALERT_N", "FAN16_SSB_ALERT_N", + /* GPORT2 */ + "FAN17_SSB_ALERT_N", "FAN18_SSB_ALERT_N", + "FAN19_SSB_ALERT_N", "FAN20_SSB_ALERT_N", + /* GPORT3 */ + "FAN21_SSB_ALERT_N", "FAN22_SSB_ALERT_N", + "FAN23_SSB_ALERT_N", "FAN24_SSB_ALERT_N", + "", "", + "", "FAN01_PWM_ALERT_N", + /* GPORT4 */ + "FAN02_PWM_ALERT_N", "FAN03_PWM_ALERT_N", + "FAN04_PWM_ALERT_N", "FAN05_PWM_ALERT_N", + "FAN06_PWM_ALERT_N", "FAN07_PWM_ALERT_N", + "FAN08_PWM_ALERT_N", "FAN09_PWM_ALERT_N", + /* GPORT5 */ + "FAN10_PWM_ALERT_N", "FAN11_PWM_ALERT_N", + "FAN12_PWM_ALERT_N", "FAN13_PWM_ALERT_N", + "FAN14_PWM_ALERT_N", "FAN15_PWM_ALERT_N", + "FAN16_PWM_ALERT_N", "FAN17_PWM_ALERT_N", + /* GPORT6 */ + "FAN18_PWM_ALERT_N", "FAN19_PWM_ALERT_N", + "FAN20_PWM_ALERT_N", "FAN21_PWM_ALERT_N", + "FAN22_PWM_ALERT_N", "FAN23_PWM_ALERT_N", + "FAN24_PWM_ALERT_N", "", + /* GPORT7 */ + "", "", + "", "", + "", "", + "", ""; + pinctrl-0 = <&U65600_pins>; + pinctrl-names = "default"; + U65600_pins: cfg-pins { + pins = "gp00", "gp01", "gp02", + "gp03", "gp04", "gp05", "gp06", + "gp07", "gp10", "gp11", "gp12", + "gp13", "gp14", "gp15", "gp16", + "gp17", "gp20", "gp21", "gp22", + "gp23", "gp30", "gp31", "gp32", + "gp33", "gp37", "gp40", "gp41", + "gp42", "gp43", "gp44", "gp45", + "gp46", "gp47", "gp50", "gp51", + "gp52", "gp53", "gp54", "gp55", + "gp56", "gp57", "gp60", "gp61", + "gp62", "gp63", "gp64", "gp65", + "gp66"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + }; + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + smb_svc_pex_cpu2_led: pinctrl@20 { + compatible = "cypress,cy8c9540"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(V, 5) IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + vdd-supply = <&p3v3_bmc_aux>; + reset-gpios = <&gpio0 ASPEED_GPIO(Q, 6) GPIO_ACTIVE_HIGH>; + gpio-reserved-ranges = <17 3>, <36 2>; + gpio-line-names = + /* GPORT0 */ + "PLUG_DETECT_DIMM_C2E2", "PLUG_DETECT_DIMM_C2E1", + "PLUG_DETECT_DIMM_C2F2", "PLUG_DETECT_DIMM_C2F1", + "PLUG_DETECT_DIMM_C2G2", "PLUG_DETECT_DIMM_C2G1", + "PLUG_DETECT_DIMM_C2H2", "PLUG_DETECT_DIMM_C2H1", + /* GPORT1 */ + "PLUG_DETECT_DIMM_C2D1", "PLUG_DETECT_DIMM_C2D2", + "PLUG_DETECT_DIMM_C2C1", "PLUG_DETECT_DIMM_C2C2", + "PLUG_DETECT_DIMM_C2B1", "PLUG_DETECT_DIMM_C2B2", + "PLUG_DETECT_DIMM_C2A1", "PLUG_DETECT_DIMM_C2A2", + /* GPORT2 */ + "PEX_CPU2_EVENT_RST", "", + "", "", + /* GPORT3 */ + "LED_ID_DIMM_C2E2", "LED_ID_DIMM_C2E1", + "LED_ID_DIMM_C2F2", "LED_ID_DIMM_C2F1", + "LED_ID_DIMM_C2G2", "LED_ID_DIMM_C2G1", + "LED_ID_DIMM_C2H2", "LED_ID_DIMM_C2H1", + /* GPORT4 */ + "LED_ID_DIMM_C2A2", "LED_ID_DIMM_C2A1", + "LED_ID_DIMM_C2B2", "LED_ID_DIMM_C2B1", + "LED_ID_DIMM_C2C2", "LED_ID_DIMM_C2C1", + "LED_ID_DIMM_C2D2", "LED_ID_DIMM_C2D1", + /* GPORT5 */ + "", "", + "FM_CPU2_SKTOCC_N", "LED_ID_CPU2"; + }; + }; + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + smb_svc_pex_cpu3_led: pinctrl@20 { + compatible = "cypress,cy8c9540"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(V, 3) IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + vdd-supply = <&p3v3_bmc_aux>; + reset-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; + gpio-reserved-ranges = <17 3>; + gpio-line-names = + /* GPORT0 */ + "PLUG_DETECT_DIMM_C3E2", "PLUG_DETECT_DIMM_C3E1", + "PLUG_DETECT_DIMM_C3F2", "PLUG_DETECT_DIMM_C3F1", + "PLUG_DETECT_DIMM_C3G2", "PLUG_DETECT_DIMM_C3G1", + "PLUG_DETECT_DIMM_C3H2", "PLUG_DETECT_DIMM_C3H1", + /* GPORT1 */ + "PLUG_DETECT_DIMM_C3D1", "PLUG_DETECT_DIMM_C3D2", + "PLUG_DETECT_DIMM_C3C1", "PLUG_DETECT_DIMM_C3C2", + "PLUG_DETECT_DIMM_C3B1", "PLUG_DETECT_DIMM_C3B2", + "PLUG_DETECT_DIMM_C3A1", "PLUG_DETECT_DIMM_C3A2", + /* GPORT2 */ + "PEX_CPU3_EVENT_RST", "", + "", "", + /* GPORT3 */ + "LED_ID_DIMM_C3E2", "LED_ID_DIMM_C3E1", + "LED_ID_DIMM_C3F2", "LED_ID_DIMM_C3F1", + "LED_ID_DIMM_C3G2", "LED_ID_DIMM_C3G1", + "LED_ID_DIMM_C3H2", "LED_ID_DIMM_C3H1", + /* GPORT4 */ + "LED_ID_DIMM_C3A2", "LED_ID_DIMM_C3A1", + "LED_ID_DIMM_C3B2", "LED_ID_DIMM_C3B1", + "LED_ID_DIMM_C3C2", "LED_ID_DIMM_C3C1", + "LED_ID_DIMM_C3D2", "LED_ID_DIMM_C3D1", + /* GPORT5 */ + "LED_PWR_DWR_FRNT", "LED_ID_DWR_FRNT_P", + "FM_CPU3_SKTOCC_N", "LED_ID_CPU3"; + }; + }; + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + smb_svc_pex_cpu0_led: pinctrl@20 { + compatible = "cypress,cy8c9540"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(O, 3) IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + vdd-supply = <&p3v3_bmc_aux>; + reset-gpios = <&gpio0 ASPEED_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; + gpio-reserved-ranges = <18 2>, <36 2>; + gpio-line-names = + /* GPORT0 */ + "PLUG_DETECT_DIMM_C0E2", "PLUG_DETECT_DIMM_C0E1", + "PLUG_DETECT_DIMM_C0F2", "PLUG_DETECT_DIMM_C0F1", + "PLUG_DETECT_DIMM_C0G2", "PLUG_DETECT_DIMM_C0G1", + "PLUG_DETECT_DIMM_C0H2", "PLUG_DETECT_DIMM_C0H1", + /* GPORT1 */ + "PLUG_DETECT_DIMM_C0D1", "PLUG_DETECT_DIMM_C0D2", + "PLUG_DETECT_DIMM_C0C1", "PLUG_DETECT_DIMM_C0C2", + "PLUG_DETECT_DIMM_C0B1", "PLUG_DETECT_DIMM_C0B2", + "PLUG_DETECT_DIMM_C0A1", "PLUG_DETECT_DIMM_C0A2", + /* GPORT2 */ + "PEX_CPU0_EVENT_RST", "SVC_PEX_RSSD01_16_RST", + "", "", + /* GPORT3 */ + "LED_ID_DIMM_C0E2", "LED_ID_DIMM_C0E1", + "LED_ID_DIMM_C0F2", "LED_ID_DIMM_C0F1", + "LED_ID_DIMM_C0G2", "LED_ID_DIMM_C0G1", + "LED_ID_DIMM_C0H2", "LED_ID_DIMM_C0H1", + /* GPORT4 */ + "LED_ID_DIMM_C0A2", "LED_ID_DIMM_C0A1", + "LED_ID_DIMM_C0B2", "LED_ID_DIMM_C0B1", + "LED_ID_DIMM_C0C2", "LED_ID_DIMM_C0C1", + "LED_ID_DIMM_C0D2", "LED_ID_DIMM_C0D1", + /* GPORT5 */ + "", "", + "FM_CPU0_SKTOCC_N", "LED_ID_CPU0"; + }; + }; +}; + +&i2c9 { + status = "okay"; + + p1v2_bmc_aux_mon: pmic@60 { + compatible = "maxim,max8952"; + reg = <0x60>; + max8952,default-mode = <3>; + max8952,dvs-mode-microvolt = <1100000>, <1100000>, + <1100000>, <1100000>; + max8952,sync-freq = <0>; + max8952,ramp-speed = <0>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&i2cmux8 { + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + fan10_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan10_ssb: sw0 { + regulator-name = "fan10_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + + }; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + fan12_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan12_ssb: sw0 { + regulator-name = "fan12_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + fan14_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan14_ssb: sw0 { + regulator-name = "fan14_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + fan16_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan16_ssb: sw0 { + regulator-name = "fan16_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + fan18_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan18_ssb: sw0 { + regulator-name = "fan18_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + fan20_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan20_ssb: sw0 { + regulator-name = "fan20_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + fan22_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan22_ssb: sw0 { + regulator-name = "fan22_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + fan24_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan24_ssb: sw0 { + regulator-name = "fan24_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; +}; + +&i2cmux7 { + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + fan17_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan17_ssb: sw0 { + regulator-name = "fan17_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + fan19_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan19_ssb: sw0 { + regulator-name = "fan19_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + fan21_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan21_ssb: sw0 { + regulator-name = "fan21_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + fan23_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan23_ssb: sw0 { + regulator-name = "fan23_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + fan02_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan02_ssb: sw0 { + regulator-name = "fan02_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + fan04_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan04_ssb: sw0 { + regulator-name = "fan04_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + fan06_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan06_ssb: sw0 { + regulator-name = "fan06_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + fan08_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan08_ssb: sw0 { + regulator-name = "fan08_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; +}; + +&i2cmux6 { + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + fan01_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan01_ssb: sw0 { + regulator-name = "fan01_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + fan03_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan03_ssb: sw0 { + regulator-name = "fan03_supply"; + + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + fan05_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan05_ssb: sw0 { + regulator-name = "fan05_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + fan07_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan07_ssb: sw0 { + regulator-name = "fan07_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + fan09_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan09_ssb: sw0 { + regulator-name = "fan09_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + fan11_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan11_ssb: sw0 { + regulator-name = "fan11_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + fan13_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan13_ssb: sw0 { + regulator-name = "fan13_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + fan15_ssb: regulator@3a { + compatible = "maxim,max5978"; + reg = <0x3a>; + vss1-supply = <&p12v>; + interrupt-parent = <&smb_svc_pex_fan_alert>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + + regulators { + sw0_fan15_ssb: sw0 { + regulator-name = "fan15_supply"; + shunt-resistor-micro-ohms = <10000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <3400000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + + }; +}; + +&i2cmux9 { + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd19: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <46 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd19:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd19: sw0 { + regulator-name = "rssd19_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd19: sw1 { + regulator-name = "rssd19_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd18: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <45 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd18:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd18: sw0 { + regulator-name = "rssd18_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd18: sw1 { + regulator-name = "rssd18_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd17: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd17:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd17: sw0 { + regulator-name = "rssd17_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd17: sw1 { + regulator-name = "rssd17_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd20: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <47 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd20:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd20: sw0 { + regulator-name = "rssd20_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd20: sw1 { + regulator-name = "rssd20_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd21: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <48 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd21:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd21: sw0 { + regulator-name = "rssd21_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd21: sw1 { + regulator-name = "rssd21_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd22: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <49 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd22:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd22: sw0 { + regulator-name = "rssd22_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd22: sw1 { + regulator-name = "rssd22_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd24: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <51 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd24:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd24: sw0 { + regulator-name = "rssd24_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd24: sw1 { + regulator-name = "rssd24_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd23: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <50 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd23:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd23: sw0 { + regulator-name = "rssd23_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd23: sw1 { + regulator-name = "rssd23_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; +}; + +&i2cmux10 { + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd25: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <52 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd25:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd25: sw0 { + regulator-name = "rssd25_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd25: sw1 { + regulator-name = "rssd25_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd26: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <53 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd26:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd26: sw0 { + regulator-name = "rssd26_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd26: sw1 { + regulator-name = "rssd26_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd27: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <54 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd27:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd27: sw0 { + regulator-name = "rssd27_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd27: sw1 { + regulator-name = "rssd27_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd32: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <59 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd32:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd32: sw0 { + regulator-name = "rssd32_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd32: sw1 { + regulator-name = "rssd32_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd31: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <58 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd31:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd31: sw0 { + regulator-name = "rssd31_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd31: sw1 { + regulator-name = "rssd31_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd30: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <57 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd30:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd30: sw0 { + regulator-name = "rssd30_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd30: sw1 { + regulator-name = "rssd30_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd29: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <56 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd29:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd29: sw0 { + regulator-name = "rssd29_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd29: sw1 { + regulator-name = "rssd29_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd28: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd17_32>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd28:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd28: sw0 { + regulator-name = "rssd28_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd28: sw1 { + regulator-name = "rssd28_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; +}; + +&i2cmux18 { + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd03: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <46 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd03:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd03: sw0 { + regulator-name = "rssd03_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd03: sw1 { + regulator-name = "rssd03_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd02: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <45 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd02:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd02: sw0 { + regulator-name = "rssd02_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd02: sw1 { + regulator-name = "rssd02_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd01: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd01:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd01: sw0 { + regulator-name = "rssd01_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd01: sw1 { + regulator-name = "rssd01_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd04: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <47 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd04:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd04: sw0 { + regulator-name = "rssd04_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd04: sw1 { + regulator-name = "rssd04_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd05: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <48 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd05:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd05: sw0 { + regulator-name = "rssd05_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd05: sw1 { + regulator-name = "rssd05_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd08: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <51 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd08:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd08: sw0 { + regulator-name = "rssd08_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd08: sw1 { + regulator-name = "rssd08_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd07: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <50 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd07:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd07: sw0 { + regulator-name = "rssd07_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd07: sw1 { + regulator-name = "rssd07_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd06: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <49 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd06:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd06: sw0 { + regulator-name = "rssd06_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd06: sw1 { + regulator-name = "rssd06_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; +}; + +&i2cmux19 { + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd14: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <57 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd14:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd14: sw0 { + regulator-name = "rssd14_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd14: sw1 { + regulator-name = "rssd14_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd13: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <56 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd13:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd13: sw0 { + regulator-name = "rssd13_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd13: sw1 { + regulator-name = "rssd13_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd12: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd12:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd12: sw0 { + regulator-name = "rssd12_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd12: sw1 { + regulator-name = "rssd12_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd11: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <54 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd11:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd11: sw0 { + regulator-name = "rssd11_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd11: sw1 { + regulator-name = "rssd11_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd10: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <53 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd10:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd10: sw0 { + regulator-name = "rssd10_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd10: sw1 { + regulator-name = "rssd10_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd09: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <52 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd09:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd09: sw0 { + regulator-name = "rssd09_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd09: sw1 { + regulator-name = "rssd09_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd15: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <58 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd15:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd15: sw0 { + regulator-name = "rssd15_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd15: sw1 { + regulator-name = "rssd15_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + ssb_rssd16: regulator@3a { + compatible = "maxim,max5970"; + reg = <0x3a>; + interrupt-parent = <&smb_svc_pex_rssd01_16>; + interrupts = <59 IRQ_TYPE_LEVEL_LOW>; + + vss1-supply = <&p3v3_aux>; + vss2-supply = <&p12v>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "rssd16:green:power"; + default-state = "off"; + }; + }; + + regulators { + sw0_ssb_rssd16: sw0 { + regulator-name = "rssd16_12v"; + shunt-resistor-micro-ohms = <9000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <4500000>; + regulator-enable-ramp-delay = <1000>; + }; + sw1_ssb_rssd16: sw1 { + regulator-name = "rssd16_3v3"; + shunt-resistor-micro-ohms = <100000>; + regulator-over-current-protection; + regulator-oc-protection-microamp = <410000>; + regulator-enable-ramp-delay = <1000>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-system1.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-system1.dts index f3efecc7eb8d..360b9ce3c850 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-system1.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-system1.dts @@ -370,17 +370,17 @@ /*K0-K7*/ "","","","","","","","", /*L0-L7*/ "","","","","","","","bmc-ready", /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", + /*N0-N7*/ "fpga-debug-enable","","","","","","","", /*O0-O7*/ "","","","","","","","", /*P0-P7*/ "","","","","","","","bmc-hb", - /*Q0-Q7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","pch-ready","", /*R0-R7*/ "","","","","","","","", /*S0-S7*/ "","","","","","","rear-enc-fault0","rear-enc-id0", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", /*V0-V7*/ "","rtc-battery-voltage-read-enable","","power-chassis-control","","","","", /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","power-chassis-good","","","","","","", + /*X0-X7*/ "fpga-pgood","power-chassis-good","pch-pgood","","","","","", /*Y0-Y7*/ "","","","","","","","", /*Z0-Z7*/ "","","","","","","",""; }; @@ -398,6 +398,12 @@ clk-phase-mmc-hs200 = <180>, <180>; }; +&sgpiom0 { + status = "okay"; + ngpios = <128>; + bus-frequency = <1000000>; +}; + &ibt { status = "okay"; }; @@ -464,6 +470,15 @@ aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; }; +&peci0 { + status = "okay"; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>, <0x81>; +}; + &i2c0 { status = "okay"; @@ -666,22 +681,22 @@ status = "okay"; power-supply@58 { - compatible = "ibm,cffps"; + compatible = "intel,crps185"; reg = <0x58>; }; power-supply@59 { - compatible = "ibm,cffps"; + compatible = "intel,crps185"; reg = <0x59>; }; power-supply@5a { - compatible = "ibm,cffps"; + compatible = "intel,crps185"; reg = <0x5a>; }; power-supply@5b { - compatible = "ibm,cffps"; + compatible = "intel,crps185"; reg = <0x5b>; }; }; @@ -1007,6 +1022,7 @@ &i2c8 { status = "okay"; + bus-frequency = <400000>; i2c-mux@71 { compatible = "nxp,pca9548"; @@ -1468,6 +1484,7 @@ &i2c15 { status = "okay"; + bus-frequency = <400000>; i2c-mux@71 { compatible = "nxp,pca9548"; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts index 983853eedaef..fd361cf073c2 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts @@ -381,7 +381,7 @@ #size-cells = <0>; reg = <5>; - U190_fru@51 { + eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; pagesize = <32>; @@ -460,7 +460,7 @@ status = "okay"; /* MB FRU (U173) @ 0xA2 */ - mb_fru: mb_fru@51 { + mb_fru: eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; pagesize = <32>; @@ -472,7 +472,7 @@ reg = <0x4a>; }; - FP_U4_fru@52 { + eeprom@52 { compatible = "atmel,24c02"; reg = <0x52>; pagesize = <16>; @@ -593,7 +593,7 @@ status = "okay"; /* SCM FRU (U19) @ 0xA2 */ - scm_fru: scm_fru@51 { + scm_fru: eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; pagesize = <32>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts index b8f0b08018a3..98f3e0437704 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts @@ -154,7 +154,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <7>; - at24@50 { + eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; pagesize = <32>; @@ -196,7 +196,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <7>; - at24@50 { + eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; pagesize = <32>; @@ -205,7 +205,7 @@ }; }; }; - at24@50 { + eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; pagesize = <32>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi index 1a5b25b2ea29..16815eede710 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi @@ -291,7 +291,7 @@ /* SMB_BMC_MGMT_LVC3 */ status = "okay"; - at24@50 { + eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; pagesize = <32>; diff --git a/arch/arm/boot/dts/broadcom/Makefile b/arch/arm/boot/dts/broadcom/Makefile index 5881bcc95eba..d23cf466127b 100644 --- a/arch/arm/boot/dts/broadcom/Makefile +++ b/arch/arm/boot/dts/broadcom/Makefile @@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2835-rpi-zero.dtb \ bcm2835-rpi-zero-w.dtb dtb-$(CONFIG_ARCH_BCMBCA) += \ + bcm6846-genexis-xg6846b.dtb \ bcm947622.dtb \ bcm963138.dtb \ bcm963138dvt.dtb \ diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi index 6bf4241fe3b7..c78ed064d166 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include "bcm2835-rpi.dtsi" -#include <dt-bindings/power/raspberrypi-power.h> #include <dt-bindings/reset/raspberrypi,firmware-reset.h> / { @@ -101,7 +100,3 @@ &vchiq { interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; }; - -&xhci { - power-domains = <&power RPI_POWER_DOMAIN_USB>; -}; diff --git a/arch/arm/boot/dts/broadcom/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi index e4e42af21ef3..c06d9f5e53c8 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2711.dtsi @@ -134,7 +134,7 @@ clocks = <&clocks BCM2835_CLOCK_UART>, <&clocks BCM2835_CLOCK_VPU>; clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; + arm,primecell-periphid = <0x00341011>; status = "disabled"; }; @@ -145,7 +145,7 @@ clocks = <&clocks BCM2835_CLOCK_UART>, <&clocks BCM2835_CLOCK_VPU>; clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; + arm,primecell-periphid = <0x00341011>; status = "disabled"; }; @@ -156,7 +156,7 @@ clocks = <&clocks BCM2835_CLOCK_UART>, <&clocks BCM2835_CLOCK_VPU>; clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; + arm,primecell-periphid = <0x00341011>; status = "disabled"; }; @@ -167,7 +167,7 @@ clocks = <&clocks BCM2835_CLOCK_UART>, <&clocks BCM2835_CLOCK_VPU>; clock-names = "uartclk", "apb_pclk"; - arm,primecell-periphid = <0x00241011>; + arm,primecell-periphid = <0x00341011>; status = "disabled"; }; @@ -451,8 +451,6 @@ IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - /* This only applies to the ARMv7 stub */ - arm,cpu-registers-not-fw-configured; }; cpus: cpus { @@ -610,6 +608,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pm BCM2835_POWER_DOMAIN_USB>; /* DWC2 and this IP block share the same USB PHY, * enabling both at the same time results in lockups. * So keep this node disabled and let the bootloader @@ -1177,6 +1176,7 @@ }; &uart0 { + arm,primecell-periphid = <0x00341011>; interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts index 53cb0c58f6d0..3da2daee0c84 100644 --- a/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts +++ b/arch/arm/boot/dts/broadcom/bcm4709-asus-rt-ac3200.dts @@ -124,19 +124,19 @@ }; port@1 { - label = "lan1"; + label = "lan4"; }; port@2 { - label = "lan2"; + label = "lan3"; }; port@3 { - label = "lan3"; + label = "lan2"; }; port@4 { - label = "lan4"; + label = "lan1"; }; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts index 6c666dc7ad23..01ec8c03686a 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac5300.dts @@ -126,11 +126,11 @@ ports { port@0 { - label = "lan4"; + label = "wan"; }; port@1 { - label = "lan3"; + label = "lan1"; }; port@2 { @@ -138,11 +138,11 @@ }; port@3 { - label = "lan1"; + label = "lan3"; }; port@4 { - label = "wan"; + label = "lan4"; }; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts b/arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts index 0bf5106f7012..08abfdc63d18 100644 --- a/arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts +++ b/arch/arm/boot/dts/broadcom/bcm53015-meraki-mr26.dts @@ -59,6 +59,9 @@ &gmac0 { status = "okay"; + + nvmem-cells = <&macaddr_board_config_66>; + nvmem-cell-names = "mac-address"; }; &gmac1 { @@ -102,8 +105,25 @@ }; partition@800000 { + compatible = "linux,ubi"; label = "ubi"; reg = <0x800000 0x7780000>; + + volumes { + ubi-volume-board-config { + volname = "board-config"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_board_config_66: macaddr@66 { + reg = <0x66 0x6>; + }; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm53340-ubnt-unifi-switch8.dts b/arch/arm/boot/dts/broadcom/bcm53340-ubnt-unifi-switch8.dts index 975f854f652f..08cf1220b655 100644 --- a/arch/arm/boot/dts/broadcom/bcm53340-ubnt-unifi-switch8.dts +++ b/arch/arm/boot/dts/broadcom/bcm53340-ubnt-unifi-switch8.dts @@ -32,7 +32,6 @@ &qspi { status = "okay"; - bspi-sel = <0>; flash: flash@0 { compatible = "m25p80"; diff --git a/arch/arm/boot/dts/broadcom/bcm6846-genexis-xg6846b.dts b/arch/arm/boot/dts/broadcom/bcm6846-genexis-xg6846b.dts new file mode 100644 index 000000000000..a3616fb7b3a8 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm6846-genexis-xg6846b.dts @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 Linus Walleij <linus.walleij@linaro.org> + */ + +/dts-v1/; + +#include "bcm6846.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Genexis XG6846B Ethernet layer 2/3 router"; + compatible = "genexis,xg6846b", "brcm,bcm6846", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* Micron D9PTK 256 MB RAM */ + memory@0 { + device_type = "memory"; + reg = <0x0 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + secondary-boot@0 { + no-map; + reg = <0x00000000 0x00008000>; + }; + pmc3-firmware@8000 { + no-map; + reg = <0x00008000 0x00100000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys-polled"; + poll-interval = <20000>; + + /* Called "canyon rescue button" in the vendor DTB */ + button-restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 41 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; + /* Totally 79 GPIOs are available */ + ngpios = <15>; +}; + +&uart0 { + status = "okay"; +}; + +&leds { + status = "okay"; + brcm,serial-shift-bits = <16>; + + led@0 { + reg = <0>; + active-low; + function = "ext"; + color = <LED_COLOR_ID_GREEN>; + }; + + led@1 { + reg = <1>; + active-low; + function = "ext"; + color = <LED_COLOR_ID_AMBER>; + }; + + led@3 { + reg = <3>; + active-low; + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_AMBER>; + }; + + led@4 { + reg = <4>; + active-low; + function = LED_FUNCTION_WAN; + color = <LED_COLOR_ID_GREEN>; + }; + + led@5 { + reg = <5>; + active-low; + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_GREEN>; + }; + + led@6 { + reg = <6>; + active-low; + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_RED>; + }; + + led@15 { + reg = <15>; + active-low; + function = LED_FUNCTION_USB; + color = <LED_COLOR_ID_GREEN>; + }; + + led@7 { + /* Activity 03 */ + reg = <7>; + active-low; + function = "lan1"; + color = <LED_COLOR_ID_AMBER>; + }; + + led@8 { + /* Activity 04 */ + reg = <8>; + active-low; + function = "lan1"; + color = <LED_COLOR_ID_GREEN>; + }; + + led@9 { + /* Activity 03 */ + reg = <9>; + active-low; + function = "lan2"; + color = <LED_COLOR_ID_AMBER>; + }; + + led@10 { + /* Activity 04 */ + reg = <10>; + active-low; + function = "lan2"; + color = <LED_COLOR_ID_GREEN>; + }; + + led@11 { + /* Activity 03 */ + reg = <11>; + active-low; + function = "lan3"; + color = <LED_COLOR_ID_AMBER>; + }; + + led@12 { + /* Activity 04 */ + reg = <12>; + active-low; + function = "lan3"; + color = <LED_COLOR_ID_GREEN>; + }; + + led@13 { + /* Activity 03 */ + reg = <13>; + active-low; + function = "lan4"; + color = <LED_COLOR_ID_AMBER>; + }; + + led@14 { + /* Activity 04 */ + reg = <14>; + active-low; + function = "lan4"; + color = <LED_COLOR_ID_GREEN>; + }; +}; + +&hsspi { + status = "okay"; +}; + +&nand_controller { + brcm,wp-not-connected; + status = "okay"; +}; + +&nandcs { + nand-on-flash-bbt; + brcm,nand-ecc-use-strap; + + /* Winbond W29N02GV, 256MB with 128KB erase blocks */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x00000000 0x00400000>; + }; + image@400000 { + label = "image"; + reg = <0x00400000 0x0fb00000>; + }; + /* 0x00ff0000-0x00ffffff: bad block list */ + }; +}; + +&mdio { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy2: ethernet-phy@2 { + reg = <2>; + }; + phy3: ethernet-phy@3 { + reg = <3>; + }; + phy4: ethernet-phy@4 { + reg = <4>; + }; + phy21: ethernet-phy@21 { + reg = <21>; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm6846.dtsi b/arch/arm/boot/dts/broadcom/bcm6846.dtsi index ee361cb00b7c..e0e06af3fe89 100644 --- a/arch/arm/boot/dts/broadcom/bcm6846.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm6846.dtsi @@ -99,6 +99,91 @@ #size-cells = <1>; ranges = <0 0xff800000 0x800000>; + watchdog@480 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x480 0x10>; + }; + + /* GPIOs 0 .. 31 */ + gpio0: gpio@500 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x500 0x04>, <0x520 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 32 .. 63 */ + gpio1: gpio@504 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x504 0x04>, <0x524 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 64 .. 95 */ + gpio2: gpio@508 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x508 0x04>, <0x528 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 96 .. 127 */ + gpio3: gpio@50c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x50c 0x04>, <0x52c 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 128 .. 159 */ + gpio4: gpio@510 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x510 0x04>, <0x530 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 160 .. 191 */ + gpio5: gpio@514 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x514 0x04>, <0x534 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 192 .. 223 */ + gpio6: gpio@518 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x518 0x04>, <0x538 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + /* GPIOs 224 .. 255 */ + gpio7: gpio@51c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x51c 0x04>, <0x53c 0x04>; + reg-names = "dirout", "dat"; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + uart0: serial@640 { compatible = "brcm,bcm6345-uart"; reg = <0x640 0x1b>; @@ -108,6 +193,19 @@ status = "disabled"; }; + rng@b80 { + compatible = "brcm,iproc-rng200"; + reg = <0xb80 0x28>; + }; + + leds: led-controller@800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63138-leds"; + reg = <0x800 0xdc>; + status = "disabled"; + }; + hsspi: spi@1000 { #address-cells = <1>; #size-cells = <0>; @@ -133,5 +231,27 @@ reg = <0>; }; }; + + mdio: mdio@2060 { + compatible = "brcm,bcm6846-mdio"; + reg = <0x02060 0x10>, <0x5a068 0x4>; + reg-names = "mdio", "mdio_indir_rw"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pl081_dma: dma-controller@59000 { + compatible = "arm,pl081", "arm,primecell"; + // The magic B105F00D info is missing + arm,primecell-periphid = <0x00041081>; + reg = <0x59000 0x1000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + clocks = <&periph_clk>; + clock-names = "apb_pclk"; + #dma-cells = <2>; + }; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm953012hr.dts b/arch/arm/boot/dts/broadcom/bcm953012hr.dts index b070b69466bd..b728cd54715e 100644 --- a/arch/arm/boot/dts/broadcom/bcm953012hr.dts +++ b/arch/arm/boot/dts/broadcom/bcm953012hr.dts @@ -74,7 +74,6 @@ &spi_nor { status = "okay"; spi-max-frequency = <62500000>; - m25p,default-addr-width = <3>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/broadcom/bcm953012k.dts b/arch/arm/boot/dts/broadcom/bcm953012k.dts index f1e6bcaa1edd..27c0992f1855 100644 --- a/arch/arm/boot/dts/broadcom/bcm953012k.dts +++ b/arch/arm/boot/dts/broadcom/bcm953012k.dts @@ -84,7 +84,6 @@ &spi_nor { status = "okay"; spi-max-frequency = <62500000>; - m25p,default-addr-width = <3>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/broadcom/bcm958522er.dts b/arch/arm/boot/dts/broadcom/bcm958522er.dts index 15f023656df0..2f20f86bd31c 100644 --- a/arch/arm/boot/dts/broadcom/bcm958522er.dts +++ b/arch/arm/boot/dts/broadcom/bcm958522er.dts @@ -135,7 +135,6 @@ &qspi { status = "okay"; - bspi-sel = <0>; flash: flash@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/broadcom/bcm958525er.dts b/arch/arm/boot/dts/broadcom/bcm958525er.dts index 9b9c225a1fb3..980c03f74a19 100644 --- a/arch/arm/boot/dts/broadcom/bcm958525er.dts +++ b/arch/arm/boot/dts/broadcom/bcm958525er.dts @@ -135,7 +135,6 @@ &qspi { status = "okay"; - bspi-sel = <0>; flash: flash@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/broadcom/bcm958525xmc.dts b/arch/arm/boot/dts/broadcom/bcm958525xmc.dts index ca9311452739..440bb2d617f2 100644 --- a/arch/arm/boot/dts/broadcom/bcm958525xmc.dts +++ b/arch/arm/boot/dts/broadcom/bcm958525xmc.dts @@ -151,7 +151,6 @@ &qspi { status = "okay"; - bspi-sel = <0>; flash: flash@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/broadcom/bcm958622hr.dts b/arch/arm/boot/dts/broadcom/bcm958622hr.dts index 9db3c851451a..116f3a7c3bc6 100644 --- a/arch/arm/boot/dts/broadcom/bcm958622hr.dts +++ b/arch/arm/boot/dts/broadcom/bcm958622hr.dts @@ -139,7 +139,6 @@ &qspi { status = "okay"; - bspi-sel = <0>; flash: flash@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/broadcom/bcm958623hr.dts b/arch/arm/boot/dts/broadcom/bcm958623hr.dts index 32786e7c4e12..fc6ab73ecf56 100644 --- a/arch/arm/boot/dts/broadcom/bcm958623hr.dts +++ b/arch/arm/boot/dts/broadcom/bcm958623hr.dts @@ -143,7 +143,6 @@ &qspi { status = "okay"; - bspi-sel = <0>; flash: flash@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/broadcom/bcm958625hr.dts b/arch/arm/boot/dts/broadcom/bcm958625hr.dts index 74263d98de73..a9b6aa04d573 100644 --- a/arch/arm/boot/dts/broadcom/bcm958625hr.dts +++ b/arch/arm/boot/dts/broadcom/bcm958625hr.dts @@ -150,7 +150,6 @@ &qspi { status = "okay"; - bspi-sel = <0>; flash: flash@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/broadcom/bcm958625k.dts b/arch/arm/boot/dts/broadcom/bcm958625k.dts index 69ebc7a913a7..7996116fc923 100644 --- a/arch/arm/boot/dts/broadcom/bcm958625k.dts +++ b/arch/arm/boot/dts/broadcom/bcm958625k.dts @@ -154,7 +154,6 @@ &qspi { status = "okay"; - bspi-sel = <0>; flash: flash@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/broadcom/bcm988312hr.dts b/arch/arm/boot/dts/broadcom/bcm988312hr.dts index e96bc3f2d5cf..663a3f27b6e4 100644 --- a/arch/arm/boot/dts/broadcom/bcm988312hr.dts +++ b/arch/arm/boot/dts/broadcom/bcm988312hr.dts @@ -139,7 +139,6 @@ &qspi { status = "okay"; - bspi-sel = <0>; flash: flash@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 6b6e77596ffa..b108265e9bde 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -440,7 +440,7 @@ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "ahb"; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -460,7 +460,7 @@ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "ahb"; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -480,7 +480,7 @@ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "ahb"; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts index ceaec29770c6..c1e1264bcb09 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts @@ -50,8 +50,6 @@ stmpe1: stmpe811@41 { compatible = "st,stmpe811"; - #address-cells = <1>; - #size-cells = <0>; reg = <0x41>; id = <0>; blocks = <0x5>; diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts index d37a982e8571..97622febc44e 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dts @@ -151,12 +151,6 @@ &spi0 { status = "okay"; - - spidev@0 { - compatible = "rohm,dh2228fv"; - reg = <0>; - spi-max-frequency = <1000000>; - }; }; &usb1 { diff --git a/arch/arm/boot/dts/marvell/mmp2-olpc-xo-1-75.dts b/arch/arm/boot/dts/marvell/mmp2-olpc-xo-1-75.dts index 55ea87870af3..86c425b72fa7 100644 --- a/arch/arm/boot/dts/marvell/mmp2-olpc-xo-1-75.dts +++ b/arch/arm/boot/dts/marvell/mmp2-olpc-xo-1-75.dts @@ -113,8 +113,8 @@ "Headphones", "HPOR", "MIC2", "Mic Jack"; widgets = "Headphone", "Headphones", "Microphone", "Mic Jack"; - hp-det-gpio = <&gpio 97 GPIO_ACTIVE_HIGH>; - mic-det-gpio = <&gpio 96 GPIO_ACTIVE_HIGH>; + hp-det-gpios = <&gpio 97 GPIO_ACTIVE_HIGH>; + mic-det-gpios = <&gpio 96 GPIO_ACTIVE_HIGH>; }; soc { diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi index 814586abc297..fd7a89cc337d 100644 --- a/arch/arm/boot/dts/mediatek/mt7623.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi @@ -308,7 +308,7 @@ clock-names = "spi", "wrap"; }; - cir: cir@10013000 { + cir: ir-receiver@10013000 { compatible = "mediatek,mt7623-cir"; reg = <0 0x10013000 0 0x1000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile index 470fe46433a9..79cd38fdc7da 100644 --- a/arch/arm/boot/dts/microchip/Makefile +++ b/arch/arm/boot/dts/microchip/Makefile @@ -12,6 +12,7 @@ DTC_FLAGS_at91-sama5d2_xplained := -@ DTC_FLAGS_at91-sama5d3_eds := -@ DTC_FLAGS_at91-sama5d3_xplained := -@ DTC_FLAGS_at91-sama5d4_xplained := -@ +DTC_FLAGS_at91-sama7d65_curiosity := -@ DTC_FLAGS_at91-sama7g54_curiosity := -@ DTC_FLAGS_at91-sama7g5ek := -@ dtb-$(CONFIG_SOC_AT91RM9200) += \ @@ -90,6 +91,8 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d4_xplained.dtb \ at91-sama5d4ek.dtb \ at91-vinco.dtb +dtb-$(CONFIG_SOC_SAMA7D65) += \ + at91-sama7d65_curiosity.dtb dtb-$(CONFIG_SOC_SAMA7G5) += \ at91-sama7g54_curiosity.dtb \ at91-sama7g5ek.dtb diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts index 87b6ea97590b..1a6a909a5043 100644 --- a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts @@ -88,8 +88,6 @@ }; &i2c6 { - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx6_default>; i2c-analog-filter; @@ -200,6 +198,52 @@ }; }; +&flx7 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>; + status = "okay"; +}; + +&i2c7 { + dmas = <0>, <0>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx7_default>; + status = "okay"; + + power-monitor@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <0x1>; + shunt-resistor-micro-ohms = <10000>; + label = "VDD3V3"; + }; + + channel@2 { + reg = <0x2>; + shunt-resistor-micro-ohms = <10000>; + label = "DCDC4"; + }; + + channel@3 { + reg = <0x3>; + shunt-resistor-micro-ohms = <10000>; + label = "VDDCORE"; + }; + + channel@4 { + reg = <0x4>; + shunt-resistor-micro-ohms = <10000>; + label = "VDDIODDR"; + }; + }; +}; + &i2s { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2s_default>; @@ -233,6 +277,12 @@ <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; }; + + pinctrl_flx7_default: flx7-default { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>, + <AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; + }; }; gpio-keys { diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts index 15239834d886..35a933eec573 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_wlsom1_ek.dts @@ -197,6 +197,7 @@ &sdmmc0 { bus-width = <4>; + no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc0_default>; status = "okay"; diff --git a/arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dts index b6684bf67d3e..7be215781549 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d29_curiosity.dts @@ -514,6 +514,7 @@ &sdmmc0 { bus-width = <4>; + no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc0_default>; disable-wp; diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts new file mode 100644 index 000000000000..0f86360fb733 --- /dev/null +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama7d65_curiosity.dts - Device Tree file for SAMA7D65 Curiosity board + * + * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Romain Sioen <romain.sioen@microchip.com> + * + */ +/dts-v1/; +#include "sama7d65-pinfunc.h" +#include "sama7d65.dtsi" +#include <dt-bindings/mfd/atmel-flexcom.h> +#include <dt-bindings/pinctrl/at91.h> + +/ { + model = "Microchip SAMA7D65 Curiosity"; + compatible = "microchip,sama7d65-curiosity", "microchip,sama7d65", + "microchip,sama7d6", "microchip,sama7"; + + aliases { + serial0 = &uart6; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; +}; + +&flx6 { + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6_default>; + status = "okay"; +}; + +&main_xtal { + clock-frequency = <24000000>; +}; + +&pioa { + pinctrl_sdmmc1_default: sdmmc1-default { + cmd-data { + pinmux = <PIN_PB22__SDMMC1_CMD>, + <PIN_PB24__SDMMC1_DAT0>, + <PIN_PB25__SDMMC1_DAT1>, + <PIN_PB26__SDMMC1_DAT2>, + <PIN_PB27__SDMMC1_DAT3>; + slew-rate = <0>; + bias-disable; + }; + + ck-cd-rstn-vddsel { + pinmux = <PIN_PB23__SDMMC1_CK>, + <PIN_PB21__SDMMC1_RSTN>, + <PIN_PB30__SDMMC1_1V8SEL>, + <PIN_PB29__SDMMC1_CD>, + <PIN_PB28__SDMMC1_WP>; + slew-rate = <0>; + bias-disable; + }; + }; + + pinctrl_uart6_default: uart6-default { + pinmux = <PIN_PD18__FLEXCOM6_IO0>, + <PIN_PD19__FLEXCOM6_IO1>; + bias-disable; + }; +}; + +&sdmmc1 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + status = "okay"; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; diff --git a/arch/arm/boot/dts/microchip/sam9x60.dtsi b/arch/arm/boot/dts/microchip/sam9x60.dtsi index 36944e18a329..b8b2c1ddf3f1 100644 --- a/arch/arm/boot/dts/microchip/sam9x60.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x60.dtsi @@ -197,6 +197,8 @@ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "spi_clk"; dmas = <&dma0 @@ -268,6 +270,8 @@ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "spi_clk"; dmas = <&dma0 @@ -768,6 +772,8 @@ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; clock-names = "spi_clk"; dmas = <&dma0 @@ -839,6 +845,8 @@ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "spi_clk"; dmas = <&dma0 @@ -910,6 +918,8 @@ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "spi_clk"; dmas = <&dma0 @@ -981,6 +991,8 @@ compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "spi_clk"; dmas = <&dma0 diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi index beb1f34b38d3..b217a908f525 100644 --- a/arch/arm/boot/dts/microchip/sam9x7.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -132,6 +132,8 @@ compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "spi_clk"; dmas = <&dma0 @@ -151,6 +153,8 @@ compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | @@ -201,6 +205,8 @@ compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "spi_clk"; dmas = <&dma0 @@ -220,6 +226,8 @@ compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | @@ -312,6 +320,8 @@ compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | @@ -362,6 +372,8 @@ compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | @@ -533,6 +545,8 @@ compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | @@ -583,6 +597,8 @@ compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | @@ -633,6 +649,8 @@ compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | @@ -683,6 +701,8 @@ compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; clock-names = "spi_clk"; dmas = <&dma0 @@ -702,6 +722,8 @@ compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | @@ -752,6 +774,8 @@ compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "spi_clk"; dmas = <&dma0 @@ -771,6 +795,8 @@ compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | @@ -821,6 +847,8 @@ compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "spi_clk"; dmas = <&dma0 @@ -840,6 +868,8 @@ compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | @@ -890,6 +920,8 @@ compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "spi_clk"; dmas = <&dma0 @@ -909,6 +941,8 @@ compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | @@ -984,6 +1018,8 @@ compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | @@ -1034,6 +1070,8 @@ compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | diff --git a/arch/arm/boot/dts/microchip/sama7d65-pinfunc.h b/arch/arm/boot/dts/microchip/sama7d65-pinfunc.h new file mode 100644 index 000000000000..c591f333cacb --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama7d65-pinfunc.h @@ -0,0 +1,947 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +#define PINMUX_PIN(no, func, ioset) \ +(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) + +#define PIN_PA0 0 +#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) +#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) +#define PIN_PA0__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA0, 2, 1) +#define PIN_PA0__NWER0 PINMUX_PIN(PIN_PA0, 3, 1) + +#define PIN_PA1 1 +#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) +#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) +#define PIN_PA1__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA1, 2, 1) +#define PIN_PA1__A21 PINMUX_PIN(PIN_PA1, 3, 1) + +#define PIN_PA2 2 +#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) +#define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1) +#define PIN_PA2__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA2, 2, 1) +#define PIN_PA2__A22 PINMUX_PIN(PIN_PA2, 3, 1) + +#define PIN_PA3 3 +#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) +#define PIN_PA3__SDMMC0_DAT0 PINMUX_PIN(PIN_PA3, 1, 1) +#define PIN_PA3__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA3, 2, 1) +#define PIN_PA3__D0 PINMUX_PIN(PIN_PA3, 3, 1) + +#define PIN_PA4 4 +#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) +#define PIN_PA4__SDMMC0_DAT1 PINMUX_PIN(PIN_PA4, 1, 1) +#define PIN_PA4__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA4, 2, 1) +#define PIN_PA4__D1 PINMUX_PIN(PIN_PA4, 3, 1) + +#define PIN_PA5 5 +#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) +#define PIN_PA5__SDMMC0_DAT4 PINMUX_PIN(PIN_PA5, 1, 1) +#define PIN_PA5__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA5, 2, 3) +#define PIN_PA5__D4 PINMUX_PIN(PIN_PA5, 3, 1) +#define PIN_PA5__TCLK4 PINMUX_PIN(PIN_PA5, 6, 3) + +#define PIN_PA6 6 +#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) +#define PIN_PA6__SDMMC0_DAT5 PINMUX_PIN(PIN_PA6, 1, 1) +#define PIN_PA6__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA6, 2, 3) +#define PIN_PA6__D5 PINMUX_PIN(PIN_PA6, 3, 1) +#define PIN_PA6__TIOB4 PINMUX_PIN(PIN_PA6, 6, 3) + +#define PIN_PA7 7 +#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) +#define PIN_PA7__SDMMC0_DAT6 PINMUX_PIN(PIN_PA7, 1, 1) +#define PIN_PA7__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA7, 2, 3) +#define PIN_PA7__D6 PINMUX_PIN(PIN_PA7, 3, 1) +#define PIN_PA7__TIOA4 PINMUX_PIN(PIN_PA7, 6, 3) + +#define PIN_PA8 8 +#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) +#define PIN_PA8__SDMMC0_DAT7 PINMUX_PIN(PIN_PA8, 1, 1) +#define PIN_PA8__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA8, 2, 3) +#define PIN_PA8__D7 PINMUX_PIN(PIN_PA8, 3, 1) +#define PIN_PA8__TIOA5 PINMUX_PIN(PIN_PA8, 6, 3) + +#define PIN_PA9 9 +#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) +#define PIN_PA9__SDMMC0_DAT2 PINMUX_PIN(PIN_PA9, 1, 1) +#define PIN_PA9__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA9, 2, 1) +#define PIN_PA9__D2 PINMUX_PIN(PIN_PA9, 3, 1) +#define PIN_PA9__TIOB5 PINMUX_PIN(PIN_PA9, 6, 3) + +#define PIN_PA10 10 +#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) +#define PIN_PA10__SDMMC0_DAT3 PINMUX_PIN(PIN_PA10, 1, 1) +#define PIN_PA10__FLEXCOM0_IO3 PINMUX_PIN(PIN_PA10, 2, 1) +#define PIN_PA10__D3 PINMUX_PIN(PIN_PA10, 3, 1) +#define PIN_PA10__TCLK5 PINMUX_PIN(PIN_PA10, 6, 3) + +#define PIN_PA11 11 +#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) +#define PIN_PA11__SDMMC0_DS PINMUX_PIN(PIN_PA11, 1, 1) +#define PIN_PA11__FLEXCOM0_IO4 PINMUX_PIN(PIN_PA11, 2, 1) +#define PIN_PA11__NANDRDY PINMUX_PIN(PIN_PA11, 3, 1) +#define PIN_PA11__TIOB3 PINMUX_PIN(PIN_PA11, 6, 3) + +#define PIN_PA12 12 +#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) +#define PIN_PA12__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA12, 2, 1) +#define PIN_PA12__NRD PINMUX_PIN(PIN_PA12, 3, 1) +#define PIN_PA12__PCK0 PINMUX_PIN(PIN_PA12, 4, 1) +#define PIN_PA12__EXT_IRQ0 PINMUX_PIN(PIN_PA12, 5, 1) +#define PIN_PA12__TIOA3 PINMUX_PIN(PIN_PA12, 6, 3) + +#define PIN_PA13 13 +#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) +#define PIN_PA13__FLEXCOM0_IO1 PINMUX_PIN(PIN_PA13, 2, 1) +#define PIN_PA13__NCS0 PINMUX_PIN(PIN_PA13, 3, 1) +#define PIN_PA13__PCK1 PINMUX_PIN(PIN_PA13, 4, 1) +#define PIN_PA13__TCLK3 PINMUX_PIN(PIN_PA13, 6, 3) + +#define PIN_PA14 14 +#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) +#define PIN_PA14__FLEXCOM4_IO4 PINMUX_PIN(PIN_PA14, 1, 1) +#define PIN_PA14__SDMMC0_WP PINMUX_PIN(PIN_PA14, 2, 1) +#define PIN_PA14__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA14, 3, 4) + +#define PIN_PA15 15 +#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) +#define PIN_PA15__FLEXCOM4_IO3 PINMUX_PIN(PIN_PA15, 1, 1) +#define PIN_PA15__SDMMC0_1V8SEL PINMUX_PIN(PIN_PA15, 2, 1) +#define PIN_PA15__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA15, 3, 4) + +#define PIN_PA16 16 +#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) +#define PIN_PA16__FLEXCOM4_IO2 PINMUX_PIN(PIN_PA16, 1, 1) +#define PIN_PA16__SDMMCo_CD PINMUX_PIN(PIN_PA16, 2, 1) +#define PIN_PA16__PCK2 PINMUX_PIN(PIN_PA16, 4, 1) +#define PIN_PA16__EXT_IRQ1 PINMUX_PIN(PIN_PA16, 5, 1) + +#define PIN_PA17 17 +#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) +#define PIN_PA17__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA17, 1, 1) + +#define PIN_PA18 18 +#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) +#define PIN_PA18__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA18, 1, 1) + +#define PIN_PA19 19 +#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) +#define PIN_PA19__TK0 PINMUX_PIN(PIN_PA19, 1, 1) +#define PIN_PA19__FLEXCOM4_IO5 PINMUX_PIN(PIN_PA19, 3, 1) +#define PIN_PA19__PWML0 PINMUX_PIN(PIN_PA19, 4, 3) + +#define PIN_PA20 20 +#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) +#define PIN_PA20__TD0 PINMUX_PIN(PIN_PA20, 1, 1) +#define PIN_PA20__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA20, 2, 2) +#define PIN_PA20__FLEXCOM4_IO6 PINMUX_PIN(PIN_PA20, 3, 1) +#define PIN_PA20__PWMH0 PINMUX_PIN(PIN_PA20, 4, 3) + +#define PIN_PA21 21 +#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) +#define PIN_PA21__TF0 PINMUX_PIN(PIN_PA21, 1, 1) +#define PIN_PA21__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA21, 2, 2) +#define PIN_PA21__PWML1 PINMUX_PIN(PIN_PA21, 4, 3) + +#define PIN_PA22 22 +#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) +#define PIN_PA22__RD0 PINMUX_PIN(PIN_PA22, 1, 1) +#define PIN_PA22__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA22, 2, 2) +#define PIN_PA22__PDMC0_DS1 PINMUX_PIN(PIN_PA22, 3, 1) +#define PIN_PA22__PWMH1 PINMUX_PIN(PIN_PA22, 4, 3) + +#define PIN_PA23 23 +#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) +#define PIN_PA23__RK0 PINMUX_PIN(PIN_PA23, 1, 1) +#define PIN_PA23__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA23, 2, 2) +#define PIN_PA23__PDMC0_CLK PINMUX_PIN(PIN_PA23, 3, 1) +#define PIN_PA23__PWML2 PINMUX_PIN(PIN_PA23, 4, 3) + +#define PIN_PA24 24 +#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) +#define PIN_PA24__RF0 PINMUX_PIN(PIN_PA24, 1, 1) +#define PIN_PA24__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA24, 2, 2) +#define PIN_PA24__PDMC0_DS0 PINMUX_PIN(PIN_PA24, 3, 1) +#define PIN_PA24__PWMH2 PINMUX_PIN(PIN_PA24, 4, 3) + +#define PIN_PA25 25 +#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) +#define PIN_PA25__G0_TXCTL PINMUX_PIN(PIN_PA25, 1, 1) +#define PIN_PA25__FLEXCOM6_IO2 PINMUX_PIN(PIN_PA25, 2, 1) + +#define PIN_PA26 26 +#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) +#define PIN_PA26__G0_TX0 PINMUX_PIN(PIN_PA26, 1, 1) +#define PIN_PA26__FLEXCOM6_IO3 PINMUX_PIN(PIN_PA26, 2, 1) + +#define PIN_PA27 27 +#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) +#define PIN_PA27__G0_TX1 PINMUX_PIN(PIN_PA27, 1, 1) +#define PIN_PA27__FLEXCOM6_IO4 PINMUX_PIN(PIN_PA27, 2, 1) + +#define PIN_PA28 28 +#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) +#define PIN_PA28__G0_RXCTL PINMUX_PIN(PIN_PA28, 1, 1) +#define PIN_PA28__FLEXCOM6_IO0 PINMUX_PIN(PIN_PA28, 2, 1) + +#define PIN_PA29 29 +#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) +#define PIN_PA29__G0_RX0 PINMUX_PIN(PIN_PA29, 1, 1) +#define PIN_PA29__FLEXCOM6_IO1 PINMUX_PIN(PIN_PA29, 2, 1) + +#define PIN_PA30 30 +#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) +#define PIN_PA30__G0_RX1 PINMUX_PIN(PIN_PA30, 1, 1) +#define PIN_PA30__FLEXCOM8_IO0 PINMUX_PIN(PIN_PA30, 2, 1) + +#define PIN_PA31 31 +#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) +#define PIN_PA31__G0_MDC PINMUX_PIN(PIN_PA31, 1, 1) +#define PIN_PA31__FLEXCOM8_IO1 PINMUX_PIN(PIN_PA31, 2, 1) + +#define PIN_PB0 32 +#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) +#define PIN_PB0__G0_MDIO PINMUX_PIN(PIN_PB0, 1, 1) +#define PIN_PB0__FLEXCOM8_IO3 PINMUX_PIN(PIN_PB0, 2, 2) + +#define PIN_PB1 33 +#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) +#define PIN_PB1__G0_REFCK PINMUX_PIN(PIN_PB1, 1, 2) +#define PIN_PB1__FLEXCOM8_IO2 PINMUX_PIN(PIN_PB1, 2, 1) + +#define PIN_PB2 34 +#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) +#define PIN_PB2__G0_RX2 PINMUX_PIN(PIN_PB2, 1, 1) +#define PIN_PB2__FLEXCOM8_IO4 PINMUX_PIN(PIN_PB2, 2, 1) +#define PIN_PB2__G0_RXER PINMUX_PIN(PIN_PB2, 3, 2) +#define PIN_PB2__RK0 PINMUX_PIN(PIN_PB2, 4, 2) + +#define PIN_PB3 35 +#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) +#define PIN_PB3__G0_RXCK PINMUX_PIN(PIN_PB3, 1, 1) +#define PIN_PB3__FLEXCOM10_IO2 PINMUX_PIN(PIN_PB3, 2, 2) +#define PIN_PB3__TK0 PINMUX_PIN(PIN_PB3, 4, 2) + +#define PIN_PB4 36 +#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) +#define PIN_PB4__G0_TX2 PINMUX_PIN(PIN_PB4, 1, 1) +#define PIN_PB4__FLEXCOM10_IO3 PINMUX_PIN(PIN_PB4, 2, 2) +#define PIN_PB4__TF0 PINMUX_PIN(PIN_PB4, 4, 2) + +#define PIN_PB5 37 +#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) +#define PIN_PB5__G0_TX3 PINMUX_PIN(PIN_PB5, 1, 1) +#define PIN_PB5__FLEXCOM10_IO4 PINMUX_PIN(PIN_PB5, 2, 1) +#define PIN_PB5__TD0 PINMUX_PIN(PIN_PB5, 4, 2) + +#define PIN_PB6 38 +#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) +#define PIN_PB6__G0_RX3 PINMUX_PIN(PIN_PB6, 1, 1) +#define PIN_PB6__FLEXCOM10_IO0 PINMUX_PIN(PIN_PB6, 2, 2) +#define PIN_PB6__RD0 PINMUX_PIN(PIN_PB6, 4, 2) + +#define PIN_PB7 39 +#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) +#define PIN_PB7__G0_TSUCOMP PINMUX_PIN(PIN_PB7, 1, 1) +#define PIN_PB7__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB7, 2, 2) +#define PIN_PB7__ADTRG PINMUX_PIN(PIN_PB7, 3, 1) +#define PIN_PB7__RF0 PINMUX_PIN(PIN_PB7, 4, 2) + +#define PIN_PB8 40 +#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) +#define PIN_PB8__QSPI0_IO3 PINMUX_PIN(PIN_PB8, 1, 1) +#define PIN_PB8__PCK3 PINMUX_PIN(PIN_PB8, 2, 1) +#define PIN_PB8__FLEXCOM2_IO1 PINMUX_PIN(PIN_PB8, 4, 2) + +#define PIN_PB9 41 +#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) +#define PIN_PB9__QSPI0_IO2 PINMUX_PIN(PIN_PB9, 1, 1) +#define PIN_PB9__FLEXCOM2_IO0 PINMUX_PIN(PIN_PB9, 4, 2) +#define PIN_PB9__PWMEXTRG0 PINMUX_PIN(PIN_PB9, 5, 1) + +#define PIN_PB10 42 +#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) +#define PIN_PB10__QSPI0_IO1 PINMUX_PIN(PIN_PB10, 1, 1) +#define PIN_PB10__FLEXCOM2_IO4 PINMUX_PIN(PIN_PB10, 4, 2) +#define PIN_PB10__PWMEXTRG1 PINMUX_PIN(PIN_PB10, 5, 1) + +#define PIN_PB11 43 +#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) +#define PIN_PB11__QSPI0_IO0 PINMUX_PIN(PIN_PB11, 1, 1) +#define PIN_PB11__FLEXCOM2_IO5 PINMUX_PIN(PIN_PB11, 4, 2) +#define PIN_PB11__PWML3 PINMUX_PIN(PIN_PB11, 5, 1) +#define PIN_PB11__TIOB3 PINMUX_PIN(PIN_PB11, 6, 2) + +#define PIN_PB12 44 +#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) +#define PIN_PB12__QSPI0_CS PINMUX_PIN(PIN_PB12, 1, 1) +#define PIN_PB12__FLEXCOM2_IO3 PINMUX_PIN(PIN_PB12, 4, 2) +#define PIN_PB12__PWMFI1 PINMUX_PIN(PIN_PB12, 6, 1) +#define PIN_PB12__TIOA3 PINMUX_PIN(PIN_PB12, 6, 2) + +#define PIN_PB13 45 +#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) +#define PIN_PB13__QSPI0_SCK PINMUX_PIN(PIN_PB13, 1, 1) +#define PIN_PB13__FLEXCOM2_IO2 PINMUX_PIN(PIN_PB13, 4, 2) +#define PIN_PB13__PWMFI0 PINMUX_PIN(PIN_PB13, 5, 1) +#define PIN_PB13__TCLK3 PINMUX_PIN(PIN_PB13, 6, 2) + +#define PIN_PB14 46 +#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) +#define PIN_PB14__QSPI0_SCKN PINMUX_PIN(PIN_PB14, 1, 1) +#define PIN_PB14__QSPI1_SCK PINMUX_PIN(PIN_PB14, 2, 1) +#define PIN_PB14__I2SMCC0_CK PINMUX_PIN(PIN_PB14, 3, 3) +#define PIN_PB14__FLEXCOM10_IO5 PINMUX_PIN(PIN_PB14, 4, 1) +#define PIN_PB14__PWMH3 PINMUX_PIN(PIN_PB14, 5, 1) +#define PIN_PB14__FLEXCOM2_IO1 PINMUX_PIN(PIN_PB14, 7, 4) + +#define PIN_PB15 47 +#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) +#define PIN_PB15__QSPI0_IO4 PINMUX_PIN(PIN_PB15, 1, 1) +#define PIN_PB15__QSPI1_IO0 PINMUX_PIN(PIN_PB15, 2, 1) +#define PIN_PB15__I2SMCC0_WS PINMUX_PIN(PIN_PB15, 3, 3) +#define PIN_PB15__FLEXCOM10_IO6 PINMUX_PIN(PIN_PB15, 4, 1) +#define PIN_PB15__PWML0 PINMUX_PIN(PIN_PB15, 5, 1) +#define PIN_PB15__TCLK4 PINMUX_PIN(PIN_PB15, 6, 2) +#define PIN_PB15__FLEXCOM2_IO0 PINMUX_PIN(PIN_PB15, 7, 4) + +#define PIN_PB16 48 +#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) +#define PIN_PB16__QSPI0_IO5 PINMUX_PIN(PIN_PB16, 1, 1) +#define PIN_PB16__QSPI1_IO1 PINMUX_PIN(PIN_PB16, 2, 1) +#define PIN_PB16__I2SMCC0_DIN0 PINMUX_PIN(PIN_PB16, 3, 3) +#define PIN_PB16__FLEXCOM10_IO4 PINMUX_PIN(PIN_PB16, 4, 1) +#define PIN_PB16__PWMH0 PINMUX_PIN(PIN_PB16, 5, 1) +#define PIN_PB16__TIOB4 PINMUX_PIN(PIN_PB16, 6, 2) + +#define PIN_PB17 49 +#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) +#define PIN_PB17__QSPI0_IO6 PINMUX_PIN(PIN_PB17, 1, 1) +#define PIN_PB17__QSPI1_IO2 PINMUX_PIN(PIN_PB17, 2, 1) +#define PIN_PB17__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PB17, 3, 3) +#define PIN_PB17__FLEXCOM10_IO3 PINMUX_PIN(PIN_PB17, 4, 1) +#define PIN_PB17__PWML1 PINMUX_PIN(PIN_PB17, 5, 1) +#define PIN_PB17__TIOA4 PINMUX_PIN(PIN_PB17, 6, 2) + +#define PIN_PB18 50 +#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) +#define PIN_PB18__QSPI0_IO7 PINMUX_PIN(PIN_PB18, 1, 1) +#define PIN_PB18__QSPI1_IO3 PINMUX_PIN(PIN_PB18, 2, 1) +#define PIN_PB18__I2SMCC0_MCK PINMUX_PIN(PIN_PB18, 3, 3) +#define PIN_PB18__FLEXCOM10_IO2 PINMUX_PIN(PIN_PB18, 4, 1) +#define PIN_PB18__PWMH1 PINMUX_PIN(PIN_PB18, 5, 1) +#define PIN_PB18__TIOA5 PINMUX_PIN(PIN_PB18, 6, 2) + +#define PIN_PB19 51 +#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) +#define PIN_PB19__QSPI0_DQS PINMUX_PIN(PIN_PB19, 1, 1) +#define PIN_PB19__EXT_IRQ1 PINMUX_PIN(PIN_PB19, 2, 2) +#define PIN_PB19__PCK4 PINMUX_PIN(PIN_PB19, 3, 1) +#define PIN_PB19__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB19, 4, 1) +#define PIN_PB19__PWML2 PINMUX_PIN(PIN_PB19, 5, 1) +#define PIN_PB19__TIOB5 PINMUX_PIN(PIN_PB19, 6, 2) + +#define PIN_PB20 52 +#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) +#define PIN_PB20__QSPI0_INT PINMUX_PIN(PIN_PB20, 1, 1) +#define PIN_PB20__QSPI1_CS PINMUX_PIN(PIN_PB20, 2, 1) +#define PIN_PB20__FLEXCOM10_IO0 PINMUX_PIN(PIN_PB20, 4, 1) +#define PIN_PB20__PWMH2 PINMUX_PIN(PIN_PB20, 5, 1) +#define PIN_PB20__TCLK5 PINMUX_PIN(PIN_PB20, 6, 2) + +#define PIN_PB21 53 +#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) +#define PIN_PB21__SDMMC1_RSTN PINMUX_PIN(PIN_PB21, 1, 1) +#define PIN_PB21__FLEXCOM6_IO4 PINMUX_PIN(PIN_PB21, 2, 2) +#define PIN_PB21__TIOB2 PINMUX_PIN(PIN_PB21, 3, 2) +#define PIN_PB21__ADTRG PINMUX_PIN(PIN_PB21, 4, 2) +#define PIN_PB21__EXT_IRQ0 PINMUX_PIN(PIN_PB21, 5, 2) + +#define PIN_PB22 54 +#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) +#define PIN_PB22__SDMMC1_CMD PINMUX_PIN(PIN_PB22, 1, 1) +#define PIN_PB22__FLEXCOM6_IO3 PINMUX_PIN(PIN_PB22, 2, 2) +#define PIN_PB22__TCLK2 PINMUX_PIN(PIN_PB22, 3, 2) + +#define PIN_PB23 55 +#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) +#define PIN_PB23__SDMMC1_CK PINMUX_PIN(PIN_PB23, 1, 1) +#define PIN_PB23__FLEXCOM6_IO2 PINMUX_PIN(PIN_PB23, 2, 2) +#define PIN_PB23__TIOA2 PINMUX_PIN(PIN_PB23, 3, 2) + +#define PIN_PB24 56 +#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) +#define PIN_PB24__SDMMC1_DAT0 PINMUX_PIN(PIN_PB24, 1, 1) +#define PIN_PB24__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB24, 2, 2) + +#define PIN_PB25 57 +#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) +#define PIN_PB25__SDMMC1_DAT1 PINMUX_PIN(PIN_PB25, 1, 1) +#define PIN_PB25__FLEXCOM6_IO1 PINMUX_PIN(PIN_PB25, 2, 2) +#define PIN_PB25__TIOB2 PINMUX_PIN(PIN_PB25, 3, 1) + +#define PIN_PB26 58 +#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) +#define PIN_PB26__SDMMC1_DAT2 PINMUX_PIN(PIN_PB26, 1, 1) +#define PIN_PB26__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB26, 2, 3) +#define PIN_PB26__TCLK2 PINMUX_PIN(PIN_PB26, 3, 1) + +#define PIN_PB27 59 +#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) +#define PIN_PB27__SDMMC1_DAT3 PINMUX_PIN(PIN_PB27, 1, 1) +#define PIN_PB27__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB27, 2, 3) +#define PIN_PB27__TIOA2 PINMUX_PIN(PIN_PB27, 3, 1) + +#define PIN_PB28 60 +#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) +#define PIN_PB28__SDMMC1_WP PINMUX_PIN(PIN_PB28, 1, 1) +#define PIN_PB28__FLEXCOM1_IO0 PINMUX_PIN(PIN_PB28, 3, 3) +#define PIN_PB28__D15 PINMUX_PIN(PIN_PB28, 5, 1) + +#define PIN_PB29 61 +#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) +#define PIN_PB29__SDMMC1_CD PINMUX_PIN(PIN_PB29, 1, 1) +#define PIN_PB29__I2SMCC0_MCK PINMUX_PIN(PIN_PB29, 2, 1) +#define PIN_PB29__FLEXCOM1_IO1 PINMUX_PIN(PIN_PB29, 3, 3) +#define PIN_PB29__D14 PINMUX_PIN(PIN_PB29, 5, 2) + +#define PIN_PB30 62 +#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) +#define PIN_PB30__SDMMC1_1V8SEL PINMUX_PIN(PIN_PB30, 1, 1) +#define PIN_PB30__I2SMCC1_MCK PINMUX_PIN(PIN_PB30, 2, 2) +#define PIN_PB30__FLEXCOM1_IO2 PINMUX_PIN(PIN_PB30, 3, 3) +#define PIN_PB30__TIOA1 PINMUX_PIN(PIN_PB30, 4, 1) +#define PIN_PB30__NCS1 PINMUX_PIN(PIN_PB30, 5, 1) + +#define PIN_PB31 63 +#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) +#define PIN_PB31__PCK7 PINMUX_PIN(PIN_PB31, 1, 2) +#define PIN_PB31__I2SMCC1_DIN1 PINMUX_PIN(PIN_PB31, 2, 1) +#define PIN_PB31__FLEXCOM1_IO3 PINMUX_PIN(PIN_PB31, 3, 3) +#define PIN_PB31__TCLK1 PINMUX_PIN(PIN_PB31, 4, 1) +#define PIN_PB31__NWE PINMUX_PIN(PIN_PB31, 5, 2) + +#define PIN_PC0 64 +#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) +#define PIN_PC0__PCK6 PINMUX_PIN(PIN_PC0, 1, 2) +#define PIN_PC0__I2SMCC1_DIN2 PINMUX_PIN(PIN_PC0, 2, 1) +#define PIN_PC0__FLEXCOM9_IO4 PINMUX_PIN(PIN_PC0, 3, 2) +#define PIN_PC0__TIOB1 PINMUX_PIN(PIN_PC0, 4, 1) +#define PIN_PC0__NWR1 PINMUX_PIN(PIN_PC0, 5, 1) + +#define PIN_PC1 65 +#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) +#define PIN_PC1__PCK5 PINMUX_PIN(PIN_PC1, 1, 1) +#define PIN_PC1__FLEXCOM9_IO2 PINMUX_PIN(PIN_PC1, 3, 2) +#define PIN_PC1__SMCK PINMUX_PIN(PIN_PC1, 5, 1) + +#define PIN_PC2 66 +#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) +#define PIN_PC2__EXT_IRQ0 PINMUX_PIN(PIN_PC2, 1, 3) +#define PIN_PC2__FLEXCOM9_IO3 PINMUX_PIN(PIN_PC2, 3, 2) +#define PIN_PC2__A11 PINMUX_PIN(PIN_PC2, 5, 1) + +#define PIN_PC3 67 +#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) +#define PIN_PC3__SPDIF_RX PINMUX_PIN(PIN_PC3, 1, 2) +#define PIN_PC3__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC3, 3, 2) +#define PIN_PC3__FLEXCOM0_IO4 PINMUX_PIN(PIN_PC3, 4, 2) +#define PIN_PC3__A10 PINMUX_PIN(PIN_PC3, 5, 1) + +#define PIN_PC4 68 +#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) +#define PIN_PC4__SPDIF_TX PINMUX_PIN(PIN_PC4, 1, 2) +#define PIN_PC4__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC4, 3, 2) +#define PIN_PC4__FLEXCOM0_IO3 PINMUX_PIN(PIN_PC4, 4, 2) +#define PIN_PC4__D0 PINMUX_PIN(PIN_PC4, 5, 2) + +#define PIN_PC5 69 +#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) +#define PIN_PC5__I3CC_SDASPUE PINMUX_PIN(PIN_PC5, 1, 1) +#define PIN_PC5__I2SMCC1_DIN3 PINMUX_PIN(PIN_PC5, 2, 1) +#define PIN_PC5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PC5, 4, 2) +#define PIN_PC5__D1 PINMUX_PIN(PIN_PC5, 5, 2) + +#define PIN_PC6 70 +#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) +#define PIN_PC6__I3CC_SCL PINMUX_PIN(PIN_PC6, 1, 1) +#define PIN_PC6__FLEXCOM0_IO1 PINMUX_PIN(PIN_PC6, 4, 2) +#define PIN_PC6__D4 PINMUX_PIN(PIN_PC6, 5, 2) + +#define PIN_PC7 71 +#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) +#define PIN_PC7__I3CC_SDA PINMUX_PIN(PIN_PC7, 1, 1) +#define PIN_PC7__FLEXCOM0_IO0 PINMUX_PIN(PIN_PC7, 4, 2) +#define PIN_PC7__D5 PINMUX_PIN(PIN_PC7, 5, 2) + +#define PIN_PC8 72 +#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) +#define PIN_PC8__I2SMCC0_DIN1 PINMUX_PIN(PIN_PC8, 1, 1) +#define PIN_PC8__PDMC0_DS1 PINMUX_PIN(PIN_PC8, 2, 2) +#define PIN_PC8__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PC8, 3, 1) +#define PIN_PC8__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC8, 4, 1) +#define PIN_PC8__D6 PINMUX_PIN(PIN_PC8, 5, 2) + +#define PIN_PC9 73 +#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) +#define PIN_PC9__I2SMCC0_DIN2 PINMUX_PIN(PIN_PC9, 1, 1) +#define PIN_PC9__PDMC0_CLK PINMUX_PIN(PIN_PC9, 2, 2) +#define PIN_PC9__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PC9, 3, 1) +#define PIN_PC9__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC9, 4, 1) +#define PIN_PC9__D7 PINMUX_PIN(PIN_PC9, 5, 2) + +#define PIN_PC10 74 +#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) +#define PIN_PC10__I2SMCC0_DIN3 PINMUX_PIN(PIN_PC10, 1, 1) +#define PIN_PC10__PDMC0_DS0 PINMUX_PIN(PIN_PC10, 2, 2) +#define PIN_PC10__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PC10, 3, 1) +#define PIN_PC10__FLEXCOM9_IO2 PINMUX_PIN(PIN_PC10, 4, 1) +#define PIN_PC10__D2 PINMUX_PIN(PIN_PC10, 5, 2) + +#define PIN_PC11 75 +#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) +#define PIN_PC11__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PC11, 1, 1) +#define PIN_PC11__PDMC1_DS0 PINMUX_PIN(PIN_PC11, 2, 1) +#define PIN_PC11__FLEXCOM9_IO3 PINMUX_PIN(PIN_PC11, 4, 1) +#define PIN_PC10__D3 PINMUX_PIN(PIN_PC10, 5, 2) + +#define PIN_PC12 76 +#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) +#define PIN_PC12__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PC12, 1, 1) +#define PIN_PC12__PDMC1_CLK PINMUX_PIN(PIN_PC12, 2, 1) +#define PIN_PC12__FLEXCOM9_IO4 PINMUX_PIN(PIN_PC12, 4, 1) +#define PIN_PC12__A9 PINMUX_PIN(PIN_PC12, 5, 1) + +#define PIN_PC13 77 +#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) +#define PIN_PC13__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PC13, 1, 1) +#define PIN_PC13__PDMC1_DS1 PINMUX_PIN(PIN_PC13, 2, 1) +#define PIN_PC13__A8 PINMUX_PIN(PIN_PC13, 5, 1) + +#define PIN_PC14 78 +#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) +#define PIN_PC14__I2SMCC1_DIN0 PINMUX_PIN(PIN_PC14, 1, 1) +#define PIN_PC14__SPDIF_RX PINMUX_PIN(PIN_PC14, 2, 3) +#define PIN_PC14__FLEXCOM1_IO0 PINMUX_PIN(PIN_PC14, 3, 2) +#define PIN_PC14__A7 PINMUX_PIN(PIN_PC14, 5, 1) + +#define PIN_PC15 79 +#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) +#define PIN_PC15__I2SMCC1_WS PINMUX_PIN(PIN_PC15, 1, 1) +#define PIN_PC15__PDMC1_DS1 PINMUX_PIN(PIN_PC15, 2, 2) +#define PIN_PC15__FLEXCOM1_IO1 PINMUX_PIN(PIN_PC15, 3, 2) +#define PIN_PC15__A6 PINMUX_PIN(PIN_PC15, 5, 1) + +#define PIN_PC16 80 +#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) +#define PIN_PC16__I2SMCC1_CK PINMUX_PIN(PIN_PC16, 1, 1) +#define PIN_PC16__PDMC1_CLK PINMUX_PIN(PIN_PC16, 2, 2) +#define PIN_PC16__FLEXCOM1_IO2 PINMUX_PIN(PIN_PC16, 3, 2) +#define PIN_PC16__TIOA1 PINMUX_PIN(PIN_PC16, 4, 2) +#define PIN_PC16__A5 PINMUX_PIN(PIN_PC16, 5, 1) + +#define PIN_PC17 81 +#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) +#define PIN_PC17__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PC17, 1, 1) +#define PIN_PC17__PDMC1_DS0 PINMUX_PIN(PIN_PC17, 2, 2) +#define PIN_PC17__FLEXCOM1_IO3 PINMUX_PIN(PIN_PC17, 3, 2) +#define PIN_PC17__TCLK1 PINMUX_PIN(PIN_PC17, 4, 2) +#define PIN_PC17__A4 PINMUX_PIN(PIN_PC17, 5, 1) + +#define PIN_PC18 82 +#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) +#define PIN_PC18__I2SMCC0_DIN0 PINMUX_PIN(PIN_PC18, 1, 1) +#define PIN_PC18__SPDIF_TX PINMUX_PIN(PIN_PC18, 2, 3) +#define PIN_PC18__FLEXCOM1_IO4 PINMUX_PIN(PIN_PC18, 3, 2) +#define PIN_PC18__TIOB1 PINMUX_PIN(PIN_PC18, 4, 2) +#define PIN_PC18__A3 PINMUX_PIN(PIN_PC18, 5, 1) + +#define PIN_PC19 83 +#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) +#define PIN_PC19__I2SMCC0_WS PINMUX_PIN(PIN_PC19, 1, 1) +#define PIN_PC19__PCK6 PINMUX_PIN(PIN_PC19, 2, 1) +#define PIN_PC19__A2 PINMUX_PIN(PIN_PC19, 5, 1) + +#define PIN_PC20 84 +#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) +#define PIN_PC20__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PC20, 1, 1) +#define PIN_PC20__A1 PINMUX_PIN(PIN_PC20, 5, 1) + +#define PIN_PC21 85 +#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) +#define PIN_PC21__I2SMCC0_CK PINMUX_PIN(PIN_PC21, 1, 1) +#define PIN_PC21__PCK7 PINMUX_PIN(PIN_PC21, 2, 1) +#define PIN_PC21__A0 PINMUX_PIN(PIN_PC21, 5, 1) + +#define PIN_PC22 86 +#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) +#define PIN_PC22__NTRST PINMUX_PIN(PIN_PC22, 1, 1) +#define PIN_PC22__NWAIT PINMUX_PIN(PIN_PC22, 5, 1) + +#define PIN_PC23 87 +#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) +#define PIN_PC23__TCK_SWCLK PINMUX_PIN(PIN_PC23, 1, 1) + +#define PIN_PC24 88 +#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) +#define PIN_PC24__TMS_SWDIO PINMUX_PIN(PIN_PC24, 1, 1) + +#define PIN_PC25 89 +#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) +#define PIN_PC25__TDI PINMUX_PIN(PIN_PC25, 1, 1) + +#define PIN_PC26 90 +#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) +#define PIN_PC26__TDO PINMUX_PIN(PIN_PC26, 1, 1) +#define PIN_PC26__A15 PINMUX_PIN(PIN_PC26, 5, 1) + +#define PIN_PC27 91 +#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) +#define PIN_PC27__SDMMC2_CMD PINMUX_PIN(PIN_PC27, 1, 1) +#define PIN_PC27__FLEXCOM8_IO0 PINMUX_PIN(PIN_PC27, 2, 2) +#define PIN_PC27__TD1 PINMUX_PIN(PIN_PC27, 4, 2) +#define PIN_PC27__D8 PINMUX_PIN(PIN_PC27, 5, 1) + +#define PIN_PC28 92 +#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) +#define PIN_PC28__SDMMC2_CK PINMUX_PIN(PIN_PC28, 1, 1) +#define PIN_PC28__FLEXCOM8_IO1 PINMUX_PIN(PIN_PC28, 2, 2) +#define PIN_PC28__TF1 PINMUX_PIN(PIN_PC28, 4, 2) +#define PIN_PC28__D9 PINMUX_PIN(PIN_PC28, 5, 1) + +#define PIN_PC29 93 +#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) +#define PIN_PC29__SDMMC2_DAT0 PINMUX_PIN(PIN_PC29, 1, 1) +#define PIN_PC29__FLEXCOM8_IO2 PINMUX_PIN(PIN_PC29, 2, 2) +#define PIN_PC29__TK1 PINMUX_PIN(PIN_PC29, 4, 2) +#define PIN_PC29__D10 PINMUX_PIN(PIN_PC29, 5, 1) +#define PIN_PC29__TCLK0 PINMUX_PIN(PIN_PC29, 6, 1) + +#define PIN_PC30 94 +#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) +#define PIN_PC30__SDMMC2_DAT1 PINMUX_PIN(PIN_PC30, 1, 1) +#define PIN_PC30__FLEXCOM8_IO3 PINMUX_PIN(PIN_PC30, 2, 2) +#define PIN_PC30__RD1 PINMUX_PIN(PIN_PC30, 4, 2) +#define PIN_PC30__D11 PINMUX_PIN(PIN_PC30, 5, 1) +#define PIN_PC30__TIOA0 PINMUX_PIN(PIN_PC30, 6, 1) + +#define PIN_PC31 95 +#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) +#define PIN_PC31__SDMMC2_DAT2 PINMUX_PIN(PIN_PC31, 1, 1) +#define PIN_PC31__FLEXCOM8_IO4 PINMUX_PIN(PIN_PC31, 2, 2) +#define PIN_PC31__PCK0 PINMUX_PIN(PIN_PC31, 3, 2) +#define PIN_PC31__RK1 PINMUX_PIN(PIN_PC31, 4, 2) +#define PIN_PC31__D12 PINMUX_PIN(PIN_PC31, 5, 1) +#define PIN_PC31__TIOB0 PINMUX_PIN(PIN_PC31, 6, 1) + +#define PIN_PD0 96 +#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) +#define PIN_PD0__SDMMC2_DAT3 PINMUX_PIN(PIN_PD0, 1, 1) +#define PIN_PD0__PCK1 PINMUX_PIN(PIN_PD0, 3, 2) +#define PIN_PD0__RF1 PINMUX_PIN(PIN_PD0, 4, 2) +#define PIN_PD0__D13 PINMUX_PIN(PIN_PD0, 5, 1) + +#define PIN_PD1 97 +#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) +#define PIN_PD1__SDMMC2_WP PINMUX_PIN(PIN_PD1, 1, 1) +#define PIN_PD1__FLEXCOM1_IO5 PINMUX_PIN(PIN_PD1, 2, 1) +#define PIN_PD1__LCDC_HSYNC PINMUX_PIN(PIN_PD1, 3, 2) +#define PIN_PD1__FLEXCOM3_IO0 PINMUX_PIN(PIN_PD1, 4, 3) + +#define PIN_PD2 98 +#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) +#define PIN_PD2__SDMMC2_CD PINMUX_PIN(PIN_PD2, 1, 1) +#define PIN_PD2__FLEXCOM1_IO6 PINMUX_PIN(PIN_PD2, 2, 1) +#define PIN_PD2__LCDC_VSYNC PINMUX_PIN(PIN_PD2, 3, 2) +#define PIN_PD2__FLEXCOM3_IO1 PINMUX_PIN(PIN_PD2, 4, 3) + +#define PIN_PD3 99 +#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) +#define PIN_PD3__SDMMC2_1V8SEL PINMUX_PIN(PIN_PD3, 1, 1) +#define PIN_PD3__FLEXCOM1_IO4 PINMUX_PIN(PIN_PD3, 2, 1) +#define PIN_PD3__TIOA0 PINMUX_PIN(PIN_PD3, 3, 2) +#define PIN_PD3__FLEXCOM3_IO2 PINMUX_PIN(PIN_PD3, 4, 3) +#define PIN_PD3__EXT_IRQ1 PINMUX_PIN(PIN_PD3, 5, 3) + +#define PIN_PD4 100 +#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) +#define PIN_PD4__LCDC_HSYNC PINMUX_PIN(PIN_PD4, 1, 1) +#define PIN_PD4__FLEXCOM1_IO2 PINMUX_PIN(PIN_PD4, 2, 1) +#define PIN_PD4__TIOB0 PINMUX_PIN(PIN_PD4, 3, 2) +#define PIN_PD4__FLEXCOM7_IO1 PINMUX_PIN(PIN_PD4, 4, 3) + +#define PIN_PD5 101 +#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) +#define PIN_PD5__LCDC_VSYNC PINMUX_PIN(PIN_PD5, 1, 1) +#define PIN_PD5__FLEXCOM1_IO3 PINMUX_PIN(PIN_PD5, 2, 1) +#define PIN_PD5__TCLK0 PINMUX_PIN(PIN_PD5, 3, 2) +#define PIN_PD5__FLEXCOM7_IO0 PINMUX_PIN(PIN_PD5, 4, 3) + +#define PIN_PD6 102 +#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) +#define PIN_PD6__LCDC_PWM PINMUX_PIN(PIN_PD6, 1, 1) +#define PIN_PD6__FLEXCOM1_IO1 PINMUX_PIN(PIN_PD6, 2, 1) +#define PIN_PD6__FLEXCOM7_IO2 PINMUX_PIN(PIN_PD6, 4, 3) + +#define PIN_PD7 103 +#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) +#define PIN_PD7__LCDC_DISP PINMUX_PIN(PIN_PD7, 1, 1) +#define PIN_PD7__FLEXCOM1_IO0 PINMUX_PIN(PIN_PD7, 2, 1) +#define PIN_PD7__FLEXCOM7_IO3 PINMUX_PIN(PIN_PD7, 4, 3) + +#define PIN_PD8 104 +#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) +#define PIN_PD8__CANTX0 PINMUX_PIN(PIN_PD8, 1, 1) +#define PIN_PD8__FLEXCOM7_IO0 PINMUX_PIN(PIN_PD8, 2, 1) + +#define PIN_PD9 105 +#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) +#define PIN_PD9__CANRX0 PINMUX_PIN(PIN_PD9, 1, 1) +#define PIN_PD9__FLEXCOM7_IO1 PINMUX_PIN(PIN_PD9, 2, 1) + +#define PIN_PD10 106 +#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) +#define PIN_PD10__CANTX1 PINMUX_PIN(PIN_PD10, 1, 1) +#define PIN_PD10__FLEXCOM7_IO2 PINMUX_PIN(PIN_PD10, 2, 1) +#define PIN_PD10__TIOA1 PINMUX_PIN(PIN_PD10, 3, 3) + +#define PIN_PD11 107 +#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) +#define PIN_PD11__CANRX1 PINMUX_PIN(PIN_PD11, 1, 1) +#define PIN_PD11__FLEXCOM7_IO3 PINMUX_PIN(PIN_PD11, 2, 1) +#define PIN_PD11__TCLK1 PINMUX_PIN(PIN_PD11, 3, 3) + +#define PIN_PD12 108 +#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) +#define PIN_PD12__CANTX2 PINMUX_PIN(PIN_PD12, 1, 1) +#define PIN_PD12__FLEXCOM7_IO4 PINMUX_PIN(PIN_PD12, 2, 1) +#define PIN_PD12__TIOB1 PINMUX_PIN(PIN_PD12, 3, 3) +#define PIN_PD12__PCK2 PINMUX_PIN(PIN_PD12, 4, 2) +#define PIN_PD12__FLEXCOM3_IO3 PINMUX_PIN(PIN_PD12, 5, 3) + +#define PIN_PD13 109 +#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) +#define PIN_PD13__CANRX2 PINMUX_PIN(PIN_PD13, 1, 1) +#define PIN_PD13__FLEXCOM5_IO4 PINMUX_PIN(PIN_PD13, 2, 1) +#define PIN_PD13__TIOA2 PINMUX_PIN(PIN_PD13, 3, 3) +#define PIN_PD13__PCK3 PINMUX_PIN(PIN_PD13, 4, 2) + +#define PIN_PD14 110 +#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) +#define PIN_PD14__CANTX3 PINMUX_PIN(PIN_PD14, 1, 1) +#define PIN_PD14__FLEXCOM5_IO2 PINMUX_PIN(PIN_PD14, 2, 1) +#define PIN_PD14__TIOB2 PINMUX_PIN(PIN_PD14, 3, 3) + +#define PIN_PD15 111 +#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) +#define PIN_PD15__CANRX3 PINMUX_PIN(PIN_PD15, 1, 1) +#define PIN_PD15__FLEXCOM5_IO3 PINMUX_PIN(PIN_PD15, 2, 1) +#define PIN_PD15__TCLK2 PINMUX_PIN(PIN_PD15, 3, 3) + +#define PIN_PD16 112 +#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) +#define PIN_PD16__CANTX4 PINMUX_PIN(PIN_PD16, 1, 1) +#define PIN_PD16__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD16, 2, 1) + +#define PIN_PD17 113 +#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) +#define PIN_PD17__CANRX4 PINMUX_PIN(PIN_PD17, 1, 1) +#define PIN_PD17__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD17, 2, 1) + +#define PIN_PD18 114 +#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) +#define PIN_PD18__FLEXCOM6_IO0 PINMUX_PIN(PIN_PD18, 2, 4) +#define PIN_PD18__CANTX1 PINMUX_PIN(PIN_PD18, 3, 2) +#define PIN_PD18__PCK4 PINMUX_PIN(PIN_PD18, 4, 2) + +#define PIN_PD19 115 +#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) +#define PIN_PD19__FLEXCOM6_IO1 PINMUX_PIN(PIN_PD19, 2, 4) +#define PIN_PD19__CANRX1 PINMUX_PIN(PIN_PD19, 3, 2) +#define PIN_PD19__PCK2 PINMUX_PIN(PIN_PD19, 4, 3) + +#define PIN_PD20 116 +#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) +#define PIN_PD20__PFLEXCOM6_IO2 PINMUX_PIN(PIN_PD20, 2, 4) +#define PIN_PD20__I2SMCC1_MCK PINMUX_PIN(PIN_PD20, 3, 2) +#define PIN_PD20__PCK3 PINMUX_PIN(PIN_PD20, 4, 3) + +#define PIN_PD21 117 +#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) +#define PIN_PD21__G1_TXCTL PINMUX_PIN(PIN_PD21, 1, 2) +#define PIN_PD21__FLEXCOM6_IO2 PINMUX_PIN(PIN_PD21, 2, 3) +#define PIN_PD21__TK1 PINMUX_PIN(PIN_PD21, 3, 1) + +#define PIN_PD22 118 +#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) +#define PIN_PD22__G1_TX0 PINMUX_PIN(PIN_PD22, 1, 1) +#define PIN_PD22__FLEXCOM6_IO3 PINMUX_PIN(PIN_PD22, 2, 3) +#define PIN_PD22__TF1 PINMUX_PIN(PIN_PD22, 3, 1) + +#define PIN_PD23 119 +#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) +#define PIN_PD23__G1_TX1 PINMUX_PIN(PIN_PD23, 1, 1) +#define PIN_PD23__FLEXCOM6_IO4 PINMUX_PIN(PIN_PD23, 2, 3) +#define PIN_PD23__TD1 PINMUX_PIN(PIN_PD23, 3, 1) + +#define PIN_PD24 120 +#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) +#define PIN_PD24__G1_RXCTL PINMUX_PIN(PIN_PD24, 1, 1) +#define PIN_PD24__FLEXCOM6_IO0 PINMUX_PIN(PIN_PD24, 2, 3) +#define PIN_PD24__RD1 PINMUX_PIN(PIN_PD24, 3, 1) +#define PIN_PD24__PDMC0_DS1 PINMUX_PIN(PIN_PD24, 5, 3) + +#define PIN_PD25 121 +#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) +#define PIN_PD25__G1_MDC PINMUX_PIN(PIN_PD25, 1, 1) +#define PIN_PD25__FLEXCOM6_IO1 PINMUX_PIN(PIN_PD25, 2, 3) +#define PIN_PD25__RK1 PINMUX_PIN(PIN_PD25, 3, 1) +#define PIN_PD25__PDMC0_CLK PINMUX_PIN(PIN_PD25, 5, 3) + +#define PIN_PD26 122 +#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) +#define PIN_PD26__G1_MDIO PINMUX_PIN(PIN_PD26, 1, 1) +#define PIN_PD26__FLEXCOM7_IO4 PINMUX_PIN(PIN_PD26, 2, 2) +#define PIN_PD26__RF1 PINMUX_PIN(PIN_PD26, 3, 1) +#define PIN_PD26__I2SMCC1_DIN2 PINMUX_PIN(PIN_PD26, 4, 2) +#define PIN_PD26__PDMC0_DS0 PINMUX_PIN(PIN_PD26, 5, 3) + +#define PIN_PD27 123 +#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) +#define PIN_PD27__G1_RX0 PINMUX_PIN(PIN_PD27, 1, 1) +#define PIN_PD27__FLEXCOM7_IO0 PINMUX_PIN(PIN_PD27, 2, 2) +#define PIN_PD27__SPDIF_RX PINMUX_PIN(PIN_PD27, 3, 1) +#define PIN_PD27__I2SMCC1_DIN3 PINMUX_PIN(PIN_PD27, 4, 2) + +#define PIN_PD28 124 +#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) +#define PIN_PD28__G1_RX1 PINMUX_PIN(PIN_PD28, 1, 1) +#define PIN_PD28__FLEXCOM7_IO1 PINMUX_PIN(PIN_PD28, 2, 2) +#define PIN_PD28__SPDIF_TX PINMUX_PIN(PIN_PD28, 3, 1) +#define PIN_PD28__I2SMCC1_DIN1 PINMUX_PIN(PIN_PD28, 4, 2) + +#define PIN_PD29 125 +#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) +#define PIN_PD29__G1_REFCK PINMUX_PIN(PIN_PD29, 1, 2) +#define PIN_PD29__FLEXCOM7_IO2 PINMUX_PIN(PIN_PD29, 2, 2) +#define PIN_PD29__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PD29, 3, 2) + +#define PIN_PD30 126 +#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) +#define PIN_PD30__G1_RX2 PINMUX_PIN(PIN_PD30, 1, 1) +#define PIN_PD30__FLEXCOM7_IO3 PINMUX_PIN(PIN_PD30, 2, 2) +#define PIN_PD30__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PD30, 3, 2) +#define PIN_PD30__PDMC1_DS1 PINMUX_PIN(PIN_PD30, 4, 3) +#define PIN_PD30__G1_RXER PINMUX_PIN(PIN_PD30, 5, 2) + +#define PIN_PD31 127 +#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) +#define PIN_PD31__G1_RX3 PINMUX_PIN(PIN_PD31, 1, 1) +#define PIN_PD31__FLEXCOM5_IO4 PINMUX_PIN(PIN_PD31, 2, 2) +#define PIN_PD31__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PD31, 3, 3) +#define PIN_PD31__PDMC1_DS0 PINMUX_PIN(PIN_PD31, 4, 3) + +#define PIN_PE0 128 +#define PIN_PE0__GPIO PINMUX_PIN(PIN_PE0, 0, 0) +#define PIN_PE0__G1_TX2 PINMUX_PIN(PIN_PE0, 1, 1) +#define PIN_PE0__FLEXCOM5_IO2 PINMUX_PIN(PIN_PE0, 2, 2) +#define PIN_PE0__I2SMCC1_DIN0 PINMUX_PIN(PIN_PE0, 3, 2) +#define PIN_PE0__PDMC1_CLK PINMUX_PIN(PIN_PE0, 4, 3) + +#define PIN_PE1 129 +#define PIN_PE1__GPIO PINMUX_PIN(PIN_PE1, 0, 0) +#define PIN_PE1__G1_TX3 PINMUX_PIN(PIN_PE1, 1, 1) +#define PIN_PE1__FLEXCOM5_IO3 PINMUX_PIN(PIN_PE1, 2, 2) +#define PIN_PE1__I2SMCC1_WS PINMUX_PIN(PIN_PE1, 3, 2) +#define PIN_PE1__PDMC0_DS1 PINMUX_PIN(PIN_PE1, 4, 4) + +#define PIN_PE2 130 +#define PIN_PE2__GPIO PINMUX_PIN(PIN_PE2, 0, 0) +#define PIN_PE2__G1_RXCK PINMUX_PIN(PIN_PE2, 1, 1) +#define PIN_PE2__FLEXCOM5_IO1 PINMUX_PIN(PIN_PE2, 2, 2) +#define PIN_PE2__I2SMCC1_CK PINMUX_PIN(PIN_PE2, 3, 2) +#define PIN_PE2__PDMC0_CLK PINMUX_PIN(PIN_PE2, 4, 4) + +#define PIN_PE3 131 +#define PIN_PE3__GPIO PINMUX_PIN(PIN_PE3, 0, 0) +#define PIN_PE3__G1_TSUCOMP PINMUX_PIN(PIN_PE3, 1, 1) +#define PIN_PE3__FLEXCOM5_IO0 PINMUX_PIN(PIN_PE3, 2, 2) +#define PIN_PE3__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PE3, 3, 2) +#define PIN_PE3__PDMC0_DS0 PINMUX_PIN(PIN_PE3, 4, 4) + +#define PIN_PE4 132 +#define PIN_PE4__GPIO PINMUX_PIN(PIN_PE4, 0, 0) +#define PIN_PE4__LCDC_DAT0 PINMUX_PIN(PIN_PE4, 1, 1) +#define PIN_PE4__FLEXCOM2_IO2 PINMUX_PIN(PIN_PE4, 2, 1) +#define PIN_PE4__PWML0 PINMUX_PIN(PIN_PE4, 3, 2) +#define PIN_PE4__TIOA3 PINMUX_PIN(PIN_PE4, 4, 1) +#define PIN_PE4__I2SMCC0_DIN1 PINMUX_PIN(PIN_PE4, 5, 2) + +#define PIN_PE5 133 +#define PIN_PE5__GPIO PINMUX_PIN(PIN_PE5, 0, 0) +#define PIN_PE5__LCDC_DAT1 PINMUX_PIN(PIN_PE5, 1, 1) +#define PIN_PE5__FLEXCOM2_IO3 PINMUX_PIN(PIN_PE5, 2, 1) +#define PIN_PE5__PWMH0 PINMUX_PIN(PIN_PE5, 3, 2) +#define PIN_PE5__TIOB3 PINMUX_PIN(PIN_PE5, 4, 1) +#define PIN_PE5__I2SMCC0_DIN2 PINMUX_PIN(PIN_PE5, 5, 2) + +#define PIN_PE6 134 +#define PIN_PE6__GPIO PINMUX_PIN(PIN_PE6, 0, 0) +#define PIN_PE6__LCDC_DAT2 PINMUX_PIN(PIN_PE6, 1, 1) +#define PIN_PE6__FLEXCOM2_IO4 PINMUX_PIN(PIN_PE6, 2, 1) +#define PIN_PE6__PWML1 PINMUX_PIN(PIN_PE6, 3, 2) +#define PIN_PE6__TCLK3 PINMUX_PIN(PIN_PE6, 4, 1) +#define PIN_PE6__I2SMCC0_DIN3 PINMUX_PIN(PIN_PE6, 5, 2) + +#define PIN_PE7 135 +#define PIN_PE7__GPIO PINMUX_PIN(PIN_PE7, 0, 0) +#define PIN_PE7__LCDC_DAT3 PINMUX_PIN(PIN_PE7, 1, 1) +#define PIN_PE7__FLEXCOM2_IO5 PINMUX_PIN(PIN_PE7, 2, 1) +#define PIN_PE7__PWMH1 PINMUX_PIN(PIN_PE7, 3, 2) +#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 4, 1) +#define PIN_PE7__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PE7, 5, 2) + +#define PIN_PE8 136 +#define PIN_PE8__GPIO PINMUX_PIN(PIN_PE8, 0, 0) +#define PIN_PE8__LCDC_DAT4 PINMUX_PIN(PIN_PE8, 1, 1) +#define PIN_PE8__FLEXCOM2_IO0 PINMUX_PIN(PIN_PE8, 2, 1) +#define PIN_PE8__PWML2 PINMUX_PIN(PIN_PE8, 3, 2) +#define PIN_PE8__TIOB4 PINMUX_PIN(PIN_PE8, 4, 1) +#define PIN_PE8__I2SMCC0_CK PINMUX_PIN(PIN_PE8, 5, 2) + +#define PIN_PE9 137 +#define PIN_PE9__GPIO PINMUX_PIN(PIN_PE9, 0, 0) +#define PIN_PE9__LCDC_DAT5 PINMUX_PIN(PIN_PE9, 1, 1) +#define PIN_PE9__FLEXCOM2_IO1 PINMUX_PIN(PIN_PE9, 2, 1) +#define PIN_PE9__PWMH2 PINMUX_PIN(PIN_PE9, 3, 2) +#define PIN_PE9__TCLK4 PINMUX_PIN(PIN_PE9, 4, 1) +#define PIN_PE9__I2SMCC0_WS PINMUX_PIN(PIN_PE9, 5, 2) + +#define PIN_PE10 138 +#define PIN_PE10__GPIO PINMUX_PIN(PIN_PE10, 0, 0) +#define PIN_PE10__LCDC_DAT6 PINMUX_PIN(PIN_PE10, 1, 1) +#define PIN_PE10__FLEXCOM2_IO6 PINMUX_PIN(PIN_PE10, 2, 1) +#define PIN_PE10__PWML3 PINMUX_PIN(PIN_PE10, 3, 2) +#define PIN_PE10__TIOA5 PINMUX_PIN(PIN_PE10, 4, 1) +#define PIN_PE10__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PE10, 5, 2) + +#define PIN_PE11 139 +#define PIN_PE11__GPIO PINMUX_PIN(PIN_PE11, 0, 0) +#define PIN_PE11__LCDC_DAT7 PINMUX_PIN(PIN_PE11, 1, 1) +#define PIN_PE11__PWMH3 PINMUX_PIN(PIN_PE11, 3, 2) +#define PIN_PE11__TIOB5 PINMUX_PIN(PIN_PE11, 4, 1) +#define PIN_PE11__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PE11, 5, 2) + +#define PIN_PE12 140 +#define PIN_PE12__GPIO PINMUX_PIN(PIN_PE12, 0, 0) +#define PIN_PE12__LCDC_DEN PINMUX_PIN(PIN_PE12, 1, 1) +#define PIN_PE12__PCK3 PINMUX_PIN(PIN_PE12, 2, 4) +#define PIN_PE12__PWMEXTRG0 PINMUX_PIN(PIN_PE12, 3, 2) +#define PIN_PE12__TCLK5 PINMUX_PIN(PIN_PE12, 4, 1) +#define PIN_PE12__I2SMCC0_DIN0 PINMUX_PIN(PIN_PE12, 5, 2) + +#define PIN_PE13 141 +#define PIN_PE13__GPIO PINMUX_PIN(PIN_PE13, 0, 0) +#define PIN_PE13__LCDC_PCK PINMUX_PIN(PIN_PE13, 1, 1) +#define PIN_PE13__PCK4 PINMUX_PIN(PIN_PE13, 2, 3) +#define PIN_PE13__PWMEXTRG1 PINMUX_PIN(PIN_PE13, 3, 2) +#define PIN_PE13__I2SMCC0DOUT0 PINMUX_PIN(PIN_PE13, 5, 2) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi new file mode 100644 index 000000000000..854b30d15dcd --- /dev/null +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC + * + * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries + * + * Author: Ryan Wanner <Ryan.Wanner@microchip.com> + * + */ + +#include <dt-bindings/clock/at91.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/mfd/at91-usart.h> + +/ { + model = "Microchip SAMA7D65 family SoC"; + compatible = "microchip,sama7d65"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + reg = <0x0>; + device_type = "cpu"; + clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; + clock-names = "cpu"; + }; + }; + + clocks { + main_xtal: clock-mainxtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + slow_xtal: clock-slowxtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + pioa: pinctrl@e0014000 { + compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; + reg = <0xe0014000 0x800>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pmc: clock-controller@e0018000 { + compatible = "microchip,sama7d65-pmc", "syscon"; + reg = <0xe0018000 0x200>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <2>; + clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; + clock-names = "td_slck", "md_slck", "main_xtal"; + }; + + clk32k: clock-controller@e001d500 { + compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; + reg = <0xe001d500 0x4>; + clocks = <&slow_xtal>; + #clock-cells = <1>; + }; + + sdmmc1: mmc@e1208000 { + compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; + reg = <0xe1208000 0x400>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 76>; + assigned-clock-rates = <200000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>; + status = "disabled"; + }; + + pit64b0: timer@e1800000 { + compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xe1800000 0x100>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; + clock-names = "pclk", "gclk"; + }; + + pit64b1: timer@e1804000 { + compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xe1804000 0x100>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>; + clock-names = "pclk", "gclk"; + }; + + flx6: flexcom@e2020000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2020000 0x200>; + ranges = <0x0 0xe2020000 0x800>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + status = "disabled"; + + uart6: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names = "usart"; + atmel,usart-mode = <AT91_USART_MODE_SERIAL>; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@e8c11000 { + compatible = "arm,cortex-a7-gic"; + reg = <0xe8c11000 0x1000>, + <0xe8c12000 0x2000>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts index 9f64c85e1c20..c3501786d600 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts @@ -661,7 +661,7 @@ clock-frequency = <100000>; status = "okay"; - mb_fru@50 { + eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; }; @@ -704,7 +704,7 @@ reg = <0x5d>; status = "okay"; }; - fan_fru@51 { + eeprom@51 { compatible = "atmel,24c64"; reg = <0x51>; }; @@ -714,7 +714,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <3>; - hsbp_fru@52 { + eeprom@52 { compatible = "atmel,24c64"; reg = <0x52>; status = "okay"; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts index 087f4ac43187..f67ede148209 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts @@ -824,7 +824,7 @@ reg = <0x4a>; status = "okay"; }; - m24128_fru@51 { + eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; pagesize = <64>; diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi index 8125c1b3e8d7..974c76f007db 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi @@ -716,6 +716,7 @@ regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + regulator-boot-on; gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; enable-active-high; gpio-open-drain; @@ -727,6 +728,7 @@ regulator-name = "+5V_USB_SS"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + regulator-boot-on; gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; enable-active-high; gpio-open-drain; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts b/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts index 7cd17b43b4b2..06545a6052f7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts @@ -160,7 +160,7 @@ }; }; - mdio_gpio: mdio-gpio { + mdio_gpio: mdio { compatible = "virtual,mdio-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_swmdio>; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts index 625f9ac671ae..26eb7a9506e4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts @@ -37,7 +37,7 @@ regulator-max-microvolt = <5000000>; }; - mdio_gpio: mdio-gpio { + mdio_gpio: mdio { compatible = "virtual,mdio-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_swmdio>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi index c1ae7c47b442..aa1adcc74019 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi @@ -94,7 +94,7 @@ mdio-gpio0 = &mdio0; }; - mdio0: mdio-gpio { + mdio0: mdio { compatible = "virtual,mdio-gpio"; gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>, /* mdc */ <&gpio2 7 GPIO_ACTIVE_HIGH>; /* mdio */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi index 1c72da417011..88be29166c1a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi @@ -108,6 +108,11 @@ }; }; + poweroff { + compatible = "regulator-poweroff"; + cpu-supply = <&vgen2_reg>; + }; + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; regulator-always-on; @@ -236,10 +241,6 @@ status = "disabled"; }; -&clks { - fsl,pmic-stby-poweroff; -}; - /* Apalis SPI1 */ &ecspi1 { cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; @@ -527,7 +528,6 @@ pmic: pmic@8 { compatible = "fsl,pfuze100"; - fsl,pmic-stby-poweroff; reg = <0x08>; regulators { @@ -691,7 +691,7 @@ adv_7280: adv7280@21 { compatible = "adi,adv7280"; - adv,force-bt656-4; + adi,force-bt656-4; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ipu1_csi0>; reg = <0x21>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi index dc8298f6db34..960e83f5e904 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi @@ -113,8 +113,8 @@ "DMICDAT", "DMIC"; mux-int-port = <2>; mux-ext-port = <3>; - hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>; - mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + hp-det-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; + mic-det-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; backlight_lvds: backlight-lvds { @@ -804,6 +804,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi index d2200c9db25a..45bcfd7faf9d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi @@ -711,8 +711,8 @@ reg_vdd3p0: regulator-3p0 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; regulator-always-on; anatop-reg-offset = <0x120>; anatop-vol-bit-shift = <8>; @@ -806,6 +806,7 @@ reg = <0x020c9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBPHY1>; + phy-3p0-supply = <®_vdd3p0>; fsl,anatop = <&anatop>; }; @@ -814,6 +815,7 @@ reg = <0x020ca000 0x1000>; interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBPHY2>; + phy-3p0-supply = <®_vdd3p0>; fsl,anatop = <&anatop>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts index 55cdfa7ea206..036705b783f4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts @@ -108,7 +108,7 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <3>; - hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; + hp-det-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; }; panel { diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi index 941a2f185056..7381fb7f8912 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi @@ -546,8 +546,8 @@ reg_vdd3p0: regulator-3p0 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; regulator-always-on; anatop-reg-offset = <0x120>; anatop-vol-bit-shift = <8>; @@ -640,6 +640,7 @@ reg = <0x020c9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBPHY1>; + phy-3p0-supply = <®_vdd3p0>; fsl,anatop = <&anatop>; }; @@ -648,6 +649,7 @@ reg = <0x020ca000 0x1000>; interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBPHY2>; + phy-3p0-supply = <®_vdd3p0>; fsl,anatop = <&anatop>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts index 05d6827ea2af..814401486792 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sll-evk.dts @@ -157,7 +157,7 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <3>; - hp-det-gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; + hp-det-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi index 1beac42c1a27..67cf09e63a63 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi @@ -167,7 +167,7 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <6>; - hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; + hp-det-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; panel { diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi index a9550f115f82..5132b575b001 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi @@ -637,8 +637,8 @@ reg_vdd3p0: regulator-3p0 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; regulator-always-on; anatop-reg-offset = <0x120>; anatop-vol-bit-shift = <8>; @@ -731,6 +731,7 @@ reg = <0x020c9000 0x1000>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_USBPHY1>; + phy-3p0-supply = <®_vdd3p0>; fsl,anatop = <&anatop>; }; @@ -739,6 +740,7 @@ reg = <0x020ca000 0x1000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_USBPHY2>; + phy-3p0-supply = <®_vdd3p0>; fsl,anatop = <&anatop>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi index b74ee8948a78..0e839bbfea08 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi @@ -68,7 +68,7 @@ audio-cpu = <&sai2>; audio-codec = <&codec>; audio-asrc = <&asrc>; - hp-det-gpio = <&gpio5 4 0>; + hp-det-gpios = <&gpio5 4 0>; audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", diff --git a/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi index e1c401f468e1..576a7df505d3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi @@ -87,34 +87,6 @@ <&adc2 0>, <&adc2 1>, <&adc2 2>, <&adc2 3>; }; - reg_sd1_vmmc: regulator-sd1-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3_SD1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_fec1_pwdn: regulator-fec1-pwdn { - compatible = "regulator-fixed"; - regulator-name = "PWDN_FEC1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_fec2_pwdn: regulator-fec2-pwdn { - compatible = "regulator-fixed"; - regulator-name = "PWDN_FEC2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { compatible = "regulator-fixed"; regulator-name = "VBUS_USBOTG1"; @@ -141,6 +113,7 @@ gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; + vin-supply = <®_mba_5v>; }; reg_mpcie_3v3: regulator-mpcie-3v3 { @@ -151,6 +124,7 @@ gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; + vin-supply = <®_mba_3v3>; }; reg_mba_12v0: regulator-mba-12v0 { @@ -162,13 +136,18 @@ enable-active-high; }; - reg_lvds_transmitter: regulator-lvds-transmitter { + reg_mba_5v: regulator-mba-5v { compatible = "regulator-fixed"; - regulator-name = "#SHTDN_LVDS"; + regulator-name = "VCC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_mba_3v3: regulator-mba-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>; - enable-active-high; }; reg_vref_1v8: regulator-vref-1v8 { @@ -186,14 +165,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; - }; - - reg_vcc_3v3: regulator-vcc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; + vin-supply = <®_mba_3v3>; }; sound { @@ -239,7 +211,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; phy-mode = "rgmii-id"; - phy-supply = <®_fec1_pwdn>; phy-handle = <ðphy1_0>; fsl,magic-packet; status = "okay"; @@ -260,6 +231,8 @@ reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <500>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; }; }; }; @@ -318,7 +291,7 @@ lm75: temperature-sensor@49 { compatible = "national,lm75a"; reg = <0x49>; - vs-supply = <®_vcc_3v3>; + vs-supply = <®_mba_3v3>; }; }; @@ -351,7 +324,7 @@ interrupts = <12 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; - vcc-supply = <®_vcc_3v3>; + vcc-supply = <®_mba_3v3>; }; }; @@ -668,7 +641,7 @@ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - vmmc-supply = <®_sd1_vmmc>; + vmmc-supply = <®_mba_3v3>; bus-width = <4>; no-1-8-v; no-sdio; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi index 028961eb7108..aa8f65cd4adf 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi @@ -135,6 +135,7 @@ lm75a: temperature-sensor@48 { compatible = "national,lm75a"; reg = <0x48>; + vs-supply = <&vgen4_reg>; }; /* NXP SE97BTP with temperature sensor + eeprom, TQMa7x 02xx */ @@ -150,7 +151,6 @@ reg = <0x50>; pagesize = <32>; vcc-supply = <&vgen4_reg>; - status = "okay"; }; at24c02: eeprom@56 { @@ -158,7 +158,6 @@ reg = <0x56>; pagesize = <16>; vcc-supply = <&vgen4_reg>; - status = "okay"; }; ds1339: rtc@68 { diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts index 0443faa3dfae..e3ee16f1aaa9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-mba7.dts @@ -21,7 +21,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; phy-mode = "rgmii-id"; - phy-supply = <®_fec2_pwdn>; phy-handle = <ðphy2_0>; fsl,magic-packet; status = "okay"; @@ -42,6 +41,8 @@ reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <500>; + interrupt-parent = <&gpio2>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts index f712537fca16..6cde84636900 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts @@ -169,7 +169,7 @@ model = "wm8960-audio"; audio-cpu = <&sai1>; audio-codec = <&codec>; - hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; + hp-det-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index d0f6120b665d..39530eb580ea 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -427,8 +427,9 @@ interrupt-names = "global", "doorbell"; - interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "pcie-mem"; + interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>, + <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>; + interconnect-names = "pcie-mem", "cpu-pcie"; resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; @@ -613,6 +614,8 @@ iommus = <&apps_smmu 0x1a0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; phys = <&usb_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; }; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 3bc67bb8c1eb..6b23ee676c9e 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -335,6 +335,10 @@ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "global", "doorbell"; + interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>, + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_PCIE_0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; @@ -526,6 +530,8 @@ iommus = <&apps_smmu 0x1a0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; phys = <&usb_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; }; diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi index b831bbc431ef..1a866dbaf5e9 100644 --- a/arch/arm/boot/dts/renesas/r7s72100.dtsi +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi @@ -238,6 +238,8 @@ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI0>; + dmas = <&dmac 0x2d21>, <&dmac 0x2d22>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; @@ -253,6 +255,8 @@ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI1>; + dmas = <&dmac 0x2d25>, <&dmac 0x2d26>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; @@ -268,6 +272,8 @@ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI2>; + dmas = <&dmac 0x2d29>, <&dmac 0x2d2a>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; @@ -283,6 +289,8 @@ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI3>; + dmas = <&dmac 0x2d2d>, <&dmac 0x2d2e>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; @@ -298,6 +306,8 @@ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI4>; + dmas = <&dmac 0x2d31>, <&dmac 0x2d32>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi index 9bc05961577d..70e3091062f9 100644 --- a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi @@ -300,12 +300,31 @@ regulator-max-microvolt = <2800000>; }; + earmic_bias_reg: voltage-regulator-6 { + compatible = "regulator-fixed"; + regulator-name = "EAR_MICBIAS_LDO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpm0 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + sound: sound { compatible = "samsung,midas-audio"; model = "TAB3"; mic-bias-supply = <&mic_bias_reg>; submic-bias-supply = <&submic_bias_reg>; + lineout-sel-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>; + + headset-mic-bias-supply = <&earmic_bias_reg>; + headset-detect-gpios = <&gpx0 4 GPIO_ACTIVE_LOW>; + headset-key-gpios = <&gpx3 6 GPIO_ACTIVE_LOW>; + samsung,headset-4pole-threshold-microvolt = <710 2000>; + samsung,headset-button-threshold-microvolt = <0 130 260>; + io-channel-names = "headset-detect"; + io-channels = <&adc 0>; + audio-routing = "HP", "HPOUT1L", "HP", "HPOUT1R", @@ -351,6 +370,11 @@ }; }; +&adc { + vdd-supply = <&ldo3_reg>; + status = "okay"; +}; + &bus_acp { devfreq = <&bus_dmc>; status = "okay"; @@ -511,12 +535,11 @@ wm1811: audio-codec@1a { compatible = "wlf,wm1811"; reg = <0x1a>; - clocks = <&pmu_system_controller 0>; - clock-names = "MCLK1"; + clocks = <&pmu_system_controller 0>, + <&s5m8767_osc S2MPS11_CLK_BT>; + clock-names = "MCLK1", "MCLK2"; interrupt-controller; #interrupt-cells = <2>; - interrupt-parent = <&gpx3>; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index eab3a9bd435f..b7d5d305cbbe 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -39,6 +39,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp151c-mect1s.dtb \ stm32mp153c-dhcom-drc02.dtb \ stm32mp153c-dhcor-drc-compact.dtb \ + stm32mp153c-lxa-tac-gen3.dtb \ stm32mp153c-mecio1r1.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ diff --git a/arch/arm/boot/dts/st/stih410-b2260.dts b/arch/arm/boot/dts/st/stih410-b2260.dts index 240b62040000..736b1e059b0a 100644 --- a/arch/arm/boot/dts/st/stih410-b2260.dts +++ b/arch/arm/boot/dts/st/stih410-b2260.dts @@ -206,5 +206,9 @@ sata1: sata@9b28000 { status = "okay"; }; + + gpu: gpu@9f00000 { + status = "okay"; + }; }; }; diff --git a/arch/arm/boot/dts/st/stih410.dtsi b/arch/arm/boot/dts/st/stih410.dtsi index a69231854f78..d56343f44fda 100644 --- a/arch/arm/boot/dts/st/stih410.dtsi +++ b/arch/arm/boot/dts/st/stih410.dtsi @@ -285,5 +285,39 @@ resets = <&softreset STIH407_LPM_SOFTRESET>; hdmi-phandle = <&sti_hdmi>; }; + + gpu: gpu@9f00000 { + compatible = "st,stih410-mali", "arm,mali-400"; + reg = <0x9f00000 0x10000>; + /* LIMA driver needs 2 clocks, use the same for both */ + clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>, + <&clk_s_c0_flexgen CLK_ICN_GPU>; + clock-names = "bus", "core"; + assigned-clocks = <&clk_s_c0_flexgen CLK_ICN_GPU>; + assigned-clock-rates = <400000000>; + resets = <&softreset STIH407_GPU_SOFTRESET>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; + + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index e1a764d269d2..0019d12c3d3d 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -261,6 +261,11 @@ dma-names = "up"; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + timer@5 { compatible = "st,stm32h7-timer-trigger"; reg = <5>; @@ -281,6 +286,11 @@ dma-names = "up"; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + timer@6 { compatible = "st,stm32h7-timer-trigger"; reg = <6>; @@ -1196,6 +1206,11 @@ access-controllers = <&etzpc 23>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -1221,6 +1236,11 @@ access-controllers = <&etzpc 24>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -1246,6 +1266,11 @@ access-controllers = <&etzpc 25>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -1276,6 +1301,11 @@ access-controllers = <&etzpc 26>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -1304,6 +1334,11 @@ access-controllers = <&etzpc 27>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -1332,6 +1367,11 @@ access-controllers = <&etzpc 28>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 3a276589fef7..19a32f7d4d7d 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -440,6 +440,9 @@ /delete-property/dmas; /delete-property/dma-names; status = "disabled"; + counter { + status = "okay"; + }; pwm { /* PWM output on pin 7 of the expansion connector (CN8.7) using TIM3_CH4 func */ pinctrl-0 = <&pwm3_pins_a>; @@ -456,6 +459,9 @@ /delete-property/dmas; /delete-property/dma-names; status = "disabled"; + counter { + status = "okay"; + }; pwm { /* PWM output on pin 31 of the expansion connector (CN8.31) using TIM4_CH2 func */ pinctrl-0 = <&pwm4_pins_a>; @@ -472,6 +478,9 @@ /delete-property/dmas; /delete-property/dma-names; status = "disabled"; + counter { + status = "okay"; + }; pwm { /* PWM output on pin 32 of the expansion connector (CN8.32) using TIM8_CH3 func */ pinctrl-0 = <&pwm8_pins_a>; @@ -486,6 +495,9 @@ &timers14 { status = "disabled"; + counter { + status = "okay"; + }; pwm { /* PWM output on pin 33 of the expansion connector (CN8.33) using TIM14_CH1 func */ pinctrl-0 = <&pwm14_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi index 5edbc790d1d2..6236ce2a6968 100644 --- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi @@ -85,8 +85,8 @@ vddcpu: buck1 { /* VDD_CPU_1V2 */ regulator-name = "vddcpu"; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; regulator-over-current-protection; @@ -201,17 +201,17 @@ pagesize = <64>; }; - eeprom0wl: eeprom@58 { - compatible = "st,24256e-wl"; /* ST M24256E WL page of 0x50 */ - pagesize = <64>; - reg = <0x58>; - }; - rv3032: rtc@51 { compatible = "microcrystal,rv3032"; reg = <0x51>; interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>; }; + + eeprom0wl: eeprom@58 { + compatible = "st,24256e-wl"; /* ST M24256E WL page of 0x50 */ + pagesize = <64>; + reg = <0x58>; + }; }; &iwdg2 { diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index b28dc90926bd..b9a87fbe971d 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -129,7 +129,7 @@ reg = <0x4c001000 0x400>; st,proc-id = <0>; interrupts-extended = - <&exti 61 1>, + <&exti 61 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "rx", "tx"; clocks = <&rcc IPCC>; @@ -578,6 +578,11 @@ access-controllers = <&etzpc 20>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + timer@5 { compatible = "st,stm32h7-timer-trigger"; reg = <5>; @@ -599,6 +604,11 @@ access-controllers = <&etzpc 21>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + timer@6 { compatible = "st,stm32h7-timer-trigger"; reg = <6>; @@ -618,6 +628,11 @@ access-controllers = <&etzpc 22>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -643,6 +658,11 @@ access-controllers = <&etzpc 23>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -668,6 +688,11 @@ access-controllers = <&etzpc 24>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -1116,6 +1141,11 @@ access-controllers = <&etzpc 54>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; @@ -1144,11 +1174,17 @@ access-controllers = <&etzpc 55>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; status = "disabled"; }; + timer@15 { compatible = "st,stm32h7-timer-trigger"; reg = <15>; @@ -1171,6 +1207,11 @@ access-controllers = <&etzpc 56>; status = "disabled"; + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + pwm { compatible = "st,stm32-pwm"; #pwm-cells = <3>; diff --git a/arch/arm/boot/dts/st/stm32mp153c-lxa-tac-gen3.dts b/arch/arm/boot/dts/st/stm32mp153c-lxa-tac-gen3.dts new file mode 100644 index 000000000000..a40b0eae8da3 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153c-lxa-tac-gen3.dts @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2021 Rouven Czerwinski, Pengutronix + * Copyright (C) 2023, 2024 Leonard Göhrs, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp153.dtsi" +#include "stm32mp15xc-lxa-tac.dtsi" + +/ { + model = "Linux Automation Test Automation Controller (TAC) Gen 3"; + compatible = "lxa,stm32mp153c-tac-gen3", "oct,stm32mp153x-osd32", "st,stm32mp153"; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&v3v3>; + + brightness-levels = <0 31 63 95 127 159 191 223 255>; + default-brightness-level = <7>; + pwms = <&led_pwm 3 1000000 0>; + }; + + reg_iobus_12v: regulator-iobus-12v { + compatible = "regulator-fixed"; + vin-supply = <®_12v>; + gpio = <&gpioh 13 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "12V_IOBUS"; + }; + + led-controller-1 { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + max-brightness = <65535>; + + led-red { + active-low; + color = <LED_COLOR_ID_RED>; + pwms = <&led_pwm 0 1000000 0>; + }; + + led-green { + active-low; + color = <LED_COLOR_ID_GREEN>; + pwms = <&led_pwm 2 1000000 0>; + }; + + led-blue { + active-low; + color = <LED_COLOR_ID_BLUE>; + pwms = <&led_pwm 1 1000000 0>; + }; + }; + }; + + led-controller-2 { + compatible = "gpio-leds"; + + led-5 { + label = "tac:green:iobus"; + gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; + }; + + led-6 { + label = "tac:green:can"; + gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; + }; + + led-7 { + label = "tac:green:out0"; + gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>; + }; + + led-8 { + label = "tac:green:out1"; + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + }; + + led-9 { + label = "tac:green:uarttx"; + gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>; + }; + + led-10 { + label = "tac:green:uartrx"; + gpios = <&gpiof 6 GPIO_ACTIVE_HIGH>; + }; + + led-11 { + label = "tac:green:usbh1"; + gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>; + }; + + led-12 { + label = "tac:green:usbh2"; + gpios = <&gpiod 6 GPIO_ACTIVE_HIGH>; + }; + + led-13 { + label = "tac:green:usbh3"; + gpios = <&gpiob 9 GPIO_ACTIVE_HIGH>; + }; + + led-14 { + label = "tac:green:usbg"; + gpios = <&gpiod 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usb-gadget"; + }; + + led-15 { + label = "tac:green:dutpwr"; + gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&board_adc1_ain_pins>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vrefbuf>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <2 5 9 10 13 14 15 18>; + st,min-sample-time-nsecs = <5000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@2 { + reg = <2>; + label = "OUT_0_FB"; + }; + + channel@5 { + reg = <5>; + label = "IOBUS_CURR_FB"; + }; + + channel@9 { + reg = <9>; + label = "IOBUS_VOLT_FB"; + }; + + channel@10 { + reg = <10>; + label = "OUT_1_FB"; + }; + + channel@13 { + reg = <13>; + label = "HOST_CURR_FB"; + }; + + channel@14 { + reg = <14>; + label = "HOST_3_CURR_FB"; + }; + + channel@15 { + reg = <15>; + label = "HOST_1_CURR_FB"; + }; + + channel@18 { + reg = <18>; + label = "HOST_2_CURR_FB"; + }; + }; + + adc2: adc@100 { + st,adc-channels = <12>; + st,min-sample-time-nsecs = <500000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@12 { + reg = <12>; + label = "TEMP_INTERNAL"; + }; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", "", /* 0 */ + "ETH_GPIO1", "ETH_INT", "", "", "", /* 5 */ + "", "", "", "BOOTROM_LED", "ETH_LAB_LEDRP", /* 10 */ + ""; /* 15 */ +}; + +&gpioc { + gpio-line-names = "", "DUT_PWR_DISCH", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", ""; /* 10 */ +}; + +&gpioe { + gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /* 0 */ + "", "", "USER_BTN2", "DUT_PWR_EN", "UART_TX_EN", /* 5 */ + "UART_RX_EN", "TP24", "", "TP25", "TP26", /* 10 */ + "TP27"; /* 15 */ +}; + +&gpiog { + gpio-line-names = "ETH_RESET", "", "", "", "", /* 0 */ + "IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /* 5 */ + "POWER_ADC_RESET", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&m_can2 { + termination-gpios = <&gpioe 4 GPIO_ACTIVE_HIGH>; + termination-ohms = <120>; +}; + +&pinctrl { + board_adc1_ain_pins: board-adc1-ain-0 { + pins { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */ + <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */ + <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */ + <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */ + <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1_INP13 */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ADC1_INP14 */ + <STM32_PINMUX('A', 3, ANALOG)>, /* ADC1_INP15 */ + <STM32_PINMUX('A', 4, ANALOG)>; /* ADC1_INP18 */ + }; + }; +}; + +&spi2 { + adc@0 { + compatible = "ti,lmp92064"; + reg = <0>; + + reset-gpios = <&gpiog 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + shunt-resistor-micro-ohms = <15000>; + spi-max-frequency = <5000000>; + vdd-supply = <®_pb_3v3>; + vdig-supply = <®_pb_3v3>; + }; +}; + +&timers8 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + led_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm8_pins_b>; + pinctrl-1 = <&pwm8_sleep_pins_b>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts index 9eb9a1bf4f2c..8f99c30f1af1 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -306,6 +306,9 @@ /delete-property/dmas; /delete-property/dma-names; status = "disabled"; + counter { + status = "okay"; + }; pwm { pinctrl-0 = <&pwm2_pins_a>; pinctrl-1 = <&pwm2_sleep_pins_a>; @@ -321,6 +324,9 @@ /delete-property/dmas; /delete-property/dma-names; status = "disabled"; + counter { + status = "okay"; + }; pwm { pinctrl-0 = <&pwm8_pins_a>; pinctrl-1 = <&pwm8_sleep_pins_a>; @@ -336,6 +342,9 @@ /delete-property/dmas; /delete-property/dma-names; status = "disabled"; + counter { + status = "okay"; + }; pwm { pinctrl-0 = <&pwm12_pins_a>; pinctrl-1 = <&pwm12_sleep_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen1.dts b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen1.dts index 81f254fb88b0..e72e42eb0eb4 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen1.dts @@ -35,6 +35,76 @@ }; }; +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_ain_pins_a>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vrefbuf>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 2 5 9 10 13 15>; + st,min-sample-time-nsecs = <5000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + reg = <0>; + label = "HOST_2_CURR_FB"; + }; + + channel@1 { + reg = <1>; + label = "HOST_3_CURR_FB"; + }; + + channel@2 { + reg = <2>; + label = "OUT_0_FB"; + }; + + channel@5 { + reg = <5>; + label = "IOBUS_CURR_FB"; + }; + + channel@9 { + reg = <9>; + label = "IOBUS_VOLT_FB"; + }; + + channel@10 { + reg = <10>; + label = "OUT_1_FB"; + }; + + channel@13 { + reg = <13>; + label = "HOST_CURR_FB"; + }; + + channel@15 { + reg = <15>; + label = "HOST_1_CURR_FB"; + }; + }; + + adc2: adc@100 { + st,adc-channels = <12>; + st,min-sample-time-nsecs = <500000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@12 { + reg = <12>; + label = "TEMP_INTERNAL"; + }; + }; +}; + &gpioa { gpio-line-names = "", "", "STACK_CS2", "", "STACK_CS3", /* 0 */ "ETH_GPIO1", "ETH_INT", "", "", "", /* 5 */ @@ -48,6 +118,20 @@ "", ""; /* 10 */ }; +&gpioe { + gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /* 0 */ + "", "", "USER_BTN2", "TP48", "UART_TX_EN", /* 5 */ + "UART_RX_EN", "TP24", "", "TP25", "TP26", /* 10 */ + "TP27"; /* 15 */ +}; + +&gpiog { + gpio-line-names = "ETH_RESET", "", "", "", "", /* 0 */ + "IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /* 5 */ + "TP49", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + &gpu { status = "disabled"; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts index 4cc177031661..2ae281725a48 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts @@ -121,6 +121,76 @@ }; }; +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_ain_pins_a>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vrefbuf>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 2 5 9 10 13 15>; + st,min-sample-time-nsecs = <5000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + reg = <0>; + label = "HOST_2_CURR_FB"; + }; + + channel@1 { + reg = <1>; + label = "HOST_3_CURR_FB"; + }; + + channel@2 { + reg = <2>; + label = "OUT_0_FB"; + }; + + channel@5 { + reg = <5>; + label = "IOBUS_CURR_FB"; + }; + + channel@9 { + reg = <9>; + label = "IOBUS_VOLT_FB"; + }; + + channel@10 { + reg = <10>; + label = "OUT_1_FB"; + }; + + channel@13 { + reg = <13>; + label = "HOST_CURR_FB"; + }; + + channel@15 { + reg = <15>; + label = "HOST_1_CURR_FB"; + }; + }; + + adc2: adc@100 { + st,adc-channels = <12>; + st,min-sample-time-nsecs = <500000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@12 { + reg = <12>; + label = "TEMP_INTERNAL"; + }; + }; +}; + &gpioa { gpio-line-names = "", "", "DUT_PWR_EN", "", "STACK_CS3", /* 0 */ "ETH_GPIO1", "ETH_INT", "", "", "", /* 5 */ @@ -134,6 +204,20 @@ "", ""; /* 10 */ }; +&gpioe { + gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /* 0 */ + "", "", "USER_BTN2", "TP48", "UART_TX_EN", /* 5 */ + "UART_RX_EN", "TP24", "", "TP25", "TP26", /* 10 */ + "TP27"; /* 15 */ +}; + +&gpiog { + gpio-line-names = "ETH_RESET", "", "", "", "", /* 0 */ + "IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /* 5 */ + "TP49", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + &gpu { status = "disabled"; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi index c87fd96cbd91..be0c355d3105 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi @@ -16,12 +16,20 @@ / { aliases { + can0 = &m_can1; + can1 = &m_can2; ethernet0 = ðernet0; ethernet1 = &port_uplink; ethernet2 = &port_dut; + i2c0 = &i2c1; + i2c1 = &i2c4; + i2c2 = &i2c5; mmc1 = &sdmmc2; serial0 = &uart4; serial1 = &usart3; + spi0 = &spi2; + spi1 = &spi4; + spi2 = &spi5; }; chosen { @@ -142,76 +150,6 @@ baseboard_eeprom: &sip_eeprom { }; -&adc { - pinctrl-names = "default"; - pinctrl-0 = <&adc1_ain_pins_a>; - vdd-supply = <&vdd>; - vdda-supply = <&vdda>; - vref-supply = <&vrefbuf>; - status = "okay"; - - adc1: adc@0 { - st,adc-channels = <0 1 2 5 9 10 13 15>; - st,min-sample-time-nsecs = <5000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - channel@0 { - reg = <0>; - label = "HOST_2_CURR_FB"; - }; - - channel@1 { - reg = <1>; - label = "HOST_3_CURR_FB"; - }; - - channel@2 { - reg = <2>; - label = "OUT_0_FB"; - }; - - channel@5 { - reg = <5>; - label = "IOBUS_CURR_FB"; - }; - - channel@9 { - reg = <9>; - label = "IOBUS_VOLT_FB"; - }; - - channel@10 { - reg = <10>; - label = "OUT_1_FB"; - }; - - channel@13 { - reg = <13>; - label = "HOST_CURR_FB"; - }; - - channel@15 { - reg = <15>; - label = "HOST_1_CURR_FB"; - }; - }; - - adc2: adc@100 { - st,adc-channels = <12>; - st,min-sample-time-nsecs = <500000>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - channel@12 { - reg = <12>; - label = "TEMP_INTERNAL"; - }; - }; -}; - &crc1 { status = "okay"; }; @@ -265,13 +203,6 @@ baseboard_eeprom: &sip_eeprom { "ETH_LAB_LEDRN"; /* 15 */ }; -&gpioe { - gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /* 0 */ - "", "", "USER_BTN2", "TP48", "UART_TX_EN", /* 5 */ - "UART_RX_EN", "TP24", "", "TP25", "TP26", /* 10 */ - "TP27"; /* 15 */ -}; - &gpiof { gpio-line-names = "TP36", "TP37", "", "", "OLED_CS", /* 0 */ "", "", "", "", "", /* 5 */ @@ -279,13 +210,6 @@ baseboard_eeprom: &sip_eeprom { ""; /* 15 */ }; -&gpiog { - gpio-line-names = "ETH_RESET", "", "", "", "", /* 0 */ - "IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /* 5 */ - "TP49", "", "", "", "", /* 10 */ - ""; /* 15 */ -}; - &gpioh { gpio-line-names = "", "", "OUT_1", "OUT_0", "OLED_RESET", /* 0 */ "", "", "", "", "", /* 5 */ @@ -379,10 +303,6 @@ baseboard_eeprom: &sip_eeprom { }; }; -&rtc { - status = "okay"; -}; - &sdmmc2 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; @@ -576,6 +496,10 @@ baseboard_eeprom: &sip_eeprom { vusb_d-supply = <&vdd_usb>; vusb_a-supply = <®18>; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <128 128 64 16 16 16 16 16>; + dr_mode = "peripheral"; status = "okay"; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi index bb4f8a0b937f..abe2dfe70636 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi @@ -6,18 +6,6 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/pwm/pwm.h> -/ { - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - &adc { status = "disabled"; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi index 171d7c7658fa..0fb4e55843b9 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi @@ -7,16 +7,6 @@ #include <dt-bindings/pwm/pwm.h> / { - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - clk_ext_audio_codec: clock-codec { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi index b5bc53accd6b..01c693cc0344 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-picoitx.dtsi @@ -7,16 +7,6 @@ #include <dt-bindings/pwm/pwm.h> / { - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart8; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - led { compatible = "gpio-leds"; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi index 74a11ccc5333..142d4a8731f8 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi @@ -14,6 +14,13 @@ ethernet1 = &ksz8851; rtc0 = &hwrtc; rtc1 = &rtc; + serial0 = &uart4; + serial1 = &uart8; + serial2 = &usart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; }; memory@c0000000 { diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi index f7634c51efb2..a5511b1f0ce3 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -570,6 +570,9 @@ /delete-property/dmas; /delete-property/dma-names; status = "disabled"; + counter { + status = "okay"; + }; pwm { pinctrl-0 = <&pwm1_pins_a>; pinctrl-1 = <&pwm1_sleep_pins_a>; @@ -585,6 +588,9 @@ /delete-property/dmas; /delete-property/dma-names; status = "disabled"; + counter { + status = "okay"; + }; pwm { pinctrl-0 = <&pwm3_pins_a>; pinctrl-1 = <&pwm3_sleep_pins_a>; @@ -600,6 +606,9 @@ /delete-property/dmas; /delete-property/dma-names; status = "disabled"; + counter { + status = "okay"; + }; pwm { pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>; pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>; @@ -615,6 +624,9 @@ /delete-property/dmas; /delete-property/dma-names; status = "disabled"; + counter { + status = "okay"; + }; pwm { pinctrl-0 = <&pwm5_pins_a>; pinctrl-1 = <&pwm5_sleep_pins_a>; @@ -630,6 +642,9 @@ /delete-property/dmas; /delete-property/dma-names; status = "disabled"; + counter { + status = "okay"; + }; timer@5 { status = "okay"; }; @@ -639,6 +654,9 @@ /delete-property/dmas; /delete-property/dma-names; status = "disabled"; + counter { + status = "okay"; + }; pwm { pinctrl-0 = <&pwm12_pins_a>; pinctrl-1 = <&pwm12_sleep_pins_a>; diff --git a/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi b/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi index 824b9415ebbe..fd4634f8c629 100644 --- a/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi @@ -180,8 +180,7 @@ <0x9058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; + SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>, @@ -698,8 +697,7 @@ <0x22058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; + SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>, @@ -726,8 +724,7 @@ <0x24058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; + SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>, @@ -1385,8 +1382,7 @@ <0xa6058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; + SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>, @@ -1413,8 +1409,7 @@ <0xa8058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; + SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>, @@ -1441,8 +1436,7 @@ <0xaa058 0x4>; reg-names = "rev", "sysc", "syss"; ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | - SYSC_OMAP2_SOFTRESET | - SYSC_OMAP2_AUTOIDLE)>; + SYSC_OMAP2_SOFTRESET)>; ti,sysc-sidle = <SYSC_IDLE_FORCE>, <SYSC_IDLE_NO>, <SYSC_IDLE_SMART>, diff --git a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi index 6e67d99832ac..ba7fdaae9c6e 100644 --- a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi @@ -12,6 +12,7 @@ ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ <0x00100000 0x4a100000 0x100000>, /* segment 1 */ <0x00200000 0x4a200000 0x100000>; /* segment 2 */ + dma-ranges; segment@0 { /* 0x4a000000 */ compatible = "simple-pm-bus"; @@ -557,6 +558,7 @@ <0x0007e000 0x0017e000 0x001000>, /* ap 124 */ <0x00059000 0x00159000 0x001000>, /* ap 125 */ <0x0005a000 0x0015a000 0x001000>; /* ap 126 */ + dma-ranges; target-module@2000 { /* 0x4a102000, ap 27 3c.0 */ compatible = "ti,sysc"; diff --git a/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi b/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi index 2ee3ddd64020..1b18ed8c1f7a 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-gta04.dtsi @@ -446,6 +446,7 @@ pinctrl-names = "default"; pinctrl-0 = < &hsusb2_2_pins + &mcspi3hog_pins >; hsusb2_2_pins: hsusb2-2-pins { @@ -459,6 +460,15 @@ >; }; + mcspi3hog_pins: mcspi3hog-pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25dc, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d0 */ + OMAP3630_CORE2_IOPAD(0x25de, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d1 */ + OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d2 */ + OMAP3630_CORE2_IOPAD(0x25e2, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* etk_d3 */ + >; + }; + spi_gpio_pins: spi-gpio-pinmux-pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ @@ -591,8 +601,10 @@ interrupts = <0 IRQ_TYPE_EDGE_FALLING>; /* GPIO_160 */ gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* GPIO_160 */ ti,x-plate-ohms = <600>; - touchscreen-size-x = <480>; - touchscreen-size-y = <640>; + touchscreen-size-x = <0xf00>; + touchscreen-size-y = <0xf00>; + touchscreen-min-x = <0x100>; + touchscreen-min-y = <0x100>; touchscreen-max-pressure = <1000>; touchscreen-fuzz-x = <3>; touchscreen-fuzz-y = <8>; diff --git a/arch/arm/common/bL_switcher.c b/arch/arm/common/bL_switcher.c index 9a9aa53547a6..d1e82a318e3b 100644 --- a/arch/arm/common/bL_switcher.c +++ b/arch/arm/common/bL_switcher.c @@ -307,13 +307,11 @@ static struct task_struct *bL_switcher_thread_create(int cpu, void *arg) { struct task_struct *task; - task = kthread_create_on_node(bL_switcher_thread, arg, - cpu_to_node(cpu), "kswitcher_%d", cpu); - if (!IS_ERR(task)) { - kthread_bind(task, cpu); - wake_up_process(task); - } else + task = kthread_run_on_cpu(bL_switcher_thread, arg, + cpu, "kswitcher_%d"); + if (IS_ERR(task)) pr_err("%s failed for CPU %d\n", __func__, cpu); + return task; } diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index f25eadcba5e6..87841e5cafe2 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -230,6 +230,7 @@ CONFIG_RN5T618_POWER=m CONFIG_SENSORS_MC13783_ADC=y CONFIG_SENSORS_GPIO_FAN=y CONFIG_SENSORS_IIO_HWMON=y +CONFIG_SENSORS_JC42=m CONFIG_SENSORS_LM75=m CONFIG_SENSORS_PWM_FAN=y CONFIG_SENSORS_SY7636A=y diff --git a/arch/arm/configs/milbeaut_m10v_defconfig b/arch/arm/configs/milbeaut_m10v_defconfig index f5eeac9c65c3..acd16204f8d7 100644 --- a/arch/arm/configs/milbeaut_m10v_defconfig +++ b/arch/arm/configs/milbeaut_m10v_defconfig @@ -107,7 +107,6 @@ CONFIG_CRYPTO_AES_ARM=m CONFIG_CRYPTO_AES_ARM_BS=m CONFIG_CRYPTO_AES_ARM_CE=m CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_CRYPTO_CRC32_ARM_CE=m # CONFIG_CRYPTO_HW is not set CONFIG_CRC_CCITT=m CONFIG_CRC_ITU_T=m diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 758276027dbc..37e3baa33b67 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH_AT91=y CONFIG_SOC_SAMA5D2=y CONFIG_SOC_SAMA5D3=y CONFIG_SOC_SAMA5D4=y +CONFIG_SOC_SAMA7D65=y CONFIG_SOC_SAMA7G5=y CONFIG_SOC_LAN966=y CONFIG_ARCH_BCM=y @@ -1306,7 +1307,6 @@ CONFIG_CRYPTO_AES_ARM=m CONFIG_CRYPTO_AES_ARM_BS=m CONFIG_CRYPTO_AES_ARM_CE=m CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_CRYPTO_CRC32_ARM_CE=m CONFIG_CRYPTO_DEV_SUN4I_SS=m CONFIG_CRYPTO_DEV_FSL_CAAM=m CONFIG_CRYPTO_DEV_EXYNOS_RNG=m diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 3a166c2f02bd..6de45d7f6078 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -428,6 +428,7 @@ CONFIG_POWER_RESET_GPIO=y CONFIG_BATTERY_BQ27XXX=m CONFIG_CHARGER_ISP1704=m CONFIG_CHARGER_TWL4030=m +CONFIG_CHARGER_TWL6030=m CONFIG_CHARGER_BQ2415X=m CONFIG_CHARGER_BQ24190=m CONFIG_CHARGER_BQ24735=m diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig index 38916ac4bce4..de0ac8f521d7 100644 --- a/arch/arm/configs/pxa_defconfig +++ b/arch/arm/configs/pxa_defconfig @@ -652,7 +652,6 @@ CONFIG_CRYPTO_TWOFISH=m CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_VMAC=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig index 1a2e93c8ee71..ea7ddf640ba7 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -12,6 +12,7 @@ CONFIG_EXPERT=y # CONFIG_IO_URING is not set CONFIG_KALLSYMS_ALL=y CONFIG_ARCH_AT91=y +CONFIG_SOC_SAMA7D65=y CONFIG_SOC_SAMA7G5=y CONFIG_ATMEL_CLOCKSOURCE_TCB=y # CONFIG_CACHE_L2X0 is not set diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 0e380e450a62..fd28f3176c6b 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -192,6 +192,7 @@ CONFIG_DW_DMAC=y CONFIG_RZN1_DMAMUX=y CONFIG_RCAR_DMAC=y CONFIG_RENESAS_USB_DMAC=y +CONFIG_RZ_DMAC=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_ARCH_EMEV2=y CONFIG_ARCH_R8A7794=y diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig index 3baec075d1ef..77048b5e1ec4 100644 --- a/arch/arm/configs/stm32_defconfig +++ b/arch/arm/configs/stm32_defconfig @@ -6,23 +6,25 @@ CONFIG_BLK_DEV_INITRD=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_EXPERT=y # CONFIG_UID16 is not set +# CONFIG_POSIX_TIMERS is not set CONFIG_BASE_SMALL=y # CONFIG_FUTEX is not set # CONFIG_EPOLL is not set # CONFIG_SIGNALFD is not set # CONFIG_EVENTFD is not set # CONFIG_AIO is not set -# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IO_URING is not set +# CONFIG_ADVISE_SYSCALLS is not set # CONFIG_MMU is not set CONFIG_ARCH_STM32=y CONFIG_CPU_V7M_NUM_IRQ=240 CONFIG_SET_MEM_PARAM=y CONFIG_DRAM_BASE=0x90000000 -CONFIG_FLASH_MEM_BASE=0x08000000 -CONFIG_FLASH_SIZE=0x00200000 # CONFIG_ATAGS is not set CONFIG_XIP_KERNEL=y CONFIG_XIP_PHYS_ADDR=0x08008000 +# CONFIG_SUSPEND is not set +# CONFIG_GCC_PLUGINS is not set CONFIG_BINFMT_FLAT=y # CONFIG_COREDUMP is not set # CONFIG_VM_EVENT_COUNTERS is not set @@ -63,6 +65,7 @@ CONFIG_DMADEVICES=y CONFIG_STM32_DMA=y CONFIG_STM32_DMAMUX=y CONFIG_STM32_MDMA=y +# CONFIG_COMMON_CLK_STM32MP is not set CONFIG_IIO=y CONFIG_STM32_ADC_CORE=y CONFIG_STM32_ADC=y @@ -74,10 +77,7 @@ CONFIG_NLS=y CONFIG_CRC_ITU_T=y CONFIG_CRC7=y CONFIG_PRINTK_TIME=y -# CONFIG_ENABLE_MUST_CHECK is not set # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y CONFIG_MAGIC_SYSRQ=y # CONFIG_SLUB_DEBUG is not set -# CONFIG_SCHED_DEBUG is not set -CONFIG_CRYPTO=y diff --git a/arch/arm/crypto/Kconfig b/arch/arm/crypto/Kconfig index 5ff49a5e9afc..32650c8431d9 100644 --- a/arch/arm/crypto/Kconfig +++ b/arch/arm/crypto/Kconfig @@ -222,30 +222,5 @@ config CRYPTO_CHACHA20_NEON Architecture: arm using: - NEON (Advanced SIMD) extensions -config CRYPTO_CRC32_ARM_CE - tristate "CRC32C and CRC32" - depends on KERNEL_MODE_NEON - depends on CRC32 - select CRYPTO_HASH - help - CRC32c CRC algorithm with the iSCSI polynomial (RFC 3385 and RFC 3720) - and CRC32 CRC algorithm (IEEE 802.3) - - Architecture: arm using: - - CRC and/or PMULL instructions - - Drivers: crc32-arm-ce and crc32c-arm-ce - -config CRYPTO_CRCT10DIF_ARM_CE - tristate "CRCT10DIF" - depends on KERNEL_MODE_NEON - depends on CRC_T10DIF - select CRYPTO_HASH - help - CRC16 CRC algorithm used for the T10 (SCSI) Data Integrity Field (DIF) - - Architecture: arm using: - - PMULL (Polynomial Multiply Long) instructions - endmenu diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile index 13e62c7c25dc..3d0e23ff9e74 100644 --- a/arch/arm/crypto/Makefile +++ b/arch/arm/crypto/Makefile @@ -20,8 +20,6 @@ obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o obj-$(CONFIG_CRYPTO_SHA2_ARM_CE) += sha2-arm-ce.o obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o -obj-$(CONFIG_CRYPTO_CRCT10DIF_ARM_CE) += crct10dif-arm-ce.o -obj-$(CONFIG_CRYPTO_CRC32_ARM_CE) += crc32-arm-ce.o aes-arm-y := aes-cipher-core.o aes-cipher-glue.o aes-arm-bs-y := aes-neonbs-core.o aes-neonbs-glue.o @@ -37,8 +35,6 @@ sha1-arm-ce-y := sha1-ce-core.o sha1-ce-glue.o sha2-arm-ce-y := sha2-ce-core.o sha2-ce-glue.o aes-arm-ce-y := aes-ce-core.o aes-ce-glue.o ghash-arm-ce-y := ghash-ce-core.o ghash-ce-glue.o -crct10dif-arm-ce-y := crct10dif-ce-core.o crct10dif-ce-glue.o -crc32-arm-ce-y:= crc32-ce-core.o crc32-ce-glue.o chacha-neon-y := chacha-scalar-core.o chacha-glue.o chacha-neon-$(CONFIG_KERNEL_MODE_NEON) += chacha-neon-core.o poly1305-arm-y := poly1305-core.o poly1305-glue.o diff --git a/arch/arm/crypto/crc32-ce-glue.c b/arch/arm/crypto/crc32-ce-glue.c deleted file mode 100644 index 20b4dff13e3a..000000000000 --- a/arch/arm/crypto/crc32-ce-glue.c +++ /dev/null @@ -1,247 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Accelerated CRC32(C) using ARM CRC, NEON and Crypto Extensions instructions - * - * Copyright (C) 2016 Linaro Ltd <ard.biesheuvel@linaro.org> - */ - -#include <linux/cpufeature.h> -#include <linux/crc32.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/string.h> - -#include <crypto/internal/hash.h> -#include <crypto/internal/simd.h> - -#include <asm/hwcap.h> -#include <asm/neon.h> -#include <asm/simd.h> -#include <linux/unaligned.h> - -#define PMULL_MIN_LEN 64L /* minimum size of buffer - * for crc32_pmull_le_16 */ -#define SCALE_F 16L /* size of NEON register */ - -asmlinkage u32 crc32_pmull_le(const u8 buf[], u32 len, u32 init_crc); -asmlinkage u32 crc32_armv8_le(u32 init_crc, const u8 buf[], u32 len); - -asmlinkage u32 crc32c_pmull_le(const u8 buf[], u32 len, u32 init_crc); -asmlinkage u32 crc32c_armv8_le(u32 init_crc, const u8 buf[], u32 len); - -static u32 (*fallback_crc32)(u32 init_crc, const u8 buf[], u32 len); -static u32 (*fallback_crc32c)(u32 init_crc, const u8 buf[], u32 len); - -static int crc32_cra_init(struct crypto_tfm *tfm) -{ - u32 *key = crypto_tfm_ctx(tfm); - - *key = 0; - return 0; -} - -static int crc32c_cra_init(struct crypto_tfm *tfm) -{ - u32 *key = crypto_tfm_ctx(tfm); - - *key = ~0; - return 0; -} - -static int crc32_setkey(struct crypto_shash *hash, const u8 *key, - unsigned int keylen) -{ - u32 *mctx = crypto_shash_ctx(hash); - - if (keylen != sizeof(u32)) - return -EINVAL; - *mctx = le32_to_cpup((__le32 *)key); - return 0; -} - -static int crc32_init(struct shash_desc *desc) -{ - u32 *mctx = crypto_shash_ctx(desc->tfm); - u32 *crc = shash_desc_ctx(desc); - - *crc = *mctx; - return 0; -} - -static int crc32_update(struct shash_desc *desc, const u8 *data, - unsigned int length) -{ - u32 *crc = shash_desc_ctx(desc); - - *crc = crc32_armv8_le(*crc, data, length); - return 0; -} - -static int crc32c_update(struct shash_desc *desc, const u8 *data, - unsigned int length) -{ - u32 *crc = shash_desc_ctx(desc); - - *crc = crc32c_armv8_le(*crc, data, length); - return 0; -} - -static int crc32_final(struct shash_desc *desc, u8 *out) -{ - u32 *crc = shash_desc_ctx(desc); - - put_unaligned_le32(*crc, out); - return 0; -} - -static int crc32c_final(struct shash_desc *desc, u8 *out) -{ - u32 *crc = shash_desc_ctx(desc); - - put_unaligned_le32(~*crc, out); - return 0; -} - -static int crc32_pmull_update(struct shash_desc *desc, const u8 *data, - unsigned int length) -{ - u32 *crc = shash_desc_ctx(desc); - unsigned int l; - - if (crypto_simd_usable()) { - if ((u32)data % SCALE_F) { - l = min_t(u32, length, SCALE_F - ((u32)data % SCALE_F)); - - *crc = fallback_crc32(*crc, data, l); - - data += l; - length -= l; - } - - if (length >= PMULL_MIN_LEN) { - l = round_down(length, SCALE_F); - - kernel_neon_begin(); - *crc = crc32_pmull_le(data, l, *crc); - kernel_neon_end(); - - data += l; - length -= l; - } - } - - if (length > 0) - *crc = fallback_crc32(*crc, data, length); - - return 0; -} - -static int crc32c_pmull_update(struct shash_desc *desc, const u8 *data, - unsigned int length) -{ - u32 *crc = shash_desc_ctx(desc); - unsigned int l; - - if (crypto_simd_usable()) { - if ((u32)data % SCALE_F) { - l = min_t(u32, length, SCALE_F - ((u32)data % SCALE_F)); - - *crc = fallback_crc32c(*crc, data, l); - - data += l; - length -= l; - } - - if (length >= PMULL_MIN_LEN) { - l = round_down(length, SCALE_F); - - kernel_neon_begin(); - *crc = crc32c_pmull_le(data, l, *crc); - kernel_neon_end(); - - data += l; - length -= l; - } - } - - if (length > 0) - *crc = fallback_crc32c(*crc, data, length); - - return 0; -} - -static struct shash_alg crc32_pmull_algs[] = { { - .setkey = crc32_setkey, - .init = crc32_init, - .update = crc32_update, - .final = crc32_final, - .descsize = sizeof(u32), - .digestsize = sizeof(u32), - - .base.cra_ctxsize = sizeof(u32), - .base.cra_init = crc32_cra_init, - .base.cra_name = "crc32", - .base.cra_driver_name = "crc32-arm-ce", - .base.cra_priority = 200, - .base.cra_flags = CRYPTO_ALG_OPTIONAL_KEY, - .base.cra_blocksize = 1, - .base.cra_module = THIS_MODULE, -}, { - .setkey = crc32_setkey, - .init = crc32_init, - .update = crc32c_update, - .final = crc32c_final, - .descsize = sizeof(u32), - .digestsize = sizeof(u32), - - .base.cra_ctxsize = sizeof(u32), - .base.cra_init = crc32c_cra_init, - .base.cra_name = "crc32c", - .base.cra_driver_name = "crc32c-arm-ce", - .base.cra_priority = 200, - .base.cra_flags = CRYPTO_ALG_OPTIONAL_KEY, - .base.cra_blocksize = 1, - .base.cra_module = THIS_MODULE, -} }; - -static int __init crc32_pmull_mod_init(void) -{ - if (elf_hwcap2 & HWCAP2_PMULL) { - crc32_pmull_algs[0].update = crc32_pmull_update; - crc32_pmull_algs[1].update = crc32c_pmull_update; - - if (elf_hwcap2 & HWCAP2_CRC32) { - fallback_crc32 = crc32_armv8_le; - fallback_crc32c = crc32c_armv8_le; - } else { - fallback_crc32 = crc32_le; - fallback_crc32c = __crc32c_le; - } - } else if (!(elf_hwcap2 & HWCAP2_CRC32)) { - return -ENODEV; - } - - return crypto_register_shashes(crc32_pmull_algs, - ARRAY_SIZE(crc32_pmull_algs)); -} - -static void __exit crc32_pmull_mod_exit(void) -{ - crypto_unregister_shashes(crc32_pmull_algs, - ARRAY_SIZE(crc32_pmull_algs)); -} - -static const struct cpu_feature __maybe_unused crc32_cpu_feature[] = { - { cpu_feature(CRC32) }, { cpu_feature(PMULL) }, { } -}; -MODULE_DEVICE_TABLE(cpu, crc32_cpu_feature); - -module_init(crc32_pmull_mod_init); -module_exit(crc32_pmull_mod_exit); - -MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); -MODULE_DESCRIPTION("Accelerated CRC32(C) using ARM CRC, NEON and Crypto Extensions"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS_CRYPTO("crc32"); -MODULE_ALIAS_CRYPTO("crc32c"); diff --git a/arch/arm/crypto/crct10dif-ce-glue.c b/arch/arm/crypto/crct10dif-ce-glue.c deleted file mode 100644 index a8b74523729e..000000000000 --- a/arch/arm/crypto/crct10dif-ce-glue.c +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions - * - * Copyright (C) 2016 Linaro Ltd <ard.biesheuvel@linaro.org> - */ - -#include <linux/crc-t10dif.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/string.h> - -#include <crypto/internal/hash.h> -#include <crypto/internal/simd.h> - -#include <asm/neon.h> -#include <asm/simd.h> - -#define CRC_T10DIF_PMULL_CHUNK_SIZE 16U - -asmlinkage u16 crc_t10dif_pmull64(u16 init_crc, const u8 *buf, size_t len); -asmlinkage void crc_t10dif_pmull8(u16 init_crc, const u8 *buf, size_t len, - u8 out[16]); - -static int crct10dif_init(struct shash_desc *desc) -{ - u16 *crc = shash_desc_ctx(desc); - - *crc = 0; - return 0; -} - -static int crct10dif_update_ce(struct shash_desc *desc, const u8 *data, - unsigned int length) -{ - u16 *crc = shash_desc_ctx(desc); - - if (length >= CRC_T10DIF_PMULL_CHUNK_SIZE && crypto_simd_usable()) { - kernel_neon_begin(); - *crc = crc_t10dif_pmull64(*crc, data, length); - kernel_neon_end(); - } else { - *crc = crc_t10dif_generic(*crc, data, length); - } - - return 0; -} - -static int crct10dif_update_neon(struct shash_desc *desc, const u8 *data, - unsigned int length) -{ - u16 *crcp = shash_desc_ctx(desc); - u8 buf[16] __aligned(16); - u16 crc = *crcp; - - if (length > CRC_T10DIF_PMULL_CHUNK_SIZE && crypto_simd_usable()) { - kernel_neon_begin(); - crc_t10dif_pmull8(crc, data, length, buf); - kernel_neon_end(); - - crc = 0; - data = buf; - length = sizeof(buf); - } - - *crcp = crc_t10dif_generic(crc, data, length); - return 0; -} - -static int crct10dif_final(struct shash_desc *desc, u8 *out) -{ - u16 *crc = shash_desc_ctx(desc); - - *(u16 *)out = *crc; - return 0; -} - -static struct shash_alg algs[] = {{ - .digestsize = CRC_T10DIF_DIGEST_SIZE, - .init = crct10dif_init, - .update = crct10dif_update_neon, - .final = crct10dif_final, - .descsize = CRC_T10DIF_DIGEST_SIZE, - - .base.cra_name = "crct10dif", - .base.cra_driver_name = "crct10dif-arm-neon", - .base.cra_priority = 150, - .base.cra_blocksize = CRC_T10DIF_BLOCK_SIZE, - .base.cra_module = THIS_MODULE, -}, { - .digestsize = CRC_T10DIF_DIGEST_SIZE, - .init = crct10dif_init, - .update = crct10dif_update_ce, - .final = crct10dif_final, - .descsize = CRC_T10DIF_DIGEST_SIZE, - - .base.cra_name = "crct10dif", - .base.cra_driver_name = "crct10dif-arm-ce", - .base.cra_priority = 200, - .base.cra_blocksize = CRC_T10DIF_BLOCK_SIZE, - .base.cra_module = THIS_MODULE, -}}; - -static int __init crc_t10dif_mod_init(void) -{ - if (!(elf_hwcap & HWCAP_NEON)) - return -ENODEV; - - return crypto_register_shashes(algs, 1 + !!(elf_hwcap2 & HWCAP2_PMULL)); -} - -static void __exit crc_t10dif_mod_exit(void) -{ - crypto_unregister_shashes(algs, 1 + !!(elf_hwcap2 & HWCAP2_PMULL)); -} - -module_init(crc_t10dif_mod_init); -module_exit(crc_t10dif_mod_exit); - -MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); -MODULE_DESCRIPTION("Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions"); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS_CRYPTO("crct10dif"); diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index e3ea34558ada..ecbc100d22a5 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -26,4 +26,10 @@ #define __read_mostly __section(".data..read_mostly") +#ifndef __ASSEMBLY__ +#ifdef CONFIG_ARCH_HAS_CACHE_LINE_SIZE +int cache_line_size(void); +#endif +#endif + #endif diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h index b9dbe1d4c8fe..b01c59076b84 100644 --- a/arch/arm/include/asm/cachetype.h +++ b/arch/arm/include/asm/cachetype.h @@ -83,6 +83,14 @@ static inline unsigned int read_ccsidr(void) asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); return val; } + +static inline unsigned int read_clidr(void) +{ + unsigned int val; + + asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (val)); + return val; +} #else /* CONFIG_CPU_V7M */ #include <linux/io.h> #include "asm/v7m.h" @@ -96,6 +104,11 @@ static inline unsigned int read_ccsidr(void) { return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR); } + +static inline unsigned int read_clidr(void) +{ + return readl(BASEADDR_V7M_SCB + V7M_SCB_CLIDR); +} #endif #endif diff --git a/arch/arm/include/asm/ecard.h b/arch/arm/include/asm/ecard.h index 4befe8d2ae19..7cbe001bf9cc 100644 --- a/arch/arm/include/asm/ecard.h +++ b/arch/arm/include/asm/ecard.h @@ -195,7 +195,7 @@ void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res, unsigned long offset, unsigned long maxsize); #define ecardm_iounmap(__ec, __addr) devm_iounmap(&(__ec)->dev, __addr) -extern struct bus_type ecard_bus_type; +extern const struct bus_type ecard_bus_type; #define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev) diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h index f40d06ad5d2a..ea4fbe7b17f6 100644 --- a/arch/arm/include/asm/tlb.h +++ b/arch/arm/include/asm/tlb.h @@ -26,14 +26,7 @@ #else /* !CONFIG_MMU */ -#include <linux/swap.h> #include <asm/tlbflush.h> - -static inline void __tlb_remove_table(void *_table) -{ - free_page_and_swap_cache((struct page *)_table); -} - #include <asm-generic/tlb.h> static inline void @@ -41,8 +34,6 @@ __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, unsigned long addr) { struct ptdesc *ptdesc = page_ptdesc(pte); - pagetable_pte_dtor(ptdesc); - #ifndef CONFIG_ARM_LPAE /* * With the classic ARM MMU, a pte page has two corresponding pmd @@ -61,7 +52,6 @@ __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp, unsigned long addr) #ifdef CONFIG_ARM_LPAE struct ptdesc *ptdesc = virt_to_ptdesc(pmdp); - pagetable_pmd_dtor(ptdesc); tlb_remove_ptdesc(tlb, ptdesc); #endif } diff --git a/arch/arm/include/asm/vfp.h b/arch/arm/include/asm/vfp.h index 157ea3426158..85ccc422d4d0 100644 --- a/arch/arm/include/asm/vfp.h +++ b/arch/arm/include/asm/vfp.h @@ -9,16 +9,6 @@ #ifndef __ASM_VFP_H #define __ASM_VFP_H -#ifndef CONFIG_AS_VFP_VMRS_FPINST -#define FPSID cr0 -#define FPSCR cr1 -#define MVFR1 cr6 -#define MVFR0 cr7 -#define FPEXC cr8 -#define FPINST cr9 -#define FPINST2 cr10 -#endif - /* FPSID bits */ #define FPSID_IMPLEMENTER_BIT (24) #define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT) diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h index ba0d4cb5377e..e2e1d5a3727a 100644 --- a/arch/arm/include/asm/vfpmacros.h +++ b/arch/arm/include/asm/vfpmacros.h @@ -8,7 +8,6 @@ #include <asm/vfp.h> -#ifdef CONFIG_AS_VFP_VMRS_FPINST .macro VFPFMRX, rd, sysreg, cond vmrs\cond \rd, \sysreg .endm @@ -16,16 +15,6 @@ .macro VFPFMXR, sysreg, rd, cond vmsr\cond \sysreg, \rd .endm -#else - @ Macros to allow building with old toolkits (with no VFP support) - .macro VFPFMRX, rd, sysreg, cond - MRC\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMRX \rd, \sysreg - .endm - - .macro VFPFMXR, sysreg, rd, cond - MCR\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMXR \sysreg, \rd - .endm -#endif @ read all the working registers back into the VFP .macro VFPFLDMIA, base, tmp diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index aaae31b8c4a5..b3333d070390 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -40,6 +40,7 @@ obj-y += entry-armv.o endif obj-$(CONFIG_MMU) += bugs.o +obj-$(CONFIG_OF) += cacheinfo.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ISA_DMA_API) += dma.o obj-$(CONFIG_FIQ) += fiq.o fiqasm.o diff --git a/arch/arm/kernel/cacheinfo.c b/arch/arm/kernel/cacheinfo.c new file mode 100644 index 000000000000..e1469b641780 --- /dev/null +++ b/arch/arm/kernel/cacheinfo.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ARM cacheinfo support + * + * Copyright (C) 2023 Linaro Ltd. + * Copyright (C) 2015 ARM Ltd. + * All Rights Reserved + */ + +#include <linux/bitfield.h> +#include <linux/cacheinfo.h> +#include <linux/of.h> + +#include <asm/cachetype.h> +#include <asm/cputype.h> +#include <asm/system_info.h> + +/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ +#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) +#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) +#define CLIDR_CTYPE(clidr, level) \ + (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) + +#define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ + +#define CTR_FORMAT_MASK GENMASK(31, 29) +#define CTR_FORMAT_ARMV6 0 +#define CTR_FORMAT_ARMV7 4 +#define CTR_CWG_MASK GENMASK(27, 24) +#define CTR_DSIZE_LEN_MASK GENMASK(13, 12) +#define CTR_ISIZE_LEN_MASK GENMASK(1, 0) + +/* Also valid for v7m */ +static inline int cache_line_size_cp15(void) +{ + u32 ctr = read_cpuid_cachetype(); + u32 format = FIELD_GET(CTR_FORMAT_MASK, ctr); + + if (format == CTR_FORMAT_ARMV7) { + u32 cwg = FIELD_GET(CTR_CWG_MASK, ctr); + + return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; + } else if (WARN_ON_ONCE(format != CTR_FORMAT_ARMV6)) { + return ARCH_DMA_MINALIGN; + } + + return 8 << max(FIELD_GET(CTR_ISIZE_LEN_MASK, ctr), + FIELD_GET(CTR_DSIZE_LEN_MASK, ctr)); +} + +int cache_line_size(void) +{ + if (coherency_max_size != 0) + return coherency_max_size; + + /* CP15 is optional / implementation defined before ARMv6 */ + if (cpu_architecture() < CPU_ARCH_ARMv6) + return ARCH_DMA_MINALIGN; + + return cache_line_size_cp15(); +} +EXPORT_SYMBOL_GPL(cache_line_size); + +static inline enum cache_type get_cache_type(int level) +{ + u32 clidr; + + if (level > MAX_CACHE_LEVEL) + return CACHE_TYPE_NOCACHE; + + clidr = read_clidr(); + + return CLIDR_CTYPE(clidr, level); +} + +static void ci_leaf_init(struct cacheinfo *this_leaf, + enum cache_type type, unsigned int level) +{ + this_leaf->level = level; + this_leaf->type = type; +} + +static int detect_cache_level(unsigned int *level_p, unsigned int *leaves_p) +{ + unsigned int ctype, level, leaves; + u32 ctr, format; + + /* CLIDR is not present before ARMv7/v7m */ + if (cpu_architecture() < CPU_ARCH_ARMv7) + return -EOPNOTSUPP; + + /* Don't try reading CLIDR if CTR declares old format */ + ctr = read_cpuid_cachetype(); + format = FIELD_GET(CTR_FORMAT_MASK, ctr); + if (format != CTR_FORMAT_ARMV7) + return -EOPNOTSUPP; + + for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { + ctype = get_cache_type(level); + if (ctype == CACHE_TYPE_NOCACHE) { + level--; + break; + } + /* Separate instruction and data caches */ + leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1; + } + + *level_p = level; + *leaves_p = leaves; + + return 0; +} + +int early_cache_level(unsigned int cpu) +{ + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + + return detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves); +} + +int init_cache_level(unsigned int cpu) +{ + unsigned int level, leaves; + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + int fw_level; + int ret; + + ret = detect_cache_level(&level, &leaves); + if (ret) + return ret; + + fw_level = of_find_last_cache_level(cpu); + + if (level < fw_level) { + /* + * some external caches not specified in CLIDR_EL1 + * the information may be available in the device tree + * only unified external caches are considered here + */ + leaves += (fw_level - level); + level = fw_level; + } + + this_cpu_ci->num_levels = level; + this_cpu_ci->num_leaves = leaves; + return 0; +} + +int populate_cache_leaves(unsigned int cpu) +{ + unsigned int level, idx; + enum cache_type type; + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + struct cacheinfo *this_leaf = this_cpu_ci->info_list; + unsigned int arch = cpu_architecture(); + + /* CLIDR is not present before ARMv7/v7m */ + if (arch < CPU_ARCH_ARMv7) + return -EOPNOTSUPP; + + for (idx = 0, level = 1; level <= this_cpu_ci->num_levels && + idx < this_cpu_ci->num_leaves; idx++, level++) { + type = get_cache_type(level); + if (type == CACHE_TYPE_SEPARATE) { + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); + } else { + ci_leaf_init(this_leaf++, type, level); + } + } + + return 0; +} diff --git a/arch/arm/kernel/isa.c b/arch/arm/kernel/isa.c index 905b1b191546..db8be609fab2 100644 --- a/arch/arm/kernel/isa.c +++ b/arch/arm/kernel/isa.c @@ -16,7 +16,7 @@ static unsigned int isa_membase, isa_portbase, isa_portshift; -static struct ctl_table ctl_isa_vars[] = { +static const struct ctl_table ctl_isa_vars[] = { { .procname = "membase", .data = &isa_membase, diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c index 80ceb5bd2680..dd430477e7c1 100644 --- a/arch/arm/kernel/machine_kexec.c +++ b/arch/arm/kernel/machine_kexec.c @@ -127,29 +127,6 @@ void crash_smp_send_stop(void) cpus_stopped = 1; } -static void machine_kexec_mask_interrupts(void) -{ - unsigned int i; - struct irq_desc *desc; - - for_each_irq_desc(i, desc) { - struct irq_chip *chip; - - chip = irq_desc_get_chip(desc); - if (!chip) - continue; - - if (chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data)) - chip->irq_eoi(&desc->irq_data); - - if (chip->irq_mask) - chip->irq_mask(&desc->irq_data); - - if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data)) - chip->irq_disable(&desc->irq_data); - } -} - void machine_crash_shutdown(struct pt_regs *regs) { local_irq_disable(); diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index e6a857bf0ce6..a41c93988d2c 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -880,10 +880,7 @@ static void __init request_standard_resources(const struct machine_desc *mdesc) */ boot_alias_start = phys_to_idmap(start); if (arm_has_idmap_alias() && boot_alias_start != IDMAP_INVALID_ADDR) { - res = memblock_alloc(sizeof(*res), SMP_CACHE_BYTES); - if (!res) - panic("%s: Failed to allocate %zu bytes\n", - __func__, sizeof(*res)); + res = memblock_alloc_or_panic(sizeof(*res), SMP_CACHE_BYTES); res->name = "System RAM (boot alias)"; res->start = boot_alias_start; res->end = phys_to_idmap(res_end); @@ -891,10 +888,7 @@ static void __init request_standard_resources(const struct machine_desc *mdesc) request_resource(&iomem_resource, res); } - res = memblock_alloc(sizeof(*res), SMP_CACHE_BYTES); - if (!res) - panic("%s: Failed to allocate %zu bytes\n", __func__, - sizeof(*res)); + res = memblock_alloc_or_panic(sizeof(*res), SMP_CACHE_BYTES); res->name = "System RAM"; res->start = start; res->end = res_end; diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 0ca5aae1bcc3..007874320937 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -45,3 +45,9 @@ ifeq ($(CONFIG_KERNEL_MODE_NEON),y) endif obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o + +obj-$(CONFIG_CRC32_ARCH) += crc32-arm.o +crc32-arm-y := crc32-glue.o crc32-core.o + +obj-$(CONFIG_CRC_T10DIF_ARCH) += crc-t10dif-arm.o +crc-t10dif-arm-y := crc-t10dif-glue.o crc-t10dif-core.o diff --git a/arch/arm/crypto/crct10dif-ce-core.S b/arch/arm/lib/crc-t10dif-core.S index 2bbf2df9c1e2..2bbf2df9c1e2 100644 --- a/arch/arm/crypto/crct10dif-ce-core.S +++ b/arch/arm/lib/crc-t10dif-core.S diff --git a/arch/arm/lib/crc-t10dif-glue.c b/arch/arm/lib/crc-t10dif-glue.c new file mode 100644 index 000000000000..d24dee62670e --- /dev/null +++ b/arch/arm/lib/crc-t10dif-glue.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions + * + * Copyright (C) 2016 Linaro Ltd <ard.biesheuvel@linaro.org> + */ + +#include <linux/crc-t10dif.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/string.h> + +#include <crypto/internal/simd.h> + +#include <asm/neon.h> +#include <asm/simd.h> + +static DEFINE_STATIC_KEY_FALSE(have_neon); +static DEFINE_STATIC_KEY_FALSE(have_pmull); + +#define CRC_T10DIF_PMULL_CHUNK_SIZE 16U + +asmlinkage u16 crc_t10dif_pmull64(u16 init_crc, const u8 *buf, size_t len); +asmlinkage void crc_t10dif_pmull8(u16 init_crc, const u8 *buf, size_t len, + u8 out[16]); + +u16 crc_t10dif_arch(u16 crc, const u8 *data, size_t length) +{ + if (length >= CRC_T10DIF_PMULL_CHUNK_SIZE) { + if (static_branch_likely(&have_pmull)) { + if (crypto_simd_usable()) { + kernel_neon_begin(); + crc = crc_t10dif_pmull64(crc, data, length); + kernel_neon_end(); + return crc; + } + } else if (length > CRC_T10DIF_PMULL_CHUNK_SIZE && + static_branch_likely(&have_neon) && + crypto_simd_usable()) { + u8 buf[16] __aligned(16); + + kernel_neon_begin(); + crc_t10dif_pmull8(crc, data, length, buf); + kernel_neon_end(); + + crc = 0; + data = buf; + length = sizeof(buf); + } + } + return crc_t10dif_generic(crc, data, length); +} +EXPORT_SYMBOL(crc_t10dif_arch); + +static int __init crc_t10dif_arm_init(void) +{ + if (elf_hwcap & HWCAP_NEON) { + static_branch_enable(&have_neon); + if (elf_hwcap2 & HWCAP2_PMULL) + static_branch_enable(&have_pmull); + } + return 0; +} +arch_initcall(crc_t10dif_arm_init); + +static void __exit crc_t10dif_arm_exit(void) +{ +} +module_exit(crc_t10dif_arm_exit); + +bool crc_t10dif_is_optimized(void) +{ + return static_key_enabled(&have_neon); +} +EXPORT_SYMBOL(crc_t10dif_is_optimized); + +MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); +MODULE_DESCRIPTION("Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions"); +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/crypto/crc32-ce-core.S b/arch/arm/lib/crc32-core.S index 88f9edf94e95..6f674f30c70b 100644 --- a/arch/arm/crypto/crc32-ce-core.S +++ b/arch/arm/lib/crc32-core.S @@ -48,7 +48,6 @@ */ #include <linux/linkage.h> -#include <linux/cfi_types.h> #include <asm/assembler.h> .text @@ -297,11 +296,11 @@ ARM_BE8(rev16 r3, r3 ) .endm .align 5 -SYM_TYPED_FUNC_START(crc32_armv8_le) +SYM_FUNC_START(crc32_armv8_le) __crc32 SYM_FUNC_END(crc32_armv8_le) .align 5 -SYM_TYPED_FUNC_START(crc32c_armv8_le) +SYM_FUNC_START(crc32c_armv8_le) __crc32 c SYM_FUNC_END(crc32c_armv8_le) diff --git a/arch/arm/lib/crc32-glue.c b/arch/arm/lib/crc32-glue.c new file mode 100644 index 000000000000..2c30ba3d80e6 --- /dev/null +++ b/arch/arm/lib/crc32-glue.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Accelerated CRC32(C) using ARM CRC, NEON and Crypto Extensions instructions + * + * Copyright (C) 2016 Linaro Ltd <ard.biesheuvel@linaro.org> + */ + +#include <linux/cpufeature.h> +#include <linux/crc32.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/string.h> + +#include <crypto/internal/simd.h> + +#include <asm/hwcap.h> +#include <asm/neon.h> +#include <asm/simd.h> + +static DEFINE_STATIC_KEY_FALSE(have_crc32); +static DEFINE_STATIC_KEY_FALSE(have_pmull); + +#define PMULL_MIN_LEN 64 /* min size of buffer for pmull functions */ + +asmlinkage u32 crc32_pmull_le(const u8 buf[], u32 len, u32 init_crc); +asmlinkage u32 crc32_armv8_le(u32 init_crc, const u8 buf[], u32 len); + +asmlinkage u32 crc32c_pmull_le(const u8 buf[], u32 len, u32 init_crc); +asmlinkage u32 crc32c_armv8_le(u32 init_crc, const u8 buf[], u32 len); + +static u32 crc32_le_scalar(u32 crc, const u8 *p, size_t len) +{ + if (static_branch_likely(&have_crc32)) + return crc32_armv8_le(crc, p, len); + return crc32_le_base(crc, p, len); +} + +u32 crc32_le_arch(u32 crc, const u8 *p, size_t len) +{ + if (len >= PMULL_MIN_LEN + 15 && + static_branch_likely(&have_pmull) && crypto_simd_usable()) { + size_t n = -(uintptr_t)p & 15; + + /* align p to 16-byte boundary */ + if (n) { + crc = crc32_le_scalar(crc, p, n); + p += n; + len -= n; + } + n = round_down(len, 16); + kernel_neon_begin(); + crc = crc32_pmull_le(p, n, crc); + kernel_neon_end(); + p += n; + len -= n; + } + return crc32_le_scalar(crc, p, len); +} +EXPORT_SYMBOL(crc32_le_arch); + +static u32 crc32c_le_scalar(u32 crc, const u8 *p, size_t len) +{ + if (static_branch_likely(&have_crc32)) + return crc32c_armv8_le(crc, p, len); + return crc32c_le_base(crc, p, len); +} + +u32 crc32c_le_arch(u32 crc, const u8 *p, size_t len) +{ + if (len >= PMULL_MIN_LEN + 15 && + static_branch_likely(&have_pmull) && crypto_simd_usable()) { + size_t n = -(uintptr_t)p & 15; + + /* align p to 16-byte boundary */ + if (n) { + crc = crc32c_le_scalar(crc, p, n); + p += n; + len -= n; + } + n = round_down(len, 16); + kernel_neon_begin(); + crc = crc32c_pmull_le(p, n, crc); + kernel_neon_end(); + p += n; + len -= n; + } + return crc32c_le_scalar(crc, p, len); +} +EXPORT_SYMBOL(crc32c_le_arch); + +u32 crc32_be_arch(u32 crc, const u8 *p, size_t len) +{ + return crc32_be_base(crc, p, len); +} +EXPORT_SYMBOL(crc32_be_arch); + +static int __init crc32_arm_init(void) +{ + if (elf_hwcap2 & HWCAP2_CRC32) + static_branch_enable(&have_crc32); + if (elf_hwcap2 & HWCAP2_PMULL) + static_branch_enable(&have_pmull); + return 0; +} +arch_initcall(crc32_arm_init); + +static void __exit crc32_arm_exit(void) +{ +} +module_exit(crc32_arm_exit); + +u32 crc32_optimizations(void) +{ + if (elf_hwcap2 & (HWCAP2_CRC32 | HWCAP2_PMULL)) + return CRC32_LE_OPTIMIZATION | CRC32C_OPTIMIZATION; + return 0; +} +EXPORT_SYMBOL(crc32_optimizations); + +MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); +MODULE_DESCRIPTION("Accelerated CRC32(C) using ARM CRC, NEON and Crypto Extensions"); +MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 344f5305f69a..04bd91c72521 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -58,6 +58,17 @@ config SOC_SAMA5D4 help Select this if you are using one of Microchip's SAMA5D4 family SoC. +config SOC_SAMA7D65 + bool "SAMA7D65 family" + depends on ARCH_MULTI_V7 + select HAVE_AT91_GENERATED_CLK + select HAVE_AT91_SAM9X60_PLL + select HAVE_AT91_USB_CLK + select HAVE_AT91_UTMI + select SOC_SAMA7 + help + Select this if you are using one of Microchip's SAMA7D65 family SoC. + config SOC_SAMA7G5 bool "SAMA7G5 family" depends on ARCH_MULTI_V7 diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index b9b995f8a36e..05a1547642b6 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -598,7 +598,21 @@ static int at91_suspend_finish(unsigned long val) return 0; } -static void at91_pm_switch_ba_to_vbat(void) +/** + * at91_pm_switch_ba_to_auto() - Configure Backup Unit Power Switch + * to automatic/hardware mode. + * + * The Backup Unit Power Switch can be managed either by software or hardware. + * Enabling hardware mode allows the automatic transition of power between + * VDDANA (or VDDIN33) and VDDBU (or VBAT, respectively), based on the + * availability of these power sources. + * + * If the Backup Unit Power Switch is already in automatic mode, no action is + * required. If it is in software-controlled mode, it is switched to automatic + * mode to enhance safety and eliminate the need for toggling between power + * sources. + */ +static void at91_pm_switch_ba_to_auto(void) { unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu); unsigned int val; @@ -609,24 +623,19 @@ static void at91_pm_switch_ba_to_vbat(void) val = readl(soc_pm.data.sfrbu + offset); - /* Already on VBAT. */ - if (!(val & soc_pm.sfrbu_regs.pswbu.state)) + /* Already on auto/hardware. */ + if (!(val & soc_pm.sfrbu_regs.pswbu.ctrl)) return; - val &= ~soc_pm.sfrbu_regs.pswbu.softsw; - val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl; + val &= ~soc_pm.sfrbu_regs.pswbu.ctrl; + val |= soc_pm.sfrbu_regs.pswbu.key; writel(val, soc_pm.data.sfrbu + offset); - - /* Wait for update. */ - val = readl(soc_pm.data.sfrbu + offset); - while (val & soc_pm.sfrbu_regs.pswbu.state) - val = readl(soc_pm.data.sfrbu + offset); } static void at91_pm_suspend(suspend_state_t state) { if (soc_pm.data.mode == AT91_PM_BACKUP) { - at91_pm_switch_ba_to_vbat(); + at91_pm_switch_ba_to_auto(); cpu_suspend(0, at91_suspend_finish); diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 2a8a9fe46586..3fa15f342240 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -27,6 +27,7 @@ config ARCH_DAVINCI_DA830 config ARCH_DAVINCI_DA850 bool "DA850/OMAP-L138/AM18x based system" + select ARCH_DAVINCI_DA8XX select DAVINCI_CP_INTC config ARCH_DAVINCI_DA8XX diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index a643b71e30a3..08ec6bd84ada 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -8,6 +8,7 @@ menuconfig ARCH_OMAP1 select ARCH_OMAP select CLKSRC_MMIO select FORCE_PCI if PCCARD + select GENERIC_IRQ_CHIP select GPIOLIB help Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 3312ef93355d..a5bf5554800f 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -289,7 +289,7 @@ static struct gpiod_lookup_table nokia770_irq_gpio_table = { GPIO_LOOKUP("gpio-0-15", 15, "ads7846_irq", GPIO_ACTIVE_HIGH), /* GPIO used for retu IRQ */ - GPIO_LOOKUP("gpio-48-63", 15, "retu_irq", + GPIO_LOOKUP("gpio-48-63", 14, "retu_irq", GPIO_ACTIVE_HIGH), /* GPIO used for tahvo IRQ */ GPIO_LOOKUP("gpio-32-47", 8, "tahvo_irq", diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 2441d96b7144..a4785302b7ae 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -523,7 +523,7 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm) * Set the powerdomain @pwrdm's next power state to @pwrst. The powerdomain * may not enter this state immediately if the preconditions for this state * have not been satisfied. Returns -EINVAL if the powerdomain pointer is - * null or if the power state is invalid for the powerdomin, or returns 0 + * null or if the power state is invalid for the powerdomain, or returns 0 * upon success. */ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index 0c8d9000df5a..dd930e3a61a4 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -31,10 +31,10 @@ /* * Constants */ -#define SHARPSL_CHARGE_ON_TIME_INTERVAL (msecs_to_jiffies(1*60*1000)) /* 1 min */ -#define SHARPSL_CHARGE_FINISH_TIME (msecs_to_jiffies(10*60*1000)) /* 10 min */ -#define SHARPSL_BATCHK_TIME (msecs_to_jiffies(15*1000)) /* 15 sec */ -#define SHARPSL_BATCHK_TIME_SUSPEND (60*10) /* 10 min */ +#define SHARPSL_CHARGE_ON_TIME_INTERVAL (secs_to_jiffies(60)) +#define SHARPSL_CHARGE_FINISH_TIME (secs_to_jiffies(10*60)) +#define SHARPSL_BATCHK_TIME (secs_to_jiffies(15)) +#define SHARPSL_BATCHK_TIME_SUSPEND (60*10) /* 10 min */ #define SHARPSL_WAIT_CO_TIME 15 /* 15 sec */ #define SHARPSL_WAIT_DISCHARGE_ON 100 /* 100 msec */ diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c index 9f7454b8efa7..2cde4c83b7f9 100644 --- a/arch/arm/mach-rpc/ecard.c +++ b/arch/arm/mach-rpc/ecard.c @@ -1124,7 +1124,7 @@ static int ecard_match(struct device *_dev, const struct device_driver *_drv) return ret; } -struct bus_type ecard_bus_type = { +const struct bus_type ecard_bus_type = { .name = "ecard", .dev_groups = ecard_dev_groups, .match = ecard_match, diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index a956b489b6ea..2bc7e73a8582 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S @@ -136,6 +136,7 @@ ENDPROC(shmobile_smp_sleep) .long shmobile_smp_arg - 1b .bss + .align 2 .globl shmobile_smp_mpidr shmobile_smp_mpidr: .space NR_CPUS * 4 diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c index 2bec87c3327d..39fd5df73317 100644 --- a/arch/arm/mm/fault-armv.c +++ b/arch/arm/mm/fault-armv.c @@ -62,7 +62,7 @@ static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address, } static int adjust_pte(struct vm_area_struct *vma, unsigned long address, - unsigned long pfn, struct vm_fault *vmf) + unsigned long pfn, bool need_lock) { spinlock_t *ptl; pgd_t *pgd; @@ -99,12 +99,11 @@ again: if (!pte) return 0; - /* - * If we are using split PTE locks, then we need to take the page - * lock here. Otherwise we are using shared mm->page_table_lock - * which is already locked, thus cannot take it. - */ - if (ptl != vmf->ptl) { + if (need_lock) { + /* + * Use nested version here to indicate that we are already + * holding one similar spinlock. + */ spin_lock_nested(ptl, SINGLE_DEPTH_NESTING); if (unlikely(!pmd_same(pmdval, pmdp_get_lockless(pmd)))) { pte_unmap_unlock(pte, ptl); @@ -114,7 +113,7 @@ again: ret = do_adjust_pte(vma, address, pfn, pte); - if (ptl != vmf->ptl) + if (need_lock) spin_unlock(ptl); pte_unmap(pte); @@ -123,9 +122,10 @@ again: static void make_coherent(struct address_space *mapping, struct vm_area_struct *vma, - unsigned long addr, pte_t *ptep, unsigned long pfn, - struct vm_fault *vmf) + unsigned long addr, pte_t *ptep, unsigned long pfn) { + const unsigned long pmd_start_addr = ALIGN_DOWN(addr, PMD_SIZE); + const unsigned long pmd_end_addr = pmd_start_addr + PMD_SIZE; struct mm_struct *mm = vma->vm_mm; struct vm_area_struct *mpnt; unsigned long offset; @@ -142,6 +142,14 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, flush_dcache_mmap_lock(mapping); vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) { /* + * If we are using split PTE locks, then we need to take the pte + * lock. Otherwise we are using shared mm->page_table_lock which + * is already locked, thus cannot take it. + */ + bool need_lock = IS_ENABLED(CONFIG_SPLIT_PTE_PTLOCKS); + unsigned long mpnt_addr; + + /* * If this VMA is not in our MM, we can ignore it. * Note that we intentionally mask out the VMA * that we are fixing up. @@ -151,7 +159,12 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, if (!(mpnt->vm_flags & VM_MAYSHARE)) continue; offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; - aliases += adjust_pte(mpnt, mpnt->vm_start + offset, pfn, vmf); + mpnt_addr = mpnt->vm_start + offset; + + /* Avoid deadlocks by not grabbing the same PTE lock again. */ + if (mpnt_addr >= pmd_start_addr && mpnt_addr < pmd_end_addr) + need_lock = false; + aliases += adjust_pte(mpnt, mpnt_addr, pfn, need_lock); } flush_dcache_mmap_unlock(mapping); if (aliases) @@ -194,7 +207,7 @@ void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma, __flush_dcache_folio(mapping, folio); if (mapping) { if (cache_is_vivt()) - make_coherent(mapping, vma, addr, ptep, pfn, vmf); + make_coherent(mapping, vma, addr, ptep, pfn); else if (vma->vm_flags & VM_EXEC) __flush_icache_all(); } diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index f5b7a16c5803..f02f872ea8a9 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -726,13 +726,8 @@ EXPORT_SYMBOL(phys_mem_access_prot); static void __init *early_alloc(unsigned long sz) { - void *ptr = memblock_alloc(sz, sz); + return memblock_alloc_or_panic(sz, sz); - if (!ptr) - panic("%s: Failed to allocate %lu bytes align=0x%lx\n", - __func__, sz, sz); - - return ptr; } static void *__init late_alloc(unsigned long sz) @@ -1027,10 +1022,7 @@ void __init iotable_init(struct map_desc *io_desc, int nr) if (!nr) return; - svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm)); - if (!svm) - panic("%s: Failed to allocate %zu bytes align=0x%zx\n", - __func__, sizeof(*svm) * nr, __alignof__(*svm)); + svm = memblock_alloc_or_panic(sizeof(*svm) * nr, __alignof__(*svm)); for (md = io_desc; nr; md++, nr--) { create_mapping(md); @@ -1052,10 +1044,7 @@ void __init vm_reserve_area_early(unsigned long addr, unsigned long size, struct vm_struct *vm; struct static_vm *svm; - svm = memblock_alloc(sizeof(*svm), __alignof__(*svm)); - if (!svm) - panic("%s: Failed to allocate %zu bytes align=0x%zx\n", - __func__, sizeof(*svm), __alignof__(*svm)); + svm = memblock_alloc_or_panic(sizeof(*svm), __alignof__(*svm)); vm = &svm->vm; vm->addr = (void *)addr; diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index c415f3859b20..1a8f6914ee59 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -162,10 +162,7 @@ void __init paging_init(const struct machine_desc *mdesc) mpu_setup(); /* allocate the zero page. */ - zero_page = (void *)memblock_alloc(PAGE_SIZE, PAGE_SIZE); - if (!zero_page) - panic("%s: Failed to allocate %lu bytes align=0x%lx\n", - __func__, PAGE_SIZE, PAGE_SIZE); + zero_page = (void *)memblock_alloc_or_panic(PAGE_SIZE, PAGE_SIZE); bootmem_init(); diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index f8e9bc58a84f..4eb81b7ed03a 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -17,11 +17,11 @@ #include "mm.h" #ifdef CONFIG_ARM_LPAE -#define __pgd_alloc() kmalloc_array(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL) -#define __pgd_free(pgd) kfree(pgd) +#define _pgd_alloc(mm) kmalloc_array(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL | __GFP_ZERO) +#define _pgd_free(mm, pgd) kfree(pgd) #else -#define __pgd_alloc() (pgd_t *)__get_free_pages(GFP_KERNEL, 2) -#define __pgd_free(pgd) free_pages((unsigned long)pgd, 2) +#define _pgd_alloc(mm) __pgd_alloc(mm, 2) +#define _pgd_free(mm, pgd) __pgd_free(mm, pgd) #endif /* @@ -35,12 +35,10 @@ pgd_t *pgd_alloc(struct mm_struct *mm) pmd_t *new_pmd, *init_pmd; pte_t *new_pte, *init_pte; - new_pgd = __pgd_alloc(); + new_pgd = _pgd_alloc(mm); if (!new_pgd) goto no_pgd; - memset(new_pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t)); - /* * Copy over the kernel and IO PGD entries */ @@ -134,7 +132,7 @@ no_pmd: no_pud: p4d_free(mm, new_p4d); no_p4d: - __pgd_free(new_pgd); + _pgd_free(mm, new_pgd); no_pgd: return NULL; } @@ -207,5 +205,5 @@ no_pgd: p4d_free(mm, p4d); } #endif - __pgd_free(pgd_base); + _pgd_free(mm, pgd_base); } diff --git a/arch/arm/tools/syscall.tbl b/arch/arm/tools/syscall.tbl index 49eeb2ad8dbd..27c1d5ebcd91 100644 --- a/arch/arm/tools/syscall.tbl +++ b/arch/arm/tools/syscall.tbl @@ -481,3 +481,4 @@ 464 common getxattrat sys_getxattrat 465 common listxattrat sys_listxattrat 466 common removexattrat sys_removexattrat +467 common open_tree_attr sys_open_tree_attr diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h index 32090b0fb250..a2f0c47e0ce7 100644 --- a/arch/arm/vfp/vfpinstr.h +++ b/arch/arm/vfp/vfpinstr.h @@ -62,8 +62,6 @@ #define FPSCR_C (1 << 29) #define FPSCR_V (1 << 28) -#ifdef CONFIG_AS_VFP_VMRS_FPINST - #define fmrx(_vfp_) ({ \ u32 __v; \ asm volatile (".fpu vfpv2\n" \ @@ -78,26 +76,6 @@ : : "r" (_var_) : "cc"); \ }) -#else - -#define vfpreg(_vfp_) #_vfp_ - -#define fmrx(_vfp_) ({ \ - u32 __v; \ - asm volatile ("mrc p10, 7, %0, " vfpreg(_vfp_) "," \ - "cr0, 0 @ fmrx %0, " #_vfp_ \ - : "=r" (__v) : : "cc"); \ - __v; \ -}) - -#define fmxr(_vfp_, _var_) ({ \ - asm volatile ("mcr p10, 7, %0, " vfpreg(_vfp_) "," \ - "cr0, 0 @ fmxr " #_vfp_ ", %0" \ - : : "r" (_var_) : "cc"); \ -}) - -#endif - u32 vfp_single_cpdo(u32 inst, u32 fpscr); u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs); diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index d44867fc0c5e..7803d50b90f8 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -168,7 +168,7 @@ static void vfp_thread_copy(struct thread_info *thread) /* * When this function is called with the following 'cmd's, the following * is true while this function is being run: - * THREAD_NOFTIFY_SWTICH: + * THREAD_NOTIFY_SWITCH: * - the previously running thread will not be scheduled onto another CPU. * - the next thread to be run (v) will not be running on another CPU. * - thread->cpu is the local CPU number |