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/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2020, Intel Corporation
* DWMAC Intel header file
*/
#ifndef __DWMAC_INTEL_H__
#define __DWMAC_INTEL_H__
#define POLL_DELAY_US 8
/* SERDES Register */
#define SERDES_GCR 0x0 /* Global Conguration */
#define SERDES_GSR0 0x5 /* Global Status Reg0 */
#define SERDES_GCR0 0xb /* Global Configuration Reg0 */
/* SERDES defines */
#define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */
#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
#define SERDES_RST BIT(2) /* Serdes Reset */
#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
#define SERDES_RATE_MASK GENMASK(9, 8)
#define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */
#define SERDES_LINK_MODE_MASK GENMASK(2, 1)
#define SERDES_LINK_MODE_SHIFT 1
#define SERDES_PWR_ST_SHIFT 4
#define SERDES_PWR_ST_P0 0x0
#define SERDES_PWR_ST_P3 0x3
#define SERDES_LINK_MODE_2G5 0x3
#define SERSED_LINK_MODE_1G 0x2
#define SERDES_PCLK_37p5MHZ 0x0
#define SERDES_PCLK_70MHZ 0x1
#define SERDES_RATE_PCIE_GEN1 0x0
#define SERDES_RATE_PCIE_GEN2 0x1
#define SERDES_RATE_PCIE_SHIFT 8
#define SERDES_PCLK_SHIFT 12
#define INTEL_MGBE_ADHOC_ADDR 0x15
#define INTEL_MGBE_XPCS_ADDR 0x16
/* Cross-timestamping defines */
#define ART_CPUID_LEAF 0x15
#define EHL_PSE_ART_MHZ 19200000
/* Selection for PTP Clock Freq belongs to PSE & PCH GbE */
#define PSE_PTP_CLK_FREQ_MASK (GMAC_GPO0 | GMAC_GPO3)
#define PSE_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0)
#define PSE_PTP_CLK_FREQ_200MHZ (GMAC_GPO0 | GMAC_GPO3)
#define PSE_PTP_CLK_FREQ_256MHZ (0)
#define PCH_PTP_CLK_FREQ_MASK (GMAC_GPO0)
#define PCH_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0)
#define PCH_PTP_CLK_FREQ_200MHZ (0)
/* Modphy Register index */
#define R_PCH_FIA_15_PCR_LOS1_REG_BASE 8
#define R_PCH_FIA_15_PCR_LOS2_REG_BASE 9
#define R_PCH_FIA_15_PCR_LOS3_REG_BASE 10
#define R_PCH_FIA_15_PCR_LOS4_REG_BASE 11
#define R_PCH_FIA_15_PCR_LOS5_REG_BASE 12
#define B_PCH_FIA_PCR_L0O GENMASK(3, 0)
#define PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0 13
#define PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2 14
#define PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7 15
#define PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10 16
#define PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30 17
#define PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0 18
#define PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2 19
#define PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7 20
#define PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10 21
#define PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30 22
#define B_MODPHY_PCR_LCPLL_DWORD0_1G 0x46AAAA41
#define N_MODPHY_PCR_LCPLL_DWORD2_1G 0x00000139
#define N_MODPHY_PCR_LCPLL_DWORD7_1G 0x002A0003
#define N_MODPHY_PCR_LPPLL_DWORD10_1G 0x00170008
#define N_MODPHY_PCR_CMN_ANA_DWORD30_1G 0x0000D4AC
#define B_MODPHY_PCR_LCPLL_DWORD0_2P5G 0x58555551
#define N_MODPHY_PCR_LCPLL_DWORD2_2P5G 0x0000012D
#define N_MODPHY_PCR_LCPLL_DWORD7_2P5G 0x001F0003
#define N_MODPHY_PCR_LPPLL_DWORD10_2P5G 0x00170008
#define N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G 0x8200ACAC
#endif /* __DWMAC_INTEL_H__ */
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