blob: a5478f3e8589df8f1cdc476ce0cf47a00122aca5 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
|
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __TIMER_OF_H__
#define __TIMER_OF_H__
#include <linux/clockchips.h>
#define TIMER_OF_BASE 0x1
#define TIMER_OF_CLOCK 0x2
#define TIMER_OF_IRQ 0x4
struct of_timer_irq {
int irq;
int index;
int percpu;
const char *name;
unsigned long flags;
irq_handler_t handler;
};
struct of_timer_base {
void __iomem *base;
const char *name;
int index;
};
struct of_timer_clk {
struct clk *clk;
const char *name;
int index;
unsigned long rate;
unsigned long period;
};
struct timer_of {
unsigned int flags;
struct device_node *np;
struct clock_event_device clkevt;
struct of_timer_base of_base;
struct of_timer_irq of_irq;
struct of_timer_clk of_clk;
void *private_data;
};
static inline struct timer_of *to_timer_of(struct clock_event_device *clkevt)
{
return container_of(clkevt, struct timer_of, clkevt);
}
static inline void __iomem *timer_of_base(struct timer_of *to)
{
return to->of_base.base;
}
static inline int timer_of_irq(struct timer_of *to)
{
return to->of_irq.irq;
}
static inline unsigned long timer_of_rate(struct timer_of *to)
{
return to->of_clk.rate;
}
static inline unsigned long timer_of_period(struct timer_of *to)
{
return to->of_clk.period;
}
extern int __init timer_of_init(struct device_node *np,
struct timer_of *to);
extern void __init timer_of_cleanup(struct timer_of *to);
#endif
|