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|
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for J721S2 SoC Family Main Domain peripherals
*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
reg = <0x0 0x70000000 0x0 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x70000000 0x400000>;
atf-sram@0 {
reg = <0x0 0x20000>;
};
tifs-sram@1f0000 {
reg = <0x1f0000 0x10000>;
};
l3cache-sram@200000 {
reg = <0x200000 0x200000>;
};
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x100000>, /* GICD */
<0x00 0x01900000 0x00 0x100000>, /* GICR */
<0x00 0x6f000000 0x00 0x2000>, /* GICC */
<0x00 0x6f010000 0x00 0x1000>, /* GICH */
<0x00 0x6f020000 0x00 0x2000>; /* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: msi-controller@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
msi-controller;
#msi-cells = <1>;
};
};
main_gpio_intr: interrupt-controller@a00000 {
compatible = "ti,sci-intr";
reg = <0x00 0x00a00000 0x00 0x800>;
ti,intr-trigger-type = <1>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <148>;
ti,interrupt-ranges = <8 392 56>;
};
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x0 0x11c000 0x0 0x120>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
main_crypto: crypto@4e00000 {
compatible = "ti,j721e-sa2ul";
reg = <0x00 0x04e00000 0x00 0x1200>;
power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
<&main_udmap 0x4a41>;
dma-names = "tx", "rx1", "rx2";
rng: rng@4e10000 {
compatible = "inside-secure,safexcel-eip76";
reg = <0x00 0x04e10000 0x00 0x7d>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
};
};
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x200>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 146 3>;
clock-names = "fclk";
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x200>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 350 3>;
clock-names = "fclk";
power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x200>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 351 3>;
clock-names = "fclk";
power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x200>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 352 3>;
clock-names = "fclk";
power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x200>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 353 3>;
clock-names = "fclk";
power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x200>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 354 3>;
clock-names = "fclk";
power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x200>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 355 3>;
clock-names = "fclk";
power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x200>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 356 3>;
clock-names = "fclk";
power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x200>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 357 3>;
clock-names = "fclk";
power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x200>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
current-speed = <115200>;
clocks = <&k3_clks 358 3>;
clock-names = "fclk";
power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_gpio0: gpio@600000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00600000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <145>, <146>, <147>, <148>, <149>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 111 0>;
clock-names = "gpio";
};
main_gpio2: gpio@610000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00610000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <154>, <155>, <156>, <157>, <158>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 112 0>;
clock-names = "gpio";
};
main_gpio4: gpio@620000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00620000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <163>, <164>, <165>, <166>, <167>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 113 0>;
clock-names = "gpio";
};
main_gpio6: gpio@630000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00630000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <172>, <173>, <174>, <175>, <176>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <66>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 114 0>;
clock-names = "gpio";
};
main_i2c0: i2c@2000000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02000000 0x00 0x100>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 214 1>;
clock-names = "fck";
power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c1: i2c@2010000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02010000 0x00 0x100>;
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 215 1>;
clock-names = "fck";
power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c2: i2c@2020000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02020000 0x00 0x100>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 216 1>;
clock-names = "fck";
power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c3: i2c@2030000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02030000 0x00 0x100>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 217 1>;
clock-names = "fck";
power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c4: i2c@2040000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02040000 0x00 0x100>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 218 1>;
clock-names = "fck";
power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c5: i2c@2050000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02050000 0x00 0x100>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 219 1>;
clock-names = "fck";
power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_i2c6: i2c@2060000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02060000 0x00 0x100>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 220 1>;
clock-names = "fck";
power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
main_sdhci0: mmc@4f80000 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x00 0x04f80000 0x00 0x1000>,
<0x00 0x04f88000 0x00 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 98 1>;
assigned-clock-parents = <&k3_clks 98 2>;
bus-width = <8>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x6>;
ti,otap-del-sel-hs200 = <0x8>;
ti,otap-del-sel-hs400 = <0x5>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
ti,strobe-sel = <0x77>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
dma-coherent;
};
main_sdhci1: mmc@4fb0000 {
compatible = "ti,j721e-sdhci-4bit";
reg = <0x00 0x04fb0000 0x00 0x1000>,
<0x00 0x04fb8000 0x00 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 99 1>;
assigned-clock-parents = <&k3_clks 99 2>;
bus-width = <4>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0x0>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
ti,itap-del-sel-legacy = <0x0>;
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
/* Masking support for SDR104 capability */
sdhci-caps-mask = <0x00000003 0x00000000>;
};
main_navss: bus@30000000 {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
ti,sci-dev-id = <224>;
dma-coherent;
dma-ranges;
main_navss_intr: interrupt-controller@310e0000 {
compatible = "ti,sci-intr";
reg = <0x00 0x310e0000 0x00 0x4000>;
ti,intr-trigger-type = <4>;
interrupt-controller;
interrupt-parent = <&gic500>;
#interrupt-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <227>;
ti,interrupt-ranges = <0 64 64>,
<64 448 64>,
<128 672 64>;
};
main_udmass_inta: msi-controller@33d00000 {
compatible = "ti,sci-inta";
reg = <0x00 0x33d00000 0x00 0x100000>;
interrupt-controller;
#interrupt-cells = <0>;
interrupt-parent = <&main_navss_intr>;
msi-controller;
ti,sci = <&sms>;
ti,sci-dev-id = <265>;
ti,interrupt-ranges = <0 0 256>;
};
secure_proxy_main: mailbox@32c00000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x32c00000 0x00 0x100000>,
<0x00 0x32400000 0x00 0x100000>,
<0x00 0x32800000 0x00 0x100000>;
interrupt-names = "rx_011";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
};
hwspinlock: spinlock@30e00000 {
compatible = "ti,am654-hwspinlock";
reg = <0x00 0x30e00000 0x00 0x1000>;
#hwlock-cells = <1>;
};
mailbox0_cluster0: mailbox@31f80000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f80000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f81000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f82000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f83000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f84000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f85000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f86000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f87000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f88000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f89000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f8a000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f8b000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster0: mailbox@31f90000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f90000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster1: mailbox@31f91000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f91000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster2: mailbox@31f92000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f92000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster3: mailbox@31f93000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f93000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster4: mailbox@31f94000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f94000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster5: mailbox@31f95000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f95000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster6: mailbox@31f96000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f96000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster7: mailbox@31f97000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f97000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster8: mailbox@31f98000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f98000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster9: mailbox@31f99000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f99000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster10: mailbox@31f9a000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f9a000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
mailbox1_cluster11: mailbox@31f9b000 {
compatible = "ti,am654-mailbox";
reg = <0x00 0x31f9b000 0x00 0x200>;
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&main_navss_intr>;
status = "disabled";
};
main_ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x0 0x3c000000 0x0 0x400000>,
<0x0 0x38000000 0x0 0x400000>,
<0x0 0x31120000 0x0 0x100>,
<0x0 0x33000000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
ti,num-rings = <1024>;
ti,sci-rm-range-gp-rings = <0x1>;
ti,sci = <&sms>;
ti,sci-dev-id = <259>;
msi-parent = <&main_udmass_inta>;
};
main_udmap: dma-controller@31150000 {
compatible = "ti,j721e-navss-main-udmap";
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x80000>,
<0x0 0x35000000 0x0 0x200000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
ti,sci = <&sms>;
ti,sci-dev-id = <263>;
ti,ringacc = <&main_ringacc>;
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
<0x0f>, /* TX_HCHAN */
<0x10>; /* TX_UHCHAN */
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
<0x0b>, /* RX_HCHAN */
<0x0c>; /* RX_UHCHAN */
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
};
cpts@310d0000 {
compatible = "ti,j721e-cpts";
reg = <0x0 0x310d0000 0x0 0x400>;
reg-names = "cpts";
clocks = <&k3_clks 226 5>;
clock-names = "cpts";
interrupts-extended = <&main_navss_intr 391>;
interrupt-names = "cpts";
ti,cpts-periodic-outputs = <6>;
ti,cpts-ext-ts-inputs = <8>;
};
};
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
<0x00 0x02708000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan1: can@2711000 {
compatible = "bosch,m_can";
reg = <0x00 0x02711000 0x00 0x200>,
<0x00 0x02718000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan2: can@2721000 {
compatible = "bosch,m_can";
reg = <0x00 0x02721000 0x00 0x200>,
<0x00 0x02728000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan3: can@2731000 {
compatible = "bosch,m_can";
reg = <0x00 0x02731000 0x00 0x200>,
<0x00 0x02738000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan4: can@2741000 {
compatible = "bosch,m_can";
reg = <0x00 0x02741000 0x00 0x200>,
<0x00 0x02748000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan5: can@2751000 {
compatible = "bosch,m_can";
reg = <0x00 0x02751000 0x00 0x200>,
<0x00 0x02758000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan6: can@2761000 {
compatible = "bosch,m_can";
reg = <0x00 0x02761000 0x00 0x200>,
<0x00 0x02768000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan7: can@2771000 {
compatible = "bosch,m_can";
reg = <0x00 0x02771000 0x00 0x200>,
<0x00 0x02778000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan8: can@2781000 {
compatible = "bosch,m_can";
reg = <0x00 0x02781000 0x00 0x200>,
<0x00 0x02788000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan9: can@2791000 {
compatible = "bosch,m_can";
reg = <0x00 0x02791000 0x00 0x200>,
<0x00 0x02798000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan10: can@27a1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027a1000 0x00 0x200>,
<0x00 0x027a8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan11: can@27b1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027b1000 0x00 0x200>,
<0x00 0x027b8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan12: can@27c1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027c1000 0x00 0x200>,
<0x00 0x027c8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan13: can@27d1000 {
compatible = "bosch,m_can";
reg = <0x00 0x027d1000 0x00 0x200>,
<0x00 0x027d8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan14: can@2681000 {
compatible = "bosch,m_can";
reg = <0x00 0x02681000 0x00 0x200>,
<0x00 0x02688000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan15: can@2691000 {
compatible = "bosch,m_can";
reg = <0x00 0x02691000 0x00 0x200>,
<0x00 0x02698000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan16: can@26a1000 {
compatible = "bosch,m_can";
reg = <0x00 0x026a1000 0x00 0x200>,
<0x00 0x026a8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_mcan17: can@26b1000 {
compatible = "bosch,m_can";
reg = <0x00 0x026b1000 0x00 0x200>,
<0x00 0x026b8000 0x00 0x8000>;
reg-names = "m_can", "message_ram";
power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
clock-names = "hclk", "cclk";
interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
status = "disabled";
};
main_spi0: spi@2100000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02100000 0x00 0x400>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 339 1>;
status = "disabled";
};
main_spi1: spi@2110000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02110000 0x00 0x400>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 340 1>;
status = "disabled";
};
main_spi2: spi@2120000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02120000 0x00 0x400>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 341 1>;
status = "disabled";
};
main_spi3: spi@2130000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02130000 0x00 0x400>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 342 1>;
status = "disabled";
};
main_spi4: spi@2140000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02140000 0x00 0x400>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 343 1>;
status = "disabled";
};
main_spi5: spi@2150000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02150000 0x00 0x400>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 344 1>;
status = "disabled";
};
main_spi6: spi@2160000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02160000 0x00 0x400>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 345 1>;
status = "disabled";
};
main_spi7: spi@2170000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x02170000 0x00 0x400>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 346 1>;
status = "disabled";
};
};
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