| Age | Commit message (Collapse) | Author |
|---|
|
git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
"This consists of start of work for hiding dmaengine internals and
adding new APIs for dmaengine calls. Also couple of drivers and device
and lot of updates esp AI-assisted improvements to drivers.
Core:
- Better document descriptor flags and clarify ordering rules around
cookie completion
- New APIs to start hiding dmaengine guts so that we can start making
them internal
New Support:
- Nord and Maili GPI DMAengine support
- DW axi dma updates and support for UltraRISC DP1000 controller
- Apple M3 generation ADMACs support
- Amlogic A9 SoC DMA controller driver
- Sun6i refactoring and support for Allwinner A733 DMA controller
Updates:
- Freescale device_prep_peripheral_dma_vec support and dynamic
scatter/gather chaining
- TI crossbar and cppi DT schema conversion
- zynqmp driver updates for error patch handling
- Link list handling improvements for DW edma driver
- ST dma40 improvements and corner case handling"
* tag 'dmaengine-7.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (149 commits)
dmaengine: amlogic: Fix regmap error check issue
dmaengine: ste_dma40: Preserve the LCPA I/O address space
docs: dmaengine: clarify ordering rules around cookie completion
dmaengine: move driver-private helpers out of include/linux/dmaengine.h
dmaengine: add dmaengine_desc_set_callback() helper
dmaengine: add dmaengine_get_provider_device() API
dmaengine: add dmaengine_get_max_xor() helper
dmaengine: add dmaengine_get_cap_mask() and dmaengine_has_cap() helpers
dmaengine: add dmaengine_get_copy_align() and related alignment getter helpers
dmaengine: add dmaengine_is_*_aligned() helpers for DMA consumers
dmaengine: add dmaengine_prep_dma_(pq|pq_val|interrupt|xor)() API
dmaengine: sh: rcar-dmac: Add support for R-Car Gen5 SoCs
dt-bindings: renesas,rcar-dmac: Add support for R-Car X5H SoC
dmaengine: sh: rcar-dmac: SMMU doesn't need IPMMU workaround
dmaengine: sh: rcar-dmac: fix style in struct initialization
dmaengine: qcom: bam_dma: free interrupt before the clock in error path
dmaengine: ppc4xx: fix typo "contoller" in comment
dmaengine: ste_dma40: Search all blocks for fixed logical channels
dt-bindings: dma: dma40: Restore disabled-channels
dmaengine: ste_dma40: Validate memcpy configuration
...
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull PCI updates from Bjorn Helgaas:
"Enumeration:
- Set supported_speeds in set_pcie_port_type() so sparc64 and
powerpc, which call it via of_create_pci_dev() instead of the usual
pci_setup_device(), correctly set the supported PCIe link speeds
(Stian Halseth)
- When pcie_set_mps() changes MPS, update the value in the saved
state so a subsequent restore doesn't restore an invalid value
(Niklas Cassel)
- Skip Target Speed quirk on clamped ports with no link (Maciej W.
Rozycki)
Driver binding:
- Assume control of portdrv-related features only when portdrv is
enabled, since we can't use them without portdrv (Kuppuswamy
Sathyanarayanan)
- Centralize feature ownership checking so code only needs to check
'host->native_X' and doesn't need to also check 'pcie_ports_native'
(Kuppuswamy Sathyanarayanan)
Error handling:
- Fix leaks when ACPI APEI/GHES error events overflow the kfifo or
mention a device that no longer exists (Priyank Rathod)
- Fix aer_process_err_devices() leak when a device is recorded as an
error source purely by being mentioned in the Root Port Error
Source and the device is inaccessible or logged only masked errors
(Priyank Rathod)
ASPM:
- Disable ASPM when drivers request that, even if the OS doesn't own
ASPM; otherwise drivers do it on their own, which is worse (Ilpo
Järvinen)
Power management:
- Align hibernate poweroff flow with suspend flow for bridges so they
can be powered down at hibernate as they are for suspend (Mario
Limonciello)
- Restore BARs after powering up during enumeration to fix a
regression on devices that don't preserve state in D3hot (Keng-Yu
Lin)
- Avoid D3 on PLX PEX 8532/8533/8548 downstream ports, where putting
them in D3hot takes down the whole switch (Imre Kaloz)
Power control:
- Add GPIO driver for Toshiba TC9563 embedded GPIO controller (Alex
Elder)
- Add DT documentation and pwrctrl driver support for TC9563 embedded
GPIO controller (Lorenzo Bianconi)
- Switch the tc9563 per-port reset to use the GPIO descriptor API
instead of direct regmap accesses (Lorenzo Bianconi)
- Only destroy devices created by pwrctrl core, so that when removing
a PCIe controller driver that uses pwrctrl, we don't remove devices
populated by another mechanism (Shawn Lin)
- Power off child devices on power-on failure (Lorenzo Bianconi)
PCIe native device hotplug:
- Make the 'pciehp_poll_mode' parameter read-only to prevent changes
via sysfs, which can cause errors when unbinding (Runyu Xiao)
Virtualization:
- Read SR-IOV VF Revision ID and Subsystem ID from VF instead of
assuming they're the same as VF 0; they may differ (Logan Odell)
- Add ACS quirk for Pericom PI7C9X2G304 switches (Hans de Goede)
Peer-to-peer DMA:
- Add Zhaoxin KX-6000, KH-40000, KX-6000G, KX-7000, and KH-50000 host
bridges to allowlist (LeoLiu-oc)
- Add Alibaba T-HEAD Yitian 710 host bridge to allowlist (Feng Tang)
- Add Intel Haswell client host bridge to allowlist (Scott Lee)
- Intel Xeon E3/E5/E7 0x6f00 host bridge to allowlist (kai zhang)
- Fix handling of errors in pci_p2pdma_add_resource() to avoid (a)
unmapping a BAR if registering another fails and (b) use after free
of p2p_pgmap (Leon Romanovsky)
- Wait for RCU readers before freeing state to avoid use-after-free
of pdev->p2pdma (Leon Romanovsky)
- Restrict pci_p2pmem_find_many() to providers backed by a pool (Leon
Romanovsky)
- Safely terminate ACS redirect lists to avoid out-of-bounds access
to the buffer (Leon Romanovsky)
- Silence 'Host bridge not in P2PDMA whitelist' warnings unless
caller, e.g., pci_p2pmem_find_many(), requests 'verbose' (Leon
Romanovsky)
Sysfs:
- Return -ENODEV or -EIO sysfs 'label' or 'acpi_index' attributes
when Device Name _DSM fails, not -1, which is interpreted as -EPERM
(Krzysztof Wilczyński)
- Return valid sysfs 'acpi_index' attribute even if the Device Name
_DSM returned an invalid 'label' (Krzysztof Wilczyński)
- Expose sysfs 'acpi_index' and 'label' based on whether the Device
Name _DSM returns valid data, not merely whether the _DSM is
implemented (Krzysztof Wilczyński)
- Avoid out-of-bounds reads of the label returned by the Device Name
_DSM, which is in UTF-16 characters, not bytes (Krzysztof
Wilczyński)
- Reject unaligned resource I/O port accesses, which can oops on
arm64 (Deepanshu Kartikey)
Endpoint framework:
- Pass the correct physical and virtual endpoint function numbers
when setting translation of inbound memory windows (Koichiro Den)
- Make embedded doorbell IRQ non-shared, since currently only the
first EPF can allocate doorbells (Koichiro Den)
- MSI doorbells currently target the first EPF attached to an EPC;
let other EPFs try the embedded doorbell instead of failing when
they can't use the MSI doorbell (Koichiro Den)
- Serialize scan of vNTB virtual PCI bus with other PCI topology
changes (Koichiro Den)
- Manage vNTB lifetimes to avoid leaking virtual devices and buses
and allow removal (Koichiro Den)
- Track vNTB link state from both sides so both see the same
effective link state (Koichiro Den)
- Configure vNTB MSI-X when supported to avoid IOMMU faults and
failure to deliver doorbell interrupts on RC (Koichiro Den)
APM X-Gene PCIe controller driver:
- Use devm for clocks so they're automatically disabled, unprepared,
and released if errors happen during probe (Yuho Choi)
ASPEED PCIe controller driver:
- Fix clk and PHY leaks in aspeed_pcie_port_init() error paths (Liu
Zhenlong)
Broadcom iProc PCIe controller driver:
- Expose devm_pci_alloc_host_bridge_release() so drivers can share a
devm release function even if they don't need the device tree
parsing done by devm_pci_alloc_host_bridge() (Bjorn Helgaas)
- Request only the memory window from BCMA Enumeration ROM and warn
if it doesn't match the one in DT, which fixes an iproc-bcma probe
failure (Semih Baskan)
Broadcom STB PCIe controller driver:
- Replace bool properties for each SoC configuration with a u32
bitvector and a BFLAG() helper (Jim Quinlan)
- Use a similar BQUIRK() helper to test various SoC quirks (Jim
Quinlan)
Cadence PCIe controller driver:
- Remove device links to PHY, which are redundant because the PHY
core itself adds them (Vladimir Oltean)
- Return error (not success) from cdns_plat_pcie_probe() if
pm_runtime_get_sync() or cdns_pcie_ep_setup() failed (Vladimir
Oltean)
- Correct the driver data pointer usage; previously .probe() stored
'struct cdns_plat_pcie *', but .shutdown() used the pointer as
'struct cdns_pcie *', resulting in accessing garbage (Linmao Li)
ESWIN PCIe controller driver:
- Publish the platform driver MODULE_DEVICE_TABLE so the driver can
be autoloaded when built as a module (Pengpeng Hou)
Freescale i.MX6 PCIe controller driver:
- Fix resource and pwrctrl device leaks .probe() (Zhijian Han)
- Improve i.MX95 Gen3 link stability by changing MPLLB_BANDWIDTH from
default 120 to 140 (Richard Zhu)
- Use dev_err_probe() in host init error path to silence
-EPROBE_DEFER messages (Alexander Stein)
- Avoid dereferencing NULL clock names when 'clocks' includes more
phandles than 'clock-names' has names (Rudi Heitbaum)
- Add suspend_poweroff flag so platforms like i.MX that power off RC
controllers during suspend can enter L2 so endpoints can get
PME_Turn_Off notifications before power loss (Richard Zhu)
Freescale Layerscape PCIe controller driver:
- Enable PROBE_PREFER_ASYNCHRONOUS to reduce probe time of the four
controllers on LX2160A (Vincent Jardin)
Intel VMD host bridge driver:
- Flush DMA writes before handling MSI on Meteor Lake: MSI may arrive
before write has completed, resulting in an nvme 30 second stall
before a QID timeout and possibly other similar problems (Rickey
Bartlett)
- Flush DMA writes before handling MSI on Arrow Lake (Vladimir
Nedoshivin)
Marvell Aardvark PCIe controller driver:
- Disable PHY on probe failures (Myeonghun Pak)
Marvell MVEBU PCIe controller driver:
- Refcount child OF nodes during .probe() to make a concurrent OF
overlay removal safe (Krzysztof Kozlowski)
MediaTek PCIe controller driver:
- Find INTx DT property by 'interrupt-controller' name instead of
assuming it's the first child node (Zhengping Zhang)
MediaTek PCIe Gen3 controller driver:
- Fix a 64-bit type truncation in mtk_pcie_set_trans_table() to avoid
issues with windows above or larger than 4GB (Sreeraj S Kurup)
NVIDIA Tegra264 PCIe controller driver:
- Fix the Link Capabilities offset so we read the correct register
(Bjorn Helgaas)
Qualcomm PCIe controller driver:
- Only collect reset GPIOs from PCI bridge DT nodes to avoid stealing
resets used by downstream devices like USB controllers (Christopher
Obbard)
- Block accesses to downstream devices on link down to reduce a storm
of Completion Timeout AER interrupts (Qiang Yu)
- Skip system suspend/resume for firmware-managed PCIe, where
firmware manages clocks, regulators, resets, etc (Mrinmay Sarkar)
- Honor IOMMU provider's #iommu-cells in qcom_pcie_config_sid_1_9_0()
(Manivannan Sadhasivam)
- Deinitialize endpoint on remove (Guangshuo Li)
- Treat Root Port error recovery as successful even if link doesn't
come up after reset because the device was hot-unplugged (Konrad
Dybcio)
- Skip unnecessary iMSI-RX initialization if DT 'msi-map' is present,
indicating an external MSI controller (Ayiluri Naga Rashmi)
Renesas R-Car PCIe controller driver:
- Limit Max_Read_Request_Size to 256 to avoid hardware erratum (Marek
Vasut)
- Support PERST# via reset subsystem as well as the existing GPIO
support to prepare for R-Car Gen5 SoCs (Marek Vasut)
- Add DT and driver support for the R-Car Gen 5 X5H (R8A78000) PCIe
Gen 4 core (Marek Vasut)
- Add Application/Local register reset DT description and driver
support for both host and endpoint mode (Marek Vasut)
- Add PM ops so controller works after suspend/resume (Marek Vasut)
Renesas RZ/G3S PCIe controller driver:
- Disable refclk on probe failure (Lad Prabhakar)
- Propagate platform_get_irq_byname() errors so probe deferral works
correctly (Lad Prabhakar)
- Tear down INTx handlers if subsequent initialization fails (Lad
Prabhakar)
- Add RZ/G3L (R9A08G046) DT and driver support (Biju Das)
Rockchip PCIe controller driver:
- Limit host and endpoint controllers to 2.5 GT/s since 5.0 GT/s is
unsafe per Rockchip (Geraldo Nascimento)
Synopsys DesignWare PCIe controller driver:
- Set DMA_BYPASS bit in outbound IATU CTRL2 register to avoid data
corruption if the iATU translates DMA engine transactions (Sumit
Kumar)
- Use FIELD_PREP() to remove need for *_SHIFT definitions (Hans
Zhang)
TI DRA7xx PCIe controller driver:
- Remove device links to PHY, which are redundant because the PHY
core itself adds them (Vladimir Oltean)
- Fix optional clock leak when .probe() fails by using
devm_clk_get_optional_enabled() (Felix Gu)
TI Keystone PCIe controller driver:
- Remove device links to PHY, which are redundant because the PHY
core itself adds them (Vladimir Oltean)
UltraRISC PCIe controller driver:
- Allow DWC drivers to skip outbound iATU setup if they don't need
translation between CPU and PCI addresses (Xincheng Zhang)
- Skip MEM outbound iATU setup on DP1000 (Xincheng Zhang)
Xilinx Versal CPM PCIe controller driver:
- Add DT and driver support for optional PERST# for use in warm reset
scenarios (Sai Krishna Musham)
Xilinx XDMA PCIe controller driver:
- Fix device node reference leak in xilinx_pl_dma_pcie_init_irq_domain()
(Wentao Liang)"
* tag 'pci-v7.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (139 commits)
PCI/pwrctrl: Power off child devices on power-on failure
PCI/pwrctrl: Only destroy devices created by pwrctrl core
PCI/pwrctrl: generic: Fix leaking array from of_regulator_bulk_get_all()
PCI/pwrctrl: tc9563: Switch per-port reset to GPIO descriptor API
PCI/pwrctrl: tc9563: Add GPIO auxiliary device support
dt-bindings: PCI: toshiba,tc9563: Document embedded GPIO controller
gpio: tc9563: Add support for the embedded GPIO controller
PCI: qcom: Skip DWC MSI host initialization when DT 'msi-map' is present
PCI: qcom: Ignore -ENODEV after Root Port reset
PCI: qcom-ep: Deinitialize endpoint on remove
PCI/sysfs: Reject unaligned resource I/O port accesses
PCI: rcar-gen4: Add missing PM ops
PCI: endpoint: pci-epf-vntb: Honor MSI-X selection
PCI: endpoint: pci-epf-vntb: Use a local epf pointer in interrupt setup
PCI: dwc: imx6: Use regmap_assign_bits() for conditional set/clear
PCI: dwc: Describe DWC PCIe fields with full masks and FIELD_PREP()
PCI: dwc: Rename pp->irq_domain to pp->msi_irq_domain
PCI: dwc: Rename dw_pcie_allocate_domains() to dw_pcie_allocate_msi_domains()
PCI: dwc: Correct PCIE_DW_PLAT_EP reference in Kconfig help
PCI/ASPM: Disable ASPM when driver requests it
...
|
|
- Fix device node reference leak in xilinx_pl_dma_pcie_init_irq_domain()
(Wentao Liang)
* pci/controller/xilinx-dma-pl:
PCI: xilinx-xdma: Fix device node reference leak in xilinx_pl_dma_pcie_init_irq_domain()
|
|
- Add DT and driver support for optional PERST# for use in warm reset
scenarios (Sai Krishna Musham)
* pci/controller/xilinx-cpm:
PCI: xilinx-cpm: Add support for PCIe RP PERST# signal
dt-bindings: PCI: xilinx-versal-cpm: Add PERST# and reset support
|
|
- Use devm for clocks so they're automatically disabled, unprepared, and
released if errors happen during probe (Yuho Choi)
* pci/controller/xgene:
PCI: xgene: Use managed clock for PCIe controller
|
|
- Flush DMA writes before handling MSI on Meteor Lake: MSI may arrive
before write has completed, resulting in an nvme 30 second stall before a
QID timeout and possibly other similar problems (Rickey Bartlett)
- Flush DMA writes before handling MSI on Arrow Lake (Vladimir Nedoshivin)
* pci/controller/vmd:
PCI: vmd: Flush DMA writes before handling MSI on Arrow Lake
PCI: vmd: Flush DMA writes before handling MSI on Meteor Lake
|
|
- Fix the Link Capabilities offset so we read the correct register (Bjorn
Helgaas)
* pci/controller/tegra264:
PCI: tegra264: Fix Link Capabilities register offset
|
|
- Disable refclk on probe failure (Lad Prabhakar)
- Propagate platform_get_irq_byname() errors so probe deferral works
correctly (Lad Prabhakar)
- Tear down INTx handlers if subsequent initialization fails (Lad
Prabhakar)
- Add RZ/G3L (R9A08G046) DT and driver support (Biju Das)
* pci/controller/rzg3s-host:
PCI: rzg3s-host: Add support for RZ/G3L SoC
dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3L SoC
PCI: rzg3s: Fix IRQ domain initialization error handling
PCI: rzg3s: Propagate platform_get_irq_byname() errors
PCI: rzg3s: Disable refclk on probe failure
|
|
- Fix a 64-bit type truncation in mtk_pcie_set_trans_table() to avoid
issues with windows above or larger than 4GB (Sreeraj S Kurup)
* pci/controller/mediatek-gen3:
PCI: mediatek-gen3: Fix 64-bit type truncation in mtk_pcie_set_trans_table()
|
|
- Find INTx DT property by 'interrupt-controller' name instead of assuming
it's the first child node (Zhengping Zhang)
* pci/controller/mediatek:
PCI: mediatek: Find INTx controller by property
|
|
- Expose devm_pci_alloc_host_bridge_release() so drivers can share a devm
release function even if they don't need the device tree parsing done by
devm_pci_alloc_host_bridge() (Bjorn Helgaas)
- Request only the memory window from BCMA Enumeration ROM and warn if it
doesn't match the one in DT (Semih Baskan)
* pci/controller/iproc-bcma:
PCI: iproc: Use the EROM outbound window on BCMA
PCI: Expose devm_pci_alloc_host_bridge_release()
|
|
- Allow DWC drivers to skip outbound iATU setup if they don't need
translation between CPU and PCI addresses (Xincheng Zhang)
- Skip MEM outbound iATU setup on DP1000 (Xincheng Zhang)
* pci/controller/dwc-ultrarisc:
PCI: ultrarisc: Skip MEM outbound iATU setup on DP1000
PCI: dwc: Allow drivers to skip MEM outbound iATU setup
|
|
- Limit Max_Read_Request_Size to 256 to avoid hardware erratum (Marek
Vasut)
- Add a .post_deinit() callback to handle dw_pcie_ep_init() failures (Marek
Vasut)
- Rework .additional_common_init() into .init() to simplify flow (Marek
Vasut)
- Add .deinit() and .speed_control() callbacks, both to prepare for R-Car
Gen5 SoC support (Marek Vasut)
- Support PERST# via reset subsystem as well as the existing GPIO support
to prepare for R-Car Gen5 SoCs (Marek Vasut)
- Add DT and driver support for the R-Car Gen 5 X5H (R8A78000) PCIe Gen 4
core (Marek Vasut)
- Drop documentation about obtaining R-Car platform firmware, which is
obsolete now that it's available in the linux-firmware.git repository
(Marek Vasut)
- Add Application/Local register reset DT description and driver support
for both host and endpoint mode (Marek Vasut)
- Add PM ops so controller works after suspend/resume (Marek Vasut)
* pci/controller/dwc-rcar-gen4:
PCI: rcar-gen4: Add missing PM ops
PCI: rcar-gen4: Add Application/Local register reset control
dt-bindings: PCI: rcar-gen4-pci-ep: Document Application/Local register reset
dt-bindings: PCI: rcar-gen4-pci-host: Document Application/Local register reset
PCI: rcar-gen4: Drop documentation about obtaining platform firmware
PCI: rcar-gen4: Add support for R-Car X5H PCIe4
PCI: rcar-gen4: Handle PERST# via reset subsystem
PCI: rcar-gen4: Add .speed_control() callback
PCI: rcar-gen4: Add .deinit() callback
PCI: rcar-gen4: Rework .additional_common_init() into .init()
dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car X5H PCIe4 compatible
PCI: rcar-gen4: Use .post_deinit() to handle dw_pcie_ep_init() failures
PCI: dwc: Add dw_pcie_ep_ops->post_deinit() callback
PCI: rcar-gen4: Limit Max_Read_Request_Size to 256 Bytes
# Conflicts:
# drivers/pci/controller/dwc/pcie-rcar-gen4.c
|
|
- Only collect reset GPIOs from PCI bridge DT nodes to avoid stealing
resets used by downstream devices like USB controllers (Christopher
Obbard)
- Block accesses to downstream devices on link down to reduce a storm of
Completion Timeout AER interrupts (Qiang Yu)
- Skip system suspend/resume for firmware-managed PCIe, where firmware
manages clocks, regulators, resets, etc (Mrinmay Sarkar)
- Honor IOMMU provider's #iommu-cells in qcom_pcie_config_sid_1_9_0()
(Manivannan Sadhasivam)
- Deinitialize endpoint on remove (Guangshuo Li)
- Treat Root Port error recovery as successful even if link doesn't come up
after reset because the device was hot-unplugged (Konrad Dybcio)
- Skip unnecessary iMSI-RX initialization if DT 'msi-map' is present,
indicating an external MSI controller (Ayiluri Naga Rashmi)
* pci/controller/dwc-qcom:
PCI: qcom: Skip DWC MSI host initialization when DT 'msi-map' is present
PCI: qcom: Ignore -ENODEV after Root Port reset
PCI: qcom-ep: Deinitialize endpoint on remove
PCI: qcom: Honor IOMMU provider's #iommu-cells in qcom_pcie_config_sid_1_9_0()
PCI: qcom: Skip system suspend/resume for firmware-managed PCIe
PCI: qcom: Block accesses to downstream devices on link down
PCI: qcom: Only check bridge nodes for PERST# GPIOs
|
|
- Enable PROBE_PREFER_ASYNCHRONOUS to reduce probe time of the four
controllers on LX2160A (Vincent Jardin)
* pci/controller/dwc-layerscape:
PCI: layerscape: Enable async probe by default
|
|
- Remove device links to PHY, which are redundant because the PHY core
itself adds them (Vladimir Oltean)
* pci/controller/dwc-keystone:
PCI: keystone: Remove device links to PHY
|
|
- Fix pwrctrl device leak when .probe() PM runtime setup fails (Zhijian
Han)
- Fix resource leaks in .probe() error paths (Zhijian Han)
- Improve i.MX95 Gen3 link stability by changing MPLLB_BANDWIDTH from
default 120 to 140 (Richard Zhu)
- Use dev_err_probe() in host init error path to silence -EPROBE_DEFER
messages (Alexander Stein)
- Avoid dereferencing NULL clock names when 'clocks' includes more phandles
than 'clock-names' has names (Rudi Heitbaum)
- Add suspend_poweroff flag so platforms like i.MX that power off RC
controllers during suspend can enter L2 so endpoints can get PME_Turn_Off
notifications before power loss (Richard Zhu)
- Use regmap_assign_bits() to simplify conditional set/clear blocks (Peng
Fan)
* pci/controller/dwc-imx6:
PCI: dwc: imx6: Use regmap_assign_bits() for conditional set/clear
PCI: dwc: Add suspend_poweroff flag for platforms with RC power loss
PCI: imx6: Avoid dereferencing a NULL clock name
PCI: imx6: Use dev_err_probe() in error path of pci_pwrctrl_power_on_devices()
PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability
PCI: imx6: Fix resource leaks in probe error paths
PCI: imx6: Fix pwrctrl device leak on PM runtime setup failure
|
|
- Publish the platform driver MODULE_DEVICE_TABLE so the driver can be
autoloaded when built as a module (Pengpeng Hou)
* pci/controller/dwc-eswin:
PCI: eswin: Publish the platform driver OF alias
|
|
- Remove device links to PHY, which are redundant because the PHY core
itself adds them (Vladimir Oltean)
- Fix optional clock leak when .probe() fails by using
devm_clk_get_optional_enabled() (Felix Gu)
* pci/controller/dwc-dra7xx:
PCI: dra7xx: Fix clock enable leak on probe failure
PCI: dra7xx: Remove device links to PHY
|
|
- Align register macros with Synopsys documentation (Hans Zhang)
- Remove unused PCIE_ATU_UNR_* register definitions; the driver now uses
ATU_* macros instead (Hans Zhang)
- Set DMA_BYPASS bit in outbound IATU CTRL2 register to avoid data
corruption if the iATU translates DMA engine transactions (Sumit Kumar)
- Correct Kconfig help text reference to PCIE_DW_PLAT_EP (Philippe
Lecointre)
- Rename dw_pcie_allocate_domains() to dw_pcie_allocate_msi_domains() for
clarity (Shawn Lin)
- Rename pp->irq_domain to pp->msi_irq_domain for clarity (Shawn Lin)
- Use FIELD_PREP() to remove need for *_SHIFT definitions (Hans Zhang)
* pci/controller/dwc:
PCI: dwc: Describe DWC PCIe fields with full masks and FIELD_PREP()
PCI: dwc: Rename pp->irq_domain to pp->msi_irq_domain
PCI: dwc: Rename dw_pcie_allocate_domains() to dw_pcie_allocate_msi_domains()
PCI: dwc: Correct PCIE_DW_PLAT_EP reference in Kconfig help
PCI: dwc: Set DMA_BYPASS bit in outbound IATU CTRL2 register
PCI: dwc: Remove unused PCIE_ATU_UNR_* register definitions
PCI: dwc: Align register macros with Synopsys documentation
|
|
- Limit host and endpoint controllers to 2.5 GT/s since 5.0 GT/s is unsafe
per Rockchip (Geraldo Nascimento)
* pci/controller/rockchip:
PCI: rockchip: Drive at 2.5 GT/s, error other speeds
PCI: rockchip-host: Do not attempt 5.0 GT/s retraining
PCI: rockchip-ep: Do not attempt 5.0 GT/s retraining
|
|
- Use for_each_available_child_of_node_scoped() to simplify probe loop over
children (Krzysztof Kozlowski)
- Refcount child OF nodes during .probe() to make a concurrent OF overlay
removal safe (Krzysztof Kozlowski)
* pci/controller/mvebu:
PCI: mvebu: Keep child node refcnt for probe duration
PCI: mvebu: Simplify with scoped for each OF child loop
|
|
- Fix enum type mismatch warning in LTSSM debugfs (Hans Zhang)
- Remove device links to PHY, which are redundant because the PHY core
itself adds them (Vladimir Oltean)
- Return error (not success) from cdns_plat_pcie_probe() if
pm_runtime_get_sync() or cdns_pcie_ep_setup() failed (Vladimir Oltean)
- Correct the driver data pointer usage; previously .probe() stored
'struct cdns_plat_pcie *', but .shutdown() used the pointer as
'struct cdns_pcie *', resulting in accessing garbage (Linmao Li)
* pci/controller/cadence:
PCI: cadence: Store the core controller in platform drvdata
PCI: cadence: Preserve all error codes in cdns_plat_pcie_probe()
PCI: cadence: Remove device links to PHY
PCI: cadence: Fix enum type mismatch warning in LTSSM debugfs
|
|
- Remove unnecessary 'const' specifier from struct pcie_cfg_data members
(Jim Quinlan)
- Replace bool properties for each SoC configuration with a u32 bitvector
and a BFLAG() helper (Jim Quinlan)
- Use a similar BQUIRK() helper to test various SoC quirks (Jim Quinlan)
* pci/controller/brcmstb:
PCI: brcmstb: Declare and assign quirk PERST_PCIE_REV_CUTOFF
PCI: brcmstb: Declare and assign quirk EARLY_PERST_ASSERT
PCI: brcmstb: Declare and assign quirk NO_RGR1_TIMER
PCI: brcmstb: Declare and assign quirk 32BIT_PCI_OPS
PCI: brcmstb: Declare and assign flag IS_BMIPS
PCI: brcmstb: Declare and assign quirk OB_WIN_MAXSZ_128MB
PCI: brcmstb: Declare and assign quirk OB_WIN_32BIT_ADDR
PCI: brcmstb: Add Broadcom quirks macro
PCI: brcmstb: Use flags u32 instead of bools
PCI: brcmstb: Remove redundant const specifier for struct fields
|
|
- Fix clk and PHY leaks in aspeed_pcie_port_init() error paths (Liu
Zhenlong)
* pci/controller/aspeed:
PCI: aspeed: Fix clk and PHY leak in aspeed_pcie_port_init() error paths
|
|
- Disable PHY on probe failures (Myeonghun Pak)
* pci/controller/aardvark:
PCI: aardvark: Disable PHY on probe failures
|
|
qcom_pcie_ecam_host_init() unconditionally initializes the DesignWare
internal MSI controller and sets use_imsi_rx, irrespective of whether an
external MSI controller is described for the host bridge. When an 'msi-map'
DT property is present, MSI interrupts are handled by the mapped external
MSI controller. Initializing the internal iMSI-RX domain in this case is
unnecessary.
Set use_imsi_rx based on the presence of 'msi-map' in DT and initialize the
DesignWare MSI host only when iMSI-RX is required.
Signed-off-by: Ayiluri Naga Rashmi <ayiluri.rashmi@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260917-skipmsi_forlpi-v1-1-14a4932a4311@oss.qualcomm.com
|
|
Root Port recovery may race with a device hot-unplug. In that case,
dw_pcie_wait_for_link() returns -ENODEV because no device is detected
after the controller has been successfully reset.
This is a valid outcome and should not cause Root Port recovery to
fail. Ignore -ENODEV while continuing to propagate other link-training
errors.
Fixes: 4d88cb82a6d9 ("PCI: qcom: Implement .reset_root_port() and use for link down")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Link: https://patch.msgid.link/20260916-topic-pcie_portrec_enodev-v1-1-5dc7bde39552@oss.qualcomm.com
Assisted-by: LLM
|
|
qcom_pcie_ep_probe() initializes the DesignWare PCIe endpoint with
dw_pcie_ep_init(). The probe failure paths call dw_pcie_ep_deinit() to
release the corresponding endpoint resources, but the remove path does
not perform the matching teardown after a successful probe.
As a result, resources initialized by the DesignWare endpoint core can
remain allocated when the endpoint controller is removed.
Notify endpoint functions about EPC deinitialization and call
dw_pcie_ep_deinit() before disabling the controller resources. Keep the
existing early return when the link is already disabled since Qualcomm
endpoint controllers depend on the host refclk for hardware cleanup.
This issue was found by manual code inspection.
Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver")
Signed-off-by: Guangshuo Li <lgs201920130244@gmail.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260916090126.2963064-1-lgs201920130244@gmail.com
|
|
'hyper-v', 'samsung/exynos', 'riscv', 'broadcom', 'intel/vt-d', 'amd/amd-vi' and 'core' into next
|
|
The R-Car Gen4 PCIe controller is part of a power domain. On R-Car S4
and V4H, this is an always-on power domain which is not shut down in
suspend. On R-Car V4M, this is a dedicated A2PCIPHY power domain,
which is shut down during suspend, and the controller loses state,
which prevents the PCIe from working after resume.
Fix this by adding generic suspend/resume noirq ops for the controller,
which tear the link down on suspend, and restart it on resume. Use the
same PM ops on all of R-Car Gen4 to gracefully suspend and resume the
PCIe link on V4H and S4 too.
Test case which demonstrates the problem on R-Car V4M:
$ hexdump -vC /sys/bus/pci/devices/0000:00:00.0/config > /tmp/pre
$ echo s2idle > /sys/power/mem_sleep
$ echo platform > /sys/power/pm_test
$ echo mem > /sys/power/state
$ hexdump -vC /sys/bus/pci/devices/0000:00:00.0/config > /tmp/post
$ diff -Naru /tmp/pre /tmp/post
...
-00000000 12 19 32 00 07 05 10 00 00 00 04 06 00 00 01 00
+00000000 12 19 32 00 07 05 10 00 00 00 00 ff 00 00 80 00
^^^^^
Class 0604->00ff
Fixes: 0270dbe4f891 ("arm64: dts: renesas: r8a779h0: Add PCIe Host and Endpoint nodes")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Koichiro Den <den@valinux.co.jp>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20261004011851.866833-1-marek.vasut+renesas@mailbox.org
|
|
Replace multiple if/else blocks using regmap_set_bits()/regmap_clear_bits()
with the simpler regmap_assign_bits() calls.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
Link: https://patch.msgid.link/20260924083429.461746-1-peng.fan@oss.nxp.com
|
|
Several DWC PCIe register fields are described with a shift macro next
to their mask, or with only a shift and the field width implied by the
value written. Document the field position and width in a single full
mask and use FIELD_PREP() to encode it.
No functional change intended.
Signed-off-by: Hans Zhang <18255117159@163.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/20260930013842.82476-1-18255117159@163.com
|
|
pp->irq_domain is exclusively the MSI parent irq domain: it is created
by dw_pcie_allocate_msi_domains() with msi_create_parent_irq_domain()
and is only used to resolve the MSI child virqs in dw_handle_msi_irq()
and in the keystone and dra7xx MSI handlers. The name gives no hint
about that, in the same way dw_pcie_allocate_domains() did not say that
it was only about MSI.
Rename it to pp->msi_irq_domain, matching the previous rename.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://patch.msgid.link/1790734930-217000-3-git-send-email-shawn.lin@rock-chips.com
|
|
Rename dw_pcie_allocate_domains() to dw_pcie_allocate_msi_domains() so that
the name says what it allocates and cannot be mistaken for a generic domain
allocator.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/1790734930-217000-2-git-send-email-shawn.lin@rock-chips.com
|
|
The Kconfig help text for PCIE_DW_PLAT_HOST and PCIE_DW_PLAT_EP
incorrectly refers to PCI_DW_PLAT_EP.
Replace the typo with the correct symbol name, PCIE_DW_PLAT_EP, so the
help text matches the actual Kconfig option.
Signed-off-by: Philippe Lecointre <philippe.lecointre@thalesgroup.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/305ef70ecadb4db9aa42c66607240aba@thalesgroup.com
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux
Pull Hyper-V fixes from Wei Liu:
- Typo and comment fixes (Hemanth Selam, Jiangshan Yi)
- Update maintainers list (Wei Liu, Long Li)
- Two Hyper-V PCI driver fixes (Naman Jain, Sahil Chandna)
- Small fixes for core Hyper-V code (Hardik Garg, Michael Kelley,
Waiman Long)
* tag 'hyperv-fixes-signed-20261015' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux:
MAINTAINERS: drop KY from Hyper-V maintainers list
PCI: hv: Warn when wait_for_response() waits indefinitely
PCI: hv: Probe vPCI buses asynchronously
MAINTAINERS: remove myself from the Hyper-V entries
mshv_vtl: Check per-CPU register page before mmap
tools/hv: fix typo "retrive" in comment
Drivers: hv: vmbus: fix typo "substract" in comment
Drivers: hv: Don't reset VMBus connection state on error/exit paths
x86/hyperv: Avoid using per-cpu output page in hv_apicid_to_vp_index()
x86/hyperv: Fix stale comments after stimer message mode removal
Drivers: hv: Avoid infinite retry loop in init_vp_index()
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull PCI fixes from Bjorn Helgaas:
- Leave ANFE masked on Apple T2 Secure Enclave, which fixes spontaneous
poweroff regressions on MacBookPro16,1 and likely other models with
the T2 caused by new Advisory Non-Fatal Error support (Jason Perlow)
- Move dw-rockchip INTx IRQ setup from rockchip_pcie_host_init(), where
it runs after every reset, to the rockchip_pcie_probe() path to avoid
installing new IRQ handler (which causes INTx IRQs to be lost) and
leaking an IRQ domain on every reset; fixes a regression added this
cycle (Shawn Lin)
* tag 'pci-v7.3-fixes-5' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
PCI: dw-rockchip: Move INTx IRQ setup to probe
PCI/AER: Keep ANFE masked on Apple T2 Secure Enclave
|
|
xilinx_pl_dma_pcie_init_irq_domain()
xilinx_pl_dma_pcie_init_irq_domain() takes a reference to the PCIe
interrupt-controller child node with of_get_child_by_name(), but the
error paths after the two irq_domain_create_linear() calls and after
xilinx_pl_dma_pcie_init_msi_irq_domain() return directly without
dropping it. irq_domain_create_linear() gets its own reference on the
fwnode, so the domains do not consume the caller's one.
Add an err_put_node label that drops the reference before returning.
Fixes: 8d786149d78c ("PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver")
Signed-off-by: Wentao Liang <vulab@iscas.ac.cn>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260917132459.2153240-1-vulab@iscas.ac.cn
|
|
The PCIe outbound window base on Northstar depends on the PCIe Gen2 core
revision. Revision 0x01 uses 0x08000000, 0x40000000 and 0x48000000 for
controllers 0 to 2, while revision 0x07 (NS-B0) uses 0x08000000,
0x20000000 and 0x28000000. Broadcom's own driver branches on the core
revision for exactly this reason.
bcm-ns.dtsi is shared by every Northstar SoC, so it cannot carry a value
that is correct on both. Commit 767012397976 ("ARM: dts: BCM5301X:
Describe PCIe controllers fully") gave the controllers a ranges property.
The commit shipped in v7.1.
With that property present, two things go wrong with this driver:
1) devm_pci_alloc_host_bridge() parses those ranges and requests them,
then this driver adds its own window and requests the whole list a
second time, so every controller fails to probe with -EBUSY.
2) The DT window itself is only correct on core revision 0x07. On
revision 0x01 it points at an address the hardware does not decode,
and the first MMIO access to a BAR takes an imprecise external abort.
The enumeration ROM reports the correct base for the revision actually
present, and bcma already provides it as addr_s[0].
To solve 1), use pci_alloc_host_bridge() directly to avoid the request of
all the DT resources done in pci_parse_request_of_pci_ranges(). Instead,
request the memory window from the EROM.
To solve 2), parse the memory resources from DT and emit a warning if it
describes a window that doesn't match the window from the EROM. The
mismatch means the devicetree describes a window the hardware does not
decode, and that should be fixed in the dts rather than ignored silently.
The driver is correct whether or not the DT describes a window.
The same commit also added compatible = "brcm,iproc-pcie", so these
nodes now match pcie-iproc-platform. With CONFIG_PCIE_IPROC_PLATFORM
enabled, which is the default on ARCH_BCM_IPROC, that driver binds them
first and this driver's probe fails inside devm_pci_alloc_host_bridge().
This commit fixes the configurations where the BCMA driver is the one in
use; OpenWrt builds that way, with PCIE_IPROC_PLATFORM disabled. The
platform path takes the DT window as-is and has the same wrong address
on core revision 0x01, so that side needs a devicetree fix either way.
Based on:
https://patch.msgid.link/20260807160526.379-1-strst.gs@gmail.com
https://patch.msgid.link/20260912043626.437-1-strst.gs@gmail.com
Fixes: 767012397976 ("ARM: dts: BCM5301X: Describe PCIe controllers fully")
Signed-off-by: Semih Baskan <strst.gs@gmail.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Semih Baskan <strst.gs@gmail.com>
Link: https://patch.msgid.link/20261013220421.1588051-3-bhelgaas@google.com
|
|
dw_pcie_wait_for_link() polls for up to PCIE_LINK_WAIT_MAX_RETRIES *
PCIE_LINK_WAIT_SLEEP_MS (10 * 90 ms) per controller.
The controllers are probed one after the other, so, it leads to slow
boot time.
On an LX2160A board with 4 enabled controllers and no link on any of them,
dw_pcie_host_init() took almost 4s. Probing the 4 controllers in parallel
allows to have it down to 1s.
So enable async probe by default.
Signed-off-by: Vincent Jardin <vjardin@free.fr>
[mani: commit log]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260928-for-upstream-pci-layerscape-async-probe-v1-1-76412d887baa@free.fr
|
|
Some platforms like i.MX power off their PCIe RC controllers during
system suspend, requiring full re-initialization on resume. These
platforms need to enter L2 state to properly notify endpoints before
power loss.
According to PCIe r7.0, sec 5.2, system software should transition the
device into D3hot before broadcasting the PME_Turn_Off message to initiate
L2 entry. In practice, endpoint drivers properly put their devices into
D3hot during the suspend flow. However, some wakeup-capable endpoint
devices that don't support PME from D3cold fail the D3cold capability check
in pci_host_common_d3cold_possible(), which currently prevents L2 entry
even though the devices are already in the required D3hot state.
For platforms where the RC loses power during suspend, L2 entry is
essential regardless of D3cold support, as the link will be lost anyway
when the RC powers off. Without L2 entry, endpoints are not properly
notified before power loss, which can cause issues during resume and
reinitialization.
Add a suspend_poweroff flag to allow L2 entry for devices that are in
D3hot but fail the D3cold capability check, and enable it for i.MX PCIe
controllers that lose power during suspend.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[mani: removed redundant comment]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260917063322.4102035-1-hongxing.zhu@oss.nxp.com
|
|
An outbound iATU region matches any local (AXI/application-side)
address that falls within its Base/Limit window and rewrites it to
the PCIe-side address programmed in that region's Target Address
Registers before the transaction goes out on the link. This matching
does not distinguish CPU-initiated transactions from ones issued by
the internal DMA engine (eDMA/HDMA).
Example: outbound region 0 is programmed with Base/Limit covering
local addresses 0x8000_0000-0x8000_0FFF and Target 0x1_0000_0000, for
CPU-initiated accesses. The DMA engine is later given a descriptor
whose destination is the host address 0x8000_0080, which happens to
fall inside region 0's Base/Limit range. The iATU matches the DMA
transaction against region 0 too and rewrites it to 0x1_0000_0080
instead of passing 0x8000_0080 through unchanged. The transaction
then lands on the wrong host address, causing data corruption or an
IOMMU fault when the rewritten address has no valid mapping.
Set the DMA_BYPASS bit (bit 27) in PCIE_ATU_REGION_CTRL2 when
programming outbound iATU regions so only CPU/AXI-initiated
transactions are matched against the region; DMA engine transactions
bypass the translation and go out on the PCIe link with their
original address.
Signed-off-by: Sumit Kumar <sumit.kumar@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260908-dma_bypass-v2-1-c3c81d408c0c@oss.qualcomm.com
|
|
cdns_plat_pcie_probe() stores a struct cdns_plat_pcie pointer with
platform_set_drvdata(). cdns_plat_pcie_shutdown() and the callbacks in
cdns_pcie_pm_ops retrieve the same pointer with dev_get_drvdata() but use
it as a struct cdns_pcie pointer. This makes them read phy_count and phy
beyond the wrapper.
struct cdns_plat_pcie only contains a pointer to struct cdns_pcie. Drop
the redundant wrapper and store the struct cdns_pcie pointer directly.
Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library")
Signed-off-by: Linmao Li <lilinmao@kylinos.cn>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Aksh Garg <a-garg7@ti.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260915082826.4135665-1-lilinmao@kylinos.cn
|
|
The SW behavior for asserting PERST# for some SoCs only works up to a
specific PCIe HW version. Declare this as a quirk and assign it
accordingly.
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/20260911233541.1650895-11-james.quinlan@broadcom.com
|
|
Declare and assign a quirk where PERST# must be asserted prior to an
internal bus being turned on.
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/20260911233541.1650895-10-james.quinlan@broadcom.com
|
|
Very few SoCs do not have an internal bus timer whose timeout value may be
adusted for L1SS operation. Declare this as a quirk and assign it
accordingly.
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/20260911233541.1650895-9-james.quinlan@broadcom.com
|
|
Declare a new quirk that indicates SoCs where the config-space accesses are
restricted to 32bit R/W.
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/20260911233541.1650895-8-james.quinlan@broadcom.com
|
|
Eliminate is_bmips(), which evaluates SoC chip IDs, and instead declare and
use CFG_FLG_IS_BMIPS, a flag that indicates the SoC employs a CPU with a
variant of the MIPS-1 ISA.
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/20260911233541.1650895-7-james.quinlan@broadcom.com
|
|
Even though only BMIPs chips have this quirk, it is more uniform and
readable to define this specific quirk where each outbound window is must
be <= SZ_128M.
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/20260911233541.1650895-6-james.quinlan@broadcom.com
|
