summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)Author
2016-02-17drm/i915: Fix hpd live status bits for g4xVille Syrjälä
2016-02-10drm/i915/skl: Fix typo in DPLL_CFGCR1 definitionLyude
2015-12-23Merge tag 'drm-intel-next-2015-12-18' of git://anongit.freedesktop.org/drm-in...Dave Airlie
2015-12-15drm/doc: Convert to markdownDanilo Cesar Lemes de Paula
2015-12-11drm/i915: dual link pipe selection for bxtDeepak M
2015-12-08drm/i915: Disable CLKOUT_DP bending on LPT/WPT as neededVille Syrjälä
2015-12-04drm/i915: Correct the Ref clock value for BXTDeepak M
2015-12-02drm/i915: Don't register the CRT connector when it's fused off on LPT-HVille Syrjälä
2015-12-02drm/i915/bxt: backlight clock gating workaroundImre Deak
2015-11-18drm/i915: Type safe register read/writeVille Syrjälä
2015-11-18drm/i915: Add missing ')' to SKL_PS_ECC_STAT defineVille Syrjälä
2015-11-18drm/i915: Give names to more ring registersVille Syrjälä
2015-11-18drm/i915: Make the cmd parser 64bit regs explicitVille Syrjälä
2015-11-18drm/i915: Make the high dword offset more explicit in i915_reg_read_ioctlVille Syrjälä
2015-11-18drm/i915: Parametrize MOCS registersVille Syrjälä
2015-11-18drm/i915: Parametrize L3 error registersVille Syrjälä
2015-11-18drm/i915: Prefix raw register defines with underscoreVille Syrjälä
2015-11-17drm/i915/gen9: Turn DC handling into a power wellPatrik Jakobsson
2015-11-17drm/i915: Explain usage of power well IDs vs bit groupsPatrik Jakobsson
2015-11-17drm/i915/gen9: simplify DC toggling codeImre Deak
2015-11-17drm/i915: fix the power well ID for always on wellsImre Deak
2015-11-16drm/i915: Add dev_priv->psr_mmio_baseVille Syrjälä
2015-11-16drm/i915: Remove the magic AUX_CTL is at DP + foo tricksVille Syrjälä
2015-11-16drm/i915: Parametrize AUX registersVille Syrjälä
2015-11-10drm/i915: s/DP_PLL_FREQ_160MHZ/DP_PLL_FREQ_162MHZ/Ville Syrjälä
2015-11-09drm/i915: Add csr programming registers to dmc debugfs entryMika Kuoppala
2015-11-09drm/i915/bxt: Expose DC5 entry countMika Kuoppala
2015-11-09drm/i915/skl: Expose DC5/DC6 entry countsDamien Lespiau
2015-11-05drm/i915/skl: While sanitizing cdclock check the SWF18 as wellShobhit Kumar
2015-10-26drm/i915: Use paramtrized WRPLL_CTL()Ville Syrjälä
2015-10-13drm/i915: Parametrize and fix SWF registersVille Syrjälä
2015-10-13drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.Ville Syrjälä
2015-10-13drm/i915: Fix a few bad hex numbers in register definesVille Syrjälä
2015-10-13drm/i915: Protect register macro argumentsVille Syrjälä
2015-10-13drm/i915: Include gpio_mmio_base in GMBUS reg definesVille Syrjälä
2015-10-13drm/i915: Parametrize HSW video DIP data registersVille Syrjälä
2015-10-13drm/i915: Eliminate weird parameter inversion from BXT PPS registersVille Syrjälä
2015-10-07drm/i915/bxt: Set time interval unit to 0.833usAkash Goel
2015-10-06drm/i915: Add GEN7_GPGPU_DISPATCHDIMX/Y/Z to the register whitelistJordan Justen
2015-10-02drm/i915/bxt: Modify BXT BLC according to VBT changesSunil Kamath
2015-10-02drm/i915/bxt: Program Tx Rx and Dphy clocksShashank Sharma
2015-10-02drm/i915/bxt: DSI enable for BXTShashank Sharma
2015-10-02drm/i915: rename INSTDONE1 to GEN4_INSTDONE1Imre Deak
2015-10-02drm/i915: rename INSTDONE to GEN2_INSTDONEImre Deak
2015-10-02drm/i915: remove duplicate names for the render ring INSTDONE registerImre Deak
2015-10-01drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.Ville Syrjälä
2015-09-30drm/i915/bdw: Check for slice, subslice and EU count for BDWŁukasz Daniluk
2015-09-30drm/i915: Read czclk from CCK on vlv/chvVille Syrjälä
2015-09-30drm/i915: Renaming CCK related reg definitionsVandana Kannan
2015-09-30drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASEVille Syrjälä