summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/display
AgeCommit message (Collapse)Author
6 daysMerge tag 'drm-next-2026-06-17' of https://gitlab.freedesktop.org/drm/kernelLinus Torvalds
Pull drm updates from Dave Airlie: "Highlights: - xe: add initial CRI platform support - amdgpu: initial HDMI 2.1 FRL support - rust: add some new type concepts for device lifetimes - scheduler: moves to a fair algorithm and lots of cleanups But it's mostly the usual mountain of changes across the board. core: - add docbook for DRM_IOCTL_SYNCOBJ_EVENTFD - change signature of drm_connector_attach_hdr_output_metadata_property - dedup counter and timestamp retrieval in vblank code - parse AMD VSDB v3 in CTA extension blocks - add P230, Y7, XYYY2101010, T430, XVUY210101010 formats - don't call drop master on file close if not master - use drm_printf_indent in atomic / bridge - fix 32b format descriptions - docs: fix toctree - hdmi: add common TMDS character rates - fix drm_syncobj_find_fence leak rust: - introduce Higher-Ranked lifetime types - replace drvdata with scoped registration data - add GPUVM immediate mode abstraction for rust GPU drivers - introduce DeviceContext type state for drm::Device bridge: - clarify drm_bridge_get/put - create drm_get_bridge_by_endpoint and use it - analogix_dp: add panel probing - ite-it6211 - use drm audio hdmi helpers buddy: - add lockdep annotations dp: - add PR and VRR updates - mst: fix buffer overflows - add Adaptive Sync SDP decoding support - fix OOB reads in dp-mst ttm: - bump fpfn/lpfn to 64-bit scheduler: - change default to fair scheduler - map runqueue 1:1 with scheduler dma-buf: - port selftests to kunit - convert dma-buf system/heap allocators to module - add separate DMABUF_HEAPS_SYSTEM_CC_SHARED Kconfig udmabuf: - revert hugetlb support - fix error with CONFIG_DMA_API_DEBUG dma-fence: - fix tracepoints lifetime - remove unused signal on any support ras: - add clear error counter netlink command to drm ras gpusvm: - reject VMAs with VM_IO or VM_PFNMAP when creating SVM ranges - use IOVA allocations pagemap: - use IOVA allocations panels: - update to use ref counts - add support for CSW PNB601LS1-2, LGD LP116WHA-SPB1 - add support for waveshare panels - CMN N116BCN-EA1, CMN N140HCA-EEK, IVO M140NWFQ R5, - IVO, R140NWFW R0, BOE NT140*, BOE NV133FHM-N4F, - AUO B140*, AUO B133HAN06.6 and AUO B116XTN02.3 eDP panels - Surface Pro 12 Panel xe: - add CRI PCI-IDs - debugfs add multi-lrc info - engine init cleanup - PF fair scheduling auto provisioning - system controller support for CRI/Xe3p - PXP state machine fixes - Reset/wedge/unload corner case fixes - Wedge path memory allocation fixes - PAT type cleanups - Reject unsafe PAT for CPU cached memory - OA improvements for CRI device memory - kernel doc syntax in xe headers - xe_drm.h documentation fixes - include guard cleanups - VF CCS memory pool - i915/xe step unification - Xe3p GT tuning fixes - forcewake cleanup in GT and GuC - admin-only PF mode - enable hwmon energy attributes for CRI - enable GT_MI_USER_INTERRUPT - refactor emit functions - oa workarounds - multi_queue: allow QUEUE_TIMESTAMP register - convert stolen memory to ttm range manager - use xe2 style blitter as a feature flag - make drm_driver const - add/use IRQ page to HW engine definition - fix oops when display disabled i915: - enable PIPEDMC_ERROR interrupt - more common display code refactoring - restructure DP/HDMI sink format handling - eliminate FB usage from lowlevel pinning code - panel replay bw optimization - integrate sharpness filter into the scaler - new fb_pin abstraction for xe/i915 fb transparent handling - skip inactive MST connectors on HDCP - start switching to display specific registers - use polling when irq unavailable - Adaptive-sync SDP prep amdgpu: - use drm_display_info for AMD VSDB data - Initial HDMI 2.1 FRL support - Initial DCN 4.2.1 support - GART fixes for non-4k pages - GC 11.5.6/SDMA 6.4.0/and other new IPs - GFX9/DCE6/Hawaii/SDMA4/GART/Userq fixes - Finish support for using multiple SDMA queues for TTM operations - SWSMU updates - GC 12.1 updates - SMU 15.0.8 updates - DCN 4.2 updates - DC type conversion fixes - Enable DC power module - Replay/PSR updates - SMU 13.x updates - Compute queue quantum MQD updates - ASPM fix - Align VKMS with common implementation - DC analog support fixes - UVD 3 fixes - TCC harvesting fixes for SI - GC 11 APU module reload fix - NBIO 6.3.2 support - IH 7.1 updates - DC cursor fixes - VCN/JPEG user fence fixes - DC support for connectors without DDC - Prefer ROM BAR for default VGA device - DC bandwidth fixes - Add PTL support for profiler - Introduce dc_plane_cm and migrate surface update color path - Add FRL registers for HDMI 2.1 - Restructure VM state machine - Auxless ALPM support - GEM_OP locking/warning fixes - switch to system_dfl_wq amdkfd: - GPUVM TLB flush fix - Hotplug fix - Boundary check fixes - SVM fixes - CRIU fixes - add profiler API - MES 12.1 updates msm: - core: - fix shrinker documentation - IFPC enabled for gen8 - PERFCNTR_CONFIG ioctl support - GPU: - reworked UBWC handling - a810 support - MDSS: - add support for Milos platform - reworked UBWC handling - DisplayPort: - reworked HPD handling as prep for MST - DPU: - Milos platform support - reworked UBWC handling - DSI: - Milos platform support nova: - Hopper/Blackwell enablement (GH100/GB100/GB202) - FSP support - 32-bit firmware support - HAL functions - refactor GSP boot/unload - GA100 support - VBIOS hardening/refactoring - Adopt higher order lifetime types tyr: - define register blocks - add shmem backed GEM objects - adopt higher order lifetime types - move clock cleanup into Drop radeon: - Hawaii SMU fixes - CS parser fix - use struct drm_edid instead of edid amdxdna: - export per-client BO memory via fdinfo - AIE4 device support - support medium/lower power modes - expandable device heap support - revert read-only user-pointer BO mappings ivpu: - support frequency limiting panthor: - enable GEM shrinker support - add eviction and reclaim info to fdinfo v3d: - enable runtime PM mgag200: - support XRGB1555 + C8 ast: - support XRGB1555 + C8 - use constants for lots of registers - fix register handling imagination: - fence handling refactoring nouveau: - fix sched double call - expose VBIOS on GSP-RM systems - add GA100 support virtio: - add VIRTIO_GPU_F_BLOB_ALIGNMENT flag - add deferred mapping support gud: - add RCade Display Adapter hibmc: - fix no connectors usage mediatek: - hdmi: convert error handling - simplify mtk_crtc allocation exynos: - move fbdev emulation to drm client buffers - use drm format helpers for geometry/size - adopt core DMA tracking - fix framebuffer offset handling renesas: - add RZ/T2H SOC support versilicon: - add cursor plane support tegra: - use drm client for framebuffer" * tag 'drm-next-2026-06-17' of https://gitlab.freedesktop.org/drm/kernel: (1731 commits) dma-buf: move system_cc_shared heap under separate Kconfig accel/amdxdna: Clear sva pointer after unbind agp/amd64: Fix broken error propagation in agp_amd64_probe() accel/amdxdna: Require carveout when PASID and force_iova are disabled drm/amdkfd: always resume_all after suspend_all drm/amdgpu/gfx: move fault and EOP IRQ get/put to hw_init/hw_fini drm/amd/display: Consult MCCS FreeSync cap only if requested & supported drm/amd/pm: Use strscpy in profile mode parsing drm/amdkfd: Fix infinite loop parsing CRAT with zero subtype length drm/amdkfd: fix sysfs topology prop length on buffer truncation drm/amdgpu: drop retry loop in amdgpu_hmm_range_get_pages drm/amd/pm: bound OD parameter parsing to stack array size drm/amd/pm: Stop pp_od_clk_voltage emit at PAGE_SIZE drm/amdkfd: Unwind debug trap enable on copy_to_user failure drm/amdgpu: validate the mes firmware version for gfx12.1 drm/amdgpu: validate the mes firmware version for gfx12 drm/amdgpu: compare MES firmware version ucode for gfx11 drm/amdkfd: Add bounds check for AMDKFD_IOC_WAIT_EVENTS drm/amdgpu: restart the CS if some parts of the VM are still invalidated drm/amd/display: use unsigned types for local pipe and REG_GET counters ...
2026-06-09drm/i915/edp: Check supported link rates DPCD readNikita Zhandarovich
intel_edp_set_sink_rates() reads DP_SUPPORTED_LINK_RATES into a local stack array and then parses the array unconditionally. If the read fails, the array contents are not valid and may result in bogus sink link rates being used. Use drm_dp_dpcd_read_data() and clear the sink rate array on failure, so the existing parser falls back to the default sink rate handling. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 68f357cb7347 ("drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4") Signed-off-by: Nikita Zhandarovich <n.zhandarovich@fintech.ru> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20260529145759.1640646-1-n.zhandarovich@fintech.ru Signed-off-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit bd61c7756b34157e093028225a69383b4b1203cc) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2026-06-05Revert "drm/i915/backlight: Remove try_vesa_interface"Suraj Kandpal
This reverts commit 40d2f5820951dee818d05c14677277048bd85f9f. Removing the try_vesa_interface gate caused a backlight regression on panels whose VBT correctly reports INTEL_BACKLIGHT_DISPLAY_DDI and whose PWM path is the actual backlight control, but whose DPCD optimistically advertises DP_EDP_BACKLIGHT_AUX_ENABLE_CAP / _BRIGHTNESS_AUX_SET_CAP. After the commit such panels silently bind to the VESA AUX backlight funcs; AUX writes complete but the panel ignores them, leaving brightness stuck (no-op backlight). Observed on at least KBL and TGL eDP setups. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260517024709.1016121-1-suraj.kandpal@intel.com (cherry picked from commit f30fddb4402313aa5301a74d721638d343395269) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
2026-06-03drm/i915: Fix color blob reference handling in intel_plane_stateChaitanya Kumar Borah
Take proper references for hw color blobs (degamma_lut, gamma_lut, ctm, lut_3d) in intel_plane_duplicate_state() and drop them in intel_plane_destroy_state(). v2: - handle blobs in hw state clear Cc: <stable@vger.kernel.org> #v6.19+ Fixes: 3b7476e786c2 ("drm/i915/color: Add framework to program PRE/POST CSC LUT") Fixes: a78f1b6baf4d ("drm/i915/color: Add framework to program CSC") Fixes: 65db7a1f9cf7 ("drm/i915/color: Add 3D LUT to color pipeline") Reviewed-by: Pranay Samala <pranay.samala@intel.com> #v1 Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patch.msgid.link/20260601082953.128539-4-chaitanya.kumar.borah@intel.com (cherry picked from commit c6eea1925154b6697fe22b217faab9bb30635e6b) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2026-05-28drm/i915/dp: Account for AS_SDP guardband only when enabledAnkit Nautiyal
Currently the intel_dp_sdp_min_guardband() accounts for AS_SDP for all platforms that support adaptive sync SDP even for configurations where it cannot be enabled. Instead account for adaptive sync SDP guardband only when it is enabled. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260527041050.601735-13-ankit.k.nautiyal@intel.com
2026-05-28drm/i915/dp: Enable AS SDP whenever VRR is possible or PR !asyncAnkit Nautiyal
Currently AS SDP is only configured when VRR is enabled. With optimized guardband, we also need to account for wakeup time and other relevant details that depend on the AS SDP position whenever AS SDP is enabled. If a feature enabling AS SDP gets turned on later (after modeset), the guardband might not be sufficient and may need to increase, triggering a full modeset. Additionally, for Panel Replay with Aux-less ALPM where the sink does not support asynchronous video timing in PR active, the source must keep transmitting Adaptive-Sync SDPs while PR is active. So, always send AS SDP whenever there is a possibility to use it for VRR OR for Panel Replay for synchronization. v2: Check if AS SDP can be used for synchronization for VRR or PR. (Ville) v3: Use intel_psr_needs_alpm_aux_less() instead of intel_alpm_is_alpm_aux_less() to avoid including the LOBF case. (Ville) Modify the commit message and subject. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260527041050.601735-12-ankit.k.nautiyal@intel.com
2026-05-28drm/i915/dp: Compute AS SDP after PSR compute configAnkit Nautiyal
A subsequent change makes intel_dp_needs_as_sdp() depend on crtc_state->has_panel_replay, which is set by intel_psr_compute_config(). Move call for intel_dp_compute_as_sdp() after the intel_psr_compute_config(). Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260527041050.601735-11-ankit.k.nautiyal@intel.com
2026-05-28drm/i915/dp: Compute and include coasting vtotal for AS SDPAnkit Nautiyal
DP v2.1 allows the source to temporarily suspend Adaptive-Sync SDP transmission while Panel Replay is active when the sink supports asynchronous video timing. In such cases, the sink relies on the last transmitted AS SDP timing information to maintain the refresh rate. To support this behavior, compute and populate the coasting vtotal field in the AS SDP payload. Include coasting vtotal in AS SDP packing, unpacking, and comparison, and set it during late AS SDP configuration for PR with Aux-less ALPM when asynchronous video timing is supported. Note: The coasting vtotal value is fully under driver control i.e. the HW does not overwrite these payload bytes. HW only samples the PR_ALPM_CTL[AS SDP Transmission in Active Disable] bit during PR active state and reflects it in the AS SDP payload at the appropriate time. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260527041050.601735-10-ankit.k.nautiyal@intel.com
2026-05-28drm/i915/dp: Program AS SDP DB[1:0] for PR with Link offAnkit Nautiyal
For Panel Replay with AUX-less ALPM (link-off PR), the source must send Adaptive-Sync SDP v2. Program DB[1:0] per DP spec v2.1: - VRR AVT: 00b (variable VTotal) - VRR FAVT: 10b/11b (TRR not reached/reached) - Fixed timing with PR link-off (VRR off): 01b (AS disabled; VTotal fixed) Also, drop the redundant target_rr assignment. v2: Fix the else case. (Ville) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260527041050.601735-9-ankit.k.nautiyal@intel.com
2026-05-28drm/i915/dp: Set relevant Downspread Ctrl DPCD bits for PR + Auxless ALPMAnkit Nautiyal
If a Panel Replay capable sink, supports Async Video timing in PR active state, then source does not necessarily need to send AS SDPs during PR active. However, if asynchronous video timing is not supported, then for PR with Aux-less ALPM, the source must transmit Adaptive-Sync SDPs for video timing synchronization while PR is active. If the source needs to send AS SDP during PR active, this requires setting DPCD 0x0107[6] (FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE). This applies whether VRR is enabled (AVT/FAVT) or fixed-timing mode is used. This bit defines AS SDP timing behavior during PR Active, even if AS SDPs are briefly suspended. Program the relevant Downspread Ctrl DPCD bits accordingly. v2: Instead of Panel Replay check simply use AS SDP enable check. (Ville) v3: Since the bit is defined in context of Panel Replay and AS SDP, add a check for both. (Ville) v4: Extract pr_with_as_sdp logic into helper function. (Ville) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260527041050.601735-8-ankit.k.nautiyal@intel.com
2026-05-28drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission timeAnkit Nautiyal
Panel Replay requires the AS SDP transmission time to be written into PANEL_REPLAY_CONFIG3. This field was previously not programmed. Use the AS SDP transmission-time helper to populate CONFIG3. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260527041050.601735-7-ankit.k.nautiyal@intel.com
2026-05-28drm/i915/display: Add helper for AS SDP transmission time selectionAnkit Nautiyal
AS SDP may be transmitted at T1 or T2 depending on Panel Replay and Adaptive Sync SDP configuration as per DP 2.1. Current we are using T1 only, but future PR/AS SDP modes/features may require T2 or dynamic selection. Introduce a helper to return the appropriate AS SDP transmission time so that a single value is consistently used for programming PR_ALPM. For now this returns T1. v2: Avoid adding new member to crtc_state; use a helper. (Ville) v3: Clarify why AS SDP transmission time is fixed to T1. (Ville) v4: Return u8 from intel_dp_as_sdp_transmission_time(). (Ville) Bspec: 68920 Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260527041050.601735-6-ankit.k.nautiyal@intel.com
2026-05-28drm/i915/psr: Write the PR config DPCDs in burst modeAnkit Nautiyal
Replace the consecutive single-byte writes to PANEL_REPLAY_CONFIG and CONFIG2 with one drm_dp_dpcd_write() burst starting at PANEL_REPLAY_CONFIG, reducing AUX transactions. v2: Drop extra conditions, and optimize variables. (Ville) v3: Drop the error check after write. (Ville) Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260527041050.601735-5-ankit.k.nautiyal@intel.com
2026-05-28drm/i915/dp: Allow AS SDP only if v2 is supportedAnkit Nautiyal
We do not support AS SDP version 1, so allow AS SDP only if AS SDP v2 is supported. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260527041050.601735-4-ankit.k.nautiyal@intel.com
2026-05-28drm/i915/dp: Add member to intel_dp to store AS SDP v2 supportAnkit Nautiyal
eDP v1.5a advertises support for Adaptive Sync SDP and with that the support for AS SDP v2 is mandatory. DP v2.1 SCR advertises support for FAVT payload fields parsing in DPCD 0x2214 Bit 2. This indicates the support for Adaptive-Sync SDP version 2 (AS SDP v2), which allows the source to set the version in HB2[4:0] and the payload length in HB3[5:0] of the AS SDP header. DP v2.1 SCR also introduces ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR in the Panel Replay Capability DPCD 0x00b1 (Bit 3). When this bit is set, the sink does not support asynchronous video timing while in a Panel Replay Active state and the source is required to keep transmitting Adaptive-Sync SDPs. The spec mandates that such sinks shall support AS SDP v2. Infer AS SDP v2 support from these capabilities and store it in struct intel_dp for use by subsequent feature enablement changes. v2: - Include parsing ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR bit to determine AS SDP v2 support. (Ville) v3: - Use helper to determine asynch video timing support. v4: - Add AS SDP v2 support for eDP as per v1.5a. - Add a check for Panel Replay support before checking for Async video timing support in PR - Add a TODO for Display ID and PCON considerations. (Ville) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260527041050.601735-3-ankit.k.nautiyal@intel.com
2026-05-28drm/i915/psr: Add helper to get Async Video timing support in PR activeAnkit Nautiyal
Introduce a helper to check if Panel Replay has Async Video Timing support during PR Active state. v2: Confirm that Panel Replay is supported before checking for Async Video Timing Support during PR active. (Ville) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260527041050.601735-2-ankit.k.nautiyal@intel.com
2026-05-28drm/i915/power: add "runtime" to intel_display_power_{suspend, resume}() namesJani Nikula
The intel_display_power_suspend() and intel_display_power_resume() functions are supposed to be called from the struct dev_pm_pops .runtime_suspend and .runtime_resume hook paths. Name them accordingly to intel_display_power_runtime_suspend() and intel_display_power_runtime_resume(). Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.coM> Link: https://patch.msgid.link/4a8ae520e3151d6cf5d9e9e3a452f620cf781ee5.1779876087.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-28drm/i915/bw: Do not consider tile4 as tileYVille Syrjälä
For the purposes of memory bandwidth calculations tile4 should not be considered the same as tileY. Make it so. This should not actually change anything as the affected code only applies to pre-MTL integrated GPUs, which don't have tile4. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260522200346.17377-11-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-05-28drm/i915/bw: Remove deinterleave fallback for TGL+Ville Syrjälä
Remove the deinterleave fallback calculation from the TGL+ codepath. The fallback is using the ICL deinterleave calculation which was never in the TGL+ algorithm. All supported memory types have the correct deinterleave already specified for TGL+ anyway, so this is dead code. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260522200346.17377-10-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-05-28drm/i915/bw: Round the PM demand bandwidth downVille Syrjälä
Bspec asks us to round down instead of closest doing the /100 for the PM demand bandwidth. Make it so. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260522200346.17377-9-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-05-28drm/i915/bw: Fix/unify peakbw calculationsVille Syrjälä
We have several copies of the same memory peak bandwidth calculations, and the rounding directions are all over the place in some of them. Unify it all into one small function (with rounding matching what Bspec says). Note that 'channel_width' is always a multiple of 8 anyway, so for 'channel_width / 8' the rounding direction doesn't actually matter. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260522200346.17377-8-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-05-28drm/i915/bw: Fix DEPROGBWPCLIMIT handling on BMGVille Syrjälä
DEPROGBWPCLIMIT is specified in %, so divide by 100 instead of 10. Fortunately the deprobbwlimit is much lower than the peak memory bandwidth on BMG, so whether we take 60% or 600% of the peak bandwidth doesn't matter as the min() will pick the lower deprobbwlimit anyway. Eg. on the BMG here I get (with or without the fix): QGV 0: deratedbw=33600 peakbw=48000 QGV 1: deratedbw=53000 peakbw=456000 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260522200346.17377-7-ville.syrjala@linux.intel.com Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
2026-05-28drm/i915/bw: Fix rounding direction in clperchgroup calculationVille Syrjälä
The '8/num_channels' in the clperchgroup is supposed to be rounded down according to the spec. Make it so. Not sure we can ever actually have a non-power of two number of channels, so this might not matter. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260522200346.17377-6-ville.syrjala@linux.intel.com Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
2026-05-28drm/i915/bw: Fix 'deinterleave' rounding directionVille Syrjälä
For some reason we're rounding up when calculating the deinterleave value. But the spec says we should round down. Fix it. But I suppose this doesn't actually matter since the deinterleave values should always be power of two. The only exception is therefore the deinterleave==1 case, which gets handled by the max(..., 1). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260522200346.17377-5-ville.syrjala@linux.intel.com Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
2026-05-28drm/i915/bw: Fix bw rounding directionVille Syrjälä
The DRAM bandwidth value should be rounded down, not up. Bspec: 64631 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260522200346.17377-4-ville.syrjala@linux.intel.com Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-05-28drm/i915/bw: Fix DCLK rounding messVille Syrjälä
Fix up the total mess when calculating the DCLK frequency. Some codepaths are trying to do both DIV_ROUND_UP() and an open coded "round to nearest" at the same time. The MTL+ codepath was the only one that was correct (using DIV_ROUND_CLOSEST()). Let's unify all of them, and borrow the actual '100/6' approach from adl_calc_psf_bw() so that we get even less rounding errors. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260522200346.17377-3-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2026-05-28drm/i915/bw: Fix num_planes handling on TGL+Ville Syrjälä
The TGL+ bw code has an off by one error on the num_planes calculation, and tgl_max_bw_index() incorrectly bumps the num_planes to 1 from 0. That approach made sense on ICL where num_planes is more or less a minimum number of planes to consider for the group, but on TGL+ num_planes really is a maximum number of planes, so these adjustments no longer make any sense there. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260522200346.17377-2-ville.syrjala@linux.intel.com Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
2026-05-27drm/i915/power: drop resume parameter from intel_display_power_init_hw()Jani Nikula
intel_power_domains_resume() calling intel_display_power_init_hw() with the resume parameter is an internal implementation detail. Hide it inside intel_display_power.c, and provide a clean external interface without the parameter. Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/63666514d457f548c69ccd35c02f2b8200ca08a1.1779800132.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-27drm/i915/power: rename intel_power_domains_*() to intel_display_power_*()Jani Nikula
It's confusing that intel_display_power.[ch] exposes two groups of interfaces, one named intel_power_domains_*() and one intel_display_power_*(). Unify on the latter, based on the file name, but also because it's more generic. This makes the caller side easier to follow. Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/8fae4b0e3476aeffb0164215b7e0f0ae1d825f72.1779800132.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-27drm/i915/power: make intel_power_domains_{suspend, resume}() staticJani Nikula
intel_power_domains_suspend() and intel_power_domains_resume() are only used inside intel_display_power.c. Make them static. Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/bfb5f09794b6b5035839d0182d22980119da2165.1779800132.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-27drm/i915/display: stop passing i to for_each_pipe_crtc_modeset_{enable, ↵Jani Nikula
disable}() Refactor for_each_pipe_crtc_modeset_{enable,disable}() and their underlying for_each_crtc_in_masks{,_reverse}() helpers to utilize __UNIQUE_ID() to avoid having to pass the for loop variable to them. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/2270d4a10663bb55d5b16902b02798234f440517.1778659089.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-27drm/i915/display: stop passing i to for_each_*_intel_crtc_in_state() macrosJani Nikula
None of the for_each_*_intel_crtc_in_state() macros or their users actually need the CRTC index i variable anymore. Remove them. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/edb9dc76cb9cad50622a1f425abaf076d1509888.1778659089.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-27drm/i915/display: pass struct intel_display to all for_each_intel_crtc*() macrosJani Nikula
Now that the for_each_intel_crtc*() iterator macros primarily use display->pipe_list for iteration, it's more convenient to pass struct intel_display to them directly instead of struct drm_device. Make it so. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/90ec6b84d772a4842d4816efc10042ec4403e996.1778659089.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-27drm/i915/display: always pass display->drm to for_each_intel_crtc*()Jani Nikula
In preparation for always passing struct intel_display to for_each_intel_crtc*() family of iterators, start off by unifying their usage to always having struct intel_display *display around, and passing display->drm to them. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/447a5b2309e213abb849601727d45b406d440c88.1778659089.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-27drm/i915/display: switch from drm_for_each_crtc() to for_each_intel_crtc()Jani Nikula
intel_has_pending_fb_unpin() has the last direct user of drm_for_each_crtc() in i915. Switch to for_each_intel_crtc() to ensure pipe order iteration in all cases. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/8ee4320cd15bc35a8b40676faae6db4b33eb50eb.1778659089.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-27drm/{i915, xe}: move xe_display_flush_cleanup_work() to i915 displayJani Nikula
xe_display_flush_cleanup_work() is a bit of an oddball function in xe display code. There shouldn't be anything this specific or xe specific. While I'm not sure what the correct refactor for the function should be, move it to shared display code for starters, next to the eerily similar but slightly different intel_has_pending_fb_unpin() that is only called from i915 core. The main goal here is to unblock some refactors on for_each_intel_crtc(). v2: Add FIXME comment (Ville) Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260525110553.651208-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2026-05-26drm/i915/psr: Use DC_OFF wake reference to block DC6 on vblank enableJouni Högander
We are observing following warnings: *ERROR* power well DC_off state mismatch (refcount 0/enabled 1) gen9_dc_off_power_well_enabled is considering target state DC_STATE_DISABLE as DC_OFF power well being enabled. Fix this by using wakeref for the purpose. To achieve this we need to modify notification code as well. Currently it is possible that PSR gets notified vblank enable/disable twice on same status. This is currently not a problem as it is just triggering call to intel_display_power_set_target_dc_state with same target state as a parameter. When using wakeref this becomes a problem due to reference counting. Fix this storing vbank status on last notification and use that to ensure there are no more than one notification with same vblank status. v2: ensure there is no subsequent notifications with same status Fixes: aa451abcffb5 ("drm/i915/display: Prevent DC6 while vblank is enabled for Panel Replay") Cc: <stable@vger.kernel.org> # v6.13+ Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/20260520104944.239797-2-jouni.hogander@intel.com (cherry picked from commit 35485ac56d878192a3829a58cb26503125ec7104) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2026-05-26drm/i915/psr: Block DC states on vblank enable when Panel Replay supportedJouni Högander
Currently we are blocking DC states only when Panel Replay is enabled on vblank enable. It may happen that Panel Replay is getting enabled when vblank is already enabled. Fix this by blocking DC states always if Panel Replay is supported. While at it take care of possible dual eDP case by looping all encoders supporting PSR. Fixes: 0c427ac78a1d ("drm/i915/psr: Add interface to notify PSR of vblank enable/disable") Cc: <stable@vger.kernel.org> # v6.16+ Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/20260520104944.239797-1-jouni.hogander@intel.com (cherry picked from commit eb5911f990554f7ce947dd53df00c114362e4465) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2026-05-26drm/i915/color: Fix HDR pre-CSC LUT programming loopPranay Samala
The integer lut programming loop never executes completely due to incorrect condition (i++ > 130). Fix to properly program 129th+ entries for values > 1.0. Cc: <stable@vger.kernel.org> #v6.19 Fixes: 82caa1c8813f ("drm/i915/color: Program Pre-CSC registers") Signed-off-by: Pranay Samala <pranay.samala@intel.com> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patch.msgid.link/20260519075308.383877-1-pranay.samala@intel.com (cherry picked from commit f33862ec3e8849ad7c0a3dd46719083b13ade248) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2026-05-26drm/i915/aux: use polling when irqs are unavailableMichał Grzelak
PTL with physically disconnected display was observed to have 40s longer execution time when testing xe_fault_injection@xe_guc_mmio_send_recv. The issue has not been seen when reverting commit 40a9f77a28fa ("Revert "drm/i915/dp: change aux_ctl reg read to polling read""). Apparently the configuration suffers from not having AUX enabled when using interrupts. One probable cause can be xe enabling interrupts too late: interrupts need memory allocations which currently can't be done before the display FB takeover is done. As for now, use polling for AUX in case interrupts are unavailable. Fixes: 40a9f77a28fa ("Revert "drm/i915/dp: change aux_ctl reg read to polling read"") Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Michał Grzelak <michal.grzelak@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260416163744.288107-1-michal.grzelak@intel.com (cherry picked from commit 05e0550b65cd1604bd515fbc65f522bce4c10a87) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2026-05-25drm/i915/dp: Detect changes in common link parametersImre Deak
Detect DPRX capability changes without a long HPD or RX_CAP_CHANGED signal and queue a corresponding link params reset. Besides detecting the above unexpected capability changes, this also avoids races between queuing and handling a deferred link params reset. v2: (Ville) - Query/set intel_dp::reset_link_params instead of using helpers for these. - Assert matching types for old/new common rate elements as well. - Add TODO: for adding a struct tracking both rates and number of rates. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260522160514.2628249-5-imre.deak@intel.com
2026-05-25drm/i915/dp: Cache max common lane countImre Deak
Cache the maximum common lane count together with the common link rates. This is safe because the cached value is updated: - during driver probe, before the connector is registered and can be used for mode validation or modesetting - during resume, before output HW state readout can query it - during connector detection, right after updating the sink/link capabilities Caching the value allows detecting max common lane count changes in a follow-up change and keeps the tracking of max common lane count aligned with that of common rates. Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260522160514.2628249-4-imre.deak@intel.com
2026-05-25drm/i915/dp: Add helper to set common link paramsImre Deak
Add intel_dp_set_common_link_params() to prepare for updating the maximum common lane count together with the common rates. Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260522160514.2628249-3-imre.deak@intel.com
2026-05-25drm/i915/dp: Reset link params after a DPRX capability changeImre Deak
There is no reason to distinguish between DPRX capability changes signaled via a long HPD and via an RX_CAP_CHANGED HPD IRQ. Both cases result in reading out the DPRX capabilities and updating the corresponding sink and common capabilities cached in intel_dp, however only the long HPD resets the link training/recovery state and MST link probe parameters correspondingly. The link training/recovery state may contain reduced maximum link rate/lane count values left over from a previous link training failure. Based on the above after an RX_CAP_CHANGED increased the link rate, lane count parameters the maximum link rate/lane count in the link training/recovery state may remain below these, leaving the newly added valid configurations unavailable for subsequent modesets in an inconsistent way. Handle RX_CAP_CHANGED IRQs the same way as long HPDs and reset the link recovery state and MST link probe parameters in that case as well. v2: Set intel_dp::reset_link_params instead of using a helper for this. (Ville). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patch.msgid.link/20260522160514.2628249-2-imre.deak@intel.com
2026-05-25drm/i915/psr: Allow SCL=0 on platforms with always-on VRR TGAnkit Nautiyal
For Legacy timing generator, if there are no panel replay/sel_update or other SRD constraints, the Set context latency (SCL) window should be at least 1. However, for VRR timing generator the SCL window can be 0. It has other guardband constraints, but that are checked during guardband computation. Allow SCL to be 0 for platforms that have VRR TG always on. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patch.msgid.link/20260517142753.2813959-3-ankit.k.nautiyal@intel.com
2026-05-25drm/i915/psr: Simplify the conditions for SCL computationAnkit Nautiyal
'needs_sel_update' is common for both display version branches, so check it once and keep the version specific checks as separate early returns. v2: Split into separate early returns. (Jani) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patch.msgid.link/20260517142753.2813959-2-ankit.k.nautiyal@intel.com
2026-05-25drm/i915/display: Handle odd position for planar formats in selective fetchJouni Högander
Since Lunarlake there is no restriction planar planes has to be even positions. Due to this we may end up having odd offset for UV-plane in selective fetch configuration. Add handling for this case into selective fetch configuration. Bspec: 68927 Suggested-by: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Vidya Srinivas <vidya.srinivas@intel.com> Link: https://patch.msgid.link/20260512080022.2527094-1-jouni.hogander@intel.com
2026-05-25drm/i915/psr: Use DC_OFF wake reference to block DC6 on vblank enableJouni Högander
We are observing following warnings: *ERROR* power well DC_off state mismatch (refcount 0/enabled 1) gen9_dc_off_power_well_enabled is considering target state DC_STATE_DISABLE as DC_OFF power well being enabled. Fix this by using wakeref for the purpose. To achieve this we need to modify notification code as well. Currently it is possible that PSR gets notified vblank enable/disable twice on same status. This is currently not a problem as it is just triggering call to intel_display_power_set_target_dc_state with same target state as a parameter. When using wakeref this becomes a problem due to reference counting. Fix this storing vbank status on last notification and use that to ensure there are no more than one notification with same vblank status. v2: ensure there is no subsequent notifications with same status Fixes: aa451abcffb5 ("drm/i915/display: Prevent DC6 while vblank is enabled for Panel Replay") Cc: <stable@vger.kernel.org> # v6.13+ Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/20260520104944.239797-2-jouni.hogander@intel.com
2026-05-25drm/i915/psr: Block DC states on vblank enable when Panel Replay supportedJouni Högander
Currently we are blocking DC states only when Panel Replay is enabled on vblank enable. It may happen that Panel Replay is getting enabled when vblank is already enabled. Fix this by blocking DC states always if Panel Replay is supported. While at it take care of possible dual eDP case by looping all encoders supporting PSR. Fixes: 0c427ac78a1d ("drm/i915/psr: Add interface to notify PSR of vblank enable/disable") Cc: <stable@vger.kernel.org> # v6.16+ Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com> Link: https://patch.msgid.link/20260520104944.239797-1-jouni.hogander@intel.com
2026-05-22drm/intel/display: Add support for pipe background color (v4)Maarten Lankhorst
Gen9 platforms allow CRTC's to be programmed with a background/canvas color below the programmable planes. Let's expose this as a property to allow userspace to program a desired value. This patch is based on earlier work by Chandra Konduru and Matt Roper. Between 2018 and now, intel/display has changed so much that another rewrite was necessary. v2: - Set initial background color (black) via proper helper function (Bob) - Fix debugfs output - General rebasing v3 (Maarten): - Rebase on top of recent changes. v4 (Maarten): - Complete rewrite based on the solution that went upstream, and on the new intel color management features. Cc: Chandra Konduru <chandra.konduru@intel.com> Cc: dri-devel@lists.freedesktop.org Co-developed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://patch.msgid.link/20260505200133.636584-2-dev@lankhorst.se Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>