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path: root/drivers/gpu/drm/amd/amdgpu/sid.h
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2020-07-02drm/amdgpu: Clean up KFD VMID assignmentFelix Kuehling
The KFD VMID assignment was hard-coded in a few places. Consolidate that in a single variable adev->vm_manager.first_kfd_vmid. The value is still assigned in gmc-ip-version-specific code. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-02drm/amdgpu: SI support for VCE clock controlAlex Jivin
Port functionality from the Radeon driver to support VCE clock control. Signed-off-by: Alex Jivin <alex.jivin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-02drm/amdgpu: SI support for UVD clock controlAlex Jivin
Port functionality from the Radeon driver to support UVD clock control. Signed-off-by: Alex Jivin <alex.jivin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm amdgpu: SI UVD PACKET_TYPE0Sonny Jiang
Fix packet_type0 definition in sid. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/uvd3.x: fix register definition warningsAlex Deucher
drop the duplicate register macros from sid.h and use the standard ones in the oss register headers. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-27drm/amdgpu: enable ABGR and XBGR formats (v2)Mauro Rossi
Add support for DRM_FORMAT_{A,X}BGR8888 in amdgpu with amd dc disabled (v2) Crossbar registers are defined and used to swap red and blue channels, keeping the existing coding style in each of the dce modules. After setting crossbar bits in fb_swap, use bitwise OR for big endian where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD() Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: move misc si headers into amdgpuAlex Deucher
Move these to the amdgpu directory to match what we do for other asics. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>