lwn.git - Linux kernel documentation tree maintained by Jonathan Corbet

Age	Commit message (Expand)	Author
2023-06-08	clk: ingenic: tcu: Switch to determine_rate	Maxime Ripard
2023-06-08	clk: ingenic: cgu: Switch to determine_rate	Maxime Ripard
2023-01-25	clk: ingenic: jz4760: Update M/N/OD calculation algorithm	Paul Cercueil
2022-11-01	clk: Add Ingenic JZ4755 CGU driver	Siarhei Volkau
2022-10-27	clk: ingenic: Minor cosmetic fixups for X1000	Aidan MacDonald
2022-10-27	clk: ingenic: Add X1000 audio clocks	Aidan MacDonald
2022-10-27	clk: ingenic: Add .set_rate_hook() for PLL clocks	Aidan MacDonald
2022-10-27	clk: ingenic: Make PLL clock enable_bit and stable_bit optional	Aidan MacDonald
2022-10-27	clk: ingenic: Make PLL clock "od" field optional	Aidan MacDonald
2022-08-31	clk: ingenic-tcu: Properly enable registers before accessing timers	Aidan MacDonald
2022-05-18	clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCs	Aidan MacDonald
2022-05-18	clk: ingenic: Mark critical clocks in Ingenic SoCs	Aidan MacDonald
2022-05-18	clk: ingenic: Allow specifying common clock flags	Aidan MacDonald
2022-02-17	clk: jz4725b: fix mmc0 clock gating	Siarhei Volkau
2022-01-06	clk: ingenic: Add MDMA and BDMA clocks	Paul Cercueil
2021-11-14	Merge tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux...	Linus Torvalds
2021-11-11	dt-bindings: Rename Ingenic CGU headers to ingenic,*.h	Paul Cercueil
2021-11-02	clk: ingenic: Fix bugs with divided dividers	Paul Cercueil
2021-06-27	clk: ingenic: Add support for the JZ4760	Paul Cercueil
2021-06-27	clk: ingenic: Support overriding PLLs M/N/OD calc algorithm	Paul Cercueil
2021-06-27	clk: ingenic: Remove pll_info.no_bypass_bit	Paul Cercueil
2021-06-27	clk: ingenic: Read bypass register only when there is one	Paul Cercueil
2021-06-27	clk: Support bypassing dividers	Paul Cercueil
2020-12-19	clk: ingenic: Fix divider calculation with div tables	Paul Cercueil
2020-10-13	clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate	Paul Cercueil
2020-10-13	clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT	Paul Cercueil
2020-10-13	clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL	Paul Cercueil
2020-10-13	clk: ingenic: Use readl_poll_timeout instead of custom loop	Paul Cercueil
2020-10-13	clk: ingenic: Use to_clk_info() macro for all clocks	Paul Cercueil
2020-07-27	clk: X1000: Add support for calculat REFCLK of USB PHY.	周琰杰 (Zhou Yanjie)
2020-07-27	clk: JZ4780: Reformat the code to align it.	周琰杰 (Zhou Yanjie)
2020-07-27	clk: JZ4780: Add functions for enable and disable USB PHY.	周琰杰 (Zhou Yanjie)
2020-07-27	clk: Ingenic: Add RTC related clocks for Ingenic SoCs.	周琰杰 (Zhou Yanjie)
2020-05-28	clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused	Stephen Boyd
2020-05-28	clk: X1000: Add FIXDIV for SSI clock of X1000.	周琰杰 (Zhou Yanjie)
2020-05-28	clk: Ingenic: Add CGU driver for X1830.	周琰杰 (Zhou Yanjie)
2020-05-28	clk: Ingenic: Adjust cgu code to make it compatible with X1830.	周琰杰 (Zhou Yanjie)
2020-05-28	clk: Ingenic: Remove unnecessary spinlock when reading registers.	周琰杰 (Zhou Yanjie)
2020-03-20	clk: ingenic/TCU: Fix round_rate returning error	Paul Cercueil
2020-03-20	clk: ingenic/jz4770: Exit with error if CGU init failed	Paul Cercueil
2020-03-20	clk: JZ4780: Add function for enable the second core.	周琰杰 (Zhou Yanjie)
2020-03-20	clk: Ingenic: Add support for TCU of X1000.	周琰杰 (Zhou Yanjie)
2019-11-27	Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ...	Stephen Boyd
2019-11-22	clk: ingenic: Allow drivers to be built with COMPILE_TEST	Stephen Boyd
2019-11-13	clk: Ingenic: Add CGU driver for X1000.	Zhou Yanjie
2019-11-08	drivers/clk: convert VL struct to struct_size	Stephen Kitt
2019-09-22	Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux	Linus Torvalds
2019-08-12	clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro	Paul Cercueil
2019-08-08	clk: jz4740: Add TCU clock	Paul Cercueil
2019-08-08	clk: ingenic: Add driver for the TCU clocks	Paul Cercueil