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path: root/drivers/clk/clk-versaclock5.c
AgeCommit message (Expand)Author
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner
2019-01-09clk: vc5: Abort clock configuration without upstream clockMarek Vasut
2018-12-14clk: vc5: Add suspend/resume supportMarek Vasut
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V5925Vladimir Barinov
2017-07-17clk: vc5: Add support for IDT VersaClock 5P49V6901Marek Vasut
2017-07-17clk: vc5: Add support for the input frequency doublerMarek Vasut
2017-07-17clk: vc5: Split clock input mux and predividerMarek Vasut
2017-07-17clk: vc5: Configure the output buffer input mux on prepareMarek Vasut
2017-07-17clk: vc5: Do not warn about disabled output buffer input muxesMarek Vasut
2017-07-17clk: vc5: Fix trivial typoMarek Vasut
2017-07-17clk: vc5: Prevent division by zero on unconfigured outputsMarek Vasut
2017-04-19clk: vc5: Add support for IDT VersaClock 5P49V5935Alexey Firago
2017-04-19clk: vc5: Add structure to describe particular chip featuresAlexey Firago
2017-01-20clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933Marek Vasut