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AgeCommit message (Expand)Author
2023-11-07RISC-V: Show accurate per-hart isa in /proc/cpuinfoEvan Green
2023-11-07RISC-V: Don't rely on positional structure initializationPalmer Dabbelt
2023-11-07Merge patch series "riscv: Add remaining module relocations and tests"Palmer Dabbelt
2023-11-07riscv: Add tests for riscv module loadingCharlie Jenkins
2023-11-07riscv: Add remaining module relocationsCharlie Jenkins
2023-11-07riscv: Avoid unaligned access when relocating modulesEmil Renner Berthing
2023-11-07riscv: split cache ops out of dma-noncoherent.cChristoph Hellwig
2023-11-06riscv: select ARCH_PROC_KCORE_TEXTAndreas Schwab
2023-11-06riscv: kernel: Use correct SYM_DATA_*() macro for dataClément Léger
2023-11-06riscv: Use SYM_*() assembly macros instead of deprecated onesClément Léger
2023-11-06riscv: use ".L" local labels in assembly when applicableClément Léger
2023-11-06riscv: boot: Fix creation of loader.binGeert Uytterhoeven
2023-11-06Merge patch series "riscv: tlb flush improvements"Palmer Dabbelt
2023-11-06riscv: Improve flush_tlb_kernel_range()Alexandre Ghiti
2023-11-06riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlbAlexandre Ghiti
2023-11-06riscv: Improve flush_tlb_range() for hugetlb pagesAlexandre Ghiti
2023-11-06riscv: Improve tlb_flush()Alexandre Ghiti
2023-11-05riscv: mm: update T-Head memory type definitionsJisheng Zhang
2023-11-05Merge patch series "riscv: vdso.lds.S: some improvement"Palmer Dabbelt
2023-11-05riscv: vdso.lds.S: remove hardcoded 0x800 .text start addrJisheng Zhang
2023-11-05riscv: vdso.lds.S: merge .data section into .rodata sectionJisheng Zhang
2023-11-05riscv: vdso.lds.S: drop __alt_start and __alt_end symbolsJisheng Zhang
2023-11-05riscv: add userland instruction dump to RISC-V splatsYunhui Cui
2023-11-05riscv: kprobes: allow writing to x0Nam Cao
2023-11-05riscv: provide riscv-specific is_trap_insn()Nam Cao
2023-11-05Merge patch series "Improve PTDUMP and introduce new fields"Palmer Dabbelt
2023-11-05riscv: Introduce NAPOT field to PTDUMPYu Chien Peter Lin
2023-11-05riscv: Introduce PBMT field to PTDUMPYu Chien Peter Lin
2023-11-05riscv: Improve PTDUMP to show RSW with non-zero valueYu Chien Peter Lin
2023-11-05RISC-V: capitalise CMO op macrosConor Dooley
2023-11-05riscv: don't probe unaligned access speed if already doneJisheng Zhang
2023-11-05riscv: defconfig : add CONFIG_MMC_DW for starfiveJinyu Tang
2023-11-05riscv: signal: handle syscall restart before get_signalHaorong Lu
2023-11-05Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt
2023-11-02RISC-V: hwprobe: Fix vDSO SIGSEGVAndrew Jones
2023-11-02riscv: configs: defconfig: Enable configs required for RZ/Five SoCLad Prabhakar
2023-11-02Merge patch series "riscv: SCS support"Palmer Dabbelt
2023-11-02Merge patch "riscv: errata: improve T-Head CMO"Palmer Dabbelt
2023-11-02riscv: errata: prefix T-Head mnemonics with th.Icenowy Zheng
2023-11-01riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGNClément Léger
2023-11-01riscv: report misaligned accesses emulation to hwprobeClément Léger
2023-11-01riscv: annotate check_unaligned_access_boot_cpu() with __initClément Léger
2023-11-01riscv: add support for sysctl unaligned_enabled controlClément Léger
2023-11-01riscv: add floating point insn support to misaligned access emulationClément Léger
2023-11-01riscv: report perf event for misaligned faultClément Léger
2023-11-01riscv: add support for misaligned trap handling in S-modeClément Léger
2023-11-01riscv: remove unused functions in traps_misaligned.cClément Léger
2023-10-31Merge patch series "RISC-V: ACPI improvements"Palmer Dabbelt
2023-10-31riscv: put interrupt entries into .irqentry.textNam Cao
2023-10-31riscv: mm: Update the comment of CONFIG_PAGE_OFFSETSong Shuai