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path: root/arch/arm/include/asm/cacheflush.h
AgeCommit message (Expand)Author
2023-12-14mm: Introduce flush_cache_vmap_early()Alexandre Ghiti
2023-08-24mm: rationalise flush_icache_pages() and flush_icache_page()Matthew Wilcox (Oracle)
2023-08-24arm: implement the new page table range APIMatthew Wilcox (Oracle)
2022-03-23Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-armLinus Torvalds
2022-02-09ARM: cacheflush: avoid clobbering the frame pointerArd Biesheuvel
2021-11-17Add linux/cacheflush.hMatthew Wilcox (Oracle)
2021-10-18mm: Add flush_dcache_folio()Matthew Wilcox (Oracle)
2021-09-03mm: remove flush_kernel_dcache_pageChristoph Hellwig
2020-06-08arm: rename flush_cache_user_range to flush_icache_user_rangeChristoph Hellwig
2020-06-08arm,sparc,unicore32: remove flush_icache_user_rangeChristoph Hellwig
2019-07-08Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-armLinus Torvalds
2019-06-20ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU coresMarek Szyprowski
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner
2018-06-15docs: Fix some broken referencesMauro Carvalho Chehab
2018-04-11page cache: use xa_lockMatthew Wilcox
2017-06-30randstruct: opt-out externally exposed function pointer structsKees Cook
2017-05-08treewide: decouple cacheflush.h and set_memory.hLaura Abbott
2017-05-08treewide: move set_memory_* functions away from cacheflush.hLaura Abbott
2017-02-07arch: Rename CONFIG_DEBUG_RODATA and CONFIG_DEBUG_MODULE_RONXLaura Abbott
2016-08-26ARM: 8601/1: Remove unused secure_flush_area APIAndy Gross
2016-02-22asm-generic: Consolidate mark_rodata_ro()Kees Cook
2015-08-11firmware: qcom_scm-32: replace open-coded call to __cpuc_flush_dcache_area()Russell King
2015-08-01ARM: reduce visibility of dmac_* functionsRussell King
2015-05-28ARM: 8380/1: bpf: fix NOMMU buildArnd Bergmann
2014-10-16ARM: mm: allow text and rodata sections to be read-onlyKees Cook
2014-09-30ARM: 8177/1: cacheflush: Fix v7_exit_coherency_flush exynos build breakage on...Krzysztof Kozlowski
2014-08-27ARM: 8129/1: errata: work around Cortex-A15 erratum 830321 using dummy strexMark Rutland
2014-05-25ARM: 8043/1: uprobes need icache flush after xol writeVictor Kamensky
2014-05-25ARM: 8055/1: cacheflush: use -st dsb option for ensuring completionWill Deacon
2014-02-17ARM: 7957/1: add DSB after icache flush in __flush_icache_all()Vinayak Kale
2013-12-11ARM: mm: Define set_memory_* functions for ARMLaura Abbott
2013-10-29ARM: 7861/1: cacheflush: consolidate single-CPU ARMv7 cache disabling codeNicolas Pitre
2013-08-28Merge branch 'for-rmk/cacheflush-v2' of git://git.kernel.org/pub/scm/linux/ke...Russell King
2013-08-20ARM: cacheflush: don't round address range up to nearest pageWill Deacon
2013-08-12ARM: cacheflush: use -ishst dsb variant for ensuring flush completionWill Deacon
2013-06-17ARM: 7755/1: handle user space mapped pages in flush_kernel_dcache_pageSimon Baatz
2013-04-24ARM: cacheflush: add synchronization helpers for mixed cache state accessesNicolas Pitre
2012-09-25ARM: mm: implement LoUIS API for cache maintenance opsLorenzo Pieralisi
2012-07-31ARM: 7479/1: mm: avoid NULL dereference when flushing gate_vma with VIVT cachesWill Deacon
2012-05-02ARM: 7408/1: cacheflush: return error to userspace when flushing syscall failsWill Deacon
2012-04-19ARM: 7365/1: drop unused parameter from flush_cache_user_rangeDima Zavin
2011-03-16Merge branch 'v6v7' into develRussell King
2011-02-12ARM: move cache/processor/fault glue to separate include filesRussell King
2011-02-02ARM: v6/v7 cache: allow cache calls to be optimizedRussell King
2011-02-02ARM: v6k: introduce CPU_V6K optionRussell King
2010-10-18Merge branches 'at91', 'dcache', 'ftrace', 'hwbpt', 'misc', 'mmci', 's3c', 's...Russell King
2010-10-04ARM: 6405/1: Handle __flush_icache_all for CONFIG_SMP_ON_UPTony Lindgren
2010-09-19ARM: 6382/1: Remove superfluous flush_kernel_dcache_page()Catalin Marinas
2010-09-19ARM: 6379/1: Assume new page cache pages have dirty D-cacheCatalin Marinas
2010-05-08ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMPCatalin Marinas