diff options
Diffstat (limited to 'include/sound')
47 files changed, 3695 insertions, 318 deletions
diff --git a/include/sound/ac97/codec.h b/include/sound/ac97/codec.h index 882b849b9255..69aa7ee15b91 100644 --- a/include/sound/ac97/codec.h +++ b/include/sound/ac97/codec.h @@ -33,7 +33,7 @@ struct ac97_id { }; /** - * ac97_codec_device - a ac97 codec + * struct ac97_codec_device - a ac97 codec * @dev: the core device * @vendor_id: the vendor_id of the codec, as sensed on the AC-link * @num: the codec number, 0 is primary, 1 is first slave, etc ... @@ -53,7 +53,7 @@ struct ac97_codec_device { }; /** - * ac97_codec_driver - a ac97 codec driver + * struct ac97_codec_driver - a ac97 codec driver * @driver: the device driver structure * @probe: the function called when a ac97_codec_device is matched * @remove: the function called when the device is unbound/removed @@ -108,6 +108,9 @@ static inline void ac97_set_drvdata(struct ac97_codec_device *adev, dev_set_drvdata(ac97_codec_dev2dev(adev), data); } -void *snd_ac97_codec_get_platdata(const struct ac97_codec_device *adev); +static inline void *snd_ac97_codec_get_platdata(const struct ac97_codec_device *adev) +{ + return NULL; +} #endif diff --git a/include/sound/ac97/controller.h b/include/sound/ac97/controller.h index 06b5afb7fa6b..d5895ea3922b 100644 --- a/include/sound/ac97/controller.h +++ b/include/sound/ac97/controller.h @@ -62,14 +62,13 @@ struct ac97_controller_ops { #if IS_ENABLED(CONFIG_AC97_BUS_NEW) struct ac97_controller *snd_ac97_controller_register( const struct ac97_controller_ops *ops, struct device *dev, - unsigned short slots_available, void **codecs_pdata); + unsigned short slots_available); void snd_ac97_controller_unregister(struct ac97_controller *ac97_ctrl); #else static inline struct ac97_controller * snd_ac97_controller_register(const struct ac97_controller_ops *ops, struct device *dev, - unsigned short slots_available, - void **codecs_pdata) + unsigned short slots_available) { return ERR_PTR(-ENODEV); } diff --git a/include/sound/acp7x_chip_offset_byte.h b/include/sound/acp7x_chip_offset_byte.h new file mode 100644 index 000000000000..772c3d38cb8d --- /dev/null +++ b/include/sound/acp7x_chip_offset_byte.h @@ -0,0 +1,2519 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * AMD ACP 7.x Register Documentation + * + * Copyright 2026 Advanced Micro Devices, Inc. + */ + +#ifndef _acp_ip_7x_chip_OFFSET_BYTE_H +#define _acp_ip_7x_chip_OFFSET_BYTE_H + +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x000C00 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x000C04 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x000C08 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x000C0C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x000C10 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x000C14 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x000C18 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x000C1C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x000C20 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x000C24 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x000C28 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x000C2C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x000C30 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x000C34 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x000C38 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x000C3C +#define ACPAXI2AXI_ATU_CTRL 0x000C40 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x000C44 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x000C48 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x000C4C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x000C50 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x000C54 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x000C58 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x000C5C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x000C60 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x000C64 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x000C68 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x000C6C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x000C70 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x000C74 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x000C78 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x000C7C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x000C80 + +#define ACP_SOFT_RESET 0x001000 +#define ACP_CONTROL 0x001004 +#define ACP_STATUS 0x001008 +#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x001010 +#define ACP_ZSC_DSP_CTRL 0x001014 +#define ACP_ZSC_STS 0x001018 +#define ACP_PGFSM_CONTROL 0x001024 +#define ACP_PGFSM_STATUS 0x001028 +#define ACP_CLKMUX_SEL 0x00102C +#define ACP_SW_48MHz_CLK_SEL 0x001030 +#define ACP_AUDIO_CLK_SEL 0x001038 +#define ACP_PDM_CORE_CLK_SEL 0x00103C + +#define ACP_PME_EN 0x001400 +#define ACP_DEVICE_STATE 0x001404 +#define SW_DEVICE_STATE 0x001430 +#define ACP_PIN_CONFIG 0x001440 +#define ACP_PAD_PULLUP_CTRL 0x001444 +#define ACP_PAD_PULLDOWN_CTRL 0x001448 +#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x00144C +#define ACP_PAD_SCHMEN_CTRL 0x001450 +#define ACP_SW_PAD_KEEPER_EN 0x001454 +#define ACP_SW_WAKE_EN 0x001458 +#define ACP_I2S_WAKE_EN 0x00145C +#define ACP_ACLK_AUDIOCLK_CTRL 0x001464 +#define ACP_PAD_DISABLE_OE_CTRL 0x001468 +#define ACP_SW0_PME_STS 0x001474 +#define ACP_SW1_PME_STS 0x001478 +#define ACP_SW2_PME_STS 0x00147C +#define ACP_SW3_PME_STS 0x001480 +#define ACP_I2S_PME_STS 0x001484 +#define ACP_TDM_LOOPBACK_EN 0x001488 + +#define ACP_FUTURE_REG_ACLK_0 0x0018E0 +#define ACP_FUTURE_REG_ACLK_1 0x0018E4 +#define ACP_FUTURE_REG_ACLK_2 0x0018E8 +#define ACP_FUTURE_REG_ACLK_3 0x0018EC +#define ACP_FUTURE_REG_ACLK_4 0x0018F0 +#define ACP_AXI2DAGB_SEM_0 0x0018F4 + +#define ACP_EXTERNAL_INTR_ENB 0x001A00 +#define ACP_EXTERNAL_INTR_CNTL 0x001A04 +#define ACP_EXTERNAL_INTR_CNTL1 0x001A08 +#define ACP_EXTERNAL_SW0_INTR_CNTL 0x001A0C +#define ACP_EXTERNAL_SW1_INTR_CNTL 0x001A10 +#define ACP_EXTERNAL_SW2_INTR_CNTL 0x001A14 +#define ACP_EXTERNAL_SW3_INTR_CNTL 0x001A18 +#define ACP_EXTERNAL_INTR_STAT 0x001A1C +#define ACP_EXTERNAL_INTR_STAT1 0x001A20 +#define ACP_EXTERNAL_SW0_INTR_STAT 0x001A24 +#define ACP_EXTERNAL_SW1_INTR_STAT 0x001A28 +#define ACP_EXTERNAL_SW2_INTR_STAT 0x001A2C +#define ACP_EXTERNAL_SW3_INTR_STAT 0x001A30 +#define ACP_ERROR_STATUS 0x001A88 +#define ACP_ERROR_INTR_CTRL1 0x001AA4 +#define ACP_P1_FUTURE_REG_ACLK_0 0x001AB4 +#define ACP_P1_FUTURE_REG_ACLK_1 0x001AB8 + +#define ACP_I2S_TDM0_RX_RINGBUFADDR 0x002000 +#define ACP_I2S_TDM0_RX_RINGBUFSIZE 0x002004 +#define ACP_I2S_TDM0_RX_LINKPOSITIONCNTR 0x002008 +#define ACP_I2S_TDM0_RX_FIFOADDR 0x00200C +#define ACP_I2S_TDM0_RX_FIFOSIZE 0x002010 +#define ACP_I2S_TDM0_RX_DMA_SIZE 0x002014 +#define ACP_I2S_TDM0_RX_LINEARPOSITIONCNTR_HIGH 0x002018 +#define ACP_I2S_TDM0_RX_LINEARPOSITIONCNTR_LOW 0x00201C +#define ACP_I2S_TDM0_RX_INTR_WATERMARK_SIZE 0x002020 +#define ACP_I2S_TDM0_TX_RINGBUFADDR 0x002024 +#define ACP_I2S_TDM0_TX_RINGBUFSIZE 0x002028 +#define ACP_I2S_TDM0_TX_LINKPOSITIONCNTR 0x00202C +#define ACP_I2S_TDM0_TX_FIFOADDR 0x002030 +#define ACP_I2S_TDM0_TX_FIFOSIZE 0x002034 +#define ACP_I2S_TDM0_TX_DMA_SIZE 0x002038 +#define ACP_I2S_TDM0_TX_LINEARPOSITIONCNTR_HIGH 0x00203C +#define ACP_I2S_TDM0_TX_LINEARPOSITIONCNTR_LOW 0x002040 +#define ACP_I2S_TDM0_TX_INTR_WATERMARK_SIZE 0x002044 +#define ACP_I2S_TDM0_POS_TRACK_TX_CTRL 0x002048 +#define ACP_I2S_TDM0_TX_DMA_POS 0x00204C +#define ACP_I2S_TDM0_POS_TRACK_I2S_RX_CTRL 0x002050 +#define ACP_I2S_TDM0_RX_DMA_POS 0x002054 +#define ACP_I2S_TDM0_ERROR_STATUS 0x002058 +#define ACP_I2S_TDM0_ERROR_MASK 0x00205C +#define ACP_I2S_TDM0_IER 0x002100 +#define ACP_I2S_TDM0_IRER 0x002104 +#define ACP_I2S_TDM0_RXFRMT 0x002108 +#define ACP_I2S_TDM0_ITER 0x00210C +#define ACP_I2S_TDM0_TXFRMT 0x002110 +#define ACP_I2S_TDM0_MSTRCLKGEN 0x002114 +#define ACP_I2S_TDM0_OUTPUT_SPLIT_EN 0x002118 +#define ACP_I2S_TDM0_WALLCLK_MISC 0x00211C +#define ACP_I2S_TDM0_WALL_CLK_COUNTER 0x002120 +#define ACP_I2S_TDM_REFCLKGEN 0x002124 +#define ACP_TDM_SYNCEN 0x002128 +#define ACP_TDM_LRCLK_START 0x00212C +#define ACP_I2S_TDM0_WALLCLK_INTR_CNTL 0x002130 + +#define ACP_I2S_TDM1_RX_RINGBUFADDR 0x002200 +#define ACP_I2S_TDM1_RX_RINGBUFSIZE 0x002204 +#define ACP_I2S_TDM1_RX_LINKPOSITIONCNTR 0x002208 +#define ACP_I2S_TDM1_RX_FIFOADDR 0x00220C +#define ACP_I2S_TDM1_RX_FIFOSIZE 0x002210 +#define ACP_I2S_TDM1_RX_DMA_SIZE 0x002214 +#define ACP_I2S_TDM1_RX_LINEARPOSITIONCNTR_HIGH 0x002218 +#define ACP_I2S_TDM1_RX_LINEARPOSITIONCNTR_LOW 0x00221C +#define ACP_I2S_TDM1_RX_INTR_WATERMARK_SIZE 0x002220 +#define ACP_I2S_TDM1_TX_RINGBUFADDR 0x002224 +#define ACP_I2S_TDM1_TX_RINGBUFSIZE 0x002228 +#define ACP_I2S_TDM1_TX_LINKPOSITIONCNTR 0x00222C +#define ACP_I2S_TDM1_TX_FIFOADDR 0x002230 +#define ACP_I2S_TDM1_TX_FIFOSIZE 0x002234 +#define ACP_I2S_TDM1_TX_DMA_SIZE 0x002238 +#define ACP_I2S_TDM1_TX_LINEARPOSITIONCNTR_HIGH 0x00223C +#define ACP_I2S_TDM1_TX_LINEARPOSITIONCNTR_LOW 0x002240 +#define ACP_I2S_TDM1_TX_INTR_WATERMARK_SIZE 0x002244 +#define ACP_I2S_TDM1_POS_TRACK_TX_CTRL 0x002248 +#define ACP_I2S_TDM1_TX_DMA_POS 0x00224C +#define ACP_I2S_TDM1_POS_TRACK_I2S_RX_CTRL 0x002250 +#define ACP_I2S_TDM1_RX_DMA_POS 0x002254 +#define ACP_I2S_TDM1_ERROR_STATUS 0x002258 +#define ACP_I2S_TDM1_ERROR_MASK 0x00225C +#define ACP_I2S_TDM1_IER 0x002300 +#define ACP_I2S_TDM1_IRER 0x002304 +#define ACP_I2S_TDM1_RXFRMT 0x002308 +#define ACP_I2S_TDM1_ITER 0x00230C +#define ACP_I2S_TDM1_TXFRMT 0x002310 +#define ACP_I2S_TDM1_MSTRCLKGEN 0x002314 +#define ACP_I2S_TDM1_OUTPUT_SPLIT_EN 0x002318 +#define ACP_I2S_TDM1_WALLCLK_MISC 0x00231C +#define ACP_I2S_TDM1_WALL_CLK_COUNTER 0x002320 +#define ACP_I2S_TDM1_WALLCLK_INTR_CNTL 0x002330 + +#define ACP_I2S_TDM2_RX_RINGBUFADDR 0x002400 +#define ACP_I2S_TDM2_RX_RINGBUFSIZE 0x002404 +#define ACP_I2S_TDM2_RX_LINKPOSITIONCNTR 0x002408 +#define ACP_I2S_TDM2_RX_FIFOADDR 0x00240C +#define ACP_I2S_TDM2_RX_FIFOSIZE 0x002410 +#define ACP_I2S_TDM2_RX_DMA_SIZE 0x002414 +#define ACP_I2S_TDM2_RX_LINEARPOSITIONCNTR_HIGH 0x002418 +#define ACP_I2S_TDM2_RX_LINEARPOSITIONCNTR_LOW 0x00241C +#define ACP_I2S_TDM2_RX_INTR_WATERMARK_SIZE 0x002420 +#define ACP_I2S_TDM2_TX_RINGBUFADDR 0x002424 +#define ACP_I2S_TDM2_TX_RINGBUFSIZE 0x002428 +#define ACP_I2S_TDM2_TX_LINKPOSITIONCNTR 0x00242C +#define ACP_I2S_TDM2_TX_FIFOADDR 0x002430 +#define ACP_I2S_TDM2_TX_FIFOSIZE 0x002434 +#define ACP_I2S_TDM2_TX_DMA_SIZE 0x002438 +#define ACP_I2S_TDM2_TX_LINEARPOSITIONCNTR_HIGH 0x00243C +#define ACP_I2S_TDM2_TX_LINEARPOSITIONCNTR_LOW 0x002440 +#define ACP_I2S_TDM2_TX_INTR_WATERMARK_SIZE 0x002444 +#define ACP_I2S_TDM2_POS_TRACK_TX_CTRL 0x002448 +#define ACP_I2S_TDM2_TX_DMA_POS 0x00244C +#define ACP_I2S_TDM2_POS_TRACK_I2S_RX_CTRL 0x002450 +#define ACP_I2S_TDM2_RX_DMA_POS 0x002454 +#define ACP_I2S_TDM2_ERROR_STATUS 0x002458 +#define ACP_I2S_TDM2_ERROR_MASK 0x00245C +#define ACP_I2S_TDM2_IER 0x002500 +#define ACP_I2S_TDM2_IRER 0x002504 +#define ACP_I2S_TDM2_RXFRMT 0x002508 +#define ACP_I2S_TDM2_ITER 0x00250C +#define ACP_I2S_TDM2_TXFRMT 0x002510 +#define ACP_I2S_TDM2_MSTRCLKGEN 0x002514 +#define ACP_I2S_TDM2_OUTPUT_SPLIT_EN 0x002518 +#define ACP_I2S_TDM2_WALLCLK_MISC 0x00251C +#define ACP_I2S_TDM2_WALL_CLK_COUNTER 0x002520 +#define ACP_I2S_TDM2_WALLCLK_INTR_CNTL 0x002530 + +#define ACP_SW_CTRL_COUNT 0x004D00 +#define ACP_SW_GSYNC_EN 0x004D04 +#define ACP_SW_GSYNC_EN_PRE_SELECT 0x004D08 +#define ACP_SW_GSYNC_DP_EN 0x004D0C + +#define ACP_SW0_GLOBAL_CAPABILITIES 0x004E00 +#define ACP_SW0_RX_DMA0_RINGBUFADDR 0x004E04 +#define ACP_SW0_RX_DMA0_RINGBUFSIZE 0x004E08 +#define ACP_SW0_RX_DMA0_FIFOADDR 0x004E0C +#define ACP_SW0_RX_DMA0_FIFOSIZE 0x004E10 +#define ACP_SW0_RX_DMA0_BURST_SIZE 0x004E14 +#define ACP_SW0_RX_DMA0_LINKPOSITIONCNTR 0x004E18 +#define ACP_SW0_RX_DMA0_LINEARPOSITIONCNTR_HIGH 0x004E1C +#define ACP_SW0_RX_DMA0_LINEARPOSITIONCNTR_LOW 0x004E20 +#define ACP_SW0_RX_DMA0_INTR_WATERMARK_SIZE 0x004E24 +#define ACP_SW0_RX_DMA1_RINGBUFADDR 0x004E28 +#define ACP_SW0_RX_DMA1_RINGBUFSIZE 0x004E2C +#define ACP_SW0_RX_DMA1_FIFOADDR 0x004E30 +#define ACP_SW0_RX_DMA1_FIFOSIZE 0x004E34 +#define ACP_SW0_RX_DMA1_BURST_SIZE 0x004E38 +#define ACP_SW0_RX_DMA1_LINKPOSITIONCNTR 0x004E3C +#define ACP_SW0_RX_DMA1_LINEARPOSITIONCNTR_HIGH 0x004E40 +#define ACP_SW0_RX_DMA1_LINEARPOSITIONCNTR_LOW 0x004E44 +#define ACP_SW0_RX_DMA1_INTR_WATERMARK_SIZE 0x004E48 +#define ACP_SW0_RX_DMA2_RINGBUFADDR 0x004E4C +#define ACP_SW0_RX_DMA2_RINGBUFSIZE 0x004E50 +#define ACP_SW0_RX_DMA2_FIFOADDR 0x004E54 +#define ACP_SW0_RX_DMA2_FIFOSIZE 0x004E58 +#define ACP_SW0_RX_DMA2_BURST_SIZE 0x004E5C +#define ACP_SW0_RX_DMA2_LINKPOSITIONCNTR 0x004E60 +#define ACP_SW0_RX_DMA2_LINEARPOSITIONCNTR_HIGH 0x004E64 +#define ACP_SW0_RX_DMA2_LINEARPOSITIONCNTR_LOW 0x004E68 +#define ACP_SW0_RX_DMA2_INTR_WATERMARK_SIZE 0x004E6C +#define ACP_SW0_RX_DMA3_RINGBUFADDR 0x004E70 +#define ACP_SW0_RX_DMA3_RINGBUFSIZE 0x004E74 +#define ACP_SW0_RX_DMA3_FIFOADDR 0x004E78 +#define ACP_SW0_RX_DMA3_FIFOSIZE 0x004E7C +#define ACP_SW0_RX_DMA3_BURST_SIZE 0x004E80 +#define ACP_SW0_RX_DMA3_LINKPOSITIONCNTR 0x004E84 +#define ACP_SW0_RX_DMA3_LINEARPOSITIONCNTR_HIGH 0x004E88 +#define ACP_SW0_RX_DMA3_LINEARPOSITIONCNTR_LOW 0x004E8C +#define ACP_SW0_RX_DMA3_INTR_WATERMARK_SIZE 0x004E90 +#define ACP_SW0_RX_DMA4_RINGBUFADDR 0x004E94 +#define ACP_SW0_RX_DMA4_RINGBUFSIZE 0x004E98 +#define ACP_SW0_RX_DMA4_FIFOADDR 0x004E9C +#define ACP_SW0_RX_DMA4_FIFOSIZE 0x004EA0 +#define ACP_SW0_RX_DMA4_BURST_SIZE 0x004EA4 +#define ACP_SW0_RX_DMA4_LINKPOSITIONCNTR 0x004EA8 +#define ACP_SW0_RX_DMA4_LINEARPOSITIONCNTR_HIGH 0x004EAC +#define ACP_SW0_RX_DMA4_LINEARPOSITIONCNTR_LOW 0x004EB0 +#define ACP_SW0_RX_DMA4_INTR_WATERMARK_SIZE 0x004EB4 +#define ACP_SW0_RX_DMA5_RINGBUFADDR 0x004EB8 +#define ACP_SW0_RX_DMA5_RINGBUFSIZE 0x004EBC +#define ACP_SW0_RX_DMA5_FIFOADDR 0x004EC0 +#define ACP_SW0_RX_DMA5_FIFOSIZE 0x004EC4 +#define ACP_SW0_RX_DMA5_BURST_SIZE 0x004EC8 +#define ACP_SW0_RX_DMA5_LINKPOSITIONCNTR 0x004ECC +#define ACP_SW0_RX_DMA5_LINEARPOSITIONCNTR_HIGH 0x004ED0 +#define ACP_SW0_RX_DMA5_LINEARPOSITIONCNTR_LOW 0x004ED4 +#define ACP_SW0_RX_DMA5_INTR_WATERMARK_SIZE 0x004ED8 +#define ACP_SW0_RX_DMA6_RINGBUFADDR 0x004EDC +#define ACP_SW0_RX_DMA6_RINGBUFSIZE 0x004EE0 +#define ACP_SW0_RX_DMA6_FIFOADDR 0x004EE4 +#define ACP_SW0_RX_DMA6_FIFOSIZE 0x004EE8 +#define ACP_SW0_RX_DMA6_BURST_SIZE 0x004EEC +#define ACP_SW0_RX_DMA6_LINKPOSITIONCNTR 0x004EF0 +#define ACP_SW0_RX_DMA6_LINEARPOSITIONCNTR_HIGH 0x004EF4 +#define ACP_SW0_RX_DMA6_LINEARPOSITIONCNTR_LOW 0x004EF8 +#define ACP_SW0_RX_DMA6_INTR_WATERMARK_SIZE 0x004EFC +#define ACP_SW0_RX_DMA7_RINGBUFADDR 0x004F00 +#define ACP_SW0_RX_DMA7_RINGBUFSIZE 0x004F04 +#define ACP_SW0_RX_DMA7_FIFOADDR 0x004F08 +#define ACP_SW0_RX_DMA7_FIFOSIZE 0x004F0C +#define ACP_SW0_RX_DMA7_BURST_SIZE 0x004F10 +#define ACP_SW0_RX_DMA7_LINKPOSITIONCNTR 0x004F14 +#define ACP_SW0_RX_DMA7_LINEARPOSITIONCNTR_HIGH 0x004F18 +#define ACP_SW0_RX_DMA7_LINEARPOSITIONCNTR_LOW 0x004F1C +#define ACP_SW0_RX_DMA7_INTR_WATERMARK_SIZE 0x004F20 +#define ACP_SW0_TX_DMA0_RINGBUFADDR 0x004F24 +#define ACP_SW0_TX_DMA0_RINGBUFSIZE 0x004F28 +#define ACP_SW0_TX_DMA0_FIFOADDR 0x004F2C +#define ACP_SW0_TX_DMA0_FIFOSIZE 0x004F30 +#define ACP_SW0_TX_DMA0_BURST_SIZE 0x004F34 +#define ACP_SW0_TX_DMA0_LINKPOSITIONCNTR 0x004F38 +#define ACP_SW0_TX_DMA0_LINEARPOSITIONCNTR_HIGH 0x004F3C +#define ACP_SW0_TX_DMA0_LINEARPOSITIONCNTR_LOW 0x004F40 +#define ACP_SW0_TX_DMA0_INTR_WATERMARK_SIZE 0x004F44 +#define ACP_SW0_TX_DMA1_RINGBUFADDR 0x004F48 +#define ACP_SW0_TX_DMA1_RINGBUFSIZE 0x004F4C +#define ACP_SW0_TX_DMA1_FIFOADDR 0x004F50 +#define ACP_SW0_TX_DMA1_FIFOSIZE 0x004F54 +#define ACP_SW0_TX_DMA1_BURST_SIZE 0x004F58 +#define ACP_SW0_TX_DMA1_LINKPOSITIONCNTR 0x004F5C +#define ACP_SW0_TX_DMA1_LINEARPOSITIONCNTR_HIGH 0x004F60 +#define ACP_SW0_TX_DMA1_LINEARPOSITIONCNTR_LOW 0x004F64 +#define ACP_SW0_TX_DMA1_INTR_WATERMARK_SIZE 0x004F68 +#define ACP_SW0_TX_DMA2_RINGBUFADDR 0x004F6C +#define ACP_SW0_TX_DMA2_RINGBUFSIZE 0x004F70 +#define ACP_SW0_TX_DMA2_FIFOADDR 0x004F74 +#define ACP_SW0_TX_DMA2_FIFOSIZE 0x004F78 +#define ACP_SW0_TX_DMA2_BURST_SIZE 0x004F7C +#define ACP_SW0_TX_DMA2_LINKPOSITIONCNTR 0x004F80 +#define ACP_SW0_TX_DMA2_LINEARPOSITIONCNTR_HIGH 0x004F84 +#define ACP_SW0_TX_DMA2_LINEARPOSITIONCNTR_LOW 0x004F88 +#define ACP_SW0_TX_DMA2_INTR_WATERMARK_SIZE 0x004F8C +#define ACP_SW0_TX_DMA3_RINGBUFADDR 0x004F90 +#define ACP_SW0_TX_DMA3_RINGBUFSIZE 0x004F94 +#define ACP_SW0_TX_DMA3_FIFOADDR 0x004F98 +#define ACP_SW0_TX_DMA3_FIFOSIZE 0x004F9C +#define ACP_SW0_TX_DMA3_BURST_SIZE 0x004FA0 +#define ACP_SW0_TX_DMA3_LINKPOSITIONCNTR 0x004FA4 +#define ACP_SW0_TX_DMA3_LINEARPOSITIONCNTR_HIGH 0x004FA8 +#define ACP_SW0_TX_DMA3_LINEARPOSITIONCNTR_LOW 0x004FAC +#define ACP_SW0_TX_DMA3_INTR_WATERMARK_SIZE 0x004FB0 +#define ACP_SW0_TX_DMA4_RINGBUFADDR 0x004FB4 +#define ACP_SW0_TX_DMA4_RINGBUFSIZE 0x004FB8 +#define ACP_SW0_TX_DMA4_FIFOADDR 0x004FBC +#define ACP_SW0_TX_DMA4_FIFOSIZE 0x004FC0 +#define ACP_SW0_TX_DMA4_BURST_SIZE 0x004FC4 +#define ACP_SW0_TX_DMA4_LINKPOSITIONCNTR 0x004FC8 +#define ACP_SW0_TX_DMA4_LINEARPOSITIONCNTR_HIGH 0x004FCC +#define ACP_SW0_TX_DMA4_LINEARPOSITIONCNTR_LOW 0x004FD0 +#define ACP_SW0_TX_DMA4_INTR_WATERMARK_SIZE 0x004FD4 +#define ACP_SW0_TX_DMA5_RINGBUFADDR 0x004FD8 +#define ACP_SW0_TX_DMA5_RINGBUFSIZE 0x004FDC +#define ACP_SW0_TX_DMA5_FIFOADDR 0x004FE0 +#define ACP_SW0_TX_DMA5_FIFOSIZE 0x004FE4 +#define ACP_SW0_TX_DMA5_BURST_SIZE 0x004FE8 +#define ACP_SW0_TX_DMA5_LINKPOSITIONCNTR 0x004FEC +#define ACP_SW0_TX_DMA5_LINEARPOSITIONCNTR_HIGH 0x004FF0 +#define ACP_SW0_TX_DMA5_LINEARPOSITIONCNTR_LOW 0x004FF4 +#define ACP_SW0_TX_DMA5_INTR_WATERMARK_SIZE 0x004FF8 +#define ACP_SW0_TX_DMA6_RINGBUFADDR 0x004FFC +#define ACP_SW0_TX_DMA6_RINGBUFSIZE 0x005000 +#define ACP_SW0_TX_DMA6_FIFOADDR 0x005004 +#define ACP_SW0_TX_DMA6_FIFOSIZE 0x005008 +#define ACP_SW0_TX_DMA6_BURST_SIZE 0x00500C +#define ACP_SW0_TX_DMA6_LINKPOSITIONCNTR 0x005010 +#define ACP_SW0_TX_DMA6_LINEARPOSITIONCNTR_HIGH 0x005014 +#define ACP_SW0_TX_DMA6_LINEARPOSITIONCNTR_LOW 0x005018 +#define ACP_SW0_TX_DMA6_INTR_WATERMARK_SIZE 0x00501C +#define ACP_SW0_TX_DMA7_RINGBUFADDR 0x005020 +#define ACP_SW0_TX_DMA7_RINGBUFSIZE 0x005024 +#define ACP_SW0_TX_DMA7_FIFOADDR 0x005028 +#define ACP_SW0_TX_DMA7_FIFOSIZE 0x00502C +#define ACP_SW0_TX_DMA7_BURST_SIZE 0x005030 +#define ACP_SW0_TX_DMA7_LINKPOSITIONCNTR 0x005034 +#define ACP_SW0_TX_DMA7_LINEARPOSITIONCNTR_HIGH 0x005038 +#define ACP_SW0_TX_DMA7_LINEARPOSITIONCNTR_LOW 0x00503C +#define ACP_SW0_TX_DMA7_INTR_WATERMARK_SIZE 0x005040 +#define ACP_SW0_RX_DMA0_POS_TRACK 0x005044 +#define ACP_SW0_RX_DMA0_POS 0x005048 +#define ACP_SW0_RX_DMA1_POS_TRACK 0x00504C +#define ACP_SW0_RX_DMA1_POS 0x005050 +#define ACP_SW0_RX_DMA2_POS_TRACK 0x005054 +#define ACP_SW0_RX_DMA2_POS 0x005058 +#define ACP_SW0_RX_DMA3_POS_TRACK 0x00505C +#define ACP_SW0_RX_DMA3_POS 0x005060 +#define ACP_SW0_RX_DMA4_POS_TRACK 0x005064 +#define ACP_SW0_RX_DMA4_POS 0x005068 +#define ACP_SW0_RX_DMA5_POS_TRACK 0x00506C +#define ACP_SW0_RX_DMA5_POS 0x005070 +#define ACP_SW0_RX_DMA6_POS_TRACK 0x005074 +#define ACP_SW0_RX_DMA6_POS 0x005078 +#define ACP_SW0_RX_DMA7_POS_TRACK 0x00507C +#define ACP_SW0_RX_DMA7_POS 0x005080 +#define ACP_SW0_TX_DMA0_POS_TRACK 0x005084 +#define ACP_SW0_TX_DMA0_POS 0x005088 +#define ACP_SW0_TX_DMA1_POS_TRACK 0x00508C +#define ACP_SW0_TX_DMA1_POS 0x005090 +#define ACP_SW0_TX_DMA2_POS_TRACK 0x005094 +#define ACP_SW0_TX_DMA2_POS 0x005098 +#define ACP_SW0_TX_DMA3_POS_TRACK 0x00509C +#define ACP_SW0_TX_DMA3_POS 0x0050A0 +#define ACP_SW0_TX_DMA4_POS_TRACK 0x0050A4 +#define ACP_SW0_TX_DMA4_POS 0x0050A8 +#define ACP_SW0_TX_DMA5_POS_TRACK 0x0050AC +#define ACP_SW0_TX_DMA5_POS 0x0050B0 +#define ACP_SW0_TX_DMA6_POS_TRACK 0x0050B4 +#define ACP_SW0_TX_DMA6_POS 0x0050B8 +#define ACP_SW0_TX_DMA7_POS_TRACK 0x0050BC +#define ACP_SW0_TX_DMA7_POS 0x0050C0 +#define ACP_SW0_FIFO_ERROR_REASON 0x0050C4 +#define ACP_SW0_FIFO_ERROR_INTR_MASK 0x0050C8 +#define ACP_SW0_ERROR_REASON1 0x0050CC +#define ACP_SW0_ERROR_INTR_MASK1 0x0050D0 +#define ACP_SW0_ERROR_REASON2 0x0050D4 +#define ACP_SW0_ERROR_INTR_MASK2 0x0050D8 + +#define ACP_SW0_CORB_BASE_ADDRESS 0x005100 +#define ACP_SW0_CORB_WRITE_POINTER 0x005104 +#define ACP_SW0_CORB_READ_POINTER 0x005108 +#define ACP_SW0_CORB_CONTROL 0x00510C +#define ACP_SW0_CORB_SIZE 0x005114 +#define ACP_SW0_RIRB_BASE_ADDRESS 0x005118 +#define ACP_SW0_RIRB_WRITE_POINTER 0x00511C +#define ACP_SW0_RIRB_RESPONSE_INTERRUPT_COUNT 0x005120 +#define ACP_SW0_RIRB_CONTROL 0x005124 +#define ACP_SW0_RIRB_SIZE 0x005128 +#define ACP_SW0_RIRB_FIFO_MIN_THDL 0x00512C +#define ACP_SW0_IMM_CMD_UPPER_WORD 0x005130 +#define ACP_SW0_IMM_CMD_LOWER_QWORD 0x005134 +#define ACP_SW0_IMM_RESP_UPPER_WORD 0x005138 +#define ACP_SW0_IMM_RESP_LOWER_QWORD 0x00513C +#define ACP_SW0_IMM_CMD_STS 0x005140 +#define ACP_SW0_BRA_BASE_ADDRESS 0x005144 +#define ACP_SW0_BRA_TRANSFER_SIZE 0x005148 +#define ACP_SW0_BRA_DMA_BUSY 0x00514C +#define ACP_SW0_BRA_RESP 0x005150 +#define ACP_SW0_BRA_RESP_FRAME_ADDR 0x005154 +#define ACP_SW0_BRA_CURRENT_TRANSFER_SIZE 0x005158 +#define ACP_SW0_STATE_CHANGE_STATUS_0TO7 0x00515C +#define ACP_SW0_STATE_CHANGE_STATUS_8TO11 0x005160 +#define ACP_SW0_STATE_CHANGE_STATUS_MASK_0TO7 0x005164 +#define ACP_SW0_STATE_CHANGE_STATUS_MASK_8TO11 0x005168 +#define ACP_SW0_CLK_FREQUENCY_CTRL_BANK0 0x00516C +#define ACP_SW0_CLK_FREQUENCY_CTRL_BANK1 0x005170 +#define ACP_SW0_ERROR_INTR_MASK 0x005174 +#define ACP_SW0_PHY_TEST_MODE_DATA_OFF 0x005178 +#define ACP_SW0_DATA_TO_PDM_EN 0x00517C + +#define ACP_SW0_EN 0x005200 +#define ACP_SW0_EN_STATUS 0x005204 +#define ACP_SW0_FRAMESIZE_BANK0 0x005208 +#define ACP_SW0_FRAMESIZE_BANK1 0x00520C +#define ACP_SW0_SSP_COUNTER 0x005210 +#define ACP_SW0_TX_STREAM0_EN 0x005214 +#define ACP_SW0_TX_STREAM1_EN 0x005218 +#define ACP_SW0_TX_STREAM2_EN 0x00521C +#define ACP_SW0_TX_STREAM3_EN 0x005220 +#define ACP_SW0_TX_STREAM4_EN 0x005224 +#define ACP_SW0_TX_STREAM5_EN 0x005228 +#define ACP_SW0_TX_STREAM6_EN 0x00522C +#define ACP_SW0_TX_STREAM7_EN 0x005230 +#define ACP_SW0_TX_STREAM0_EN_STATUS 0x005234 +#define ACP_SW0_TX_STREAM1_EN_STATUS 0x005238 +#define ACP_SW0_TX_STREAM2_EN_STATUS 0x00523C +#define ACP_SW0_TX_STREAM3_EN_STATUS 0x005240 +#define ACP_SW0_TX_STREAM4_EN_STATUS 0x005244 +#define ACP_SW0_TX_STREAM5_EN_STATUS 0x005248 +#define ACP_SW0_TX_STREAM6_EN_STATUS 0x00524C +#define ACP_SW0_TX_STREAM7_EN_STATUS 0x005250 +#define ACP_SW0_TX_DP0_FRAME_FORMAT 0x005254 +#define ACP_SW0_TX_DP1_FRAME_FORMAT 0x005258 +#define ACP_SW0_TX_DP2_FRAME_FORMAT 0x00525C +#define ACP_SW0_TX_DP3_FRAME_FORMAT 0x005260 +#define ACP_SW0_TX_DP4_FRAME_FORMAT 0x005264 +#define ACP_SW0_TX_DP5_FRAME_FORMAT 0x005268 +#define ACP_SW0_TX_DP6_FRAME_FORMAT 0x00526C +#define ACP_SW0_TX_DP7_FRAME_FORMAT 0x005270 +#define ACP_SW0_TX_DP0_0_SAMPLEINTERVAL_BANK0 0x005280 +#define ACP_SW0_TX_DP0_0_HCTRL_BANK0 0x005284 +#define ACP_SW0_TX_DP0_0_HCTRL_OFFSET_BANK0 0x005288 +#define ACP_SW0_TX_DP0_0_LANE_CTRL_BANK0 0x00528C +#define ACP_SW0_TX_DP0_0_CHANNEL_ENABLE_BANK0 0x005290 +#define ACP_SW0_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005294 +#define ACP_SW0_TX_DP0_0_SAMPLEINTERVAL_BANK1 0x005298 +#define ACP_SW0_TX_DP0_0_HCTRL_BANK1 0x00529C +#define ACP_SW0_TX_DP0_0_HCTRL_OFFSET_BANK1 0x0052A0 +#define ACP_SW0_TX_DP0_0_LANE_CTRL_BANK1 0x0052A4 +#define ACP_SW0_TX_DP0_0_CHANNEL_ENABLE_BANK1 0x0052A8 +#define ACP_SW0_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0052AC +#define ACP_SW0_TX_DP0_1_SAMPLEINTERVAL_BANK0 0x0052B0 +#define ACP_SW0_TX_DP0_1_HCTRL_BANK0 0x0052B4 +#define ACP_SW0_TX_DP0_1_HCTRL_OFFSET_BANK0 0x0052B8 +#define ACP_SW0_TX_DP0_1_LANE_CTRL_BANK0 0x0052BC +#define ACP_SW0_TX_DP0_1_CHANNEL_ENABLE_BANK0 0x0052C0 +#define ACP_SW0_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0052C4 +#define ACP_SW0_TX_DP0_1_SAMPLEINTERVAL_BANK1 0x0052C8 +#define ACP_SW0_TX_DP0_1_HCTRL_BANK1 0x0052CC +#define ACP_SW0_TX_DP0_1_HCTRL_OFFSET_BANK1 0x0052D0 +#define ACP_SW0_TX_DP0_1_LANE_CTRL_BANK1 0x0052D4 +#define ACP_SW0_TX_DP0_1_CHANNEL_ENABLE_BANK1 0x0052D8 +#define ACP_SW0_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0052DC +#define ACP_SW0_TX_DP0_2_SAMPLEINTERVAL_BANK0 0x0052E0 +#define ACP_SW0_TX_DP0_2_HCTRL_BANK0 0x0052E4 +#define ACP_SW0_TX_DP0_2_HCTRL_OFFSET_BANK0 0x0052E8 +#define ACP_SW0_TX_DP0_2_LANE_CTRL_BANK0 0x0052EC +#define ACP_SW0_TX_DP0_2_CHANNEL_ENABLE_BANK0 0x0052F0 +#define ACP_SW0_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0052F4 +#define ACP_SW0_TX_DP0_2_SAMPLEINTERVAL_BANK1 0x0052F8 +#define ACP_SW0_TX_DP0_2_HCTRL_BANK1 0x0052FC +#define ACP_SW0_TX_DP0_2_HCTRL_OFFSET_BANK1 0x005300 +#define ACP_SW0_TX_DP0_2_LANE_CTRL_BANK1 0x005304 +#define ACP_SW0_TX_DP0_2_CHANNEL_ENABLE_BANK1 0x005308 +#define ACP_SW0_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00530C +#define ACP_SW0_TX_DP0_3_SAMPLEINTERVAL_BANK0 0x005310 +#define ACP_SW0_TX_DP0_3_HCTRL_BANK0 0x005314 +#define ACP_SW0_TX_DP0_3_HCTRL_OFFSET_BANK0 0x005318 +#define ACP_SW0_TX_DP0_3_LANE_CTRL_BANK0 0x00531C +#define ACP_SW0_TX_DP0_3_CHANNEL_ENABLE_BANK0 0x005320 +#define ACP_SW0_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005324 +#define ACP_SW0_TX_DP0_3_SAMPLEINTERVAL_BANK1 0x005328 +#define ACP_SW0_TX_DP0_3_HCTRL_BANK1 0x00532C +#define ACP_SW0_TX_DP0_3_HCTRL_OFFSET_BANK1 0x005330 +#define ACP_SW0_TX_DP0_3_LANE_CTRL_BANK1 0x005334 +#define ACP_SW0_TX_DP0_3_CHANNEL_ENABLE_BANK1 0x005338 +#define ACP_SW0_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00533C +#define ACP_SW0_TX_DP1_SAMPLEINTERVAL_BANK0 0x005370 +#define ACP_SW0_TX_DP1_HCTRL_BANK0 0x005374 +#define ACP_SW0_TX_DP1_HCTRL_OFFSET_BANK0 0x005378 +#define ACP_SW0_TX_DP1_LANE_CTRL_BANK0 0x00537C +#define ACP_SW0_TX_DP1_CHANNEL_ENABLE_BANK0 0x005380 +#define ACP_SW0_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005384 +#define ACP_SW0_TX_DP1_SAMPLEINTERVAL_BANK1 0x005388 +#define ACP_SW0_TX_DP1_HCTRL_BANK1 0x00538C +#define ACP_SW0_TX_DP1_HCTRL_OFFSET_BANK1 0x005390 +#define ACP_SW0_TX_DP1_LANE_CTRL_BANK1 0x005394 +#define ACP_SW0_TX_DP1_CHANNEL_ENABLE_BANK1 0x005398 +#define ACP_SW0_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00539C +#define ACP_SW0_TX_DP2_SAMPLEINTERVAL_BANK0 0x0053A0 +#define ACP_SW0_TX_DP2_HCTRL_BANK0 0x0053A4 +#define ACP_SW0_TX_DP2_HCTRL_OFFSET_BANK0 0x0053A8 +#define ACP_SW0_TX_DP2_LANE_CTRL_BANK0 0x0053AC +#define ACP_SW0_TX_DP2_CHANNEL_ENABLE_BANK0 0x0053B0 +#define ACP_SW0_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0053B4 +#define ACP_SW0_TX_DP2_SAMPLEINTERVAL_BANK1 0x0053B8 +#define ACP_SW0_TX_DP2_HCTRL_BANK1 0x0053BC +#define ACP_SW0_TX_DP2_HCTRL_OFFSET_BANK1 0x0053C0 +#define ACP_SW0_TX_DP2_LANE_CTRL_BANK1 0x0053C4 +#define ACP_SW0_TX_DP2_CHANNEL_ENABLE_BANK1 0x0053C8 +#define ACP_SW0_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0053CC +#define ACP_SW0_TX_DP3_SAMPLEINTERVAL_BANK0 0x0053D0 +#define ACP_SW0_TX_DP3_HCTRL_BANK0 0x0053D4 +#define ACP_SW0_TX_DP3_HCTRL_OFFSET_BANK0 0x0053D8 +#define ACP_SW0_TX_DP3_LANE_CTRL_BANK0 0x0053DC +#define ACP_SW0_TX_DP3_CHANNEL_ENABLE_BANK0 0x0053E0 +#define ACP_SW0_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0053E4 +#define ACP_SW0_TX_DP3_SAMPLEINTERVAL_BANK1 0x0053E8 +#define ACP_SW0_TX_DP3_HCTRL_BANK1 0x0053EC +#define ACP_SW0_TX_DP3_HCTRL_OFFSET_BANK1 0x0053F0 +#define ACP_SW0_TX_DP3_LANE_CTRL_BANK1 0x0053F4 +#define ACP_SW0_TX_DP3_CHANNEL_ENABLE_BANK1 0x0053F8 +#define ACP_SW0_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0053FC +#define ACP_SW0_TX_DP4_SAMPLEINTERVAL_BANK0 0x005400 +#define ACP_SW0_TX_DP4_HCTRL_BANK0 0x005404 +#define ACP_SW0_TX_DP4_HCTRL_OFFSET_BANK0 0x005408 +#define ACP_SW0_TX_DP4_LANE_CTRL_BANK0 0x00540C +#define ACP_SW0_TX_DP4_CHANNEL_ENABLE_BANK0 0x005410 +#define ACP_SW0_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005414 +#define ACP_SW0_TX_DP4_SAMPLEINTERVAL_BANK1 0x005418 +#define ACP_SW0_TX_DP4_HCTRL_BANK1 0x00541C +#define ACP_SW0_TX_DP4_HCTRL_OFFSET_BANK1 0x005420 +#define ACP_SW0_TX_DP4_LANE_CTRL_BANK1 0x005424 +#define ACP_SW0_TX_DP4_CHANNEL_ENABLE_BANK1 0x005428 +#define ACP_SW0_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00542C +#define ACP_SW0_TX_DP5_SAMPLEINTERVAL_BANK0 0x005430 +#define ACP_SW0_TX_DP5_HCTRL_BANK0 0x005434 +#define ACP_SW0_TX_DP5_HCTRL_OFFSET_BANK0 0x005438 +#define ACP_SW0_TX_DP5_LANE_CTRL_BANK0 0x00543C +#define ACP_SW0_TX_DP5_CHANNEL_ENABLE_BANK0 0x005440 +#define ACP_SW0_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005444 +#define ACP_SW0_TX_DP5_SAMPLEINTERVAL_BANK1 0x005448 +#define ACP_SW0_TX_DP5_HCTRL_BANK1 0x00544C +#define ACP_SW0_TX_DP5_HCTRL_OFFSET_BANK1 0x005450 +#define ACP_SW0_TX_DP5_LANE_CTRL_BANK1 0x005454 +#define ACP_SW0_TX_DP5_CHANNEL_ENABLE_BANK1 0x005458 +#define ACP_SW0_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00545C +#define ACP_SW0_TX_DP6_SAMPLEINTERVAL_BANK0 0x005460 +#define ACP_SW0_TX_DP6_HCTRL_BANK0 0x005464 +#define ACP_SW0_TX_DP6_HCTRL_OFFSET_BANK0 0x005468 +#define ACP_SW0_TX_DP6_LANE_CTRL_BANK0 0x00546C +#define ACP_SW0_TX_DP6_CHANNEL_ENABLE_BANK0 0x005470 +#define ACP_SW0_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005474 +#define ACP_SW0_TX_DP6_SAMPLEINTERVAL_BANK1 0x005478 +#define ACP_SW0_TX_DP6_HCTRL_BANK1 0x00547C +#define ACP_SW0_TX_DP6_HCTRL_OFFSET_BANK1 0x005480 +#define ACP_SW0_TX_DP6_LANE_CTRL_BANK1 0x005484 +#define ACP_SW0_TX_DP6_CHANNEL_ENABLE_BANK1 0x005488 +#define ACP_SW0_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00548C +#define ACP_SW0_TX_DP7_SAMPLEINTERVAL_BANK0 0x005490 +#define ACP_SW0_TX_DP7_HCTRL_BANK0 0x005494 +#define ACP_SW0_TX_DP7_HCTRL_OFFSET_BANK0 0x005498 +#define ACP_SW0_TX_DP7_LANE_CTRL_BANK0 0x00549C +#define ACP_SW0_TX_DP7_CHANNEL_ENABLE_BANK0 0x0054A0 +#define ACP_SW0_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0054A4 +#define ACP_SW0_TX_DP7_SAMPLEINTERVAL_BANK1 0x0054A8 +#define ACP_SW0_TX_DP7_HCTRL_BANK1 0x0054AC +#define ACP_SW0_TX_DP7_HCTRL_OFFSET_BANK1 0x0054B0 +#define ACP_SW0_TX_DP7_LANE_CTRL_BANK1 0x0054B4 +#define ACP_SW0_TX_DP7_CHANNEL_ENABLE_BANK1 0x0054B8 +#define ACP_SW0_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0054BC +#define ACP_SW0_RX_STREAM0_EN 0x005514 +#define ACP_SW0_RX_STREAM1_EN 0x005518 +#define ACP_SW0_RX_STREAM2_EN 0x00551C +#define ACP_SW0_RX_STREAM3_EN 0x005520 +#define ACP_SW0_RX_STREAM4_EN 0x005524 +#define ACP_SW0_RX_STREAM5_EN 0x005528 +#define ACP_SW0_RX_STREAM6_EN 0x00552C +#define ACP_SW0_RX_STREAM7_EN 0x005530 +#define ACP_SW0_RX_STREAM0_EN_STATUS 0x005534 +#define ACP_SW0_RX_STREAM1_EN_STATUS 0x005538 +#define ACP_SW0_RX_STREAM2_EN_STATUS 0x00553C +#define ACP_SW0_RX_STREAM3_EN_STATUS 0x005540 +#define ACP_SW0_RX_STREAM4_EN_STATUS 0x005544 +#define ACP_SW0_RX_STREAM5_EN_STATUS 0x005548 +#define ACP_SW0_RX_STREAM6_EN_STATUS 0x00554C +#define ACP_SW0_RX_STREAM7_EN_STATUS 0x005550 +#define ACP_SW0_RX_DP0_FRAME_FORMAT 0x005554 +#define ACP_SW0_RX_DP1_FRAME_FORMAT 0x005558 +#define ACP_SW0_RX_DP2_FRAME_FORMAT 0x00555C +#define ACP_SW0_RX_DP3_FRAME_FORMAT 0x005560 +#define ACP_SW0_RX_DP4_FRAME_FORMAT 0x005564 +#define ACP_SW0_RX_DP5_FRAME_FORMAT 0x005568 +#define ACP_SW0_RX_DP6_FRAME_FORMAT 0x00556C +#define ACP_SW0_RX_DP7_FRAME_FORMAT 0x005570 +#define ACP_SW0_RX_DP0_0_SAMPLEINTERVAL_BANK0 0x005580 +#define ACP_SW0_RX_DP0_0_HCTRL_BANK0 0x005584 +#define ACP_SW0_RX_DP0_0_HCTRL_OFFSET_BANK0 0x005588 +#define ACP_SW0_RX_DP0_0_LANE_CTRL_BANK0 0x00558C +#define ACP_SW0_RX_DP0_0_CHANNEL_ENABLE_BANK0 0x005590 +#define ACP_SW0_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005594 +#define ACP_SW0_RX_DP0_0_SAMPLEINTERVAL_BANK1 0x005598 +#define ACP_SW0_RX_DP0_0_HCTRL_BANK1 0x00559C +#define ACP_SW0_RX_DP0_0_HCTRL_OFFSET_BANK1 0x0055A0 +#define ACP_SW0_RX_DP0_0_LANE_CTRL_BANK1 0x0055A4 +#define ACP_SW0_RX_DP0_0_CHANNEL_ENABLE_BANK1 0x0055A8 +#define ACP_SW0_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0055AC +#define ACP_SW0_RX_DP0_1_SAMPLEINTERVAL_BANK0 0x0055B0 +#define ACP_SW0_RX_DP0_1_HCTRL_BANK0 0x0055B4 +#define ACP_SW0_RX_DP0_1_HCTRL_OFFSET_BANK0 0x0055B8 +#define ACP_SW0_RX_DP0_1_LANE_CTRL_BANK0 0x0055BC +#define ACP_SW0_RX_DP0_1_CHANNEL_ENABLE_BANK0 0x0055C0 +#define ACP_SW0_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0055C4 +#define ACP_SW0_RX_DP0_1_SAMPLEINTERVAL_BANK1 0x0055C8 +#define ACP_SW0_RX_DP0_1_HCTRL_BANK1 0x0055CC +#define ACP_SW0_RX_DP0_1_HCTRL_OFFSET_BANK1 0x0055D0 +#define ACP_SW0_RX_DP0_1_LANE_CTRL_BANK1 0x0055D4 +#define ACP_SW0_RX_DP0_1_CHANNEL_ENABLE_BANK1 0x0055D8 +#define ACP_SW0_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0055DC +#define ACP_SW0_RX_DP0_2_SAMPLEINTERVAL_BANK0 0x0055E0 +#define ACP_SW0_RX_DP0_2_HCTRL_BANK0 0x0055E4 +#define ACP_SW0_RX_DP0_2_HCTRL_OFFSET_BANK0 0x0055E8 +#define ACP_SW0_RX_DP0_2_LANE_CTRL_BANK0 0x0055EC +#define ACP_SW0_RX_DP0_2_CHANNEL_ENABLE_BANK0 0x0055F0 +#define ACP_SW0_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0055F4 +#define ACP_SW0_RX_DP0_2_SAMPLEINTERVAL_BANK1 0x0055F8 +#define ACP_SW0_RX_DP0_2_HCTRL_BANK1 0x0055FC +#define ACP_SW0_RX_DP0_2_HCTRL_OFFSET_BANK1 0x005600 +#define ACP_SW0_RX_DP0_2_LANE_CTRL_BANK1 0x005604 +#define ACP_SW0_RX_DP0_2_CHANNEL_ENABLE_BANK1 0x005608 +#define ACP_SW0_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00560C +#define ACP_SW0_RX_DP0_3_SAMPLEINTERVAL_BANK0 0x005610 +#define ACP_SW0_RX_DP0_3_HCTRL_BANK0 0x005614 +#define ACP_SW0_RX_DP0_3_HCTRL_OFFSET_BANK0 0x005618 +#define ACP_SW0_RX_DP0_3_LANE_CTRL_BANK0 0x00561C +#define ACP_SW0_RX_DP0_3_CHANNEL_ENABLE_BANK0 0x005620 +#define ACP_SW0_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005624 +#define ACP_SW0_RX_DP0_3_SAMPLEINTERVAL_BANK1 0x005628 +#define ACP_SW0_RX_DP0_3_HCTRL_BANK1 0x00562C +#define ACP_SW0_RX_DP0_3_HCTRL_OFFSET_BANK1 0x005630 +#define ACP_SW0_RX_DP0_3_LANE_CTRL_BANK1 0x005634 +#define ACP_SW0_RX_DP0_3_CHANNEL_ENABLE_BANK1 0x005638 +#define ACP_SW0_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00563C +#define ACP_SW0_RX_DP1_SAMPLEINTERVAL_BANK0 0x005670 +#define ACP_SW0_RX_DP1_HCTRL_BANK0 0x005674 +#define ACP_SW0_RX_DP1_HCTRL_OFFSET_BANK0 0x005678 +#define ACP_SW0_RX_DP1_LANE_CTRL_BANK0 0x00567C +#define ACP_SW0_RX_DP1_CHANNEL_ENABLE_BANK0 0x005680 +#define ACP_SW0_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005684 +#define ACP_SW0_RX_DP1_SAMPLEINTERVAL_BANK1 0x005688 +#define ACP_SW0_RX_DP1_HCTRL_BANK1 0x00568C +#define ACP_SW0_RX_DP1_HCTRL_OFFSET_BANK1 0x005690 +#define ACP_SW0_RX_DP1_LANE_CTRL_BANK1 0x005694 +#define ACP_SW0_RX_DP1_CHANNEL_ENABLE_BANK1 0x005698 +#define ACP_SW0_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00569C +#define ACP_SW0_RX_DP2_SAMPLEINTERVAL_BANK0 0x0056A0 +#define ACP_SW0_RX_DP2_HCTRL_BANK0 0x0056A4 +#define ACP_SW0_RX_DP2_HCTRL_OFFSET_BANK0 0x0056A8 +#define ACP_SW0_RX_DP2_LANE_CTRL_BANK0 0x0056AC +#define ACP_SW0_RX_DP2_CHANNEL_ENABLE_BANK0 0x0056B0 +#define ACP_SW0_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0056B4 +#define ACP_SW0_RX_DP2_SAMPLEINTERVAL_BANK1 0x0056B8 +#define ACP_SW0_RX_DP2_HCTRL_BANK1 0x0056BC +#define ACP_SW0_RX_DP2_HCTRL_OFFSET_BANK1 0x0056C0 +#define ACP_SW0_RX_DP2_LANE_CTRL_BANK1 0x0056C4 +#define ACP_SW0_RX_DP2_CHANNEL_ENABLE_BANK1 0x0056C8 +#define ACP_SW0_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0056CC +#define ACP_SW0_RX_DP3_SAMPLEINTERVAL_BANK0 0x0056D0 +#define ACP_SW0_RX_DP3_HCTRL_BANK0 0x0056D4 +#define ACP_SW0_RX_DP3_HCTRL_OFFSET_BANK0 0x0056D8 +#define ACP_SW0_RX_DP3_LANE_CTRL_BANK0 0x0056DC +#define ACP_SW0_RX_DP3_CHANNEL_ENABLE_BANK0 0x0056E0 +#define ACP_SW0_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0056E4 +#define ACP_SW0_RX_DP3_SAMPLEINTERVAL_BANK1 0x0056E8 +#define ACP_SW0_RX_DP3_HCTRL_BANK1 0x0056EC +#define ACP_SW0_RX_DP3_HCTRL_OFFSET_BANK1 0x0056F0 +#define ACP_SW0_RX_DP3_LANE_CTRL_BANK1 0x0056F4 +#define ACP_SW0_RX_DP3_CHANNEL_ENABLE_BANK1 0x0056F8 +#define ACP_SW0_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0056FC +#define ACP_SW0_RX_DP4_SAMPLEINTERVAL_BANK0 0x005700 +#define ACP_SW0_RX_DP4_HCTRL_BANK0 0x005704 +#define ACP_SW0_RX_DP4_HCTRL_OFFSET_BANK0 0x005708 +#define ACP_SW0_RX_DP4_LANE_CTRL_BANK0 0x00570C +#define ACP_SW0_RX_DP4_CHANNEL_ENABLE_BANK0 0x005710 +#define ACP_SW0_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005714 +#define ACP_SW0_RX_DP4_SAMPLEINTERVAL_BANK1 0x005718 +#define ACP_SW0_RX_DP4_HCTRL_BANK1 0x00571C +#define ACP_SW0_RX_DP4_HCTRL_OFFSET_BANK1 0x005720 +#define ACP_SW0_RX_DP4_LANE_CTRL_BANK1 0x005724 +#define ACP_SW0_RX_DP4_CHANNEL_ENABLE_BANK1 0x005728 +#define ACP_SW0_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00572C +#define ACP_SW0_RX_DP5_SAMPLEINTERVAL_BANK0 0x005730 +#define ACP_SW0_RX_DP5_HCTRL_BANK0 0x005734 +#define ACP_SW0_RX_DP5_HCTRL_OFFSET_BANK0 0x005738 +#define ACP_SW0_RX_DP5_LANE_CTRL_BANK0 0x00573C +#define ACP_SW0_RX_DP5_CHANNEL_ENABLE_BANK0 0x005740 +#define ACP_SW0_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005744 +#define ACP_SW0_RX_DP5_SAMPLEINTERVAL_BANK1 0x005748 +#define ACP_SW0_RX_DP5_HCTRL_BANK1 0x00574C +#define ACP_SW0_RX_DP5_HCTRL_OFFSET_BANK1 0x005750 +#define ACP_SW0_RX_DP5_LANE_CTRL_BANK1 0x005754 +#define ACP_SW0_RX_DP5_CHANNEL_ENABLE_BANK1 0x005758 +#define ACP_SW0_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00575C +#define ACP_SW0_RX_DP6_SAMPLEINTERVAL_BANK0 0x005760 +#define ACP_SW0_RX_DP6_HCTRL_BANK0 0x005764 +#define ACP_SW0_RX_DP6_HCTRL_OFFSET_BANK0 0x005768 +#define ACP_SW0_RX_DP6_LANE_CTRL_BANK0 0x00576C +#define ACP_SW0_RX_DP6_CHANNEL_ENABLE_BANK0 0x005770 +#define ACP_SW0_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x005774 +#define ACP_SW0_RX_DP6_SAMPLEINTERVAL_BANK1 0x005778 +#define ACP_SW0_RX_DP6_HCTRL_BANK1 0x00577C +#define ACP_SW0_RX_DP6_HCTRL_OFFSET_BANK1 0x005780 +#define ACP_SW0_RX_DP6_LANE_CTRL_BANK1 0x005784 +#define ACP_SW0_RX_DP6_CHANNEL_ENABLE_BANK1 0x005788 +#define ACP_SW0_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00578C +#define ACP_SW0_RX_DP7_SAMPLEINTERVAL_BANK0 0x005790 +#define ACP_SW0_RX_DP7_HCTRL_BANK0 0x005794 +#define ACP_SW0_RX_DP7_HCTRL_OFFSET_BANK0 0x005798 +#define ACP_SW0_RX_DP7_LANE_CTRL_BANK0 0x00579C +#define ACP_SW0_RX_DP7_CHANNEL_ENABLE_BANK0 0x0057A0 +#define ACP_SW0_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0057A4 +#define ACP_SW0_RX_DP7_SAMPLEINTERVAL_BANK1 0x0057A8 +#define ACP_SW0_RX_DP7_HCTRL_BANK1 0x0057AC +#define ACP_SW0_RX_DP7_HCTRL_OFFSET_BANK1 0x0057B0 +#define ACP_SW0_RX_DP7_LANE_CTRL_BANK1 0x0057B4 +#define ACP_SW0_RX_DP7_CHANNEL_ENABLE_BANK1 0x0057B8 +#define ACP_SW0_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0057BC +#define ACP_SW0_BPT_PORT_EN 0x0057C0 +#define ACP_SW0_BPT_PORT_EN_STATUS 0x0057C4 +#define ACP_SW0_BPT_PORT_FRAME_FORMAT 0x0057C8 +#define ACP_SW0_BPT_PORT_SAMPLEINTERVAL_BANK0 0x0057CC +#define ACP_SW0_BPT_PORT_HCTRL_BANK0 0x0057D0 +#define ACP_SW0_BPT_PORT_OFFSET_BANK0 0x0057D4 +#define ACP_SW0_BPT_PORT_LANE_SELECT_BANK0 0x0057D8 +#define ACP_SW0_BPT_PORT_CHANNEL_ENABLE_BANK0 0x0057DC +#define ACP_SW0_BPT_PORT_SAMPLEINTERVAL_BANK1 0x0057E0 +#define ACP_SW0_BPT_PORT_HCTRL_BANK1 0x0057E4 +#define ACP_SW0_BPT_PORT_OFFSET_BANK1 0x0057E8 +#define ACP_SW0_BPT_PORT_LANE_SELECT_BANK1 0x0057EC +#define ACP_SW0_BPT_PORT_CHANNEL_ENABLE_BANK1 0x0057F0 +#define ACP_SW0_BPT_PORT_FIRST_BYTE_ADDR 0x0057F4 +#define ACP_SW0_CLK_RESUME_CTRL 0x0057F8 +#define ACP_SW0_CLK_RESUME_DELAY_CNTR 0x0057FC +#define ACP_SW0_BUS_RESET_CTRL 0x005800 +#define ACP_SW0_PRBS_ERR_STATUS 0x005804 +#define ACP_SW0_WALLCLK_MISC 0x005808 +#define ACP_SW0_WALL_CLK_COUNTER 0x00580C +#define ACP_SW0_PING_STATUS_REGISTER_LOW 0x005810 +#define ACP_SW0_PING_STATUS_REGISTER_HIGH 0x005814 +#define ACP_SW0_PING_STATUS_CURRENT_BANK_SEL 0x005818 +#define ACP_SW0_TZD_CHANGE 0x00581C +#define ACP_SW0_WALLCLK_INTR_CNTL 0x005820 + +#define ACP_SW1_GLOBAL_CAPABILITIES 0x006E00 +#define ACP_SW1_RX_DMA0_RINGBUFADDR 0x006E04 +#define ACP_SW1_RX_DMA0_RINGBUFSIZE 0x006E08 +#define ACP_SW1_RX_DMA0_FIFOADDR 0x006E0C +#define ACP_SW1_RX_DMA0_FIFOSIZE 0x006E10 +#define ACP_SW1_RX_DMA0_BURST_SIZE 0x006E14 +#define ACP_SW1_RX_DMA0_LINKPOSITIONCNTR 0x006E18 +#define ACP_SW1_RX_DMA0_LINEARPOSITIONCNTR_HIGH 0x006E1C +#define ACP_SW1_RX_DMA0_LINEARPOSITIONCNTR_LOW 0x006E20 +#define ACP_SW1_RX_DMA0_INTR_WATERMARK_SIZE 0x006E24 +#define ACP_SW1_RX_DMA1_RINGBUFADDR 0x006E28 +#define ACP_SW1_RX_DMA1_RINGBUFSIZE 0x006E2C +#define ACP_SW1_RX_DMA1_FIFOADDR 0x006E30 +#define ACP_SW1_RX_DMA1_FIFOSIZE 0x006E34 +#define ACP_SW1_RX_DMA1_BURST_SIZE 0x006E38 +#define ACP_SW1_RX_DMA1_LINKPOSITIONCNTR 0x006E3C +#define ACP_SW1_RX_DMA1_LINEARPOSITIONCNTR_HIGH 0x006E40 +#define ACP_SW1_RX_DMA1_LINEARPOSITIONCNTR_LOW 0x006E44 +#define ACP_SW1_RX_DMA1_INTR_WATERMARK_SIZE 0x006E48 +#define ACP_SW1_RX_DMA2_RINGBUFADDR 0x006E4C +#define ACP_SW1_RX_DMA2_RINGBUFSIZE 0x006E50 +#define ACP_SW1_RX_DMA2_FIFOADDR 0x006E54 +#define ACP_SW1_RX_DMA2_FIFOSIZE 0x006E58 +#define ACP_SW1_RX_DMA2_BURST_SIZE 0x006E5C +#define ACP_SW1_RX_DMA2_LINKPOSITIONCNTR 0x006E60 +#define ACP_SW1_RX_DMA2_LINEARPOSITIONCNTR_HIGH 0x006E64 +#define ACP_SW1_RX_DMA2_LINEARPOSITIONCNTR_LOW 0x006E68 +#define ACP_SW1_RX_DMA2_INTR_WATERMARK_SIZE 0x006E6C +#define ACP_SW1_RX_DMA3_RINGBUFADDR 0x006E70 +#define ACP_SW1_RX_DMA3_RINGBUFSIZE 0x006E74 +#define ACP_SW1_RX_DMA3_FIFOADDR 0x006E78 +#define ACP_SW1_RX_DMA3_FIFOSIZE 0x006E7C +#define ACP_SW1_RX_DMA3_BURST_SIZE 0x006E80 +#define ACP_SW1_RX_DMA3_LINKPOSITIONCNTR 0x006E84 +#define ACP_SW1_RX_DMA3_LINEARPOSITIONCNTR_HIGH 0x006E88 +#define ACP_SW1_RX_DMA3_LINEARPOSITIONCNTR_LOW 0x006E8C +#define ACP_SW1_RX_DMA3_INTR_WATERMARK_SIZE 0x006E90 +#define ACP_SW1_RX_DMA4_RINGBUFADDR 0x006E94 +#define ACP_SW1_RX_DMA4_RINGBUFSIZE 0x006E98 +#define ACP_SW1_RX_DMA4_FIFOADDR 0x006E9C +#define ACP_SW1_RX_DMA4_FIFOSIZE 0x006EA0 +#define ACP_SW1_RX_DMA4_BURST_SIZE 0x006EA4 +#define ACP_SW1_RX_DMA4_LINKPOSITIONCNTR 0x006EA8 +#define ACP_SW1_RX_DMA4_LINEARPOSITIONCNTR_HIGH 0x006EAC +#define ACP_SW1_RX_DMA4_LINEARPOSITIONCNTR_LOW 0x006EB0 +#define ACP_SW1_RX_DMA4_INTR_WATERMARK_SIZE 0x006EB4 +#define ACP_SW1_RX_DMA5_RINGBUFADDR 0x006EB8 +#define ACP_SW1_RX_DMA5_RINGBUFSIZE 0x006EBC +#define ACP_SW1_RX_DMA5_FIFOADDR 0x006EC0 +#define ACP_SW1_RX_DMA5_FIFOSIZE 0x006EC4 +#define ACP_SW1_RX_DMA5_BURST_SIZE 0x006EC8 +#define ACP_SW1_RX_DMA5_LINKPOSITIONCNTR 0x006ECC +#define ACP_SW1_RX_DMA5_LINEARPOSITIONCNTR_HIGH 0x006ED0 +#define ACP_SW1_RX_DMA5_LINEARPOSITIONCNTR_LOW 0x006ED4 +#define ACP_SW1_RX_DMA5_INTR_WATERMARK_SIZE 0x006ED8 +#define ACP_SW1_RX_DMA6_RINGBUFADDR 0x006EDC +#define ACP_SW1_RX_DMA6_RINGBUFSIZE 0x006EE0 +#define ACP_SW1_RX_DMA6_FIFOADDR 0x006EE4 +#define ACP_SW1_RX_DMA6_FIFOSIZE 0x006EE8 +#define ACP_SW1_RX_DMA6_BURST_SIZE 0x006EEC +#define ACP_SW1_RX_DMA6_LINKPOSITIONCNTR 0x006EF0 +#define ACP_SW1_RX_DMA6_LINEARPOSITIONCNTR_HIGH 0x006EF4 +#define ACP_SW1_RX_DMA6_LINEARPOSITIONCNTR_LOW 0x006EF8 +#define ACP_SW1_RX_DMA6_INTR_WATERMARK_SIZE 0x006EFC +#define ACP_SW1_RX_DMA7_RINGBUFADDR 0x006F00 +#define ACP_SW1_RX_DMA7_RINGBUFSIZE 0x006F04 +#define ACP_SW1_RX_DMA7_FIFOADDR 0x006F08 +#define ACP_SW1_RX_DMA7_FIFOSIZE 0x006F0C +#define ACP_SW1_RX_DMA7_BURST_SIZE 0x006F10 +#define ACP_SW1_RX_DMA7_LINKPOSITIONCNTR 0x006F14 +#define ACP_SW1_RX_DMA7_LINEARPOSITIONCNTR_HIGH 0x006F18 +#define ACP_SW1_RX_DMA7_LINEARPOSITIONCNTR_LOW 0x006F1C +#define ACP_SW1_RX_DMA7_INTR_WATERMARK_SIZE 0x006F20 +#define ACP_SW1_TX_DMA0_RINGBUFADDR 0x006F24 +#define ACP_SW1_TX_DMA0_RINGBUFSIZE 0x006F28 +#define ACP_SW1_TX_DMA0_FIFOADDR 0x006F2C +#define ACP_SW1_TX_DMA0_FIFOSIZE 0x006F30 +#define ACP_SW1_TX_DMA0_BURST_SIZE 0x006F34 +#define ACP_SW1_TX_DMA0_LINKPOSITIONCNTR 0x006F38 +#define ACP_SW1_TX_DMA0_LINEARPOSITIONCNTR_HIGH 0x006F3C +#define ACP_SW1_TX_DMA0_LINEARPOSITIONCNTR_LOW 0x006F40 +#define ACP_SW1_TX_DMA0_INTR_WATERMARK_SIZE 0x006F44 +#define ACP_SW1_TX_DMA1_RINGBUFADDR 0x006F48 +#define ACP_SW1_TX_DMA1_RINGBUFSIZE 0x006F4C +#define ACP_SW1_TX_DMA1_FIFOADDR 0x006F50 +#define ACP_SW1_TX_DMA1_FIFOSIZE 0x006F54 +#define ACP_SW1_TX_DMA1_BURST_SIZE 0x006F58 +#define ACP_SW1_TX_DMA1_LINKPOSITIONCNTR 0x006F5C +#define ACP_SW1_TX_DMA1_LINEARPOSITIONCNTR_HIGH 0x006F60 +#define ACP_SW1_TX_DMA1_LINEARPOSITIONCNTR_LOW 0x006F64 +#define ACP_SW1_TX_DMA1_INTR_WATERMARK_SIZE 0x006F68 +#define ACP_SW1_TX_DMA2_RINGBUFADDR 0x006F6C +#define ACP_SW1_TX_DMA2_RINGBUFSIZE 0x006F70 +#define ACP_SW1_TX_DMA2_FIFOADDR 0x006F74 +#define ACP_SW1_TX_DMA2_FIFOSIZE 0x006F78 +#define ACP_SW1_TX_DMA2_BURST_SIZE 0x006F7C +#define ACP_SW1_TX_DMA2_LINKPOSITIONCNTR 0x006F80 +#define ACP_SW1_TX_DMA2_LINEARPOSITIONCNTR_HIGH 0x006F84 +#define ACP_SW1_TX_DMA2_LINEARPOSITIONCNTR_LOW 0x006F88 +#define ACP_SW1_TX_DMA2_INTR_WATERMARK_SIZE 0x006F8C +#define ACP_SW1_TX_DMA3_RINGBUFADDR 0x006F90 +#define ACP_SW1_TX_DMA3_RINGBUFSIZE 0x006F94 +#define ACP_SW1_TX_DMA3_FIFOADDR 0x006F98 +#define ACP_SW1_TX_DMA3_FIFOSIZE 0x006F9C +#define ACP_SW1_TX_DMA3_BURST_SIZE 0x006FA0 +#define ACP_SW1_TX_DMA3_LINKPOSITIONCNTR 0x006FA4 +#define ACP_SW1_TX_DMA3_LINEARPOSITIONCNTR_HIGH 0x006FA8 +#define ACP_SW1_TX_DMA3_LINEARPOSITIONCNTR_LOW 0x006FAC +#define ACP_SW1_TX_DMA3_INTR_WATERMARK_SIZE 0x006FB0 +#define ACP_SW1_TX_DMA4_RINGBUFADDR 0x006FB4 +#define ACP_SW1_TX_DMA4_RINGBUFSIZE 0x006FB8 +#define ACP_SW1_TX_DMA4_FIFOADDR 0x006FBC +#define ACP_SW1_TX_DMA4_FIFOSIZE 0x006FC0 +#define ACP_SW1_TX_DMA4_BURST_SIZE 0x006FC4 +#define ACP_SW1_TX_DMA4_LINKPOSITIONCNTR 0x006FC8 +#define ACP_SW1_TX_DMA4_LINEARPOSITIONCNTR_HIGH 0x006FCC +#define ACP_SW1_TX_DMA4_LINEARPOSITIONCNTR_LOW 0x006FD0 +#define ACP_SW1_TX_DMA4_INTR_WATERMARK_SIZE 0x006FD4 +#define ACP_SW1_TX_DMA5_RINGBUFADDR 0x006FD8 +#define ACP_SW1_TX_DMA5_RINGBUFSIZE 0x006FDC +#define ACP_SW1_TX_DMA5_FIFOADDR 0x006FE0 +#define ACP_SW1_TX_DMA5_FIFOSIZE 0x006FE4 +#define ACP_SW1_TX_DMA5_BURST_SIZE 0x006FE8 +#define ACP_SW1_TX_DMA5_LINKPOSITIONCNTR 0x006FEC +#define ACP_SW1_TX_DMA5_LINEARPOSITIONCNTR_HIGH 0x006FF0 +#define ACP_SW1_TX_DMA5_LINEARPOSITIONCNTR_LOW 0x006FF4 +#define ACP_SW1_TX_DMA5_INTR_WATERMARK_SIZE 0x006FF8 +#define ACP_SW1_TX_DMA6_RINGBUFADDR 0x006FFC +#define ACP_SW1_TX_DMA6_RINGBUFSIZE 0x007000 +#define ACP_SW1_TX_DMA6_FIFOADDR 0x007004 +#define ACP_SW1_TX_DMA6_FIFOSIZE 0x007008 +#define ACP_SW1_TX_DMA6_BURST_SIZE 0x00700C +#define ACP_SW1_TX_DMA6_LINKPOSITIONCNTR 0x007010 +#define ACP_SW1_TX_DMA6_LINEARPOSITIONCNTR_HIGH 0x007014 +#define ACP_SW1_TX_DMA6_LINEARPOSITIONCNTR_LOW 0x007018 +#define ACP_SW1_TX_DMA6_INTR_WATERMARK_SIZE 0x00701C +#define ACP_SW1_TX_DMA7_RINGBUFADDR 0x007020 +#define ACP_SW1_TX_DMA7_RINGBUFSIZE 0x007024 +#define ACP_SW1_TX_DMA7_FIFOADDR 0x007028 +#define ACP_SW1_TX_DMA7_FIFOSIZE 0x00702C +#define ACP_SW1_TX_DMA7_BURST_SIZE 0x007030 +#define ACP_SW1_TX_DMA7_LINKPOSITIONCNTR 0x007034 +#define ACP_SW1_TX_DMA7_LINEARPOSITIONCNTR_HIGH 0x007038 +#define ACP_SW1_TX_DMA7_LINEARPOSITIONCNTR_LOW 0x00703C +#define ACP_SW1_TX_DMA7_INTR_WATERMARK_SIZE 0x007040 +#define ACP_SW1_RX_DMA0_POS_TRACK 0x007044 +#define ACP_SW1_RX_DMA0_POS 0x007048 +#define ACP_SW1_RX_DMA1_POS_TRACK 0x00704C +#define ACP_SW1_RX_DMA1_POS 0x007050 +#define ACP_SW1_RX_DMA2_POS_TRACK 0x007054 +#define ACP_SW1_RX_DMA2_POS 0x007058 +#define ACP_SW1_RX_DMA3_POS_TRACK 0x00705C +#define ACP_SW1_RX_DMA3_POS 0x007060 +#define ACP_SW1_RX_DMA4_POS_TRACK 0x007064 +#define ACP_SW1_RX_DMA4_POS 0x007068 +#define ACP_SW1_RX_DMA5_POS_TRACK 0x00706C +#define ACP_SW1_RX_DMA5_POS 0x007070 +#define ACP_SW1_RX_DMA6_POS_TRACK 0x007074 +#define ACP_SW1_RX_DMA6_POS 0x007078 +#define ACP_SW1_RX_DMA7_POS_TRACK 0x00707C +#define ACP_SW1_RX_DMA7_POS 0x007080 +#define ACP_SW1_TX_DMA0_POS_TRACK 0x007084 +#define ACP_SW1_TX_DMA0_POS 0x007088 +#define ACP_SW1_TX_DMA1_POS_TRACK 0x00708C +#define ACP_SW1_TX_DMA1_POS 0x007090 +#define ACP_SW1_TX_DMA2_POS_TRACK 0x007094 +#define ACP_SW1_TX_DMA2_POS 0x007098 +#define ACP_SW1_TX_DMA3_POS_TRACK 0x00709C +#define ACP_SW1_TX_DMA3_POS 0x0070A0 +#define ACP_SW1_TX_DMA4_POS_TRACK 0x0070A4 +#define ACP_SW1_TX_DMA4_POS 0x0070A8 +#define ACP_SW1_TX_DMA5_POS_TRACK 0x0070AC +#define ACP_SW1_TX_DMA5_POS 0x0070B0 +#define ACP_SW1_TX_DMA6_POS_TRACK 0x0070B4 +#define ACP_SW1_TX_DMA6_POS 0x0070B8 +#define ACP_SW1_TX_DMA7_POS_TRACK 0x0070BC +#define ACP_SW1_TX_DMA7_POS 0x0070C0 +#define ACP_SW1_FIFO_ERROR_REASON 0x0070C4 +#define ACP_SW1_FIFO_ERROR_INTR_MASK 0x0070C8 +#define ACP_SW1_ERROR_REASON1 0x0070CC +#define ACP_SW1_ERROR_INTR_MASK1 0x0070D0 +#define ACP_SW1_ERROR_REASON2 0x0070D4 +#define ACP_SW1_ERROR_INTR_MASK2 0x0070D8 + +#define ACP_SW1_CORB_BASE_ADDRESS 0x007100 +#define ACP_SW1_CORB_WRITE_POINTER 0x007104 +#define ACP_SW1_CORB_READ_POINTER 0x007108 +#define ACP_SW1_CORB_CONTROL 0x00710C +#define ACP_SW1_CORB_SIZE 0x007114 +#define ACP_SW1_RIRB_BASE_ADDRESS 0x007118 +#define ACP_SW1_RIRB_WRITE_POINTER 0x00711C +#define ACP_SW1_RIRB_RESPONSE_INTERRUPT_COUNT 0x007120 +#define ACP_SW1_RIRB_CONTROL 0x007124 +#define ACP_SW1_RIRB_SIZE 0x007128 +#define ACP_SW1_RIRB_FIFO_MIN_THDL 0x00712C +#define ACP_SW1_IMM_CMD_UPPER_WORD 0x007130 +#define ACP_SW1_IMM_CMD_LOWER_QWORD 0x007134 +#define ACP_SW1_IMM_RESP_UPPER_WORD 0x007138 +#define ACP_SW1_IMM_RESP_LOWER_QWORD 0x00713C +#define ACP_SW1_IMM_CMD_STS 0x007140 +#define ACP_SW1_BRA_BASE_ADDRESS 0x007144 +#define ACP_SW1_BRA_TRANSFER_SIZE 0x007148 +#define ACP_SW1_BRA_DMA_BUSY 0x00714C +#define ACP_SW1_BRA_RESP 0x007150 +#define ACP_SW1_BRA_RESP_FRAME_ADDR 0x007154 +#define ACP_SW1_BRA_CURRENT_TRANSFER_SIZE 0x007158 +#define ACP_SW1_STATE_CHANGE_STATUS_0TO7 0x00715C +#define ACP_SW1_STATE_CHANGE_STATUS_8TO11 0x007160 +#define ACP_SW1_STATE_CHANGE_STATUS_MASK_0TO7 0x007164 +#define ACP_SW1_STATE_CHANGE_STATUS_MASK_8TO11 0x007168 +#define ACP_SW1_CLK_FREQUENCY_CTRL_BANK0 0x00716C +#define ACP_SW1_CLK_FREQUENCY_CTRL_BANK1 0x007170 +#define ACP_SW1_ERROR_INTR_MASK 0x007174 +#define ACP_SW1_PHY_TEST_MODE_DATA_OFF 0x007178 +#define ACP_SW1_DATA_TO_PDM_EN 0x00717C + +#define ACP_SW1_EN 0x007200 +#define ACP_SW1_EN_STATUS 0x007204 +#define ACP_SW1_FRAMESIZE_BANK0 0x007208 +#define ACP_SW1_FRAMESIZE_BANK1 0x00720C +#define ACP_SW1_SSP_COUNTER 0x007210 +#define ACP_SW1_TX_STREAM0_EN 0x007214 +#define ACP_SW1_TX_STREAM1_EN 0x007218 +#define ACP_SW1_TX_STREAM2_EN 0x00721C +#define ACP_SW1_TX_STREAM3_EN 0x007220 +#define ACP_SW1_TX_STREAM4_EN 0x007224 +#define ACP_SW1_TX_STREAM5_EN 0x007228 +#define ACP_SW1_TX_STREAM6_EN 0x00722C +#define ACP_SW1_TX_STREAM7_EN 0x007230 +#define ACP_SW1_TX_STREAM0_EN_STATUS 0x007234 +#define ACP_SW1_TX_STREAM1_EN_STATUS 0x007238 +#define ACP_SW1_TX_STREAM2_EN_STATUS 0x00723C +#define ACP_SW1_TX_STREAM3_EN_STATUS 0x007240 +#define ACP_SW1_TX_STREAM4_EN_STATUS 0x007244 +#define ACP_SW1_TX_STREAM5_EN_STATUS 0x007248 +#define ACP_SW1_TX_STREAM6_EN_STATUS 0x00724C +#define ACP_SW1_TX_STREAM7_EN_STATUS 0x007250 +#define ACP_SW1_TX_DP0_FRAME_FORMAT 0x007254 +#define ACP_SW1_TX_DP1_FRAME_FORMAT 0x007258 +#define ACP_SW1_TX_DP2_FRAME_FORMAT 0x00725C +#define ACP_SW1_TX_DP3_FRAME_FORMAT 0x007260 +#define ACP_SW1_TX_DP4_FRAME_FORMAT 0x007264 +#define ACP_SW1_TX_DP5_FRAME_FORMAT 0x007268 +#define ACP_SW1_TX_DP6_FRAME_FORMAT 0x00726C +#define ACP_SW1_TX_DP7_FRAME_FORMAT 0x007270 +#define ACP_SW1_TX_DP0_0_SAMPLEINTERVAL_BANK0 0x007280 +#define ACP_SW1_TX_DP0_0_HCTRL_BANK0 0x007284 +#define ACP_SW1_TX_DP0_0_HCTRL_OFFSET_BANK0 0x007288 +#define ACP_SW1_TX_DP0_0_LANE_CTRL_BANK0 0x00728C +#define ACP_SW1_TX_DP0_0_CHANNEL_ENABLE_BANK0 0x007290 +#define ACP_SW1_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007294 +#define ACP_SW1_TX_DP0_0_SAMPLEINTERVAL_BANK1 0x007298 +#define ACP_SW1_TX_DP0_0_HCTRL_BANK1 0x00729C +#define ACP_SW1_TX_DP0_0_HCTRL_OFFSET_BANK1 0x0072A0 +#define ACP_SW1_TX_DP0_0_LANE_CTRL_BANK1 0x0072A4 +#define ACP_SW1_TX_DP0_0_CHANNEL_ENABLE_BANK1 0x0072A8 +#define ACP_SW1_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0072AC +#define ACP_SW1_TX_DP0_1_SAMPLEINTERVAL_BANK0 0x0072B0 +#define ACP_SW1_TX_DP0_1_HCTRL_BANK0 0x0072B4 +#define ACP_SW1_TX_DP0_1_HCTRL_OFFSET_BANK0 0x0072B8 +#define ACP_SW1_TX_DP0_1_LANE_CTRL_BANK0 0x0072BC +#define ACP_SW1_TX_DP0_1_CHANNEL_ENABLE_BANK0 0x0072C0 +#define ACP_SW1_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0072C4 +#define ACP_SW1_TX_DP0_1_SAMPLEINTERVAL_BANK1 0x0072C8 +#define ACP_SW1_TX_DP0_1_HCTRL_BANK1 0x0072CC +#define ACP_SW1_TX_DP0_1_HCTRL_OFFSET_BANK1 0x0072D0 +#define ACP_SW1_TX_DP0_1_LANE_CTRL_BANK1 0x0072D4 +#define ACP_SW1_TX_DP0_1_CHANNEL_ENABLE_BANK1 0x0072D8 +#define ACP_SW1_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0072DC +#define ACP_SW1_TX_DP0_2_SAMPLEINTERVAL_BANK0 0x0072E0 +#define ACP_SW1_TX_DP0_2_HCTRL_BANK0 0x0072E4 +#define ACP_SW1_TX_DP0_2_HCTRL_OFFSET_BANK0 0x0072E8 +#define ACP_SW1_TX_DP0_2_LANE_CTRL_BANK0 0x0072EC +#define ACP_SW1_TX_DP0_2_CHANNEL_ENABLE_BANK0 0x0072F0 +#define ACP_SW1_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0072F4 +#define ACP_SW1_TX_DP0_2_SAMPLEINTERVAL_BANK1 0x0072F8 +#define ACP_SW1_TX_DP0_2_HCTRL_BANK1 0x0072FC +#define ACP_SW1_TX_DP0_2_HCTRL_OFFSET_BANK1 0x007300 +#define ACP_SW1_TX_DP0_2_LANE_CTRL_BANK1 0x007304 +#define ACP_SW1_TX_DP0_2_CHANNEL_ENABLE_BANK1 0x007308 +#define ACP_SW1_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00730C +#define ACP_SW1_TX_DP0_3_SAMPLEINTERVAL_BANK0 0x007310 +#define ACP_SW1_TX_DP0_3_HCTRL_BANK0 0x007314 +#define ACP_SW1_TX_DP0_3_HCTRL_OFFSET_BANK0 0x007318 +#define ACP_SW1_TX_DP0_3_LANE_CTRL_BANK0 0x00731C +#define ACP_SW1_TX_DP0_3_CHANNEL_ENABLE_BANK0 0x007320 +#define ACP_SW1_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007324 +#define ACP_SW1_TX_DP0_3_SAMPLEINTERVAL_BANK1 0x007328 +#define ACP_SW1_TX_DP0_3_HCTRL_BANK1 0x00732C +#define ACP_SW1_TX_DP0_3_HCTRL_OFFSET_BANK1 0x007330 +#define ACP_SW1_TX_DP0_3_LANE_CTRL_BANK1 0x007334 +#define ACP_SW1_TX_DP0_3_CHANNEL_ENABLE_BANK1 0x007338 +#define ACP_SW1_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00733C +#define ACP_SW1_TX_DP1_SAMPLEINTERVAL_BANK0 0x007370 +#define ACP_SW1_TX_DP1_HCTRL_BANK0 0x007374 +#define ACP_SW1_TX_DP1_HCTRL_OFFSET_BANK0 0x007378 +#define ACP_SW1_TX_DP1_LANE_CTRL_BANK0 0x00737C +#define ACP_SW1_TX_DP1_CHANNEL_ENABLE_BANK0 0x007380 +#define ACP_SW1_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007384 +#define ACP_SW1_TX_DP1_SAMPLEINTERVAL_BANK1 0x007388 +#define ACP_SW1_TX_DP1_HCTRL_BANK1 0x00738C +#define ACP_SW1_TX_DP1_HCTRL_OFFSET_BANK1 0x007390 +#define ACP_SW1_TX_DP1_LANE_CTRL_BANK1 0x007394 +#define ACP_SW1_TX_DP1_CHANNEL_ENABLE_BANK1 0x007398 +#define ACP_SW1_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00739C +#define ACP_SW1_TX_DP2_SAMPLEINTERVAL_BANK0 0x0073A0 +#define ACP_SW1_TX_DP2_HCTRL_BANK0 0x0073A4 +#define ACP_SW1_TX_DP2_HCTRL_OFFSET_BANK0 0x0073A8 +#define ACP_SW1_TX_DP2_LANE_CTRL_BANK0 0x0073AC +#define ACP_SW1_TX_DP2_CHANNEL_ENABLE_BANK0 0x0073B0 +#define ACP_SW1_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0073B4 +#define ACP_SW1_TX_DP2_SAMPLEINTERVAL_BANK1 0x0073B8 +#define ACP_SW1_TX_DP2_HCTRL_BANK1 0x0073BC +#define ACP_SW1_TX_DP2_HCTRL_OFFSET_BANK1 0x0073C0 +#define ACP_SW1_TX_DP2_LANE_CTRL_BANK1 0x0073C4 +#define ACP_SW1_TX_DP2_CHANNEL_ENABLE_BANK1 0x0073C8 +#define ACP_SW1_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0073CC +#define ACP_SW1_TX_DP3_SAMPLEINTERVAL_BANK0 0x0073D0 +#define ACP_SW1_TX_DP3_HCTRL_BANK0 0x0073D4 +#define ACP_SW1_TX_DP3_HCTRL_OFFSET_BANK0 0x0073D8 +#define ACP_SW1_TX_DP3_LANE_CTRL_BANK0 0x0073DC +#define ACP_SW1_TX_DP3_CHANNEL_ENABLE_BANK0 0x0073E0 +#define ACP_SW1_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0073E4 +#define ACP_SW1_TX_DP3_SAMPLEINTERVAL_BANK1 0x0073E8 +#define ACP_SW1_TX_DP3_HCTRL_BANK1 0x0073EC +#define ACP_SW1_TX_DP3_HCTRL_OFFSET_BANK1 0x0073F0 +#define ACP_SW1_TX_DP3_LANE_CTRL_BANK1 0x0073F4 +#define ACP_SW1_TX_DP3_CHANNEL_ENABLE_BANK1 0x0073F8 +#define ACP_SW1_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0073FC +#define ACP_SW1_TX_DP4_SAMPLEINTERVAL_BANK0 0x007400 +#define ACP_SW1_TX_DP4_HCTRL_BANK0 0x007404 +#define ACP_SW1_TX_DP4_HCTRL_OFFSET_BANK0 0x007408 +#define ACP_SW1_TX_DP4_LANE_CTRL_BANK0 0x00740C +#define ACP_SW1_TX_DP4_CHANNEL_ENABLE_BANK0 0x007410 +#define ACP_SW1_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007414 +#define ACP_SW1_TX_DP4_SAMPLEINTERVAL_BANK1 0x007418 +#define ACP_SW1_TX_DP4_HCTRL_BANK1 0x00741C +#define ACP_SW1_TX_DP4_HCTRL_OFFSET_BANK1 0x007420 +#define ACP_SW1_TX_DP4_LANE_CTRL_BANK1 0x007424 +#define ACP_SW1_TX_DP4_CHANNEL_ENABLE_BANK1 0x007428 +#define ACP_SW1_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00742C +#define ACP_SW1_TX_DP5_SAMPLEINTERVAL_BANK0 0x007430 +#define ACP_SW1_TX_DP5_HCTRL_BANK0 0x007434 +#define ACP_SW1_TX_DP5_HCTRL_OFFSET_BANK0 0x007438 +#define ACP_SW1_TX_DP5_LANE_CTRL_BANK0 0x00743C +#define ACP_SW1_TX_DP5_CHANNEL_ENABLE_BANK0 0x007440 +#define ACP_SW1_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007444 +#define ACP_SW1_TX_DP5_SAMPLEINTERVAL_BANK1 0x007448 +#define ACP_SW1_TX_DP5_HCTRL_BANK1 0x00744C +#define ACP_SW1_TX_DP5_HCTRL_OFFSET_BANK1 0x007450 +#define ACP_SW1_TX_DP5_LANE_CTRL_BANK1 0x007454 +#define ACP_SW1_TX_DP5_CHANNEL_ENABLE_BANK1 0x007458 +#define ACP_SW1_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00745C +#define ACP_SW1_TX_DP6_SAMPLEINTERVAL_BANK0 0x007460 +#define ACP_SW1_TX_DP6_HCTRL_BANK0 0x007464 +#define ACP_SW1_TX_DP6_HCTRL_OFFSET_BANK0 0x007468 +#define ACP_SW1_TX_DP6_LANE_CTRL_BANK0 0x00746C +#define ACP_SW1_TX_DP6_CHANNEL_ENABLE_BANK0 0x007470 +#define ACP_SW1_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007474 +#define ACP_SW1_TX_DP6_SAMPLEINTERVAL_BANK1 0x007478 +#define ACP_SW1_TX_DP6_HCTRL_BANK1 0x00747C +#define ACP_SW1_TX_DP6_HCTRL_OFFSET_BANK1 0x007480 +#define ACP_SW1_TX_DP6_LANE_CTRL_BANK1 0x007484 +#define ACP_SW1_TX_DP6_CHANNEL_ENABLE_BANK1 0x007488 +#define ACP_SW1_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00748C +#define ACP_SW1_TX_DP7_SAMPLEINTERVAL_BANK0 0x007490 +#define ACP_SW1_TX_DP7_HCTRL_BANK0 0x007494 +#define ACP_SW1_TX_DP7_HCTRL_OFFSET_BANK0 0x007498 +#define ACP_SW1_TX_DP7_LANE_CTRL_BANK0 0x00749C +#define ACP_SW1_TX_DP7_CHANNEL_ENABLE_BANK0 0x0074A0 +#define ACP_SW1_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0074A4 +#define ACP_SW1_TX_DP7_SAMPLEINTERVAL_BANK1 0x0074A8 +#define ACP_SW1_TX_DP7_HCTRL_BANK1 0x0074AC +#define ACP_SW1_TX_DP7_HCTRL_OFFSET_BANK1 0x0074B0 +#define ACP_SW1_TX_DP7_LANE_CTRL_BANK1 0x0074B4 +#define ACP_SW1_TX_DP7_CHANNEL_ENABLE_BANK1 0x0074B8 +#define ACP_SW1_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0074BC +#define ACP_SW1_RX_STREAM0_EN 0x007514 +#define ACP_SW1_RX_STREAM1_EN 0x007518 +#define ACP_SW1_RX_STREAM2_EN 0x00751C +#define ACP_SW1_RX_STREAM3_EN 0x007520 +#define ACP_SW1_RX_STREAM4_EN 0x007524 +#define ACP_SW1_RX_STREAM5_EN 0x007528 +#define ACP_SW1_RX_STREAM6_EN 0x00752C +#define ACP_SW1_RX_STREAM7_EN 0x007530 +#define ACP_SW1_RX_STREAM0_EN_STATUS 0x007534 +#define ACP_SW1_RX_STREAM1_EN_STATUS 0x007538 +#define ACP_SW1_RX_STREAM2_EN_STATUS 0x00753C +#define ACP_SW1_RX_STREAM3_EN_STATUS 0x007540 +#define ACP_SW1_RX_STREAM4_EN_STATUS 0x007544 +#define ACP_SW1_RX_STREAM5_EN_STATUS 0x007548 +#define ACP_SW1_RX_STREAM6_EN_STATUS 0x00754C +#define ACP_SW1_RX_STREAM7_EN_STATUS 0x007550 +#define ACP_SW1_RX_DP0_FRAME_FORMAT 0x007554 +#define ACP_SW1_RX_DP1_FRAME_FORMAT 0x007558 +#define ACP_SW1_RX_DP2_FRAME_FORMAT 0x00755C +#define ACP_SW1_RX_DP3_FRAME_FORMAT 0x007560 +#define ACP_SW1_RX_DP4_FRAME_FORMAT 0x007564 +#define ACP_SW1_RX_DP5_FRAME_FORMAT 0x007568 +#define ACP_SW1_RX_DP6_FRAME_FORMAT 0x00756C +#define ACP_SW1_RX_DP7_FRAME_FORMAT 0x007570 +#define ACP_SW1_RX_DP0_0_SAMPLEINTERVAL_BANK0 0x007580 +#define ACP_SW1_RX_DP0_0_HCTRL_BANK0 0x007584 +#define ACP_SW1_RX_DP0_0_HCTRL_OFFSET_BANK0 0x007588 +#define ACP_SW1_RX_DP0_0_LANE_CTRL_BANK0 0x00758C +#define ACP_SW1_RX_DP0_0_CHANNEL_ENABLE_BANK0 0x007590 +#define ACP_SW1_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007594 +#define ACP_SW1_RX_DP0_0_SAMPLEINTERVAL_BANK1 0x007598 +#define ACP_SW1_RX_DP0_0_HCTRL_BANK1 0x00759C +#define ACP_SW1_RX_DP0_0_HCTRL_OFFSET_BANK1 0x0075A0 +#define ACP_SW1_RX_DP0_0_LANE_CTRL_BANK1 0x0075A4 +#define ACP_SW1_RX_DP0_0_CHANNEL_ENABLE_BANK1 0x0075A8 +#define ACP_SW1_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0075AC +#define ACP_SW1_RX_DP0_1_SAMPLEINTERVAL_BANK0 0x0075B0 +#define ACP_SW1_RX_DP0_1_HCTRL_BANK0 0x0075B4 +#define ACP_SW1_RX_DP0_1_HCTRL_OFFSET_BANK0 0x0075B8 +#define ACP_SW1_RX_DP0_1_LANE_CTRL_BANK0 0x0075BC +#define ACP_SW1_RX_DP0_1_CHANNEL_ENABLE_BANK0 0x0075C0 +#define ACP_SW1_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0075C4 +#define ACP_SW1_RX_DP0_1_SAMPLEINTERVAL_BANK1 0x0075C8 +#define ACP_SW1_RX_DP0_1_HCTRL_BANK1 0x0075CC +#define ACP_SW1_RX_DP0_1_HCTRL_OFFSET_BANK1 0x0075D0 +#define ACP_SW1_RX_DP0_1_LANE_CTRL_BANK1 0x0075D4 +#define ACP_SW1_RX_DP0_1_CHANNEL_ENABLE_BANK1 0x0075D8 +#define ACP_SW1_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0075DC +#define ACP_SW1_RX_DP0_2_SAMPLEINTERVAL_BANK0 0x0075E0 +#define ACP_SW1_RX_DP0_2_HCTRL_BANK0 0x0075E4 +#define ACP_SW1_RX_DP0_2_HCTRL_OFFSET_BANK0 0x0075E8 +#define ACP_SW1_RX_DP0_2_LANE_CTRL_BANK0 0x0075EC +#define ACP_SW1_RX_DP0_2_CHANNEL_ENABLE_BANK0 0x0075F0 +#define ACP_SW1_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0075F4 +#define ACP_SW1_RX_DP0_2_SAMPLEINTERVAL_BANK1 0x0075F8 +#define ACP_SW1_RX_DP0_2_HCTRL_BANK1 0x0075FC +#define ACP_SW1_RX_DP0_2_HCTRL_OFFSET_BANK1 0x007600 +#define ACP_SW1_RX_DP0_2_LANE_CTRL_BANK1 0x007604 +#define ACP_SW1_RX_DP0_2_CHANNEL_ENABLE_BANK1 0x007608 +#define ACP_SW1_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00760C +#define ACP_SW1_RX_DP0_3_SAMPLEINTERVAL_BANK0 0x007610 +#define ACP_SW1_RX_DP0_3_HCTRL_BANK0 0x007614 +#define ACP_SW1_RX_DP0_3_HCTRL_OFFSET_BANK0 0x007618 +#define ACP_SW1_RX_DP0_3_LANE_CTRL_BANK0 0x00761C +#define ACP_SW1_RX_DP0_3_CHANNEL_ENABLE_BANK0 0x007620 +#define ACP_SW1_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007624 +#define ACP_SW1_RX_DP0_3_SAMPLEINTERVAL_BANK1 0x007628 +#define ACP_SW1_RX_DP0_3_HCTRL_BANK1 0x00762C +#define ACP_SW1_RX_DP0_3_HCTRL_OFFSET_BANK1 0x007630 +#define ACP_SW1_RX_DP0_3_LANE_CTRL_BANK1 0x007634 +#define ACP_SW1_RX_DP0_3_CHANNEL_ENABLE_BANK1 0x007638 +#define ACP_SW1_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00763C +#define ACP_SW1_RX_DP1_SAMPLEINTERVAL_BANK0 0x007670 +#define ACP_SW1_RX_DP1_HCTRL_BANK0 0x007674 +#define ACP_SW1_RX_DP1_HCTRL_OFFSET_BANK0 0x007678 +#define ACP_SW1_RX_DP1_LANE_CTRL_BANK0 0x00767C +#define ACP_SW1_RX_DP1_CHANNEL_ENABLE_BANK0 0x007680 +#define ACP_SW1_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007684 +#define ACP_SW1_RX_DP1_SAMPLEINTERVAL_BANK1 0x007688 +#define ACP_SW1_RX_DP1_HCTRL_BANK1 0x00768C +#define ACP_SW1_RX_DP1_HCTRL_OFFSET_BANK1 0x007690 +#define ACP_SW1_RX_DP1_LANE_CTRL_BANK1 0x007694 +#define ACP_SW1_RX_DP1_CHANNEL_ENABLE_BANK1 0x007698 +#define ACP_SW1_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00769C +#define ACP_SW1_RX_DP2_SAMPLEINTERVAL_BANK0 0x0076A0 +#define ACP_SW1_RX_DP2_HCTRL_BANK0 0x0076A4 +#define ACP_SW1_RX_DP2_HCTRL_OFFSET_BANK0 0x0076A8 +#define ACP_SW1_RX_DP2_LANE_CTRL_BANK0 0x0076AC +#define ACP_SW1_RX_DP2_CHANNEL_ENABLE_BANK0 0x0076B0 +#define ACP_SW1_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0076B4 +#define ACP_SW1_RX_DP2_SAMPLEINTERVAL_BANK1 0x0076B8 +#define ACP_SW1_RX_DP2_HCTRL_BANK1 0x0076BC +#define ACP_SW1_RX_DP2_HCTRL_OFFSET_BANK1 0x0076C0 +#define ACP_SW1_RX_DP2_LANE_CTRL_BANK1 0x0076C4 +#define ACP_SW1_RX_DP2_CHANNEL_ENABLE_BANK1 0x0076C8 +#define ACP_SW1_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0076CC +#define ACP_SW1_RX_DP3_SAMPLEINTERVAL_BANK0 0x0076D0 +#define ACP_SW1_RX_DP3_HCTRL_BANK0 0x0076D4 +#define ACP_SW1_RX_DP3_HCTRL_OFFSET_BANK0 0x0076D8 +#define ACP_SW1_RX_DP3_LANE_CTRL_BANK0 0x0076DC +#define ACP_SW1_RX_DP3_CHANNEL_ENABLE_BANK0 0x0076E0 +#define ACP_SW1_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0076E4 +#define ACP_SW1_RX_DP3_SAMPLEINTERVAL_BANK1 0x0076E8 +#define ACP_SW1_RX_DP3_HCTRL_BANK1 0x0076EC +#define ACP_SW1_RX_DP3_HCTRL_OFFSET_BANK1 0x0076F0 +#define ACP_SW1_RX_DP3_LANE_CTRL_BANK1 0x0076F4 +#define ACP_SW1_RX_DP3_CHANNEL_ENABLE_BANK1 0x0076F8 +#define ACP_SW1_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0076FC +#define ACP_SW1_RX_DP4_SAMPLEINTERVAL_BANK0 0x007700 +#define ACP_SW1_RX_DP4_HCTRL_BANK0 0x007704 +#define ACP_SW1_RX_DP4_HCTRL_OFFSET_BANK0 0x007708 +#define ACP_SW1_RX_DP4_LANE_CTRL_BANK0 0x00770C +#define ACP_SW1_RX_DP4_CHANNEL_ENABLE_BANK0 0x007710 +#define ACP_SW1_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007714 +#define ACP_SW1_RX_DP4_SAMPLEINTERVAL_BANK1 0x007718 +#define ACP_SW1_RX_DP4_HCTRL_BANK1 0x00771C +#define ACP_SW1_RX_DP4_HCTRL_OFFSET_BANK1 0x007720 +#define ACP_SW1_RX_DP4_LANE_CTRL_BANK1 0x007724 +#define ACP_SW1_RX_DP4_CHANNEL_ENABLE_BANK1 0x007728 +#define ACP_SW1_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00772C +#define ACP_SW1_RX_DP5_SAMPLEINTERVAL_BANK0 0x007730 +#define ACP_SW1_RX_DP5_HCTRL_BANK0 0x007734 +#define ACP_SW1_RX_DP5_HCTRL_OFFSET_BANK0 0x007738 +#define ACP_SW1_RX_DP5_LANE_CTRL_BANK0 0x00773C +#define ACP_SW1_RX_DP5_CHANNEL_ENABLE_BANK0 0x007740 +#define ACP_SW1_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007744 +#define ACP_SW1_RX_DP5_SAMPLEINTERVAL_BANK1 0x007748 +#define ACP_SW1_RX_DP5_HCTRL_BANK1 0x00774C +#define ACP_SW1_RX_DP5_HCTRL_OFFSET_BANK1 0x007750 +#define ACP_SW1_RX_DP5_LANE_CTRL_BANK1 0x007754 +#define ACP_SW1_RX_DP5_CHANNEL_ENABLE_BANK1 0x007758 +#define ACP_SW1_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00775C +#define ACP_SW1_RX_DP6_SAMPLEINTERVAL_BANK0 0x007760 +#define ACP_SW1_RX_DP6_HCTRL_BANK0 0x007764 +#define ACP_SW1_RX_DP6_HCTRL_OFFSET_BANK0 0x007768 +#define ACP_SW1_RX_DP6_LANE_CTRL_BANK0 0x00776C +#define ACP_SW1_RX_DP6_CHANNEL_ENABLE_BANK0 0x007770 +#define ACP_SW1_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x007774 +#define ACP_SW1_RX_DP6_SAMPLEINTERVAL_BANK1 0x007778 +#define ACP_SW1_RX_DP6_HCTRL_BANK1 0x00777C +#define ACP_SW1_RX_DP6_HCTRL_OFFSET_BANK1 0x007780 +#define ACP_SW1_RX_DP6_LANE_CTRL_BANK1 0x007784 +#define ACP_SW1_RX_DP6_CHANNEL_ENABLE_BANK1 0x007788 +#define ACP_SW1_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00778C +#define ACP_SW1_RX_DP7_SAMPLEINTERVAL_BANK0 0x007790 +#define ACP_SW1_RX_DP7_HCTRL_BANK0 0x007794 +#define ACP_SW1_RX_DP7_HCTRL_OFFSET_BANK0 0x007798 +#define ACP_SW1_RX_DP7_LANE_CTRL_BANK0 0x00779C +#define ACP_SW1_RX_DP7_CHANNEL_ENABLE_BANK0 0x0077A0 +#define ACP_SW1_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0077A4 +#define ACP_SW1_RX_DP7_SAMPLEINTERVAL_BANK1 0x0077A8 +#define ACP_SW1_RX_DP7_HCTRL_BANK1 0x0077AC +#define ACP_SW1_RX_DP7_HCTRL_OFFSET_BANK1 0x0077B0 +#define ACP_SW1_RX_DP7_LANE_CTRL_BANK1 0x0077B4 +#define ACP_SW1_RX_DP7_CHANNEL_ENABLE_BANK1 0x0077B8 +#define ACP_SW1_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0077BC +#define ACP_SW1_BPT_PORT_EN 0x0077C0 +#define ACP_SW1_BPT_PORT_EN_STATUS 0x0077C4 +#define ACP_SW1_BPT_PORT_FRAME_FORMAT 0x0077C8 +#define ACP_SW1_BPT_PORT_SAMPLEINTERVAL_BANK0 0x0077CC +#define ACP_SW1_BPT_PORT_HCTRL_BANK0 0x0077D0 +#define ACP_SW1_BPT_PORT_OFFSET_BANK0 0x0077D4 +#define ACP_SW1_BPT_PORT_LANE_SELECT_BANK0 0x0077D8 +#define ACP_SW1_BPT_PORT_CHANNEL_ENABLE_BANK0 0x0077DC +#define ACP_SW1_BPT_PORT_SAMPLEINTERVAL_BANK1 0x0077E0 +#define ACP_SW1_BPT_PORT_HCTRL_BANK1 0x0077E4 +#define ACP_SW1_BPT_PORT_OFFSET_BANK1 0x0077E8 +#define ACP_SW1_BPT_PORT_LANE_SELECT_BANK1 0x0077EC +#define ACP_SW1_BPT_PORT_CHANNEL_ENABLE_BANK1 0x0077F0 +#define ACP_SW1_BPT_PORT_FIRST_BYTE_ADDR 0x0077F4 +#define ACP_SW1_CLK_RESUME_CTRL 0x0077F8 +#define ACP_SW1_CLK_RESUME_DELAY_CNTR 0x0077FC +#define ACP_SW1_BUS_RESET_CTRL 0x007800 +#define ACP_SW1_PRBS_ERR_STATUS 0x007804 +#define ACP_SW1_WALLCLK_MISC 0x007808 +#define ACP_SW1_WALL_CLK_COUNTER 0x00780C +#define ACP_SW1_PING_STATUS_REGISTER_LOW 0x007810 +#define ACP_SW1_PING_STATUS_REGISTER_HIGH 0x007814 +#define ACP_SW1_PING_STATUS_CURRENT_BANK_SEL 0x007818 +#define ACP_SW1_TZD_CHANGE 0x00781C +#define ACP_SW1_WALLCLK_INTR_CNTL 0x007820 + +#define ACP_SW2_GLOBAL_CAPABILITIES 0x008E00 +#define ACP_SW2_RX_DMA0_RINGBUFADDR 0x008E04 +#define ACP_SW2_RX_DMA0_RINGBUFSIZE 0x008E08 +#define ACP_SW2_RX_DMA0_FIFOADDR 0x008E0C +#define ACP_SW2_RX_DMA0_FIFOSIZE 0x008E10 +#define ACP_SW2_RX_DMA0_BURST_SIZE 0x008E14 +#define ACP_SW2_RX_DMA0_LINKPOSITIONCNTR 0x008E18 +#define ACP_SW2_RX_DMA0_LINEARPOSITIONCNTR_HIGH 0x008E1C +#define ACP_SW2_RX_DMA0_LINEARPOSITIONCNTR_LOW 0x008E20 +#define ACP_SW2_RX_DMA0_INTR_WATERMARK_SIZE 0x008E24 +#define ACP_SW2_RX_DMA1_RINGBUFADDR 0x008E28 +#define ACP_SW2_RX_DMA1_RINGBUFSIZE 0x008E2C +#define ACP_SW2_RX_DMA1_FIFOADDR 0x008E30 +#define ACP_SW2_RX_DMA1_FIFOSIZE 0x008E34 +#define ACP_SW2_RX_DMA1_BURST_SIZE 0x008E38 +#define ACP_SW2_RX_DMA1_LINKPOSITIONCNTR 0x008E3C +#define ACP_SW2_RX_DMA1_LINEARPOSITIONCNTR_HIGH 0x008E40 +#define ACP_SW2_RX_DMA1_LINEARPOSITIONCNTR_LOW 0x008E44 +#define ACP_SW2_RX_DMA1_INTR_WATERMARK_SIZE 0x008E48 +#define ACP_SW2_RX_DMA2_RINGBUFADDR 0x008E4C +#define ACP_SW2_RX_DMA2_RINGBUFSIZE 0x008E50 +#define ACP_SW2_RX_DMA2_FIFOADDR 0x008E54 +#define ACP_SW2_RX_DMA2_FIFOSIZE 0x008E58 +#define ACP_SW2_RX_DMA2_BURST_SIZE 0x008E5C +#define ACP_SW2_RX_DMA2_LINKPOSITIONCNTR 0x008E60 +#define ACP_SW2_RX_DMA2_LINEARPOSITIONCNTR_HIGH 0x008E64 +#define ACP_SW2_RX_DMA2_LINEARPOSITIONCNTR_LOW 0x008E68 +#define ACP_SW2_RX_DMA2_INTR_WATERMARK_SIZE 0x008E6C +#define ACP_SW2_RX_DMA3_RINGBUFADDR 0x008E70 +#define ACP_SW2_RX_DMA3_RINGBUFSIZE 0x008E74 +#define ACP_SW2_RX_DMA3_FIFOADDR 0x008E78 +#define ACP_SW2_RX_DMA3_FIFOSIZE 0x008E7C +#define ACP_SW2_RX_DMA3_BURST_SIZE 0x008E80 +#define ACP_SW2_RX_DMA3_LINKPOSITIONCNTR 0x008E84 +#define ACP_SW2_RX_DMA3_LINEARPOSITIONCNTR_HIGH 0x008E88 +#define ACP_SW2_RX_DMA3_LINEARPOSITIONCNTR_LOW 0x008E8C +#define ACP_SW2_RX_DMA3_INTR_WATERMARK_SIZE 0x008E90 +#define ACP_SW2_RX_DMA4_RINGBUFADDR 0x008E94 +#define ACP_SW2_RX_DMA4_RINGBUFSIZE 0x008E98 +#define ACP_SW2_RX_DMA4_FIFOADDR 0x008E9C +#define ACP_SW2_RX_DMA4_FIFOSIZE 0x008EA0 +#define ACP_SW2_RX_DMA4_BURST_SIZE 0x008EA4 +#define ACP_SW2_RX_DMA4_LINKPOSITIONCNTR 0x008EA8 +#define ACP_SW2_RX_DMA4_LINEARPOSITIONCNTR_HIGH 0x008EAC +#define ACP_SW2_RX_DMA4_LINEARPOSITIONCNTR_LOW 0x008EB0 +#define ACP_SW2_RX_DMA4_INTR_WATERMARK_SIZE 0x008EB4 +#define ACP_SW2_RX_DMA5_RINGBUFADDR 0x008EB8 +#define ACP_SW2_RX_DMA5_RINGBUFSIZE 0x008EBC +#define ACP_SW2_RX_DMA5_FIFOADDR 0x008EC0 +#define ACP_SW2_RX_DMA5_FIFOSIZE 0x008EC4 +#define ACP_SW2_RX_DMA5_BURST_SIZE 0x008EC8 +#define ACP_SW2_RX_DMA5_LINKPOSITIONCNTR 0x008ECC +#define ACP_SW2_RX_DMA5_LINEARPOSITIONCNTR_HIGH 0x008ED0 +#define ACP_SW2_RX_DMA5_LINEARPOSITIONCNTR_LOW 0x008ED4 +#define ACP_SW2_RX_DMA5_INTR_WATERMARK_SIZE 0x008ED8 +#define ACP_SW2_RX_DMA6_RINGBUFADDR 0x008EDC +#define ACP_SW2_RX_DMA6_RINGBUFSIZE 0x008EE0 +#define ACP_SW2_RX_DMA6_FIFOADDR 0x008EE4 +#define ACP_SW2_RX_DMA6_FIFOSIZE 0x008EE8 +#define ACP_SW2_RX_DMA6_BURST_SIZE 0x008EEC +#define ACP_SW2_RX_DMA6_LINKPOSITIONCNTR 0x008EF0 +#define ACP_SW2_RX_DMA6_LINEARPOSITIONCNTR_HIGH 0x008EF4 +#define ACP_SW2_RX_DMA6_LINEARPOSITIONCNTR_LOW 0x008EF8 +#define ACP_SW2_RX_DMA6_INTR_WATERMARK_SIZE 0x008EFC +#define ACP_SW2_RX_DMA7_RINGBUFADDR 0x008F00 +#define ACP_SW2_RX_DMA7_RINGBUFSIZE 0x008F04 +#define ACP_SW2_RX_DMA7_FIFOADDR 0x008F08 +#define ACP_SW2_RX_DMA7_FIFOSIZE 0x008F0C +#define ACP_SW2_RX_DMA7_BURST_SIZE 0x008F10 +#define ACP_SW2_RX_DMA7_LINKPOSITIONCNTR 0x008F14 +#define ACP_SW2_RX_DMA7_LINEARPOSITIONCNTR_HIGH 0x008F18 +#define ACP_SW2_RX_DMA7_LINEARPOSITIONCNTR_LOW 0x008F1C +#define ACP_SW2_RX_DMA7_INTR_WATERMARK_SIZE 0x008F20 +#define ACP_SW2_TX_DMA0_RINGBUFADDR 0x008F24 +#define ACP_SW2_TX_DMA0_RINGBUFSIZE 0x008F28 +#define ACP_SW2_TX_DMA0_FIFOADDR 0x008F2C +#define ACP_SW2_TX_DMA0_FIFOSIZE 0x008F30 +#define ACP_SW2_TX_DMA0_BURST_SIZE 0x008F34 +#define ACP_SW2_TX_DMA0_LINKPOSITIONCNTR 0x008F38 +#define ACP_SW2_TX_DMA0_LINEARPOSITIONCNTR_HIGH 0x008F3C +#define ACP_SW2_TX_DMA0_LINEARPOSITIONCNTR_LOW 0x008F40 +#define ACP_SW2_TX_DMA0_INTR_WATERMARK_SIZE 0x008F44 +#define ACP_SW2_TX_DMA1_RINGBUFADDR 0x008F48 +#define ACP_SW2_TX_DMA1_RINGBUFSIZE 0x008F4C +#define ACP_SW2_TX_DMA1_FIFOADDR 0x008F50 +#define ACP_SW2_TX_DMA1_FIFOSIZE 0x008F54 +#define ACP_SW2_TX_DMA1_BURST_SIZE 0x008F58 +#define ACP_SW2_TX_DMA1_LINKPOSITIONCNTR 0x008F5C +#define ACP_SW2_TX_DMA1_LINEARPOSITIONCNTR_HIGH 0x008F60 +#define ACP_SW2_TX_DMA1_LINEARPOSITIONCNTR_LOW 0x008F64 +#define ACP_SW2_TX_DMA1_INTR_WATERMARK_SIZE 0x008F68 +#define ACP_SW2_TX_DMA2_RINGBUFADDR 0x008F6C +#define ACP_SW2_TX_DMA2_RINGBUFSIZE 0x008F70 +#define ACP_SW2_TX_DMA2_FIFOADDR 0x008F74 +#define ACP_SW2_TX_DMA2_FIFOSIZE 0x008F78 +#define ACP_SW2_TX_DMA2_BURST_SIZE 0x008F7C +#define ACP_SW2_TX_DMA2_LINKPOSITIONCNTR 0x008F80 +#define ACP_SW2_TX_DMA2_LINEARPOSITIONCNTR_HIGH 0x008F84 +#define ACP_SW2_TX_DMA2_LINEARPOSITIONCNTR_LOW 0x008F88 +#define ACP_SW2_TX_DMA2_INTR_WATERMARK_SIZE 0x008F8C +#define ACP_SW2_TX_DMA3_RINGBUFADDR 0x008F90 +#define ACP_SW2_TX_DMA3_RINGBUFSIZE 0x008F94 +#define ACP_SW2_TX_DMA3_FIFOADDR 0x008F98 +#define ACP_SW2_TX_DMA3_FIFOSIZE 0x008F9C +#define ACP_SW2_TX_DMA3_BURST_SIZE 0x008FA0 +#define ACP_SW2_TX_DMA3_LINKPOSITIONCNTR 0x008FA4 +#define ACP_SW2_TX_DMA3_LINEARPOSITIONCNTR_HIGH 0x008FA8 +#define ACP_SW2_TX_DMA3_LINEARPOSITIONCNTR_LOW 0x008FAC +#define ACP_SW2_TX_DMA3_INTR_WATERMARK_SIZE 0x008FB0 +#define ACP_SW2_TX_DMA4_RINGBUFADDR 0x008FB4 +#define ACP_SW2_TX_DMA4_RINGBUFSIZE 0x008FB8 +#define ACP_SW2_TX_DMA4_FIFOADDR 0x008FBC +#define ACP_SW2_TX_DMA4_FIFOSIZE 0x008FC0 +#define ACP_SW2_TX_DMA4_BURST_SIZE 0x008FC4 +#define ACP_SW2_TX_DMA4_LINKPOSITIONCNTR 0x008FC8 +#define ACP_SW2_TX_DMA4_LINEARPOSITIONCNTR_HIGH 0x008FCC +#define ACP_SW2_TX_DMA4_LINEARPOSITIONCNTR_LOW 0x008FD0 +#define ACP_SW2_TX_DMA4_INTR_WATERMARK_SIZE 0x008FD4 +#define ACP_SW2_TX_DMA5_RINGBUFADDR 0x008FD8 +#define ACP_SW2_TX_DMA5_RINGBUFSIZE 0x008FDC +#define ACP_SW2_TX_DMA5_FIFOADDR 0x008FE0 +#define ACP_SW2_TX_DMA5_FIFOSIZE 0x008FE4 +#define ACP_SW2_TX_DMA5_BURST_SIZE 0x008FE8 +#define ACP_SW2_TX_DMA5_LINKPOSITIONCNTR 0x008FEC +#define ACP_SW2_TX_DMA5_LINEARPOSITIONCNTR_HIGH 0x008FF0 +#define ACP_SW2_TX_DMA5_LINEARPOSITIONCNTR_LOW 0x008FF4 +#define ACP_SW2_TX_DMA5_INTR_WATERMARK_SIZE 0x008FF8 +#define ACP_SW2_TX_DMA6_RINGBUFADDR 0x008FFC +#define ACP_SW2_TX_DMA6_RINGBUFSIZE 0x009000 +#define ACP_SW2_TX_DMA6_FIFOADDR 0x009004 +#define ACP_SW2_TX_DMA6_FIFOSIZE 0x009008 +#define ACP_SW2_TX_DMA6_BURST_SIZE 0x00900C +#define ACP_SW2_TX_DMA6_LINKPOSITIONCNTR 0x009010 +#define ACP_SW2_TX_DMA6_LINEARPOSITIONCNTR_HIGH 0x009014 +#define ACP_SW2_TX_DMA6_LINEARPOSITIONCNTR_LOW 0x009018 +#define ACP_SW2_TX_DMA6_INTR_WATERMARK_SIZE 0x00901C +#define ACP_SW2_TX_DMA7_RINGBUFADDR 0x009020 +#define ACP_SW2_TX_DMA7_RINGBUFSIZE 0x009024 +#define ACP_SW2_TX_DMA7_FIFOADDR 0x009028 +#define ACP_SW2_TX_DMA7_FIFOSIZE 0x00902C +#define ACP_SW2_TX_DMA7_BURST_SIZE 0x009030 +#define ACP_SW2_TX_DMA7_LINKPOSITIONCNTR 0x009034 +#define ACP_SW2_TX_DMA7_LINEARPOSITIONCNTR_HIGH 0x009038 +#define ACP_SW2_TX_DMA7_LINEARPOSITIONCNTR_LOW 0x00903C +#define ACP_SW2_TX_DMA7_INTR_WATERMARK_SIZE 0x009040 +#define ACP_SW2_RX_DMA0_POS_TRACK 0x009044 +#define ACP_SW2_RX_DMA0_POS 0x009048 +#define ACP_SW2_RX_DMA1_POS_TRACK 0x00904C +#define ACP_SW2_RX_DMA1_POS 0x009050 +#define ACP_SW2_RX_DMA2_POS_TRACK 0x009054 +#define ACP_SW2_RX_DMA2_POS 0x009058 +#define ACP_SW2_RX_DMA3_POS_TRACK 0x00905C +#define ACP_SW2_RX_DMA3_POS 0x009060 +#define ACP_SW2_RX_DMA4_POS_TRACK 0x009064 +#define ACP_SW2_RX_DMA4_POS 0x009068 +#define ACP_SW2_RX_DMA5_POS_TRACK 0x00906C +#define ACP_SW2_RX_DMA5_POS 0x009070 +#define ACP_SW2_RX_DMA6_POS_TRACK 0x009074 +#define ACP_SW2_RX_DMA6_POS 0x009078 +#define ACP_SW2_RX_DMA7_POS_TRACK 0x00907C +#define ACP_SW2_RX_DMA7_POS 0x009080 +#define ACP_SW2_TX_DMA0_POS_TRACK 0x009084 +#define ACP_SW2_TX_DMA0_POS 0x009088 +#define ACP_SW2_TX_DMA1_POS_TRACK 0x00908C +#define ACP_SW2_TX_DMA1_POS 0x009090 +#define ACP_SW2_TX_DMA2_POS_TRACK 0x009094 +#define ACP_SW2_TX_DMA2_POS 0x009098 +#define ACP_SW2_TX_DMA3_POS_TRACK 0x00909C +#define ACP_SW2_TX_DMA3_POS 0x0090A0 +#define ACP_SW2_TX_DMA4_POS_TRACK 0x0090A4 +#define ACP_SW2_TX_DMA4_POS 0x0090A8 +#define ACP_SW2_TX_DMA5_POS_TRACK 0x0090AC +#define ACP_SW2_TX_DMA5_POS 0x0090B0 +#define ACP_SW2_TX_DMA6_POS_TRACK 0x0090B4 +#define ACP_SW2_TX_DMA6_POS 0x0090B8 +#define ACP_SW2_TX_DMA7_POS_TRACK 0x0090BC +#define ACP_SW2_TX_DMA7_POS 0x0090C0 +#define ACP_SW2_FIFO_ERROR_REASON 0x0090C4 +#define ACP_SW2_FIFO_ERROR_INTR_MASK 0x0090C8 +#define ACP_SW2_ERROR_REASON1 0x0090CC +#define ACP_SW2_ERROR_INTR_MASK1 0x0090D0 +#define ACP_SW2_ERROR_REASON2 0x0090D4 +#define ACP_SW2_ERROR_INTR_MASK2 0x0090D8 + +#define ACP_SW2_CORB_BASE_ADDRESS 0x009100 +#define ACP_SW2_CORB_WRITE_POINTER 0x009104 +#define ACP_SW2_CORB_READ_POINTER 0x009108 +#define ACP_SW2_CORB_CONTROL 0x00910C +#define ACP_SW2_CORB_SIZE 0x009114 +#define ACP_SW2_RIRB_BASE_ADDRESS 0x009118 +#define ACP_SW2_RIRB_WRITE_POINTER 0x00911C +#define ACP_SW2_RIRB_RESPONSE_INTERRUPT_COUNT 0x009120 +#define ACP_SW2_RIRB_CONTROL 0x009124 +#define ACP_SW2_RIRB_SIZE 0x009128 +#define ACP_SW2_RIRB_FIFO_MIN_THDL 0x00912C +#define ACP_SW2_IMM_CMD_UPPER_WORD 0x009130 +#define ACP_SW2_IMM_CMD_LOWER_QWORD 0x009134 +#define ACP_SW2_IMM_RESP_UPPER_WORD 0x009138 +#define ACP_SW2_IMM_RESP_LOWER_QWORD 0x00913C +#define ACP_SW2_IMM_CMD_STS 0x009140 +#define ACP_SW2_BRA_BASE_ADDRESS 0x009144 +#define ACP_SW2_BRA_TRANSFER_SIZE 0x009148 +#define ACP_SW2_BRA_DMA_BUSY 0x00914C +#define ACP_SW2_BRA_RESP 0x009150 +#define ACP_SW2_BRA_RESP_FRAME_ADDR 0x009154 +#define ACP_SW2_BRA_CURRENT_TRANSFER_SIZE 0x009158 +#define ACP_SW2_STATE_CHANGE_STATUS_0TO7 0x00915C +#define ACP_SW2_STATE_CHANGE_STATUS_8TO11 0x009160 +#define ACP_SW2_STATE_CHANGE_STATUS_MASK_0TO7 0x009164 +#define ACP_SW2_STATE_CHANGE_STATUS_MASK_8TO11 0x009168 +#define ACP_SW2_CLK_FREQUENCY_CTRL_BANK0 0x00916C +#define ACP_SW2_CLK_FREQUENCY_CTRL_BANK1 0x009170 +#define ACP_SW2_ERROR_INTR_MASK 0x009174 +#define ACP_SW2_PHY_TEST_MODE_DATA_OFF 0x009178 +#define ACP_SW2_DATA_TO_PDM_EN 0x00917C + +#define ACP_SW2_EN 0x009200 +#define ACP_SW2_EN_STATUS 0x009204 +#define ACP_SW2_FRAMESIZE_BANK0 0x009208 +#define ACP_SW2_FRAMESIZE_BANK1 0x00920C +#define ACP_SW2_SSP_COUNTER 0x009210 +#define ACP_SW2_TX_STREAM0_EN 0x009214 +#define ACP_SW2_TX_STREAM1_EN 0x009218 +#define ACP_SW2_TX_STREAM2_EN 0x00921C +#define ACP_SW2_TX_STREAM3_EN 0x009220 +#define ACP_SW2_TX_STREAM4_EN 0x009224 +#define ACP_SW2_TX_STREAM5_EN 0x009228 +#define ACP_SW2_TX_STREAM6_EN 0x00922C +#define ACP_SW2_TX_STREAM7_EN 0x009230 +#define ACP_SW2_TX_STREAM0_EN_STATUS 0x009234 +#define ACP_SW2_TX_STREAM1_EN_STATUS 0x009238 +#define ACP_SW2_TX_STREAM2_EN_STATUS 0x00923C +#define ACP_SW2_TX_STREAM3_EN_STATUS 0x009240 +#define ACP_SW2_TX_STREAM4_EN_STATUS 0x009244 +#define ACP_SW2_TX_STREAM5_EN_STATUS 0x009248 +#define ACP_SW2_TX_STREAM6_EN_STATUS 0x00924C +#define ACP_SW2_TX_STREAM7_EN_STATUS 0x009250 +#define ACP_SW2_TX_DP0_FRAME_FORMAT 0x009254 +#define ACP_SW2_TX_DP1_FRAME_FORMAT 0x009258 +#define ACP_SW2_TX_DP2_FRAME_FORMAT 0x00925C +#define ACP_SW2_TX_DP3_FRAME_FORMAT 0x009260 +#define ACP_SW2_TX_DP4_FRAME_FORMAT 0x009264 +#define ACP_SW2_TX_DP5_FRAME_FORMAT 0x009268 +#define ACP_SW2_TX_DP6_FRAME_FORMAT 0x00926C +#define ACP_SW2_TX_DP7_FRAME_FORMAT 0x009270 +#define ACP_SW2_TX_DP0_0_SAMPLEINTERVAL_BANK0 0x009280 +#define ACP_SW2_TX_DP0_0_HCTRL_BANK0 0x009284 +#define ACP_SW2_TX_DP0_0_HCTRL_OFFSET_BANK0 0x009288 +#define ACP_SW2_TX_DP0_0_LANE_CTRL_BANK0 0x00928C +#define ACP_SW2_TX_DP0_0_CHANNEL_ENABLE_BANK0 0x009290 +#define ACP_SW2_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009294 +#define ACP_SW2_TX_DP0_0_SAMPLEINTERVAL_BANK1 0x009298 +#define ACP_SW2_TX_DP0_0_HCTRL_BANK1 0x00929C +#define ACP_SW2_TX_DP0_0_HCTRL_OFFSET_BANK1 0x0092A0 +#define ACP_SW2_TX_DP0_0_LANE_CTRL_BANK1 0x0092A4 +#define ACP_SW2_TX_DP0_0_CHANNEL_ENABLE_BANK1 0x0092A8 +#define ACP_SW2_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0092AC +#define ACP_SW2_TX_DP0_1_SAMPLEINTERVAL_BANK0 0x0092B0 +#define ACP_SW2_TX_DP0_1_HCTRL_BANK0 0x0092B4 +#define ACP_SW2_TX_DP0_1_HCTRL_OFFSET_BANK0 0x0092B8 +#define ACP_SW2_TX_DP0_1_LANE_CTRL_BANK0 0x0092BC +#define ACP_SW2_TX_DP0_1_CHANNEL_ENABLE_BANK0 0x0092C0 +#define ACP_SW2_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0092C4 +#define ACP_SW2_TX_DP0_1_SAMPLEINTERVAL_BANK1 0x0092C8 +#define ACP_SW2_TX_DP0_1_HCTRL_BANK1 0x0092CC +#define ACP_SW2_TX_DP0_1_HCTRL_OFFSET_BANK1 0x0092D0 +#define ACP_SW2_TX_DP0_1_LANE_CTRL_BANK1 0x0092D4 +#define ACP_SW2_TX_DP0_1_CHANNEL_ENABLE_BANK1 0x0092D8 +#define ACP_SW2_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0092DC +#define ACP_SW2_TX_DP0_2_SAMPLEINTERVAL_BANK0 0x0092E0 +#define ACP_SW2_TX_DP0_2_HCTRL_BANK0 0x0092E4 +#define ACP_SW2_TX_DP0_2_HCTRL_OFFSET_BANK0 0x0092E8 +#define ACP_SW2_TX_DP0_2_LANE_CTRL_BANK0 0x0092EC +#define ACP_SW2_TX_DP0_2_CHANNEL_ENABLE_BANK0 0x0092F0 +#define ACP_SW2_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0092F4 +#define ACP_SW2_TX_DP0_2_SAMPLEINTERVAL_BANK1 0x0092F8 +#define ACP_SW2_TX_DP0_2_HCTRL_BANK1 0x0092FC +#define ACP_SW2_TX_DP0_2_HCTRL_OFFSET_BANK1 0x009300 +#define ACP_SW2_TX_DP0_2_LANE_CTRL_BANK1 0x009304 +#define ACP_SW2_TX_DP0_2_CHANNEL_ENABLE_BANK1 0x009308 +#define ACP_SW2_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00930C +#define ACP_SW2_TX_DP0_3_SAMPLEINTERVAL_BANK0 0x009310 +#define ACP_SW2_TX_DP0_3_HCTRL_BANK0 0x009314 +#define ACP_SW2_TX_DP0_3_HCTRL_OFFSET_BANK0 0x009318 +#define ACP_SW2_TX_DP0_3_LANE_CTRL_BANK0 0x00931C +#define ACP_SW2_TX_DP0_3_CHANNEL_ENABLE_BANK0 0x009320 +#define ACP_SW2_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009324 +#define ACP_SW2_TX_DP0_3_SAMPLEINTERVAL_BANK1 0x009328 +#define ACP_SW2_TX_DP0_3_HCTRL_BANK1 0x00932C +#define ACP_SW2_TX_DP0_3_HCTRL_OFFSET_BANK1 0x009330 +#define ACP_SW2_TX_DP0_3_LANE_CTRL_BANK1 0x009334 +#define ACP_SW2_TX_DP0_3_CHANNEL_ENABLE_BANK1 0x009338 +#define ACP_SW2_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00933C +#define ACP_SW2_TX_DP1_SAMPLEINTERVAL_BANK0 0x009370 +#define ACP_SW2_TX_DP1_HCTRL_BANK0 0x009374 +#define ACP_SW2_TX_DP1_HCTRL_OFFSET_BANK0 0x009378 +#define ACP_SW2_TX_DP1_LANE_CTRL_BANK0 0x00937C +#define ACP_SW2_TX_DP1_CHANNEL_ENABLE_BANK0 0x009380 +#define ACP_SW2_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009384 +#define ACP_SW2_TX_DP1_SAMPLEINTERVAL_BANK1 0x009388 +#define ACP_SW2_TX_DP1_HCTRL_BANK1 0x00938C +#define ACP_SW2_TX_DP1_HCTRL_OFFSET_BANK1 0x009390 +#define ACP_SW2_TX_DP1_LANE_CTRL_BANK1 0x009394 +#define ACP_SW2_TX_DP1_CHANNEL_ENABLE_BANK1 0x009398 +#define ACP_SW2_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00939C +#define ACP_SW2_TX_DP2_SAMPLEINTERVAL_BANK0 0x0093A0 +#define ACP_SW2_TX_DP2_HCTRL_BANK0 0x0093A4 +#define ACP_SW2_TX_DP2_HCTRL_OFFSET_BANK0 0x0093A8 +#define ACP_SW2_TX_DP2_LANE_CTRL_BANK0 0x0093AC +#define ACP_SW2_TX_DP2_CHANNEL_ENABLE_BANK0 0x0093B0 +#define ACP_SW2_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0093B4 +#define ACP_SW2_TX_DP2_SAMPLEINTERVAL_BANK1 0x0093B8 +#define ACP_SW2_TX_DP2_HCTRL_BANK1 0x0093BC +#define ACP_SW2_TX_DP2_HCTRL_OFFSET_BANK1 0x0093C0 +#define ACP_SW2_TX_DP2_LANE_CTRL_BANK1 0x0093C4 +#define ACP_SW2_TX_DP2_CHANNEL_ENABLE_BANK1 0x0093C8 +#define ACP_SW2_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0093CC +#define ACP_SW2_TX_DP3_SAMPLEINTERVAL_BANK0 0x0093D0 +#define ACP_SW2_TX_DP3_HCTRL_BANK0 0x0093D4 +#define ACP_SW2_TX_DP3_HCTRL_OFFSET_BANK0 0x0093D8 +#define ACP_SW2_TX_DP3_LANE_CTRL_BANK0 0x0093DC +#define ACP_SW2_TX_DP3_CHANNEL_ENABLE_BANK0 0x0093E0 +#define ACP_SW2_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0093E4 +#define ACP_SW2_TX_DP3_SAMPLEINTERVAL_BANK1 0x0093E8 +#define ACP_SW2_TX_DP3_HCTRL_BANK1 0x0093EC +#define ACP_SW2_TX_DP3_HCTRL_OFFSET_BANK1 0x0093F0 +#define ACP_SW2_TX_DP3_LANE_CTRL_BANK1 0x0093F4 +#define ACP_SW2_TX_DP3_CHANNEL_ENABLE_BANK1 0x0093F8 +#define ACP_SW2_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0093FC +#define ACP_SW2_TX_DP4_SAMPLEINTERVAL_BANK0 0x009400 +#define ACP_SW2_TX_DP4_HCTRL_BANK0 0x009404 +#define ACP_SW2_TX_DP4_HCTRL_OFFSET_BANK0 0x009408 +#define ACP_SW2_TX_DP4_LANE_CTRL_BANK0 0x00940C +#define ACP_SW2_TX_DP4_CHANNEL_ENABLE_BANK0 0x009410 +#define ACP_SW2_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009414 +#define ACP_SW2_TX_DP4_SAMPLEINTERVAL_BANK1 0x009418 +#define ACP_SW2_TX_DP4_HCTRL_BANK1 0x00941C +#define ACP_SW2_TX_DP4_HCTRL_OFFSET_BANK1 0x009420 +#define ACP_SW2_TX_DP4_LANE_CTRL_BANK1 0x009424 +#define ACP_SW2_TX_DP4_CHANNEL_ENABLE_BANK1 0x009428 +#define ACP_SW2_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00942C +#define ACP_SW2_TX_DP5_SAMPLEINTERVAL_BANK0 0x009430 +#define ACP_SW2_TX_DP5_HCTRL_BANK0 0x009434 +#define ACP_SW2_TX_DP5_HCTRL_OFFSET_BANK0 0x009438 +#define ACP_SW2_TX_DP5_LANE_CTRL_BANK0 0x00943C +#define ACP_SW2_TX_DP5_CHANNEL_ENABLE_BANK0 0x009440 +#define ACP_SW2_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009444 +#define ACP_SW2_TX_DP5_SAMPLEINTERVAL_BANK1 0x009448 +#define ACP_SW2_TX_DP5_HCTRL_BANK1 0x00944C +#define ACP_SW2_TX_DP5_HCTRL_OFFSET_BANK1 0x009450 +#define ACP_SW2_TX_DP5_LANE_CTRL_BANK1 0x009454 +#define ACP_SW2_TX_DP5_CHANNEL_ENABLE_BANK1 0x009458 +#define ACP_SW2_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00945C +#define ACP_SW2_TX_DP6_SAMPLEINTERVAL_BANK0 0x009460 +#define ACP_SW2_TX_DP6_HCTRL_BANK0 0x009464 +#define ACP_SW2_TX_DP6_HCTRL_OFFSET_BANK0 0x009468 +#define ACP_SW2_TX_DP6_LANE_CTRL_BANK0 0x00946C +#define ACP_SW2_TX_DP6_CHANNEL_ENABLE_BANK0 0x009470 +#define ACP_SW2_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009474 +#define ACP_SW2_TX_DP6_SAMPLEINTERVAL_BANK1 0x009478 +#define ACP_SW2_TX_DP6_HCTRL_BANK1 0x00947C +#define ACP_SW2_TX_DP6_HCTRL_OFFSET_BANK1 0x009480 +#define ACP_SW2_TX_DP6_LANE_CTRL_BANK1 0x009484 +#define ACP_SW2_TX_DP6_CHANNEL_ENABLE_BANK1 0x009488 +#define ACP_SW2_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00948C +#define ACP_SW2_TX_DP7_SAMPLEINTERVAL_BANK0 0x009490 +#define ACP_SW2_TX_DP7_HCTRL_BANK0 0x009494 +#define ACP_SW2_TX_DP7_HCTRL_OFFSET_BANK0 0x009498 +#define ACP_SW2_TX_DP7_LANE_CTRL_BANK0 0x00949C +#define ACP_SW2_TX_DP7_CHANNEL_ENABLE_BANK0 0x0094A0 +#define ACP_SW2_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0094A4 +#define ACP_SW2_TX_DP7_SAMPLEINTERVAL_BANK1 0x0094A8 +#define ACP_SW2_TX_DP7_HCTRL_BANK1 0x0094AC +#define ACP_SW2_TX_DP7_HCTRL_OFFSET_BANK1 0x0094B0 +#define ACP_SW2_TX_DP7_LANE_CTRL_BANK1 0x0094B4 +#define ACP_SW2_TX_DP7_CHANNEL_ENABLE_BANK1 0x0094B8 +#define ACP_SW2_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0094BC +#define ACP_SW2_RX_STREAM0_EN 0x009514 +#define ACP_SW2_RX_STREAM1_EN 0x009518 +#define ACP_SW2_RX_STREAM2_EN 0x00951C +#define ACP_SW2_RX_STREAM3_EN 0x009520 +#define ACP_SW2_RX_STREAM4_EN 0x009524 +#define ACP_SW2_RX_STREAM5_EN 0x009528 +#define ACP_SW2_RX_STREAM6_EN 0x00952C +#define ACP_SW2_RX_STREAM7_EN 0x009530 +#define ACP_SW2_RX_STREAM0_EN_STATUS 0x009534 +#define ACP_SW2_RX_STREAM1_EN_STATUS 0x009538 +#define ACP_SW2_RX_STREAM2_EN_STATUS 0x00953C +#define ACP_SW2_RX_STREAM3_EN_STATUS 0x009540 +#define ACP_SW2_RX_STREAM4_EN_STATUS 0x009544 +#define ACP_SW2_RX_STREAM5_EN_STATUS 0x009548 +#define ACP_SW2_RX_STREAM6_EN_STATUS 0x00954C +#define ACP_SW2_RX_STREAM7_EN_STATUS 0x009550 +#define ACP_SW2_RX_DP0_FRAME_FORMAT 0x009554 +#define ACP_SW2_RX_DP1_FRAME_FORMAT 0x009558 +#define ACP_SW2_RX_DP2_FRAME_FORMAT 0x00955C +#define ACP_SW2_RX_DP3_FRAME_FORMAT 0x009560 +#define ACP_SW2_RX_DP4_FRAME_FORMAT 0x009564 +#define ACP_SW2_RX_DP5_FRAME_FORMAT 0x009568 +#define ACP_SW2_RX_DP6_FRAME_FORMAT 0x00956C +#define ACP_SW2_RX_DP7_FRAME_FORMAT 0x009570 +#define ACP_SW2_RX_DP0_0_SAMPLEINTERVAL_BANK0 0x009580 +#define ACP_SW2_RX_DP0_0_HCTRL_BANK0 0x009584 +#define ACP_SW2_RX_DP0_0_HCTRL_OFFSET_BANK0 0x009588 +#define ACP_SW2_RX_DP0_0_LANE_CTRL_BANK0 0x00958C +#define ACP_SW2_RX_DP0_0_CHANNEL_ENABLE_BANK0 0x009590 +#define ACP_SW2_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009594 +#define ACP_SW2_RX_DP0_0_SAMPLEINTERVAL_BANK1 0x009598 +#define ACP_SW2_RX_DP0_0_HCTRL_BANK1 0x00959C +#define ACP_SW2_RX_DP0_0_HCTRL_OFFSET_BANK1 0x0095A0 +#define ACP_SW2_RX_DP0_0_LANE_CTRL_BANK1 0x0095A4 +#define ACP_SW2_RX_DP0_0_CHANNEL_ENABLE_BANK1 0x0095A8 +#define ACP_SW2_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0095AC +#define ACP_SW2_RX_DP0_1_SAMPLEINTERVAL_BANK0 0x0095B0 +#define ACP_SW2_RX_DP0_1_HCTRL_BANK0 0x0095B4 +#define ACP_SW2_RX_DP0_1_HCTRL_OFFSET_BANK0 0x0095B8 +#define ACP_SW2_RX_DP0_1_LANE_CTRL_BANK0 0x0095BC +#define ACP_SW2_RX_DP0_1_CHANNEL_ENABLE_BANK0 0x0095C0 +#define ACP_SW2_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0095C4 +#define ACP_SW2_RX_DP0_1_SAMPLEINTERVAL_BANK1 0x0095C8 +#define ACP_SW2_RX_DP0_1_HCTRL_BANK1 0x0095CC +#define ACP_SW2_RX_DP0_1_HCTRL_OFFSET_BANK1 0x0095D0 +#define ACP_SW2_RX_DP0_1_LANE_CTRL_BANK1 0x0095D4 +#define ACP_SW2_RX_DP0_1_CHANNEL_ENABLE_BANK1 0x0095D8 +#define ACP_SW2_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0095DC +#define ACP_SW2_RX_DP0_2_SAMPLEINTERVAL_BANK0 0x0095E0 +#define ACP_SW2_RX_DP0_2_HCTRL_BANK0 0x0095E4 +#define ACP_SW2_RX_DP0_2_HCTRL_OFFSET_BANK0 0x0095E8 +#define ACP_SW2_RX_DP0_2_LANE_CTRL_BANK0 0x0095EC +#define ACP_SW2_RX_DP0_2_CHANNEL_ENABLE_BANK0 0x0095F0 +#define ACP_SW2_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0095F4 +#define ACP_SW2_RX_DP0_2_SAMPLEINTERVAL_BANK1 0x0095F8 +#define ACP_SW2_RX_DP0_2_HCTRL_BANK1 0x0095FC +#define ACP_SW2_RX_DP0_2_HCTRL_OFFSET_BANK1 0x009600 +#define ACP_SW2_RX_DP0_2_LANE_CTRL_BANK1 0x009604 +#define ACP_SW2_RX_DP0_2_CHANNEL_ENABLE_BANK1 0x009608 +#define ACP_SW2_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00960C +#define ACP_SW2_RX_DP0_3_SAMPLEINTERVAL_BANK0 0x009610 +#define ACP_SW2_RX_DP0_3_HCTRL_BANK0 0x009614 +#define ACP_SW2_RX_DP0_3_HCTRL_OFFSET_BANK0 0x009618 +#define ACP_SW2_RX_DP0_3_LANE_CTRL_BANK0 0x00961C +#define ACP_SW2_RX_DP0_3_CHANNEL_ENABLE_BANK0 0x009620 +#define ACP_SW2_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009624 +#define ACP_SW2_RX_DP0_3_SAMPLEINTERVAL_BANK1 0x009628 +#define ACP_SW2_RX_DP0_3_HCTRL_BANK1 0x00962C +#define ACP_SW2_RX_DP0_3_HCTRL_OFFSET_BANK1 0x009630 +#define ACP_SW2_RX_DP0_3_LANE_CTRL_BANK1 0x009634 +#define ACP_SW2_RX_DP0_3_CHANNEL_ENABLE_BANK1 0x009638 +#define ACP_SW2_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00963C +#define ACP_SW2_RX_DP1_SAMPLEINTERVAL_BANK0 0x009670 +#define ACP_SW2_RX_DP1_HCTRL_BANK0 0x009674 +#define ACP_SW2_RX_DP1_HCTRL_OFFSET_BANK0 0x009678 +#define ACP_SW2_RX_DP1_LANE_CTRL_BANK0 0x00967C +#define ACP_SW2_RX_DP1_CHANNEL_ENABLE_BANK0 0x009680 +#define ACP_SW2_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009684 +#define ACP_SW2_RX_DP1_SAMPLEINTERVAL_BANK1 0x009688 +#define ACP_SW2_RX_DP1_HCTRL_BANK1 0x00968C +#define ACP_SW2_RX_DP1_HCTRL_OFFSET_BANK1 0x009690 +#define ACP_SW2_RX_DP1_LANE_CTRL_BANK1 0x009694 +#define ACP_SW2_RX_DP1_CHANNEL_ENABLE_BANK1 0x009698 +#define ACP_SW2_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00969C +#define ACP_SW2_RX_DP2_SAMPLEINTERVAL_BANK0 0x0096A0 +#define ACP_SW2_RX_DP2_HCTRL_BANK0 0x0096A4 +#define ACP_SW2_RX_DP2_HCTRL_OFFSET_BANK0 0x0096A8 +#define ACP_SW2_RX_DP2_LANE_CTRL_BANK0 0x0096AC +#define ACP_SW2_RX_DP2_CHANNEL_ENABLE_BANK0 0x0096B0 +#define ACP_SW2_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0096B4 +#define ACP_SW2_RX_DP2_SAMPLEINTERVAL_BANK1 0x0096B8 +#define ACP_SW2_RX_DP2_HCTRL_BANK1 0x0096BC +#define ACP_SW2_RX_DP2_HCTRL_OFFSET_BANK1 0x0096C0 +#define ACP_SW2_RX_DP2_LANE_CTRL_BANK1 0x0096C4 +#define ACP_SW2_RX_DP2_CHANNEL_ENABLE_BANK1 0x0096C8 +#define ACP_SW2_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0096CC +#define ACP_SW2_RX_DP3_SAMPLEINTERVAL_BANK0 0x0096D0 +#define ACP_SW2_RX_DP3_HCTRL_BANK0 0x0096D4 +#define ACP_SW2_RX_DP3_HCTRL_OFFSET_BANK0 0x0096D8 +#define ACP_SW2_RX_DP3_LANE_CTRL_BANK0 0x0096DC +#define ACP_SW2_RX_DP3_CHANNEL_ENABLE_BANK0 0x0096E0 +#define ACP_SW2_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0096E4 +#define ACP_SW2_RX_DP3_SAMPLEINTERVAL_BANK1 0x0096E8 +#define ACP_SW2_RX_DP3_HCTRL_BANK1 0x0096EC +#define ACP_SW2_RX_DP3_HCTRL_OFFSET_BANK1 0x0096F0 +#define ACP_SW2_RX_DP3_LANE_CTRL_BANK1 0x0096F4 +#define ACP_SW2_RX_DP3_CHANNEL_ENABLE_BANK1 0x0096F8 +#define ACP_SW2_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0096FC +#define ACP_SW2_RX_DP4_SAMPLEINTERVAL_BANK0 0x009700 +#define ACP_SW2_RX_DP4_HCTRL_BANK0 0x009704 +#define ACP_SW2_RX_DP4_HCTRL_OFFSET_BANK0 0x009708 +#define ACP_SW2_RX_DP4_LANE_CTRL_BANK0 0x00970C +#define ACP_SW2_RX_DP4_CHANNEL_ENABLE_BANK0 0x009710 +#define ACP_SW2_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009714 +#define ACP_SW2_RX_DP4_SAMPLEINTERVAL_BANK1 0x009718 +#define ACP_SW2_RX_DP4_HCTRL_BANK1 0x00971C +#define ACP_SW2_RX_DP4_HCTRL_OFFSET_BANK1 0x009720 +#define ACP_SW2_RX_DP4_LANE_CTRL_BANK1 0x009724 +#define ACP_SW2_RX_DP4_CHANNEL_ENABLE_BANK1 0x009728 +#define ACP_SW2_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00972C +#define ACP_SW2_RX_DP5_SAMPLEINTERVAL_BANK0 0x009730 +#define ACP_SW2_RX_DP5_HCTRL_BANK0 0x009734 +#define ACP_SW2_RX_DP5_HCTRL_OFFSET_BANK0 0x009738 +#define ACP_SW2_RX_DP5_LANE_CTRL_BANK0 0x00973C +#define ACP_SW2_RX_DP5_CHANNEL_ENABLE_BANK0 0x009740 +#define ACP_SW2_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009744 +#define ACP_SW2_RX_DP5_SAMPLEINTERVAL_BANK1 0x009748 +#define ACP_SW2_RX_DP5_HCTRL_BANK1 0x00974C +#define ACP_SW2_RX_DP5_HCTRL_OFFSET_BANK1 0x009750 +#define ACP_SW2_RX_DP5_LANE_CTRL_BANK1 0x009754 +#define ACP_SW2_RX_DP5_CHANNEL_ENABLE_BANK1 0x009758 +#define ACP_SW2_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00975C +#define ACP_SW2_RX_DP6_SAMPLEINTERVAL_BANK0 0x009760 +#define ACP_SW2_RX_DP6_HCTRL_BANK0 0x009764 +#define ACP_SW2_RX_DP6_HCTRL_OFFSET_BANK0 0x009768 +#define ACP_SW2_RX_DP6_LANE_CTRL_BANK0 0x00976C +#define ACP_SW2_RX_DP6_CHANNEL_ENABLE_BANK0 0x009770 +#define ACP_SW2_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x009774 +#define ACP_SW2_RX_DP6_SAMPLEINTERVAL_BANK1 0x009778 +#define ACP_SW2_RX_DP6_HCTRL_BANK1 0x00977C +#define ACP_SW2_RX_DP6_HCTRL_OFFSET_BANK1 0x009780 +#define ACP_SW2_RX_DP6_LANE_CTRL_BANK1 0x009784 +#define ACP_SW2_RX_DP6_CHANNEL_ENABLE_BANK1 0x009788 +#define ACP_SW2_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00978C +#define ACP_SW2_RX_DP7_SAMPLEINTERVAL_BANK0 0x009790 +#define ACP_SW2_RX_DP7_HCTRL_BANK0 0x009794 +#define ACP_SW2_RX_DP7_HCTRL_OFFSET_BANK0 0x009798 +#define ACP_SW2_RX_DP7_LANE_CTRL_BANK0 0x00979C +#define ACP_SW2_RX_DP7_CHANNEL_ENABLE_BANK0 0x0097A0 +#define ACP_SW2_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x0097A4 +#define ACP_SW2_RX_DP7_SAMPLEINTERVAL_BANK1 0x0097A8 +#define ACP_SW2_RX_DP7_HCTRL_BANK1 0x0097AC +#define ACP_SW2_RX_DP7_HCTRL_OFFSET_BANK1 0x0097B0 +#define ACP_SW2_RX_DP7_LANE_CTRL_BANK1 0x0097B4 +#define ACP_SW2_RX_DP7_CHANNEL_ENABLE_BANK1 0x0097B8 +#define ACP_SW2_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x0097BC +#define ACP_SW2_BPT_PORT_EN 0x0097C0 +#define ACP_SW2_BPT_PORT_EN_STATUS 0x0097C4 +#define ACP_SW2_BPT_PORT_FRAME_FORMAT 0x0097C8 +#define ACP_SW2_BPT_PORT_SAMPLEINTERVAL_BANK0 0x0097CC +#define ACP_SW2_BPT_PORT_HCTRL_BANK0 0x0097D0 +#define ACP_SW2_BPT_PORT_OFFSET_BANK0 0x0097D4 +#define ACP_SW2_BPT_PORT_LANE_SELECT_BANK0 0x0097D8 +#define ACP_SW2_BPT_PORT_CHANNEL_ENABLE_BANK0 0x0097DC +#define ACP_SW2_BPT_PORT_SAMPLEINTERVAL_BANK1 0x0097E0 +#define ACP_SW2_BPT_PORT_HCTRL_BANK1 0x0097E4 +#define ACP_SW2_BPT_PORT_OFFSET_BANK1 0x0097E8 +#define ACP_SW2_BPT_PORT_LANE_SELECT_BANK1 0x0097EC +#define ACP_SW2_BPT_PORT_CHANNEL_ENABLE_BANK1 0x0097F0 +#define ACP_SW2_BPT_PORT_FIRST_BYTE_ADDR 0x0097F4 +#define ACP_SW2_CLK_RESUME_CTRL 0x0097F8 +#define ACP_SW2_CLK_RESUME_DELAY_CNTR 0x0097FC +#define ACP_SW2_BUS_RESET_CTRL 0x009800 +#define ACP_SW2_PRBS_ERR_STATUS 0x009804 +#define ACP_SW2_WALLCLK_MISC 0x009808 +#define ACP_SW2_WALL_CLK_COUNTER 0x00980C +#define ACP_SW2_PING_STATUS_REGISTER_LOW 0x009810 +#define ACP_SW2_PING_STATUS_REGISTER_HIGH 0x009814 +#define ACP_SW2_PING_STATUS_CURRENT_BANK_SEL 0x009818 +#define ACP_SW2_TZD_CHANGE 0x00981C +#define ACP_SW2_WALLCLK_INTR_CNTL 0x009820 + +#define ACP_SW3_GLOBAL_CAPABILITIES 0x00AE00 +#define ACP_SW3_RX_DMA0_RINGBUFADDR 0x00AE04 +#define ACP_SW3_RX_DMA0_RINGBUFSIZE 0x00AE08 +#define ACP_SW3_RX_DMA0_FIFOADDR 0x00AE0C +#define ACP_SW3_RX_DMA0_FIFOSIZE 0x00AE10 +#define ACP_SW3_RX_DMA0_BURST_SIZE 0x00AE14 +#define ACP_SW3_RX_DMA0_LINKPOSITIONCNTR 0x00AE18 +#define ACP_SW3_RX_DMA0_LINEARPOSITIONCNTR_HIGH 0x00AE1C +#define ACP_SW3_RX_DMA0_LINEARPOSITIONCNTR_LOW 0x00AE20 +#define ACP_SW3_RX_DMA0_INTR_WATERMARK_SIZE 0x00AE24 +#define ACP_SW3_RX_DMA1_RINGBUFADDR 0x00AE28 +#define ACP_SW3_RX_DMA1_RINGBUFSIZE 0x00AE2C +#define ACP_SW3_RX_DMA1_FIFOADDR 0x00AE30 +#define ACP_SW3_RX_DMA1_FIFOSIZE 0x00AE34 +#define ACP_SW3_RX_DMA1_BURST_SIZE 0x00AE38 +#define ACP_SW3_RX_DMA1_LINKPOSITIONCNTR 0x00AE3C +#define ACP_SW3_RX_DMA1_LINEARPOSITIONCNTR_HIGH 0x00AE40 +#define ACP_SW3_RX_DMA1_LINEARPOSITIONCNTR_LOW 0x00AE44 +#define ACP_SW3_RX_DMA1_INTR_WATERMARK_SIZE 0x00AE48 +#define ACP_SW3_RX_DMA2_RINGBUFADDR 0x00AE4C +#define ACP_SW3_RX_DMA2_RINGBUFSIZE 0x00AE50 +#define ACP_SW3_RX_DMA2_FIFOADDR 0x00AE54 +#define ACP_SW3_RX_DMA2_FIFOSIZE 0x00AE58 +#define ACP_SW3_RX_DMA2_BURST_SIZE 0x00AE5C +#define ACP_SW3_RX_DMA2_LINKPOSITIONCNTR 0x00AE60 +#define ACP_SW3_RX_DMA2_LINEARPOSITIONCNTR_HIGH 0x00AE64 +#define ACP_SW3_RX_DMA2_LINEARPOSITIONCNTR_LOW 0x00AE68 +#define ACP_SW3_RX_DMA2_INTR_WATERMARK_SIZE 0x00AE6C +#define ACP_SW3_RX_DMA3_RINGBUFADDR 0x00AE70 +#define ACP_SW3_RX_DMA3_RINGBUFSIZE 0x00AE74 +#define ACP_SW3_RX_DMA3_FIFOADDR 0x00AE78 +#define ACP_SW3_RX_DMA3_FIFOSIZE 0x00AE7C +#define ACP_SW3_RX_DMA3_BURST_SIZE 0x00AE80 +#define ACP_SW3_RX_DMA3_LINKPOSITIONCNTR 0x00AE84 +#define ACP_SW3_RX_DMA3_LINEARPOSITIONCNTR_HIGH 0x00AE88 +#define ACP_SW3_RX_DMA3_LINEARPOSITIONCNTR_LOW 0x00AE8C +#define ACP_SW3_RX_DMA3_INTR_WATERMARK_SIZE 0x00AE90 +#define ACP_SW3_RX_DMA4_RINGBUFADDR 0x00AE94 +#define ACP_SW3_RX_DMA4_RINGBUFSIZE 0x00AE98 +#define ACP_SW3_RX_DMA4_FIFOADDR 0x00AE9C +#define ACP_SW3_RX_DMA4_FIFOSIZE 0x00AEA0 +#define ACP_SW3_RX_DMA4_BURST_SIZE 0x00AEA4 +#define ACP_SW3_RX_DMA4_LINKPOSITIONCNTR 0x00AEA8 +#define ACP_SW3_RX_DMA4_LINEARPOSITIONCNTR_HIGH 0x00AEAC +#define ACP_SW3_RX_DMA4_LINEARPOSITIONCNTR_LOW 0x00AEB0 +#define ACP_SW3_RX_DMA4_INTR_WATERMARK_SIZE 0x00AEB4 +#define ACP_SW3_RX_DMA5_RINGBUFADDR 0x00AEB8 +#define ACP_SW3_RX_DMA5_RINGBUFSIZE 0x00AEBC +#define ACP_SW3_RX_DMA5_FIFOADDR 0x00AEC0 +#define ACP_SW3_RX_DMA5_FIFOSIZE 0x00AEC4 +#define ACP_SW3_RX_DMA5_BURST_SIZE 0x00AEC8 +#define ACP_SW3_RX_DMA5_LINKPOSITIONCNTR 0x00AECC +#define ACP_SW3_RX_DMA5_LINEARPOSITIONCNTR_HIGH 0x00AED0 +#define ACP_SW3_RX_DMA5_LINEARPOSITIONCNTR_LOW 0x00AED4 +#define ACP_SW3_RX_DMA5_INTR_WATERMARK_SIZE 0x00AED8 +#define ACP_SW3_RX_DMA6_RINGBUFADDR 0x00AEDC +#define ACP_SW3_RX_DMA6_RINGBUFSIZE 0x00AEE0 +#define ACP_SW3_RX_DMA6_FIFOADDR 0x00AEE4 +#define ACP_SW3_RX_DMA6_FIFOSIZE 0x00AEE8 +#define ACP_SW3_RX_DMA6_BURST_SIZE 0x00AEEC +#define ACP_SW3_RX_DMA6_LINKPOSITIONCNTR 0x00AEF0 +#define ACP_SW3_RX_DMA6_LINEARPOSITIONCNTR_HIGH 0x00AEF4 +#define ACP_SW3_RX_DMA6_LINEARPOSITIONCNTR_LOW 0x00AEF8 +#define ACP_SW3_RX_DMA6_INTR_WATERMARK_SIZE 0x00AEFC +#define ACP_SW3_RX_DMA7_RINGBUFADDR 0x00AF00 +#define ACP_SW3_RX_DMA7_RINGBUFSIZE 0x00AF04 +#define ACP_SW3_RX_DMA7_FIFOADDR 0x00AF08 +#define ACP_SW3_RX_DMA7_FIFOSIZE 0x00AF0C +#define ACP_SW3_RX_DMA7_BURST_SIZE 0x00AF10 +#define ACP_SW3_RX_DMA7_LINKPOSITIONCNTR 0x00AF14 +#define ACP_SW3_RX_DMA7_LINEARPOSITIONCNTR_HIGH 0x00AF18 +#define ACP_SW3_RX_DMA7_LINEARPOSITIONCNTR_LOW 0x00AF1C +#define ACP_SW3_RX_DMA7_INTR_WATERMARK_SIZE 0x00AF20 +#define ACP_SW3_TX_DMA0_RINGBUFADDR 0x00AF24 +#define ACP_SW3_TX_DMA0_RINGBUFSIZE 0x00AF28 +#define ACP_SW3_TX_DMA0_FIFOADDR 0x00AF2C +#define ACP_SW3_TX_DMA0_FIFOSIZE 0x00AF30 +#define ACP_SW3_TX_DMA0_BURST_SIZE 0x00AF34 +#define ACP_SW3_TX_DMA0_LINKPOSITIONCNTR 0x00AF38 +#define ACP_SW3_TX_DMA0_LINEARPOSITIONCNTR_HIGH 0x00AF3C +#define ACP_SW3_TX_DMA0_LINEARPOSITIONCNTR_LOW 0x00AF40 +#define ACP_SW3_TX_DMA0_INTR_WATERMARK_SIZE 0x00AF44 +#define ACP_SW3_TX_DMA1_RINGBUFADDR 0x00AF48 +#define ACP_SW3_TX_DMA1_RINGBUFSIZE 0x00AF4C +#define ACP_SW3_TX_DMA1_FIFOADDR 0x00AF50 +#define ACP_SW3_TX_DMA1_FIFOSIZE 0x00AF54 +#define ACP_SW3_TX_DMA1_BURST_SIZE 0x00AF58 +#define ACP_SW3_TX_DMA1_LINKPOSITIONCNTR 0x00AF5C +#define ACP_SW3_TX_DMA1_LINEARPOSITIONCNTR_HIGH 0x00AF60 +#define ACP_SW3_TX_DMA1_LINEARPOSITIONCNTR_LOW 0x00AF64 +#define ACP_SW3_TX_DMA1_INTR_WATERMARK_SIZE 0x00AF68 +#define ACP_SW3_TX_DMA2_RINGBUFADDR 0x00AF6C +#define ACP_SW3_TX_DMA2_RINGBUFSIZE 0x00AF70 +#define ACP_SW3_TX_DMA2_FIFOADDR 0x00AF74 +#define ACP_SW3_TX_DMA2_FIFOSIZE 0x00AF78 +#define ACP_SW3_TX_DMA2_BURST_SIZE 0x00AF7C +#define ACP_SW3_TX_DMA2_LINKPOSITIONCNTR 0x00AF80 +#define ACP_SW3_TX_DMA2_LINEARPOSITIONCNTR_HIGH 0x00AF84 +#define ACP_SW3_TX_DMA2_LINEARPOSITIONCNTR_LOW 0x00AF88 +#define ACP_SW3_TX_DMA2_INTR_WATERMARK_SIZE 0x00AF8C +#define ACP_SW3_TX_DMA3_RINGBUFADDR 0x00AF90 +#define ACP_SW3_TX_DMA3_RINGBUFSIZE 0x00AF94 +#define ACP_SW3_TX_DMA3_FIFOADDR 0x00AF98 +#define ACP_SW3_TX_DMA3_FIFOSIZE 0x00AF9C +#define ACP_SW3_TX_DMA3_BURST_SIZE 0x00AFA0 +#define ACP_SW3_TX_DMA3_LINKPOSITIONCNTR 0x00AFA4 +#define ACP_SW3_TX_DMA3_LINEARPOSITIONCNTR_HIGH 0x00AFA8 +#define ACP_SW3_TX_DMA3_LINEARPOSITIONCNTR_LOW 0x00AFAC +#define ACP_SW3_TX_DMA3_INTR_WATERMARK_SIZE 0x00AFB0 +#define ACP_SW3_TX_DMA4_RINGBUFADDR 0x00AFB4 +#define ACP_SW3_TX_DMA4_RINGBUFSIZE 0x00AFB8 +#define ACP_SW3_TX_DMA4_FIFOADDR 0x00AFBC +#define ACP_SW3_TX_DMA4_FIFOSIZE 0x00AFC0 +#define ACP_SW3_TX_DMA4_BURST_SIZE 0x00AFC4 +#define ACP_SW3_TX_DMA4_LINKPOSITIONCNTR 0x00AFC8 +#define ACP_SW3_TX_DMA4_LINEARPOSITIONCNTR_HIGH 0x00AFCC +#define ACP_SW3_TX_DMA4_LINEARPOSITIONCNTR_LOW 0x00AFD0 +#define ACP_SW3_TX_DMA4_INTR_WATERMARK_SIZE 0x00AFD4 +#define ACP_SW3_TX_DMA5_RINGBUFADDR 0x00AFD8 +#define ACP_SW3_TX_DMA5_RINGBUFSIZE 0x00AFDC +#define ACP_SW3_TX_DMA5_FIFOADDR 0x00AFE0 +#define ACP_SW3_TX_DMA5_FIFOSIZE 0x00AFE4 +#define ACP_SW3_TX_DMA5_BURST_SIZE 0x00AFE8 +#define ACP_SW3_TX_DMA5_LINKPOSITIONCNTR 0x00AFEC +#define ACP_SW3_TX_DMA5_LINEARPOSITIONCNTR_HIGH 0x00AFF0 +#define ACP_SW3_TX_DMA5_LINEARPOSITIONCNTR_LOW 0x00AFF4 +#define ACP_SW3_TX_DMA5_INTR_WATERMARK_SIZE 0x00AFF8 +#define ACP_SW3_TX_DMA6_RINGBUFADDR 0x00AFFC +#define ACP_SW3_TX_DMA6_RINGBUFSIZE 0x00B000 +#define ACP_SW3_TX_DMA6_FIFOADDR 0x00B004 +#define ACP_SW3_TX_DMA6_FIFOSIZE 0x00B008 +#define ACP_SW3_TX_DMA6_BURST_SIZE 0x00B00C +#define ACP_SW3_TX_DMA6_LINKPOSITIONCNTR 0x00B010 +#define ACP_SW3_TX_DMA6_LINEARPOSITIONCNTR_HIGH 0x00B014 +#define ACP_SW3_TX_DMA6_LINEARPOSITIONCNTR_LOW 0x00B018 +#define ACP_SW3_TX_DMA6_INTR_WATERMARK_SIZE 0x00B01C +#define ACP_SW3_TX_DMA7_RINGBUFADDR 0x00B020 +#define ACP_SW3_TX_DMA7_RINGBUFSIZE 0x00B024 +#define ACP_SW3_TX_DMA7_FIFOADDR 0x00B028 +#define ACP_SW3_TX_DMA7_FIFOSIZE 0x00B02C +#define ACP_SW3_TX_DMA7_BURST_SIZE 0x00B030 +#define ACP_SW3_TX_DMA7_LINKPOSITIONCNTR 0x00B034 +#define ACP_SW3_TX_DMA7_LINEARPOSITIONCNTR_HIGH 0x00B038 +#define ACP_SW3_TX_DMA7_LINEARPOSITIONCNTR_LOW 0x00B03C +#define ACP_SW3_TX_DMA7_INTR_WATERMARK_SIZE 0x00B040 +#define ACP_SW3_RX_DMA0_POS_TRACK 0x00B044 +#define ACP_SW3_RX_DMA0_POS 0x00B048 +#define ACP_SW3_RX_DMA1_POS_TRACK 0x00B04C +#define ACP_SW3_RX_DMA1_POS 0x00B050 +#define ACP_SW3_RX_DMA2_POS_TRACK 0x00B054 +#define ACP_SW3_RX_DMA2_POS 0x00B058 +#define ACP_SW3_RX_DMA3_POS_TRACK 0x00B05C +#define ACP_SW3_RX_DMA3_POS 0x00B060 +#define ACP_SW3_RX_DMA4_POS_TRACK 0x00B064 +#define ACP_SW3_RX_DMA4_POS 0x00B068 +#define ACP_SW3_RX_DMA5_POS_TRACK 0x00B06C +#define ACP_SW3_RX_DMA5_POS 0x00B070 +#define ACP_SW3_RX_DMA6_POS_TRACK 0x00B074 +#define ACP_SW3_RX_DMA6_POS 0x00B078 +#define ACP_SW3_RX_DMA7_POS_TRACK 0x00B07C +#define ACP_SW3_RX_DMA7_POS 0x00B080 +#define ACP_SW3_TX_DMA0_POS_TRACK 0x00B084 +#define ACP_SW3_TX_DMA0_POS 0x00B088 +#define ACP_SW3_TX_DMA1_POS_TRACK 0x00B08C +#define ACP_SW3_TX_DMA1_POS 0x00B090 +#define ACP_SW3_TX_DMA2_POS_TRACK 0x00B094 +#define ACP_SW3_TX_DMA2_POS 0x00B098 +#define ACP_SW3_TX_DMA3_POS_TRACK 0x00B09C +#define ACP_SW3_TX_DMA3_POS 0x00B0A0 +#define ACP_SW3_TX_DMA4_POS_TRACK 0x00B0A4 +#define ACP_SW3_TX_DMA4_POS 0x00B0A8 +#define ACP_SW3_TX_DMA5_POS_TRACK 0x00B0AC +#define ACP_SW3_TX_DMA5_POS 0x00B0B0 +#define ACP_SW3_TX_DMA6_POS_TRACK 0x00B0B4 +#define ACP_SW3_TX_DMA6_POS 0x00B0B8 +#define ACP_SW3_TX_DMA7_POS_TRACK 0x00B0BC +#define ACP_SW3_TX_DMA7_POS 0x00B0C0 +#define ACP_SW3_FIFO_ERROR_REASON 0x00B0C4 +#define ACP_SW3_FIFO_ERROR_INTR_MASK 0x00B0C8 +#define ACP_SW3_ERROR_REASON1 0x00B0CC +#define ACP_SW3_ERROR_INTR_MASK1 0x00B0D0 +#define ACP_SW3_ERROR_REASON2 0x00B0D4 +#define ACP_SW3_ERROR_INTR_MASK2 0x00B0D8 + +#define ACP_SW3_CORB_BASE_ADDRESS 0x00B100 +#define ACP_SW3_CORB_WRITE_POINTER 0x00B104 +#define ACP_SW3_CORB_READ_POINTER 0x00B108 +#define ACP_SW3_CORB_CONTROL 0x00B10C +#define ACP_SW3_CORB_SIZE 0x00B114 +#define ACP_SW3_RIRB_BASE_ADDRESS 0x00B118 +#define ACP_SW3_RIRB_WRITE_POINTER 0x00B11C +#define ACP_SW3_RIRB_RESPONSE_INTERRUPT_COUNT 0x00B120 +#define ACP_SW3_RIRB_CONTROL 0x00B124 +#define ACP_SW3_RIRB_SIZE 0x00B128 +#define ACP_SW3_RIRB_FIFO_MIN_THDL 0x00B12C +#define ACP_SW3_IMM_CMD_UPPER_WORD 0x00B130 +#define ACP_SW3_IMM_CMD_LOWER_QWORD 0x00B134 +#define ACP_SW3_IMM_RESP_UPPER_WORD 0x00B138 +#define ACP_SW3_IMM_RESP_LOWER_QWORD 0x00B13C +#define ACP_SW3_IMM_CMD_STS 0x00B140 +#define ACP_SW3_BRA_BASE_ADDRESS 0x00B144 +#define ACP_SW3_BRA_TRANSFER_SIZE 0x00B148 +#define ACP_SW3_BRA_DMA_BUSY 0x00B14C +#define ACP_SW3_BRA_RESP 0x00B150 +#define ACP_SW3_BRA_RESP_FRAME_ADDR 0x00B154 +#define ACP_SW3_BRA_CURRENT_TRANSFER_SIZE 0x00B158 +#define ACP_SW3_STATE_CHANGE_STATUS_0TO7 0x00B15C +#define ACP_SW3_STATE_CHANGE_STATUS_8TO11 0x00B160 +#define ACP_SW3_STATE_CHANGE_STATUS_MASK_0TO7 0x00B164 +#define ACP_SW3_STATE_CHANGE_STATUS_MASK_8TO11 0x00B168 +#define ACP_SW3_CLK_FREQUENCY_CTRL_BANK0 0x00B16C +#define ACP_SW3_CLK_FREQUENCY_CTRL_BANK1 0x00B170 +#define ACP_SW3_ERROR_INTR_MASK 0x00B174 +#define ACP_SW3_PHY_TEST_MODE_DATA_OFF 0x00B178 +#define ACP_SW3_DATA_TO_PDM_EN 0x00B17C + +#define ACP_SW3_EN 0x00B200 +#define ACP_SW3_EN_STATUS 0x00B204 +#define ACP_SW3_FRAMESIZE_BANK0 0x00B208 +#define ACP_SW3_FRAMESIZE_BANK1 0x00B20C +#define ACP_SW3_SSP_COUNTER 0x00B210 +#define ACP_SW3_TX_STREAM0_EN 0x00B214 +#define ACP_SW3_TX_STREAM1_EN 0x00B218 +#define ACP_SW3_TX_STREAM2_EN 0x00B21C +#define ACP_SW3_TX_STREAM3_EN 0x00B220 +#define ACP_SW3_TX_STREAM4_EN 0x00B224 +#define ACP_SW3_TX_STREAM5_EN 0x00B228 +#define ACP_SW3_TX_STREAM6_EN 0x00B22C +#define ACP_SW3_TX_STREAM7_EN 0x00B230 +#define ACP_SW3_TX_STREAM0_EN_STATUS 0x00B234 +#define ACP_SW3_TX_STREAM1_EN_STATUS 0x00B238 +#define ACP_SW3_TX_STREAM2_EN_STATUS 0x00B23C +#define ACP_SW3_TX_STREAM3_EN_STATUS 0x00B240 +#define ACP_SW3_TX_STREAM4_EN_STATUS 0x00B244 +#define ACP_SW3_TX_STREAM5_EN_STATUS 0x00B248 +#define ACP_SW3_TX_STREAM6_EN_STATUS 0x00B24C +#define ACP_SW3_TX_STREAM7_EN_STATUS 0x00B250 +#define ACP_SW3_TX_DP0_FRAME_FORMAT 0x00B254 +#define ACP_SW3_TX_DP1_FRAME_FORMAT 0x00B258 +#define ACP_SW3_TX_DP2_FRAME_FORMAT 0x00B25C +#define ACP_SW3_TX_DP3_FRAME_FORMAT 0x00B260 +#define ACP_SW3_TX_DP4_FRAME_FORMAT 0x00B264 +#define ACP_SW3_TX_DP5_FRAME_FORMAT 0x00B268 +#define ACP_SW3_TX_DP6_FRAME_FORMAT 0x00B26C +#define ACP_SW3_TX_DP7_FRAME_FORMAT 0x00B270 +#define ACP_SW3_TX_DP0_0_SAMPLEINTERVAL_BANK0 0x00B280 +#define ACP_SW3_TX_DP0_0_HCTRL_BANK0 0x00B284 +#define ACP_SW3_TX_DP0_0_HCTRL_OFFSET_BANK0 0x00B288 +#define ACP_SW3_TX_DP0_0_LANE_CTRL_BANK0 0x00B28C +#define ACP_SW3_TX_DP0_0_CHANNEL_ENABLE_BANK0 0x00B290 +#define ACP_SW3_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B294 +#define ACP_SW3_TX_DP0_0_SAMPLEINTERVAL_BANK1 0x00B298 +#define ACP_SW3_TX_DP0_0_HCTRL_BANK1 0x00B29C +#define ACP_SW3_TX_DP0_0_HCTRL_OFFSET_BANK1 0x00B2A0 +#define ACP_SW3_TX_DP0_0_LANE_CTRL_BANK1 0x00B2A4 +#define ACP_SW3_TX_DP0_0_CHANNEL_ENABLE_BANK1 0x00B2A8 +#define ACP_SW3_TX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B2AC +#define ACP_SW3_TX_DP0_1_SAMPLEINTERVAL_BANK0 0x00B2B0 +#define ACP_SW3_TX_DP0_1_HCTRL_BANK0 0x00B2B4 +#define ACP_SW3_TX_DP0_1_HCTRL_OFFSET_BANK0 0x00B2B8 +#define ACP_SW3_TX_DP0_1_LANE_CTRL_BANK0 0x00B2BC +#define ACP_SW3_TX_DP0_1_CHANNEL_ENABLE_BANK0 0x00B2C0 +#define ACP_SW3_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B2C4 +#define ACP_SW3_TX_DP0_1_SAMPLEINTERVAL_BANK1 0x00B2C8 +#define ACP_SW3_TX_DP0_1_HCTRL_BANK1 0x00B2CC +#define ACP_SW3_TX_DP0_1_HCTRL_OFFSET_BANK1 0x00B2D0 +#define ACP_SW3_TX_DP0_1_LANE_CTRL_BANK1 0x00B2D4 +#define ACP_SW3_TX_DP0_1_CHANNEL_ENABLE_BANK1 0x00B2D8 +#define ACP_SW3_TX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B2DC +#define ACP_SW3_TX_DP0_2_SAMPLEINTERVAL_BANK0 0x00B2E0 +#define ACP_SW3_TX_DP0_2_HCTRL_BANK0 0x00B2E4 +#define ACP_SW3_TX_DP0_2_HCTRL_OFFSET_BANK0 0x00B2E8 +#define ACP_SW3_TX_DP0_2_LANE_CTRL_BANK0 0x00B2EC +#define ACP_SW3_TX_DP0_2_CHANNEL_ENABLE_BANK0 0x00B2F0 +#define ACP_SW3_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B2F4 +#define ACP_SW3_TX_DP0_2_SAMPLEINTERVAL_BANK1 0x00B2F8 +#define ACP_SW3_TX_DP0_2_HCTRL_BANK1 0x00B2FC +#define ACP_SW3_TX_DP0_2_HCTRL_OFFSET_BANK1 0x00B300 +#define ACP_SW3_TX_DP0_2_LANE_CTRL_BANK1 0x00B304 +#define ACP_SW3_TX_DP0_2_CHANNEL_ENABLE_BANK1 0x00B308 +#define ACP_SW3_TX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B30C +#define ACP_SW3_TX_DP0_3_SAMPLEINTERVAL_BANK0 0x00B310 +#define ACP_SW3_TX_DP0_3_HCTRL_BANK0 0x00B314 +#define ACP_SW3_TX_DP0_3_HCTRL_OFFSET_BANK0 0x00B318 +#define ACP_SW3_TX_DP0_3_LANE_CTRL_BANK0 0x00B31C +#define ACP_SW3_TX_DP0_3_CHANNEL_ENABLE_BANK0 0x00B320 +#define ACP_SW3_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B324 +#define ACP_SW3_TX_DP0_3_SAMPLEINTERVAL_BANK1 0x00B328 +#define ACP_SW3_TX_DP0_3_HCTRL_BANK1 0x00B32C +#define ACP_SW3_TX_DP0_3_HCTRL_OFFSET_BANK1 0x00B330 +#define ACP_SW3_TX_DP0_3_LANE_CTRL_BANK1 0x00B334 +#define ACP_SW3_TX_DP0_3_CHANNEL_ENABLE_BANK1 0x00B338 +#define ACP_SW3_TX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B33C +#define ACP_SW3_TX_DP1_SAMPLEINTERVAL_BANK0 0x00B370 +#define ACP_SW3_TX_DP1_HCTRL_BANK0 0x00B374 +#define ACP_SW3_TX_DP1_HCTRL_OFFSET_BANK0 0x00B378 +#define ACP_SW3_TX_DP1_LANE_CTRL_BANK0 0x00B37C +#define ACP_SW3_TX_DP1_CHANNEL_ENABLE_BANK0 0x00B380 +#define ACP_SW3_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B384 +#define ACP_SW3_TX_DP1_SAMPLEINTERVAL_BANK1 0x00B388 +#define ACP_SW3_TX_DP1_HCTRL_BANK1 0x00B38C +#define ACP_SW3_TX_DP1_HCTRL_OFFSET_BANK1 0x00B390 +#define ACP_SW3_TX_DP1_LANE_CTRL_BANK1 0x00B394 +#define ACP_SW3_TX_DP1_CHANNEL_ENABLE_BANK1 0x00B398 +#define ACP_SW3_TX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B39C +#define ACP_SW3_TX_DP2_SAMPLEINTERVAL_BANK0 0x00B3A0 +#define ACP_SW3_TX_DP2_HCTRL_BANK0 0x00B3A4 +#define ACP_SW3_TX_DP2_HCTRL_OFFSET_BANK0 0x00B3A8 +#define ACP_SW3_TX_DP2_LANE_CTRL_BANK0 0x00B3AC +#define ACP_SW3_TX_DP2_CHANNEL_ENABLE_BANK0 0x00B3B0 +#define ACP_SW3_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B3B4 +#define ACP_SW3_TX_DP2_SAMPLEINTERVAL_BANK1 0x00B3B8 +#define ACP_SW3_TX_DP2_HCTRL_BANK1 0x00B3BC +#define ACP_SW3_TX_DP2_HCTRL_OFFSET_BANK1 0x00B3C0 +#define ACP_SW3_TX_DP2_LANE_CTRL_BANK1 0x00B3C4 +#define ACP_SW3_TX_DP2_CHANNEL_ENABLE_BANK1 0x00B3C8 +#define ACP_SW3_TX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B3CC +#define ACP_SW3_TX_DP3_SAMPLEINTERVAL_BANK0 0x00B3D0 +#define ACP_SW3_TX_DP3_HCTRL_BANK0 0x00B3D4 +#define ACP_SW3_TX_DP3_HCTRL_OFFSET_BANK0 0x00B3D8 +#define ACP_SW3_TX_DP3_LANE_CTRL_BANK0 0x00B3DC +#define ACP_SW3_TX_DP3_CHANNEL_ENABLE_BANK0 0x00B3E0 +#define ACP_SW3_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B3E4 +#define ACP_SW3_TX_DP3_SAMPLEINTERVAL_BANK1 0x00B3E8 +#define ACP_SW3_TX_DP3_HCTRL_BANK1 0x00B3EC +#define ACP_SW3_TX_DP3_HCTRL_OFFSET_BANK1 0x00B3F0 +#define ACP_SW3_TX_DP3_LANE_CTRL_BANK1 0x00B3F4 +#define ACP_SW3_TX_DP3_CHANNEL_ENABLE_BANK1 0x00B3F8 +#define ACP_SW3_TX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B3FC +#define ACP_SW3_TX_DP4_SAMPLEINTERVAL_BANK0 0x00B400 +#define ACP_SW3_TX_DP4_HCTRL_BANK0 0x00B404 +#define ACP_SW3_TX_DP4_HCTRL_OFFSET_BANK0 0x00B408 +#define ACP_SW3_TX_DP4_LANE_CTRL_BANK0 0x00B40C +#define ACP_SW3_TX_DP4_CHANNEL_ENABLE_BANK0 0x00B410 +#define ACP_SW3_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B414 +#define ACP_SW3_TX_DP4_SAMPLEINTERVAL_BANK1 0x00B418 +#define ACP_SW3_TX_DP4_HCTRL_BANK1 0x00B41C +#define ACP_SW3_TX_DP4_HCTRL_OFFSET_BANK1 0x00B420 +#define ACP_SW3_TX_DP4_LANE_CTRL_BANK1 0x00B424 +#define ACP_SW3_TX_DP4_CHANNEL_ENABLE_BANK1 0x00B428 +#define ACP_SW3_TX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B42C +#define ACP_SW3_TX_DP5_SAMPLEINTERVAL_BANK0 0x00B430 +#define ACP_SW3_TX_DP5_HCTRL_BANK0 0x00B434 +#define ACP_SW3_TX_DP5_HCTRL_OFFSET_BANK0 0x00B438 +#define ACP_SW3_TX_DP5_LANE_CTRL_BANK0 0x00B43C +#define ACP_SW3_TX_DP5_CHANNEL_ENABLE_BANK0 0x00B440 +#define ACP_SW3_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B444 +#define ACP_SW3_TX_DP5_SAMPLEINTERVAL_BANK1 0x00B448 +#define ACP_SW3_TX_DP5_HCTRL_BANK1 0x00B44C +#define ACP_SW3_TX_DP5_HCTRL_OFFSET_BANK1 0x00B450 +#define ACP_SW3_TX_DP5_LANE_CTRL_BANK1 0x00B454 +#define ACP_SW3_TX_DP5_CHANNEL_ENABLE_BANK1 0x00B458 +#define ACP_SW3_TX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B45C +#define ACP_SW3_TX_DP6_SAMPLEINTERVAL_BANK0 0x00B460 +#define ACP_SW3_TX_DP6_HCTRL_BANK0 0x00B464 +#define ACP_SW3_TX_DP6_HCTRL_OFFSET_BANK0 0x00B468 +#define ACP_SW3_TX_DP6_LANE_CTRL_BANK0 0x00B46C +#define ACP_SW3_TX_DP6_CHANNEL_ENABLE_BANK0 0x00B470 +#define ACP_SW3_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B474 +#define ACP_SW3_TX_DP6_SAMPLEINTERVAL_BANK1 0x00B478 +#define ACP_SW3_TX_DP6_HCTRL_BANK1 0x00B47C +#define ACP_SW3_TX_DP6_HCTRL_OFFSET_BANK1 0x00B480 +#define ACP_SW3_TX_DP6_LANE_CTRL_BANK1 0x00B484 +#define ACP_SW3_TX_DP6_CHANNEL_ENABLE_BANK1 0x00B488 +#define ACP_SW3_TX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B48C +#define ACP_SW3_TX_DP7_SAMPLEINTERVAL_BANK0 0x00B490 +#define ACP_SW3_TX_DP7_HCTRL_BANK0 0x00B494 +#define ACP_SW3_TX_DP7_HCTRL_OFFSET_BANK0 0x00B498 +#define ACP_SW3_TX_DP7_LANE_CTRL_BANK0 0x00B49C +#define ACP_SW3_TX_DP7_CHANNEL_ENABLE_BANK0 0x00B4A0 +#define ACP_SW3_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B4A4 +#define ACP_SW3_TX_DP7_SAMPLEINTERVAL_BANK1 0x00B4A8 +#define ACP_SW3_TX_DP7_HCTRL_BANK1 0x00B4AC +#define ACP_SW3_TX_DP7_HCTRL_OFFSET_BANK1 0x00B4B0 +#define ACP_SW3_TX_DP7_LANE_CTRL_BANK1 0x00B4B4 +#define ACP_SW3_TX_DP7_CHANNEL_ENABLE_BANK1 0x00B4B8 +#define ACP_SW3_TX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B4BC +#define ACP_SW3_RX_STREAM0_EN 0x00B514 +#define ACP_SW3_RX_STREAM1_EN 0x00B518 +#define ACP_SW3_RX_STREAM2_EN 0x00B51C +#define ACP_SW3_RX_STREAM3_EN 0x00B520 +#define ACP_SW3_RX_STREAM4_EN 0x00B524 +#define ACP_SW3_RX_STREAM5_EN 0x00B528 +#define ACP_SW3_RX_STREAM6_EN 0x00B52C +#define ACP_SW3_RX_STREAM7_EN 0x00B530 +#define ACP_SW3_RX_STREAM0_EN_STATUS 0x00B534 +#define ACP_SW3_RX_STREAM1_EN_STATUS 0x00B538 +#define ACP_SW3_RX_STREAM2_EN_STATUS 0x00B53C +#define ACP_SW3_RX_STREAM3_EN_STATUS 0x00B540 +#define ACP_SW3_RX_STREAM4_EN_STATUS 0x00B544 +#define ACP_SW3_RX_STREAM5_EN_STATUS 0x00B548 +#define ACP_SW3_RX_STREAM6_EN_STATUS 0x00B54C +#define ACP_SW3_RX_STREAM7_EN_STATUS 0x00B550 +#define ACP_SW3_RX_DP0_FRAME_FORMAT 0x00B554 +#define ACP_SW3_RX_DP1_FRAME_FORMAT 0x00B558 +#define ACP_SW3_RX_DP2_FRAME_FORMAT 0x00B55C +#define ACP_SW3_RX_DP3_FRAME_FORMAT 0x00B560 +#define ACP_SW3_RX_DP4_FRAME_FORMAT 0x00B564 +#define ACP_SW3_RX_DP5_FRAME_FORMAT 0x00B568 +#define ACP_SW3_RX_DP6_FRAME_FORMAT 0x00B56C +#define ACP_SW3_RX_DP7_FRAME_FORMAT 0x00B570 +#define ACP_SW3_RX_DP0_0_SAMPLEINTERVAL_BANK0 0x00B580 +#define ACP_SW3_RX_DP0_0_HCTRL_BANK0 0x00B584 +#define ACP_SW3_RX_DP0_0_HCTRL_OFFSET_BANK0 0x00B588 +#define ACP_SW3_RX_DP0_0_LANE_CTRL_BANK0 0x00B58C +#define ACP_SW3_RX_DP0_0_CHANNEL_ENABLE_BANK0 0x00B590 +#define ACP_SW3_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B594 +#define ACP_SW3_RX_DP0_0_SAMPLEINTERVAL_BANK1 0x00B598 +#define ACP_SW3_RX_DP0_0_HCTRL_BANK1 0x00B59C +#define ACP_SW3_RX_DP0_0_HCTRL_OFFSET_BANK1 0x00B5A0 +#define ACP_SW3_RX_DP0_0_LANE_CTRL_BANK1 0x00B5A4 +#define ACP_SW3_RX_DP0_0_CHANNEL_ENABLE_BANK1 0x00B5A8 +#define ACP_SW3_RX_DP0_0_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B5AC +#define ACP_SW3_RX_DP0_1_SAMPLEINTERVAL_BANK0 0x00B5B0 +#define ACP_SW3_RX_DP0_1_HCTRL_BANK0 0x00B5B4 +#define ACP_SW3_RX_DP0_1_HCTRL_OFFSET_BANK0 0x00B5B8 +#define ACP_SW3_RX_DP0_1_LANE_CTRL_BANK0 0x00B5BC +#define ACP_SW3_RX_DP0_1_CHANNEL_ENABLE_BANK0 0x00B5C0 +#define ACP_SW3_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B5C4 +#define ACP_SW3_RX_DP0_1_SAMPLEINTERVAL_BANK1 0x00B5C8 +#define ACP_SW3_RX_DP0_1_HCTRL_BANK1 0x00B5CC +#define ACP_SW3_RX_DP0_1_HCTRL_OFFSET_BANK1 0x00B5D0 +#define ACP_SW3_RX_DP0_1_LANE_CTRL_BANK1 0x00B5D4 +#define ACP_SW3_RX_DP0_1_CHANNEL_ENABLE_BANK1 0x00B5D8 +#define ACP_SW3_RX_DP0_1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B5DC +#define ACP_SW3_RX_DP0_2_SAMPLEINTERVAL_BANK0 0x00B5E0 +#define ACP_SW3_RX_DP0_2_HCTRL_BANK0 0x00B5E4 +#define ACP_SW3_RX_DP0_2_HCTRL_OFFSET_BANK0 0x00B5E8 +#define ACP_SW3_RX_DP0_2_LANE_CTRL_BANK0 0x00B5EC +#define ACP_SW3_RX_DP0_2_CHANNEL_ENABLE_BANK0 0x00B5F0 +#define ACP_SW3_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B5F4 +#define ACP_SW3_RX_DP0_2_SAMPLEINTERVAL_BANK1 0x00B5F8 +#define ACP_SW3_RX_DP0_2_HCTRL_BANK1 0x00B5FC +#define ACP_SW3_RX_DP0_2_HCTRL_OFFSET_BANK1 0x00B600 +#define ACP_SW3_RX_DP0_2_LANE_CTRL_BANK1 0x00B604 +#define ACP_SW3_RX_DP0_2_CHANNEL_ENABLE_BANK1 0x00B608 +#define ACP_SW3_RX_DP0_2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B60C +#define ACP_SW3_RX_DP0_3_SAMPLEINTERVAL_BANK0 0x00B610 +#define ACP_SW3_RX_DP0_3_HCTRL_BANK0 0x00B614 +#define ACP_SW3_RX_DP0_3_HCTRL_OFFSET_BANK0 0x00B618 +#define ACP_SW3_RX_DP0_3_LANE_CTRL_BANK0 0x00B61C +#define ACP_SW3_RX_DP0_3_CHANNEL_ENABLE_BANK0 0x00B620 +#define ACP_SW3_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B624 +#define ACP_SW3_RX_DP0_3_SAMPLEINTERVAL_BANK1 0x00B628 +#define ACP_SW3_RX_DP0_3_HCTRL_BANK1 0x00B62C +#define ACP_SW3_RX_DP0_3_HCTRL_OFFSET_BANK1 0x00B630 +#define ACP_SW3_RX_DP0_3_LANE_CTRL_BANK1 0x00B634 +#define ACP_SW3_RX_DP0_3_CHANNEL_ENABLE_BANK1 0x00B638 +#define ACP_SW3_RX_DP0_3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B63C +#define ACP_SW3_RX_DP1_SAMPLEINTERVAL_BANK0 0x00B670 +#define ACP_SW3_RX_DP1_HCTRL_BANK0 0x00B674 +#define ACP_SW3_RX_DP1_HCTRL_OFFSET_BANK0 0x00B678 +#define ACP_SW3_RX_DP1_LANE_CTRL_BANK0 0x00B67C +#define ACP_SW3_RX_DP1_CHANNEL_ENABLE_BANK0 0x00B680 +#define ACP_SW3_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B684 +#define ACP_SW3_RX_DP1_SAMPLEINTERVAL_BANK1 0x00B688 +#define ACP_SW3_RX_DP1_HCTRL_BANK1 0x00B68C +#define ACP_SW3_RX_DP1_HCTRL_OFFSET_BANK1 0x00B690 +#define ACP_SW3_RX_DP1_LANE_CTRL_BANK1 0x00B694 +#define ACP_SW3_RX_DP1_CHANNEL_ENABLE_BANK1 0x00B698 +#define ACP_SW3_RX_DP1_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B69C +#define ACP_SW3_RX_DP2_SAMPLEINTERVAL_BANK0 0x00B6A0 +#define ACP_SW3_RX_DP2_HCTRL_BANK0 0x00B6A4 +#define ACP_SW3_RX_DP2_HCTRL_OFFSET_BANK0 0x00B6A8 +#define ACP_SW3_RX_DP2_LANE_CTRL_BANK0 0x00B6AC +#define ACP_SW3_RX_DP2_CHANNEL_ENABLE_BANK0 0x00B6B0 +#define ACP_SW3_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B6B4 +#define ACP_SW3_RX_DP2_SAMPLEINTERVAL_BANK1 0x00B6B8 +#define ACP_SW3_RX_DP2_HCTRL_BANK1 0x00B6BC +#define ACP_SW3_RX_DP2_HCTRL_OFFSET_BANK1 0x00B6C0 +#define ACP_SW3_RX_DP2_LANE_CTRL_BANK1 0x00B6C4 +#define ACP_SW3_RX_DP2_CHANNEL_ENABLE_BANK1 0x00B6C8 +#define ACP_SW3_RX_DP2_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B6CC +#define ACP_SW3_RX_DP3_SAMPLEINTERVAL_BANK0 0x00B6D0 +#define ACP_SW3_RX_DP3_HCTRL_BANK0 0x00B6D4 +#define ACP_SW3_RX_DP3_HCTRL_OFFSET_BANK0 0x00B6D8 +#define ACP_SW3_RX_DP3_LANE_CTRL_BANK0 0x00B6DC +#define ACP_SW3_RX_DP3_CHANNEL_ENABLE_BANK0 0x00B6E0 +#define ACP_SW3_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B6E4 +#define ACP_SW3_RX_DP3_SAMPLEINTERVAL_BANK1 0x00B6E8 +#define ACP_SW3_RX_DP3_HCTRL_BANK1 0x00B6EC +#define ACP_SW3_RX_DP3_HCTRL_OFFSET_BANK1 0x00B6F0 +#define ACP_SW3_RX_DP3_LANE_CTRL_BANK1 0x00B6F4 +#define ACP_SW3_RX_DP3_CHANNEL_ENABLE_BANK1 0x00B6F8 +#define ACP_SW3_RX_DP3_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B6FC +#define ACP_SW3_RX_DP4_SAMPLEINTERVAL_BANK0 0x00B700 +#define ACP_SW3_RX_DP4_HCTRL_BANK0 0x00B704 +#define ACP_SW3_RX_DP4_HCTRL_OFFSET_BANK0 0x00B708 +#define ACP_SW3_RX_DP4_LANE_CTRL_BANK0 0x00B70C +#define ACP_SW3_RX_DP4_CHANNEL_ENABLE_BANK0 0x00B710 +#define ACP_SW3_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B714 +#define ACP_SW3_RX_DP4_SAMPLEINTERVAL_BANK1 0x00B718 +#define ACP_SW3_RX_DP4_HCTRL_BANK1 0x00B71C +#define ACP_SW3_RX_DP4_HCTRL_OFFSET_BANK1 0x00B720 +#define ACP_SW3_RX_DP4_LANE_CTRL_BANK1 0x00B724 +#define ACP_SW3_RX_DP4_CHANNEL_ENABLE_BANK1 0x00B728 +#define ACP_SW3_RX_DP4_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B72C +#define ACP_SW3_RX_DP5_SAMPLEINTERVAL_BANK0 0x00B730 +#define ACP_SW3_RX_DP5_HCTRL_BANK0 0x00B734 +#define ACP_SW3_RX_DP5_HCTRL_OFFSET_BANK0 0x00B738 +#define ACP_SW3_RX_DP5_LANE_CTRL_BANK0 0x00B73C +#define ACP_SW3_RX_DP5_CHANNEL_ENABLE_BANK0 0x00B740 +#define ACP_SW3_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B744 +#define ACP_SW3_RX_DP5_SAMPLEINTERVAL_BANK1 0x00B748 +#define ACP_SW3_RX_DP5_HCTRL_BANK1 0x00B74C +#define ACP_SW3_RX_DP5_HCTRL_OFFSET_BANK1 0x00B750 +#define ACP_SW3_RX_DP5_LANE_CTRL_BANK1 0x00B754 +#define ACP_SW3_RX_DP5_CHANNEL_ENABLE_BANK1 0x00B758 +#define ACP_SW3_RX_DP5_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B75C +#define ACP_SW3_RX_DP6_SAMPLEINTERVAL_BANK0 0x00B760 +#define ACP_SW3_RX_DP6_HCTRL_BANK0 0x00B764 +#define ACP_SW3_RX_DP6_HCTRL_OFFSET_BANK0 0x00B768 +#define ACP_SW3_RX_DP6_LANE_CTRL_BANK0 0x00B76C +#define ACP_SW3_RX_DP6_CHANNEL_ENABLE_BANK0 0x00B770 +#define ACP_SW3_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B774 +#define ACP_SW3_RX_DP6_SAMPLEINTERVAL_BANK1 0x00B778 +#define ACP_SW3_RX_DP6_HCTRL_BANK1 0x00B77C +#define ACP_SW3_RX_DP6_HCTRL_OFFSET_BANK1 0x00B780 +#define ACP_SW3_RX_DP6_LANE_CTRL_BANK1 0x00B784 +#define ACP_SW3_RX_DP6_CHANNEL_ENABLE_BANK1 0x00B788 +#define ACP_SW3_RX_DP6_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B78C +#define ACP_SW3_RX_DP7_SAMPLEINTERVAL_BANK0 0x00B790 +#define ACP_SW3_RX_DP7_HCTRL_BANK0 0x00B794 +#define ACP_SW3_RX_DP7_HCTRL_OFFSET_BANK0 0x00B798 +#define ACP_SW3_RX_DP7_LANE_CTRL_BANK0 0x00B79C +#define ACP_SW3_RX_DP7_CHANNEL_ENABLE_BANK0 0x00B7A0 +#define ACP_SW3_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK0 0x00B7A4 +#define ACP_SW3_RX_DP7_SAMPLEINTERVAL_BANK1 0x00B7A8 +#define ACP_SW3_RX_DP7_HCTRL_BANK1 0x00B7AC +#define ACP_SW3_RX_DP7_HCTRL_OFFSET_BANK1 0x00B7B0 +#define ACP_SW3_RX_DP7_LANE_CTRL_BANK1 0x00B7B4 +#define ACP_SW3_RX_DP7_CHANNEL_ENABLE_BANK1 0x00B7B8 +#define ACP_SW3_RX_DP7_BLOCK_PKGMODE_GRPCTRL_BANK1 0x00B7BC +#define ACP_SW3_BPT_PORT_EN 0x00B7C0 +#define ACP_SW3_BPT_PORT_EN_STATUS 0x00B7C4 +#define ACP_SW3_BPT_PORT_FRAME_FORMAT 0x00B7C8 +#define ACP_SW3_BPT_PORT_SAMPLEINTERVAL_BANK0 0x00B7CC +#define ACP_SW3_BPT_PORT_HCTRL_BANK0 0x00B7D0 +#define ACP_SW3_BPT_PORT_OFFSET_BANK0 0x00B7D4 +#define ACP_SW3_BPT_PORT_LANE_SELECT_BANK0 0x00B7D8 +#define ACP_SW3_BPT_PORT_CHANNEL_ENABLE_BANK0 0x00B7DC +#define ACP_SW3_BPT_PORT_SAMPLEINTERVAL_BANK1 0x00B7E0 +#define ACP_SW3_BPT_PORT_HCTRL_BANK1 0x00B7E4 +#define ACP_SW3_BPT_PORT_OFFSET_BANK1 0x00B7E8 +#define ACP_SW3_BPT_PORT_LANE_SELECT_BANK1 0x00B7EC +#define ACP_SW3_BPT_PORT_CHANNEL_ENABLE_BANK1 0x00B7F0 +#define ACP_SW3_BPT_PORT_FIRST_BYTE_ADDR 0x00B7F4 +#define ACP_SW3_CLK_RESUME_CTRL 0x00B7F8 +#define ACP_SW3_CLK_RESUME_DELAY_CNTR 0x00B7FC +#define ACP_SW3_BUS_RESET_CTRL 0x00B800 +#define ACP_SW3_PRBS_ERR_STATUS 0x00B804 +#define ACP_SW3_WALLCLK_MISC 0x00B808 +#define ACP_SW3_WALL_CLK_COUNTER 0x00B80C +#define ACP_SW3_PING_STATUS_REGISTER_LOW 0x00B810 +#define ACP_SW3_PING_STATUS_REGISTER_HIGH 0x00B814 +#define ACP_SW3_PING_STATUS_CURRENT_BANK_SEL 0x00B818 +#define ACP_SW3_TZD_CHANGE 0x00B81C +#define ACP_SW3_WALLCLK_INTR_CNTL 0x00B820 + +#define ACP_PDM_ENABLE 0x002C04 +#define ACP_PDM_DMA_ENABLE 0x002C08 +#define ACP_PDM_RX_RINGBUFADDR 0x002C0C +#define ACP_PDM_RX_RINGBUFSIZE 0x002C10 +#define ACP_PDM_RX_LINKPOSITIONCNTR 0x002C14 +#define ACP_PDM_RX_LINEARPOSITIONCNTR_HIGH 0x002C18 +#define ACP_PDM_RX_LINEARPOSITIONCNTR_LOW 0x002C1C +#define ACP_PDM_RX_INTR_WATERMARK_SIZE 0x002C20 +#define ACP_PDM_FIFO_FLUSH 0x002C24 +#define ACP_PDM_NO_OF_CHANNELS 0x002C28 +#define ACP_PDM_DECIMATION_FACTOR 0x002C2C +#define ACP_PDM_VAD_CTRL 0x002C30 +#define ACP_PDM_WAKE 0x002C54 +#define ACP_PDM_BUFFER_STATUS 0x002C58 +#define ACP_PDM_MISC_CTRL 0x002C5C +#define ACP_PDM_CLK_CTRL 0x002C60 +#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x002C64 +#define ACP_PDM_ERROR_STATUS_REGISTER 0x002C68 +#define ACP_PDM_CLKDIV 0x002C6C +#define ACP_PDM_WALLCLK_MISC 0x002C70 +#define ACP_PDM_WALL_CLK_COUNTER 0x002C74 +#define ACP_PDM_SW_ENABLE_REG 0x002CC4 +#define ACP_PDM_SW_CTRLREG 0x002CC8 +#define ACP_PDM_WALLCLK_INTR_CNTL 0x002CCC + +#define ACP_PDM_2_ENABLE 0x002D04 +#define ACP_PDM_2_DMA_ENABLE 0x002D08 +#define ACP_PDM_2_RX_RINGBUFADDR_96K 0x002D0C +#define ACP_PDM_2_RX_RINGBUFADDR_48K 0x002D10 +#define ACP_PDM_2_RX_RINGBUFADDR_16K 0x002D14 +#define ACP_PDM_2_RX_RINGBUFSIZE_96K 0x002D18 +#define ACP_PDM_2_RX_RINGBUFSIZE_48K 0x002D1C +#define ACP_PDM_2_RX_RINGBUFSIZE_16K 0x002D20 +#define ACP_PDM_2_RX_LINKPOSITIONCNTR_96K 0x002D24 +#define ACP_PDM_2_RX_LINKPOSITIONCNTR_48K 0x002D28 +#define ACP_PDM_2_RX_LINKPOSITIONCNTR_16K 0x002D2C +#define ACP_PDM_2_RX_LINEARPOSITIONCNTR_HIGH_96K 0x002D30 +#define ACP_PDM_2_RX_LINEARPOSITIONCNTR_LOW_96K 0x002D34 +#define ACP_PDM_2_RX_LINEARPOSITIONCNTR_HIGH_48K 0x002D38 +#define ACP_PDM_2_RX_LINEARPOSITIONCNTR_LOW_48K 0x002D3C +#define ACP_PDM_2_RX_LINEARPOSITIONCNTR_HIGH_16K 0x002D40 +#define ACP_PDM_2_RX_LINEARPOSITIONCNTR_LOW_16K 0x002D44 +#define ACP_PDM_2_RX_INTR_WATERMARK_SIZE_96K 0x002D48 +#define ACP_PDM_2_RX_INTR_WATERMARK_SIZE_48K 0x002D4C +#define ACP_PDM_2_RX_INTR_WATERMARK_SIZE_16K 0x002D50 +#define ACP_PDM_2_FIFO_FLUSH_96K 0x002D54 +#define ACP_PDM_2_FIFO_FLUSH_48K 0x002D58 +#define ACP_PDM_2_FIFO_FLUSH_16K 0x002D5C +#define ACP_PDM_2_NO_OF_CHANNELS 0x002D60 +#define ACP_PDM_2_DECIMATION_FACTOR 0x002D64 +#define ACP_PDM_2_VAD_CTRL 0x002D68 +#define ACP_PDM_2_WAKE 0x002D6C +#define ACP_PDM_2_BUFFER_STATUS_96K 0x002D70 +#define ACP_PDM_2_BUFFER_STATUS_48K 0x002D74 +#define ACP_PDM_2_BUFFER_STATUS_16K 0x002D78 +#define ACP_PDM_2_MISC_CTRL 0x002D7C +#define ACP_PDM_2_CLK_CTRL 0x002D80 +#define ACP_PDM_2_VAD_DYNAMIC_CLK_GATING_EN 0x002D84 +#define ACP_PDM_2_ERROR_STATUS_REGISTER 0x002D8C +#define ACP_PDM_2_CLKDIV 0x002D90 +#define ACP_PDM_2_WALLCLK_MISC 0x002D94 +#define ACP_PDM_2_WALL_CLK_COUNTER 0x002D98 +#define ACP_PDM_2_SW_ENABLE_REG 0x002D9C +#define ACP_PDM_2_SW_CTRLREG 0x002DA0 +#define ACP_PDM_2_WALLCLK_INTR_CNTL 0x002DA4 + +#define ACP_SCRATCH_REG_0 0x0010000 +#endif diff --git a/include/sound/asequencer.h b/include/sound/asequencer.h index ddbb6bf801bb..efad366736a4 100644 --- a/include/sound/asequencer.h +++ b/include/sound/asequencer.h @@ -11,9 +11,6 @@ #include <sound/asound.h> #include <uapi/sound/asequencer.h> -/* helper macro */ -#define snd_seq_event_bounce_ext_data(ev) ((void*)((char *)(ev)->data.ext.ptr + sizeof(struct snd_seq_event_bounce))) - /* * type check macros */ diff --git a/include/sound/aw88399.h b/include/sound/aw88399.h new file mode 100644 index 000000000000..a1e0de6be8ea --- /dev/null +++ b/include/sound/aw88399.h @@ -0,0 +1,621 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * linux/sound/aw88399.h -- Platform data for AW88399 + * + * Copyright (c) 2023 AWINIC Technology CO., LTD + * + * Author: Weidong Wang <wangweidong.a@awinic.com> + */ + +#ifndef __SOUND_AW88399_H +#define __SOUND_AW88399_H + +#include <linux/mutex.h> +#include <linux/workqueue.h> + +/* registers list */ +#define AW88399_ID_REG (0x00) +#define AW88399_SYSST_REG (0x01) +#define AW88399_SYSINT_REG (0x02) +#define AW88399_SYSINTM_REG (0x03) +#define AW88399_SYSCTRL_REG (0x04) +#define AW88399_SYSCTRL2_REG (0x05) +#define AW88399_I2SCTRL1_REG (0x06) +#define AW88399_I2SCTRL2_REG (0x07) +#define AW88399_I2SCTRL3_REG (0x08) +#define AW88399_DACCFG1_REG (0x09) +#define AW88399_DACCFG2_REG (0x0A) +#define AW88399_DACCFG3_REG (0x0B) +#define AW88399_DACCFG4_REG (0x0C) +#define AW88399_DACCFG5_REG (0x0D) +#define AW88399_DACCFG6_REG (0x0E) +#define AW88399_DACCFG7_REG (0x0F) +#define AW88399_MPDCFG1_REG (0x10) +#define AW88399_MPDCFG2_REG (0x11) +#define AW88399_MPDCFG3_REG (0x12) +#define AW88399_MPDCFG4_REG (0x13) +#define AW88399_PWMCTRL1_REG (0x14) +#define AW88399_PWMCTRL2_REG (0x15) +#define AW88399_PWMCTRL3_REG (0x16) +#define AW88399_I2SCFG1_REG (0x17) +#define AW88399_DBGCTRL_REG (0x18) +#define AW88399_HAGCST_REG (0x20) +#define AW88399_VBAT_REG (0x21) +#define AW88399_TEMP_REG (0x22) +#define AW88399_PVDD_REG (0x23) +#define AW88399_ISNDAT_REG (0x24) +#define AW88399_VSNDAT_REG (0x25) +#define AW88399_I2SINT_REG (0x26) +#define AW88399_I2SCAPCNT_REG (0x27) +#define AW88399_ANASTA1_REG (0x28) +#define AW88399_ANASTA2_REG (0x29) +#define AW88399_ANASTA3_REG (0x2A) +#define AW88399_TESTDET_REG (0x2B) +#define AW88399_DSMCFG1_REG (0x30) +#define AW88399_DSMCFG2_REG (0x31) +#define AW88399_DSMCFG3_REG (0x32) +#define AW88399_DSMCFG4_REG (0x33) +#define AW88399_DSMCFG5_REG (0x34) +#define AW88399_DSMCFG6_REG (0x35) +#define AW88399_DSMCFG7_REG (0x36) +#define AW88399_DSMCFG8_REG (0x37) +#define AW88399_TESTIN_REG (0x38) +#define AW88399_TESTOUT_REG (0x39) +#define AW88399_MEMTEST_REG (0x3A) +#define AW88399_VSNCTRL1_REG (0x3B) +#define AW88399_ISNCTRL1_REG (0x3C) +#define AW88399_ISNCTRL2_REG (0x3D) +#define AW88399_DSPMADD_REG (0x40) +#define AW88399_DSPMDAT_REG (0x41) +#define AW88399_WDT_REG (0x42) +#define AW88399_ACR1_REG (0x43) +#define AW88399_ACR2_REG (0x44) +#define AW88399_ASR1_REG (0x45) +#define AW88399_ASR2_REG (0x46) +#define AW88399_DSPCFG_REG (0x47) +#define AW88399_ASR3_REG (0x48) +#define AW88399_ASR4_REG (0x49) +#define AW88399_DSPVCALB_REG (0x4A) +#define AW88399_CRCCTRL_REG (0x4B) +#define AW88399_DSPDBG1_REG (0x4C) +#define AW88399_DSPDBG2_REG (0x4D) +#define AW88399_DSPDBG3_REG (0x4E) +#define AW88399_PLLCTRL1_REG (0x50) +#define AW88399_PLLCTRL2_REG (0x51) +#define AW88399_PLLCTRL3_REG (0x52) +#define AW88399_CDACTRL1_REG (0x53) +#define AW88399_CDACTRL2_REG (0x54) +#define AW88399_CDACTRL3_REG (0x55) +#define AW88399_SADCCTRL1_REG (0x56) +#define AW88399_SADCCTRL2_REG (0x57) +#define AW88399_BOPCTRL1_REG (0x58) +#define AW88399_BOPCTRL2_REG (0x5A) +#define AW88399_BOPCTRL3_REG (0x5B) +#define AW88399_BOPCTRL4_REG (0x5C) +#define AW88399_BOPCTRL5_REG (0x5D) +#define AW88399_BOPCTRL6_REG (0x5E) +#define AW88399_BOPCTRL7_REG (0x5F) +#define AW88399_BSTCTRL1_REG (0x60) +#define AW88399_BSTCTRL2_REG (0x61) +#define AW88399_BSTCTRL3_REG (0x62) +#define AW88399_BSTCTRL4_REG (0x63) +#define AW88399_BSTCTRL5_REG (0x64) +#define AW88399_BSTCTRL6_REG (0x65) +#define AW88399_BSTCTRL7_REG (0x66) +#define AW88399_BSTCTRL8_REG (0x67) +#define AW88399_BSTCTRL9_REG (0x68) +#define AW88399_BSTCTRL10_REG (0x69) +#define AW88399_CPCTRL_REG (0x6A) +#define AW88399_EFWH_REG (0x6C) +#define AW88399_EFWM2_REG (0x6D) +#define AW88399_EFWM1_REG (0x6E) +#define AW88399_EFWL_REG (0x6F) +#define AW88399_TESTCTRL1_REG (0x70) +#define AW88399_TESTCTRL2_REG (0x71) +#define AW88399_EFCTRL1_REG (0x72) +#define AW88399_EFCTRL2_REG (0x73) +#define AW88399_EFRH4_REG (0x74) +#define AW88399_EFRH3_REG (0x75) +#define AW88399_EFRH2_REG (0x76) +#define AW88399_EFRH1_REG (0x77) +#define AW88399_EFRL4_REG (0x78) +#define AW88399_EFRL3_REG (0x79) +#define AW88399_EFRL2_REG (0x7A) +#define AW88399_EFRL1_REG (0x7B) +#define AW88399_TM_REG (0x7C) +#define AW88399_TM2_REG (0x7D) + +#define AW88399_REG_MAX (0x7E) +#define AW88399_MUTE_VOL (1023) + +#define AW88399_DSP_CFG_ADDR (0x9B00) +#define AW88399_DSP_REG_CFG_ADPZ_RA (0x9B68) +#define AW88399_DSP_FW_ADDR (0x8980) +#define AW88399_DSP_ROM_CHECK_ADDR (0x1F40) +#define AW88399_DSP_ROM_CHECK_DATA (0x4638) + +#define AW88399_CALI_RE_HBITS_MASK (~(0xFFFF0000)) +#define AW88399_CALI_RE_HBITS_SHIFT (16) + +#define AW88399_CALI_RE_LBITS_MASK (~(0xFFFF)) +#define AW88399_CALI_RE_LBITS_SHIFT (0) + +#define AW88399_I2STXEN_START_BIT (9) +#define AW88399_I2STXEN_BITS_LEN (1) +#define AW88399_I2STXEN_MASK \ + (~(((1<<AW88399_I2STXEN_BITS_LEN)-1) << AW88399_I2STXEN_START_BIT)) + +#define AW88399_I2STXEN_DISABLE (0) +#define AW88399_I2STXEN_DISABLE_VALUE \ + (AW88399_I2STXEN_DISABLE << AW88399_I2STXEN_START_BIT) + +#define AW88399_I2STXEN_ENABLE (1) +#define AW88399_I2STXEN_ENABLE_VALUE \ + (AW88399_I2STXEN_ENABLE << AW88399_I2STXEN_START_BIT) + +#define AW88399_VOL_START_BIT (0) +#define AW88399_VOL_BITS_LEN (10) +#define AW88399_VOL_MASK \ + (~(((1<<AW88399_VOL_BITS_LEN)-1) << AW88399_VOL_START_BIT)) + +#define AW88399_PWDN_START_BIT (0) +#define AW88399_PWDN_BITS_LEN (1) +#define AW88399_PWDN_MASK \ + (~(((1<<AW88399_PWDN_BITS_LEN)-1) << AW88399_PWDN_START_BIT)) + +#define AW88399_PWDN_POWER_DOWN (1) +#define AW88399_PWDN_POWER_DOWN_VALUE \ + (AW88399_PWDN_POWER_DOWN << AW88399_PWDN_START_BIT) + +#define AW88399_PWDN_WORKING (0) +#define AW88399_PWDN_WORKING_VALUE \ + (AW88399_PWDN_WORKING << AW88399_PWDN_START_BIT) + +#define AW88399_DSPBY_START_BIT (2) +#define AW88399_DSPBY_BITS_LEN (1) +#define AW88399_DSPBY_MASK \ + (~(((1<<AW88399_DSPBY_BITS_LEN)-1) << AW88399_DSPBY_START_BIT)) + +#define AW88399_DSPBY_WORKING (0) +#define AW88399_DSPBY_WORKING_VALUE \ + (AW88399_DSPBY_WORKING << AW88399_DSPBY_START_BIT) + +#define AW88399_DSPBY_BYPASS (1) +#define AW88399_DSPBY_BYPASS_VALUE \ + (AW88399_DSPBY_BYPASS << AW88399_DSPBY_START_BIT) + +#define AW88399_MEM_CLKSEL_START_BIT (3) +#define AW88399_MEM_CLKSEL_BITS_LEN (1) +#define AW88399_MEM_CLKSEL_MASK \ + (~(((1<<AW88399_MEM_CLKSEL_BITS_LEN)-1) << AW88399_MEM_CLKSEL_START_BIT)) + +#define AW88399_MEM_CLKSEL_OSCCLK (0) +#define AW88399_MEM_CLKSEL_OSCCLK_VALUE \ + (AW88399_MEM_CLKSEL_OSCCLK << AW88399_MEM_CLKSEL_START_BIT) + +#define AW88399_MEM_CLKSEL_DAPHCLK (1) +#define AW88399_MEM_CLKSEL_DAPHCLK_VALUE \ + (AW88399_MEM_CLKSEL_DAPHCLK << AW88399_MEM_CLKSEL_START_BIT) + +#define AW88399_DITHER_EN_START_BIT (15) +#define AW88399_DITHER_EN_BITS_LEN (1) +#define AW88399_DITHER_EN_MASK \ + (~(((1<<AW88399_DITHER_EN_BITS_LEN)-1) << AW88399_DITHER_EN_START_BIT)) + +#define AW88399_DITHER_EN_DISABLE (0) +#define AW88399_DITHER_EN_DISABLE_VALUE \ + (AW88399_DITHER_EN_DISABLE << AW88399_DITHER_EN_START_BIT) + +#define AW88399_DITHER_EN_ENABLE (1) +#define AW88399_DITHER_EN_ENABLE_VALUE \ + (AW88399_DITHER_EN_ENABLE << AW88399_DITHER_EN_START_BIT) + +#define AW88399_HMUTE_START_BIT (8) +#define AW88399_HMUTE_BITS_LEN (1) +#define AW88399_HMUTE_MASK \ + (~(((1<<AW88399_HMUTE_BITS_LEN)-1) << AW88399_HMUTE_START_BIT)) + +#define AW88399_HMUTE_DISABLE (0) +#define AW88399_HMUTE_DISABLE_VALUE \ + (AW88399_HMUTE_DISABLE << AW88399_HMUTE_START_BIT) + +#define AW88399_HMUTE_ENABLE (1) +#define AW88399_HMUTE_ENABLE_VALUE \ + (AW88399_HMUTE_ENABLE << AW88399_HMUTE_START_BIT) + +#define AW88399_EF_DBMD_START_BIT (2) +#define AW88399_EF_DBMD_BITS_LEN (1) +#define AW88399_EF_DBMD_MASK \ + (~(((1<<AW88399_EF_DBMD_BITS_LEN)-1) << AW88399_EF_DBMD_START_BIT)) + +#define AW88399_EF_DBMD_OR (1) +#define AW88399_EF_DBMD_OR_VALUE \ + (AW88399_EF_DBMD_OR << AW88399_EF_DBMD_START_BIT) + +#define AW88399_VDSEL_START_BIT (5) +#define AW88399_VDSEL_BITS_LEN (1) +#define AW88399_VDSEL_MASK \ + (~(((1<<AW88399_VDSEL_BITS_LEN)-1) << AW88399_VDSEL_START_BIT)) + +#define AW88399_EF_ISN_GESLP_H_START_BIT (0) +#define AW88399_EF_ISN_GESLP_H_BITS_LEN (10) +#define AW88399_EF_ISN_GESLP_H_MASK \ + (~(((1<<AW88399_EF_ISN_GESLP_H_BITS_LEN)-1) << AW88399_EF_ISN_GESLP_H_START_BIT)) + +/* EF_VSN_GESLP_H bit 9:0 (EFRH3 0x75) */ +#define AW88399_EF_VSN_GESLP_H_START_BIT (0) +#define AW88399_EF_VSN_GESLP_H_BITS_LEN (10) +#define AW88399_EF_VSN_GESLP_H_MASK \ + (~(((1<<AW88399_EF_VSN_GESLP_H_BITS_LEN)-1) << AW88399_EF_VSN_GESLP_H_START_BIT)) + +#define AW88399_EF_ISN_GESLP_L_START_BIT (0) +#define AW88399_EF_ISN_GESLP_L_BITS_LEN (10) +#define AW88399_EF_ISN_GESLP_L_MASK \ + (~(((1<<AW88399_EF_ISN_GESLP_L_BITS_LEN)-1) << AW88399_EF_ISN_GESLP_L_START_BIT)) + +/* EF_VSN_GESLP_L bit 9:0 (EFRL3 0x79) */ +#define AW88399_EF_VSN_GESLP_L_START_BIT (0) +#define AW88399_EF_VSN_GESLP_L_BITS_LEN (10) +#define AW88399_EF_VSN_GESLP_L_MASK \ + (~(((1<<AW88399_EF_VSN_GESLP_L_BITS_LEN)-1) << AW88399_EF_VSN_GESLP_L_START_BIT)) + +#define AW88399_INTERNAL_VSN_TRIM_H_START_BIT (9) +#define AW88399_INTERNAL_VSN_TRIM_H_BITS_LEN (6) +#define AW88399_INTERNAL_VSN_TRIM_H_MASK \ + (~(((1<<AW88399_INTERNAL_VSN_TRIM_H_BITS_LEN)-1) << AW88399_INTERNAL_VSN_TRIM_H_START_BIT)) + +#define AW88399_INTERNAL_VSN_TRIM_L_START_BIT (9) +#define AW88399_INTERNAL_VSN_TRIM_L_BITS_LEN (6) +#define AW88399_INTERNAL_VSN_TRIM_L_MASK \ + (~(((1<<AW88399_INTERNAL_VSN_TRIM_L_BITS_LEN)-1) << AW88399_INTERNAL_VSN_TRIM_L_START_BIT)) + +#define AW88399_RCV_MODE_START_BIT (7) +#define AW88399_RCV_MODE_BITS_LEN (1) +#define AW88399_RCV_MODE_MASK \ + (~(((1<<AW88399_RCV_MODE_BITS_LEN)-1) << AW88399_RCV_MODE_START_BIT)) + +#define AW88399_CLKI_START_BIT (4) +#define AW88399_NOCLKI_START_BIT (5) +#define AW88399_PLLI_START_BIT (0) +#define AW88399_PLLI_INT_VALUE (1) +#define AW88399_PLLI_INT_INTERRUPT \ + (AW88399_PLLI_INT_VALUE << AW88399_PLLI_START_BIT) + +#define AW88399_CLKI_INT_VALUE (1) +#define AW88399_CLKI_INT_INTERRUPT \ + (AW88399_CLKI_INT_VALUE << AW88399_CLKI_START_BIT) + +#define AW88399_NOCLKI_INT_VALUE (1) +#define AW88399_NOCLKI_INT_INTERRUPT \ + (AW88399_NOCLKI_INT_VALUE << AW88399_NOCLKI_START_BIT) + +#define AW88399_BIT_SYSINT_CHECK \ + (AW88399_PLLI_INT_INTERRUPT | \ + AW88399_CLKI_INT_INTERRUPT | \ + AW88399_NOCLKI_INT_INTERRUPT) + +#define AW88399_CRC_CHECK_START_BIT (12) +#define AW88399_CRC_CHECK_BITS_LEN (3) +#define AW88399_CRC_CHECK_BITS_MASK \ + (~(((1<<AW88399_CRC_CHECK_BITS_LEN)-1) << AW88399_CRC_CHECK_START_BIT)) + +#define AW88399_RCV_MODE_RECEIVER (1) +#define AW88399_RCV_MODE_RECEIVER_VALUE \ + (AW88399_RCV_MODE_RECEIVER << AW88399_RCV_MODE_START_BIT) + +#define AW88399_AMPPD_START_BIT (1) +#define AW88399_AMPPD_BITS_LEN (1) +#define AW88399_AMPPD_MASK \ + (~(((1<<AW88399_AMPPD_BITS_LEN)-1) << AW88399_AMPPD_START_BIT)) + +#define AW88399_AMPPD_WORKING (0) +#define AW88399_AMPPD_WORKING_VALUE \ + (AW88399_AMPPD_WORKING << AW88399_AMPPD_START_BIT) + +#define AW88399_AMPPD_POWER_DOWN (1) +#define AW88399_AMPPD_POWER_DOWN_VALUE \ + (AW88399_AMPPD_POWER_DOWN << AW88399_AMPPD_START_BIT) + +#define AW88399_RAM_CG_BYP_START_BIT (0) +#define AW88399_RAM_CG_BYP_BITS_LEN (1) +#define AW88399_RAM_CG_BYP_MASK \ + (~(((1<<AW88399_RAM_CG_BYP_BITS_LEN)-1) << AW88399_RAM_CG_BYP_START_BIT)) + +#define AW88399_RAM_CG_BYP_WORK (0) +#define AW88399_RAM_CG_BYP_WORK_VALUE \ + (AW88399_RAM_CG_BYP_WORK << AW88399_RAM_CG_BYP_START_BIT) + +#define AW88399_RAM_CG_BYP_BYPASS (1) +#define AW88399_RAM_CG_BYP_BYPASS_VALUE \ + (AW88399_RAM_CG_BYP_BYPASS << AW88399_RAM_CG_BYP_START_BIT) + +#define AW88399_CRC_END_ADDR_START_BIT (0) +#define AW88399_CRC_END_ADDR_BITS_LEN (12) +#define AW88399_CRC_END_ADDR_MASK \ + (~(((1<<AW88399_CRC_END_ADDR_BITS_LEN)-1) << AW88399_CRC_END_ADDR_START_BIT)) + +#define AW88399_CRC_CODE_EN_START_BIT (13) +#define AW88399_CRC_CODE_EN_BITS_LEN (1) +#define AW88399_CRC_CODE_EN_MASK \ + (~(((1<<AW88399_CRC_CODE_EN_BITS_LEN)-1) << AW88399_CRC_CODE_EN_START_BIT)) + +#define AW88399_CRC_CODE_EN_DISABLE (0) +#define AW88399_CRC_CODE_EN_DISABLE_VALUE \ + (AW88399_CRC_CODE_EN_DISABLE << AW88399_CRC_CODE_EN_START_BIT) + +#define AW88399_CRC_CODE_EN_ENABLE (1) +#define AW88399_CRC_CODE_EN_ENABLE_VALUE \ + (AW88399_CRC_CODE_EN_ENABLE << AW88399_CRC_CODE_EN_START_BIT) + +#define AW88399_CRC_CFG_EN_START_BIT (12) +#define AW88399_CRC_CFG_EN_BITS_LEN (1) +#define AW88399_CRC_CFG_EN_MASK \ + (~(((1<<AW88399_CRC_CFG_EN_BITS_LEN)-1) << AW88399_CRC_CFG_EN_START_BIT)) + +#define AW88399_CRC_CFG_EN_DISABLE (0) +#define AW88399_CRC_CFG_EN_DISABLE_VALUE \ + (AW88399_CRC_CFG_EN_DISABLE << AW88399_CRC_CFG_EN_START_BIT) + +#define AW88399_CRC_CFG_EN_ENABLE (1) +#define AW88399_CRC_CFG_EN_ENABLE_VALUE \ + (AW88399_CRC_CFG_EN_ENABLE << AW88399_CRC_CFG_EN_START_BIT) + +#define AW88399_OCDS_START_BIT (3) +#define AW88399_OCDS_OC (1) +#define AW88399_OCDS_OC_VALUE \ + (AW88399_OCDS_OC << AW88399_OCDS_START_BIT) + +#define AW88399_NOCLKS_START_BIT (5) +#define AW88399_NOCLKS_NO_CLOCK (1) +#define AW88399_NOCLKS_NO_CLOCK_VALUE \ + (AW88399_NOCLKS_NO_CLOCK << AW88399_NOCLKS_START_BIT) + +#define AW88399_SWS_START_BIT (8) +#define AW88399_SWS_SWITCHING (1) +#define AW88399_SWS_SWITCHING_VALUE \ + (AW88399_SWS_SWITCHING << AW88399_SWS_START_BIT) + +#define AW88399_BSTS_START_BIT (9) +#define AW88399_BSTS_FINISHED (1) +#define AW88399_BSTS_FINISHED_VALUE \ + (AW88399_BSTS_FINISHED << AW88399_BSTS_START_BIT) + +#define AW88399_UVLS_START_BIT (14) +#define AW88399_UVLS_NORMAL (0) +#define AW88399_UVLS_NORMAL_VALUE \ + (AW88399_UVLS_NORMAL << AW88399_UVLS_START_BIT) + +#define AW88399_BSTOCS_START_BIT (11) +#define AW88399_BSTOCS_OVER_CURRENT (1) +#define AW88399_BSTOCS_OVER_CURRENT_VALUE \ + (AW88399_BSTOCS_OVER_CURRENT << AW88399_BSTOCS_START_BIT) + +#define AW88399_OTHS_START_BIT (1) +#define AW88399_OTHS_OT (1) +#define AW88399_OTHS_OT_VALUE \ + (AW88399_OTHS_OT << AW88399_OTHS_START_BIT) + +#define AW88399_PLLS_START_BIT (0) +#define AW88399_PLLS_LOCKED (1) +#define AW88399_PLLS_LOCKED_VALUE \ + (AW88399_PLLS_LOCKED << AW88399_PLLS_START_BIT) + +#define AW88399_CLKS_START_BIT (4) +#define AW88399_CLKS_STABLE (1) +#define AW88399_CLKS_STABLE_VALUE \ + (AW88399_CLKS_STABLE << AW88399_CLKS_START_BIT) + +#define AW88399_BIT_PLL_CHECK \ + (AW88399_CLKS_STABLE_VALUE | \ + AW88399_PLLS_LOCKED_VALUE) + +#define AW88399_BIT_SYSST_CHECK_MASK \ + (~(AW88399_UVLS_NORMAL_VALUE | \ + AW88399_BSTOCS_OVER_CURRENT_VALUE | \ + AW88399_BSTS_FINISHED_VALUE | \ + AW88399_SWS_SWITCHING_VALUE | \ + AW88399_NOCLKS_NO_CLOCK_VALUE | \ + AW88399_CLKS_STABLE_VALUE | \ + AW88399_OCDS_OC_VALUE | \ + AW88399_OTHS_OT_VALUE | \ + AW88399_PLLS_LOCKED_VALUE)) + +#define AW88399_BIT_SYSST_NOSWS_CHECK \ + (AW88399_BSTS_FINISHED_VALUE | \ + AW88399_CLKS_STABLE_VALUE | \ + AW88399_PLLS_LOCKED_VALUE) + +#define AW88399_BIT_SYSST_SWS_CHECK \ + (AW88399_BSTS_FINISHED_VALUE | \ + AW88399_CLKS_STABLE_VALUE | \ + AW88399_PLLS_LOCKED_VALUE | \ + AW88399_SWS_SWITCHING_VALUE) + +#define AW88399_CCO_MUX_START_BIT (14) +#define AW88399_CCO_MUX_BITS_LEN (1) +#define AW88399_CCO_MUX_MASK \ + (~(((1<<AW88399_CCO_MUX_BITS_LEN)-1) << AW88399_CCO_MUX_START_BIT)) + +#define AW88399_CCO_MUX_DIVIDED (0) +#define AW88399_CCO_MUX_DIVIDED_VALUE \ + (AW88399_CCO_MUX_DIVIDED << AW88399_CCO_MUX_START_BIT) + +#define AW88399_CCO_MUX_BYPASS (1) +#define AW88399_CCO_MUX_BYPASS_VALUE \ + (AW88399_CCO_MUX_BYPASS << AW88399_CCO_MUX_START_BIT) + +#define AW88399_NOISE_GATE_EN_START_BIT (13) +#define AW88399_NOISE_GATE_EN_BITS_LEN (1) +#define AW88399_NOISE_GATE_EN_MASK \ + (~(((1<<AW88399_NOISE_GATE_EN_BITS_LEN)-1) << AW88399_NOISE_GATE_EN_START_BIT)) + +#define AW88399_WDT_CNT_START_BIT (0) +#define AW88399_WDT_CNT_BITS_LEN (8) +#define AW88399_WDT_CNT_MASK \ + (~(((1<<AW88399_WDT_CNT_BITS_LEN)-1) << AW88399_WDT_CNT_START_BIT)) + +#define AW88399_REABS_START_BIT (3) +#define AW88399_REABS_BITS_LEN (1) +#define AW88399_REABS_MASK \ + (~(((1<<AW88399_REABS_BITS_LEN)-1) << AW88399_REABS_START_BIT)) + +#define AW88399_DSP_VOL_START_BIT (8) +#define AW88399_DSP_VOL_BITS_LEN (8) +#define AW88399_DSP_VOL_MASK \ + (~(((1<<AW88399_DSP_VOL_BITS_LEN)-1) << AW88399_DSP_VOL_START_BIT)) + +#define AW883XX_DSP_NG_EN_START (13) +#define AW883XX_DSP_NG_EN_LEN (1) +#define AW883XX_DSP_NG_EN_MASK \ + (~(((1 << AW883XX_DSP_NG_EN_LEN) - 1) << AW883XX_DSP_NG_EN_START)) +#define AW883XX_DSP_NG_EN_DISABLE (0) +#define AW883XX_DSP_NG_EN_DISABLE_VALUE \ + (AW883XX_DSP_NG_EN_DISABLE << AW883XX_DSP_NG_EN_START) + +#define AW88399_VOLUME_STEP_DB (64) +#define AW88399_VOL_DEFAULT_VALUE (0) +#define AW88399_DSP_ODD_NUM_BIT_TEST (0x5555) +#define AW88399_EF_ISN_GESLP_SIGN_MASK (~(1 << 9)) +#define AW88399_EF_ISN_GESLP_SIGN_NEG (0xfe00) + +#define AW88399_EF_VSN_GESLP_SIGN_MASK (~(1 << 9)) +#define AW88399_EF_VSN_GESLP_SIGN_NEG (0xfe00) + +#define AW88399_TEM4_SIGN_MASK (~(1 << 5)) +#define AW88399_TEM4_SIGN_NEG (0xffc0) + +#define AW88399_ICABLK_FACTOR (1) +#define AW88399_VCABLK_FACTOR (1) +#define AW88399_VCABLK_DAC_FACTOR (2) + +#define AW88399_VCALB_ADJ_FACTOR (12) +#define AW88399_VCALB_ACCURACY (1 << 12) + +#define AW88399_ISCAL_FACTOR (3125) +#define AW88399_VSCAL_FACTOR (18875) +#define AW88399_ISCAL_DAC_FACTOR (3125) +#define AW88399_VSCAL_DAC_FACTOR (12600) +#define AW88399_CABL_BASE_VALUE (1000) + +#define AW88399_DEV_DEFAULT_CH (0) +#define AW88399_DEV_DSP_CHECK_MAX (5) +#define AW88399_MAX_RAM_WRITE_BYTE_SIZE (128) +#define AW88399_DSP_RE_SHIFT (12) +#define AW88399_CALI_RE_MAX (15000) +#define AW88399_CALI_RE_MIN (4000) +#define AW_FW_ADDR_LEN (4) +#define AW88399_DSP_RE_TO_SHOW_RE(re, shift) (((re) * (1000)) >> (shift)) +#define AW88399_SHOW_RE_TO_DSP_RE(re, shift) (((re) << shift) / (1000)) +#define AW88399_CRC_CHECK_PASS_VAL (0x4) + +#define AW88399_CRC_CFG_BASE_ADDR (0xD80) +#define AW88399_CRC_FW_BASE_ADDR (0x4C0) +#define AW88399_ACF_FILE "aw88399_acf.bin" +#define AW88399_DEV_SYSST_CHECK_MAX (10) +#define AW88399_CHIP_ID 0x2183 + +#define AW88399_START_RETRIES (5) +#define AW88399_START_WORK_DELAY_MS (0) + +enum { + AW_EF_AND_CHECK = 0, + AW_EF_OR_CHECK, +}; + +enum { + AW88399_DEV_VDSEL_DAC = 0, + AW88399_DEV_VDSEL_VSENSE = 32, +}; + +enum { + AW88399_DSP_CRC_NA = 0, + AW88399_DSP_CRC_OK = 1, +}; + +enum { + AW88399_DSP_FW_UPDATE_OFF = 0, + AW88399_DSP_FW_UPDATE_ON = 1, +}; + +enum { + AW88399_FORCE_UPDATE_OFF = 0, + AW88399_FORCE_UPDATE_ON = 1, +}; + +enum { + AW88399_1000_US = 1000, + AW88399_2000_US = 2000, + AW88399_3000_US = 3000, + AW88399_4000_US = 4000, +}; + +enum AW88399_DEV_STATUS { + AW88399_DEV_PW_OFF = 0, + AW88399_DEV_PW_ON, +}; + +enum AW88399_DEV_FW_STATUS { + AW88399_DEV_FW_FAILED = 0, + AW88399_DEV_FW_OK, +}; + +enum AW88399_DEV_MEMCLK { + AW88399_DEV_MEMCLK_OSC = 0, + AW88399_DEV_MEMCLK_PLL = 1, +}; + +enum AW88399_DEV_DSP_CFG { + AW88399_DEV_DSP_WORK = 0, + AW88399_DEV_DSP_BYPASS = 1, +}; + +enum { + AW88399_NOT_RCV_MODE = 0, + AW88399_RCV_MODE = 1, +}; + +enum { + AW88399_SYNC_START = 0, + AW88399_ASYNC_START, +}; + +struct aw_device; +struct aw_container; +struct aw_cali_desc; +struct gpio_desc; +struct i2c_client; +struct regmap; + +struct aw88399 { + struct aw_device *aw_pa; + struct mutex lock; + struct gpio_desc *reset_gpio; + struct delayed_work start_work; + struct regmap *regmap; + struct aw_container *aw_cfg; + + unsigned int check_val; + unsigned int crc_init_val; + unsigned int vcalb_init_val; + unsigned int dither_st; + bool bsts_unreliable; + bool fw_needs_reload; +}; + +int aw_dev_check_syspll(struct aw_device *aw_dev); +void aw_dev_dsp_enable(struct aw_device *aw_dev, bool is_enable); +int aw_dev_get_dsp_status(struct aw_device *aw_dev); +int aw_dev_set_volume(struct aw_device *aw_dev, unsigned int value); +int aw_dev_update_cali_re(struct aw_cali_desc *cali_desc); +int aw88399_dev_get_prof_name(struct aw_device *aw_dev, int index, char **prof_name); +void aw88399_dev_mute(struct aw_device *aw_dev, bool is_mute); +void aw88399_dev_set_channel(struct aw88399 *aw88399, int channel); +void aw88399_hw_reset(struct aw88399 *aw88399); +int aw88399_init(struct aw88399 *aw88399, struct i2c_client *i2c, struct regmap *regmap); +extern const struct regmap_config aw88399_remap_config; +int aw88399_request_firmware_file(struct aw88399 *aw88399); +void aw88399_start(struct aw88399 *aw88399, bool sync_start); +void aw88399_startup_work(struct work_struct *work); +int aw88399_stop(struct aw_device *aw_dev); + +#endif /* __SOUND_AW88399_H */ diff --git a/include/sound/control.h b/include/sound/control.h index e07f6b960641..909db0d0485d 100644 --- a/include/sound/control.h +++ b/include/sound/control.h @@ -7,6 +7,7 @@ * Copyright (c) by Jaroslav Kysela <perex@perex.cz> */ +#include <linux/rwsem.h> #include <linux/wait.h> #include <linux/nospec.h> #include <sound/asound.h> @@ -167,6 +168,8 @@ snd_ctl_find_id_mixer(struct snd_card *card, const char *name) int snd_ctl_create(struct snd_card *card); +extern struct rw_semaphore snd_ioctl_rwsem; + int snd_ctl_register_ioctl(snd_kctl_ioctl_func_t fcn); int snd_ctl_unregister_ioctl(snd_kctl_ioctl_func_t fcn); #ifdef CONFIG_COMPAT diff --git a/include/sound/core.h b/include/sound/core.h index 4093ec82a0a1..15be947a730e 100644 --- a/include/sound/core.h +++ b/include/sound/core.h @@ -75,6 +75,27 @@ struct snd_device { #define snd_device(n) list_entry(n, struct snd_device, list) +/* + * A simple reference counter with a wait queue; + * typically used for usage counts, and you can synchronize at finishing + * via snd_refcount_sync(), which is woken up when the refcount reaches to + * zero again. + */ +struct snd_refcount { + atomic_t count; + wait_queue_head_t waiter; +}; + +void snd_refcount_init(struct snd_refcount *ref); + +static inline void snd_refcount_get(struct snd_refcount *ref) +{ + atomic_inc(&ref->count); +} + +void snd_refcount_put(struct snd_refcount *ref); +void snd_refcount_sync(struct snd_refcount *ref); + /* main structure for soundcard */ struct snd_card { @@ -87,8 +108,8 @@ struct snd_card { char longname[80]; /* name of this soundcard */ char irq_descr[32]; /* Interrupt description */ char mixername[80]; /* mixer name */ - char components[128]; /* card components delimited with - space */ + char *components; /* card components, space-delimited */ + unsigned int components_alloc_size; /* current allocation size of components */ struct module *module; /* top-level module */ void *private_data; /* private data for soundcard */ @@ -139,15 +160,16 @@ struct snd_card { #ifdef CONFIG_PM unsigned int power_state; /* power state */ - atomic_t power_ref; wait_queue_head_t power_sleep; - wait_queue_head_t power_ref_sleep; + struct snd_refcount power_ref; #endif #if IS_ENABLED(CONFIG_SND_MIXER_OSS) struct snd_mixer_oss *mixer_oss; int mixer_oss_change_count; #endif + + unsigned char private_data_area[] __aligned(__alignof__(unsigned long long)); }; #define dev_to_snd_card(p) container_of(p, struct snd_card, card_dev) @@ -174,7 +196,7 @@ static inline void snd_power_change_state(struct snd_card *card, unsigned int st */ static inline void snd_power_ref(struct snd_card *card) { - atomic_inc(&card->power_ref); + snd_refcount_get(&card->power_ref); } /** @@ -183,8 +205,7 @@ static inline void snd_power_ref(struct snd_card *card) */ static inline void snd_power_unref(struct snd_card *card) { - if (atomic_dec_and_test(&card->power_ref)) - wake_up(&card->power_ref_sleep); + snd_refcount_put(&card->power_ref); } /** @@ -196,7 +217,7 @@ static inline void snd_power_unref(struct snd_card *card) */ static inline void snd_power_sync_ref(struct snd_card *card) { - wait_event(card->power_ref_sleep, !atomic_read(&card->power_ref)); + snd_refcount_sync(&card->power_ref); } /* init.c */ @@ -317,6 +338,17 @@ static inline void snd_card_unref(struct snd_card *card) put_device(&card->card_dev); } +DEFINE_FREE(snd_card_unref, struct snd_card *, if (_T) snd_card_unref(_T)) + +/* + * For automatic error handling at probe time, assign the card like: + * struct snd_card *card __free(snd_card_free) = NULL; + * then create and process as usual. + * But, don't forget to clear to NULL at successful return for avoiding + * the unexpected cleanup! + */ +DEFINE_FREE(snd_card_free, struct snd_card *, if (_T) snd_card_free(_T)) + #define snd_card_set_dev(card, devptr) ((card)->dev = (devptr)) /* device.c */ diff --git a/include/sound/cs35l56.h b/include/sound/cs35l56.h index c3b10587cb4c..45a5df574aa6 100644 --- a/include/sound/cs35l56.h +++ b/include/sound/cs35l56.h @@ -286,6 +286,8 @@ struct snd_ctl_elem_value; #define CS35L56_MBOX_TIMEOUT_US 5000 #define CS35L56_MBOX_POLL_US 250 +#define CS35L56_FW_REQ_ACTIVE_TIMEOUT_MS 250 + #define CS35L56_PS0_POLL_US 500 #define CS35L56_PS0_TIMEOUT_US 50000 #define CS35L56_PS3_POLL_US 500 @@ -415,7 +417,6 @@ void cs35l56_wait_control_port_ready(void); void cs35l56_wait_min_reset_pulse(void); void cs35l56_system_reset(struct cs35l56_base *cs35l56_base, bool is_soundwire); int cs35l56_irq_request(struct cs35l56_base *cs35l56_base, int irq); -irqreturn_t cs35l56_irq(int irq, void *data); int cs35l56_is_fw_reload_needed(struct cs35l56_base *cs35l56_base); int cs35l56_runtime_suspend_common(struct cs35l56_base *cs35l56_base); int cs35l56_runtime_resume_common(struct cs35l56_base *cs35l56_base, bool is_soundwire); diff --git a/include/sound/dmaengine_pcm.h b/include/sound/dmaengine_pcm.h index 9472f0a966a2..81422219ed39 100644 --- a/include/sound/dmaengine_pcm.h +++ b/include/sound/dmaengine_pcm.h @@ -175,12 +175,6 @@ int snd_dmaengine_pcm_prepare_slave_config(struct snd_pcm_substream *substream, struct dmaengine_pcm { struct dma_chan *chan[SNDRV_PCM_STREAM_LAST + 1]; const struct snd_dmaengine_pcm_config *config; - struct snd_soc_component component; unsigned int flags; }; - -static inline struct dmaengine_pcm *soc_component_to_pcm(struct snd_soc_component *p) -{ - return container_of(p, struct dmaengine_pcm, component); -} #endif diff --git a/include/sound/emux_synth.h b/include/sound/emux_synth.h index 3f7f365ed248..2c0a976e00ab 100644 --- a/include/sound/emux_synth.h +++ b/include/sound/emux_synth.h @@ -125,7 +125,6 @@ struct snd_emux { */ struct snd_emux_port { - struct snd_midi_channel_set chset; struct snd_emux *emu; char port_mode; /* operation mode */ @@ -138,6 +137,7 @@ struct snd_emux_port { #if IS_ENABLED(CONFIG_SND_SEQUENCER_OSS) struct snd_seq_oss_arg *oss_arg; #endif + struct snd_midi_channel_set chset; }; /* port_mode */ diff --git a/include/sound/hda-mlink.h b/include/sound/hda-mlink.h index 4327317be6af..ba35f03576b9 100644 --- a/include/sound/hda-mlink.h +++ b/include/sound/hda-mlink.h @@ -9,6 +9,22 @@ struct hdac_bus; struct hdac_ext_link; +/** + * enum hda_bus_ml_link_type - mlink link type, used by SOF link DMA + * allocator constraints (see struct sof_intel_hda_dev). + * + * @HDA_BUS_ML_LINK_HDA: non-alt link, i.e. HDA codec or iDisp + * @HDA_BUS_ML_LINK_SDW: alt link, SoundWire + * @HDA_BUS_ML_LINK_UAOL: alt link, USB Audio Offload + * @HDA_BUS_ML_LINK_OTHER: alt link, SSP or DMIC + */ +enum hda_bus_ml_link_type { + HDA_BUS_ML_LINK_HDA, + HDA_BUS_ML_LINK_SDW, + HDA_BUS_ML_LINK_UAOL, + HDA_BUS_ML_LINK_OTHER, +}; + #if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_MLINK) int hda_bus_ml_init(struct hdac_bus *bus); @@ -49,18 +65,19 @@ int hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num); int hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y, int channel_mask, int stream_id, int dir); -void hda_bus_ml_put_all(struct hdac_bus *bus); void hda_bus_ml_reset_losidv(struct hdac_bus *bus); int hda_bus_ml_resume(struct hdac_bus *bus); int hda_bus_ml_suspend(struct hdac_bus *bus); +enum hda_bus_ml_link_type hda_bus_ml_link_get_type(struct hdac_ext_link *hlink); + struct hdac_ext_link *hdac_bus_eml_ssp_get_hlink(struct hdac_bus *bus); struct hdac_ext_link *hdac_bus_eml_dmic_get_hlink(struct hdac_bus *bus); struct hdac_ext_link *hdac_bus_eml_sdw_get_hlink(struct hdac_bus *bus); struct mutex *hdac_bus_eml_get_mutex(struct hdac_bus *bus, bool alt, int elid); -int hdac_bus_eml_enable_offload(struct hdac_bus *bus, bool alt, int elid, bool enable); +void hdac_bus_eml_enable_offload(struct hdac_bus *bus, bool alt, int elid, bool enable); /* microphone privacy specific function supported by ACE3+ architecture */ void hdac_bus_eml_set_mic_privacy_mask(struct hdac_bus *bus, bool alt, int elid, @@ -169,11 +186,13 @@ hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y, return 0; } -static inline void hda_bus_ml_put_all(struct hdac_bus *bus) { } static inline void hda_bus_ml_reset_losidv(struct hdac_bus *bus) { } static inline int hda_bus_ml_resume(struct hdac_bus *bus) { return 0; } static inline int hda_bus_ml_suspend(struct hdac_bus *bus) { return 0; } +static inline enum hda_bus_ml_link_type +hda_bus_ml_link_get_type(struct hdac_ext_link *hlink) { return HDA_BUS_ML_LINK_HDA; } + static inline struct hdac_ext_link * hdac_bus_eml_ssp_get_hlink(struct hdac_bus *bus) { return NULL; } @@ -186,10 +205,9 @@ hdac_bus_eml_sdw_get_hlink(struct hdac_bus *bus) { return NULL; } static inline struct mutex * hdac_bus_eml_get_mutex(struct hdac_bus *bus, bool alt, int elid) { return NULL; } -static inline int +static inline void hdac_bus_eml_enable_offload(struct hdac_bus *bus, bool alt, int elid, bool enable) { - return 0; } static inline void diff --git a/include/sound/hda-sdw-bpt.h b/include/sound/hda-sdw-bpt.h index 9b654c31829a..e24a549f7d49 100644 --- a/include/sound/hda-sdw-bpt.h +++ b/include/sound/hda-sdw-bpt.h @@ -27,7 +27,7 @@ int hda_sdw_bpt_send_async(struct device *dev, struct hdac_ext_stream *bpt_tx_st int hda_sdw_bpt_wait(struct device *dev, struct hdac_ext_stream *bpt_tx_stream, struct hdac_ext_stream *bpt_rx_stream); -int hda_sdw_bpt_close(struct device *dev, struct hdac_ext_stream *bpt_tx_stream, +int hda_sdw_bpt_close(struct device *dev, int link_id, struct hdac_ext_stream *bpt_tx_stream, struct snd_dma_buffer *dmab_tx_bdl, struct hdac_ext_stream *bpt_rx_stream, struct snd_dma_buffer *dmab_rx_bdl); @@ -58,7 +58,8 @@ static inline int hda_sdw_bpt_wait(struct device *dev, struct hdac_ext_stream *b return -EOPNOTSUPP; } -static inline int hda_sdw_bpt_close(struct device *dev, struct hdac_ext_stream *bpt_tx_stream, +static inline int hda_sdw_bpt_close(struct device *dev, int link_id, + struct hdac_ext_stream *bpt_tx_stream, struct snd_dma_buffer *dmab_tx_bdl, struct hdac_ext_stream *bpt_rx_stream, struct snd_dma_buffer *dmab_rx_bdl) diff --git a/include/sound/hda_codec.h b/include/sound/hda_codec.h index 24581080e26a..1d05f991f2ce 100644 --- a/include/sound/hda_codec.h +++ b/include/sound/hda_codec.h @@ -9,7 +9,7 @@ #define __SOUND_HDA_CODEC_H #include <linux/refcount.h> -#include <linux/mod_devicetable.h> +#include <linux/device-id/hda.h> #include <sound/info.h> #include <sound/control.h> #include <sound/pcm.h> @@ -188,8 +188,7 @@ struct hda_codec { /* PCM to create, set by hda_codec_ops.build_pcms callback */ struct list_head pcm_list_head; - refcount_t pcm_ref; - wait_queue_head_t remove_sleep; + struct snd_refcount pcm_ref; /* codec specific info */ void *spec; @@ -257,8 +256,10 @@ struct hda_codec { unsigned int link_down_at_suspend:1; /* link down at runtime suspend */ unsigned int relaxed_resume:1; /* don't resume forcibly for jack */ unsigned int forced_resume:1; /* forced resume for jack */ + unsigned int acomp_requested_resume:1; /* resume requested by acomp */ unsigned int no_stream_clean_at_suspend:1; /* do not clean streams at suspend */ unsigned int ctl_dev_id:1; /* old control element id build behaviour */ + unsigned int eld_jack_detect:1; /* Machine jack-detection by ELD */ unsigned long power_on_acct; unsigned long power_off_acct; @@ -438,9 +439,12 @@ void snd_hda_codec_cleanup_for_unbind(struct hda_codec *codec); static inline void snd_hda_codec_pcm_get(struct hda_pcm *pcm) { - refcount_inc(&pcm->codec->pcm_ref); + snd_refcount_get(&pcm->codec->pcm_ref); +} +static inline void snd_hda_codec_pcm_put(struct hda_pcm *pcm) +{ + snd_refcount_put(&pcm->codec->pcm_ref); } -void snd_hda_codec_pcm_put(struct hda_pcm *pcm); int snd_hda_codec_prepare(struct hda_codec *codec, struct hda_pcm_stream *hinfo, diff --git a/include/sound/hda_regmap.h b/include/sound/hda_regmap.h index 4c1b9bebbd60..e06e4847ed28 100644 --- a/include/sound/hda_regmap.h +++ b/include/sound/hda_regmap.h @@ -69,11 +69,14 @@ void snd_hdac_regmap_sync(struct hdac_device *codec); /** * snd_hdac_regmap_write - Write a verb with caching + * @codec: HD-audio codec base device * @nid: codec NID - * @reg: verb to write + * @verb: verb to write * @val: value to write * * For writing an amp value, use snd_hdac_regmap_update_amp(). + * + * Returns: %0 if successful or a negative error code. */ static inline int snd_hdac_regmap_write(struct hdac_device *codec, hda_nid_t nid, @@ -85,13 +88,16 @@ snd_hdac_regmap_write(struct hdac_device *codec, hda_nid_t nid, } /** - * snd_hda_regmap_update - Update a verb value with caching + * snd_hdac_regmap_update - Update a verb value with caching + * @codec: HD-audio codec * @nid: codec NID * @verb: verb to update * @mask: bit mask to update * @val: value to update * * For updating an amp value, use snd_hdac_regmap_update_amp(). + * + * Returns: %0 if successful or a negative error code. */ static inline int snd_hdac_regmap_update(struct hdac_device *codec, hda_nid_t nid, @@ -104,12 +110,15 @@ snd_hdac_regmap_update(struct hdac_device *codec, hda_nid_t nid, } /** - * snd_hda_regmap_read - Read a verb with caching + * snd_hdac_regmap_read - Read a verb with caching + * @codec: HD-audio codec * @nid: codec NID * @verb: verb to read * @val: pointer to store the value * * For reading an amp value, use snd_hda_regmap_get_amp(). + * + * Returns: %0 if successful or a negative error code. */ static inline int snd_hdac_regmap_read(struct hdac_device *codec, hda_nid_t nid, @@ -125,12 +134,12 @@ snd_hdac_regmap_read(struct hdac_device *codec, hda_nid_t nid, * @codec: HD-audio codec * @nid: NID to read the AMP value * @ch: channel (left=0 or right=1) - * @direction: #HDA_INPUT or #HDA_OUTPUT - * @index: the index value (only for input direction) - * @val: the pointer to store the value + * @dir: #HDA_INPUT or #HDA_OUTPUT + * @idx: the index value (only for input direction) * * Read AMP value. The volume is between 0 to 0x7f, 0x80 = mute bit. - * Returns the value or a negative error. + * + * Returns: the value or a negative error. */ static inline int snd_hdac_regmap_get_amp(struct hdac_device *codec, hda_nid_t nid, @@ -148,13 +157,14 @@ snd_hdac_regmap_get_amp(struct hdac_device *codec, hda_nid_t nid, * @codec: HD-audio codec * @nid: NID to read the AMP value * @ch: channel (left=0 or right=1) - * @direction: #HDA_INPUT or #HDA_OUTPUT + * @dir: #HDA_INPUT or #HDA_OUTPUT * @idx: the index value (only for input direction) * @mask: bit mask to set * @val: the bits value to set * * Update the AMP value with a bit mask. - * Returns 0 if the value is unchanged, 1 if changed, or a negative error. + * + * Returns: 0 if the value is unchanged, 1 if changed, or a negative error. */ static inline int snd_hdac_regmap_update_amp(struct hdac_device *codec, hda_nid_t nid, @@ -169,13 +179,12 @@ snd_hdac_regmap_update_amp(struct hdac_device *codec, hda_nid_t nid, * snd_hdac_regmap_get_amp_stereo - Read stereo AMP values * @codec: HD-audio codec * @nid: NID to read the AMP value - * @ch: channel (left=0 or right=1) - * @direction: #HDA_INPUT or #HDA_OUTPUT - * @index: the index value (only for input direction) - * @val: the pointer to store the value + * @dir: #HDA_INPUT or #HDA_OUTPUT + * @idx: the index value (only for input direction) * * Read stereo AMP values. The lower byte is left, the upper byte is right. - * Returns the value or a negative error. + * + * Returns: the value or a negative error. */ static inline int snd_hdac_regmap_get_amp_stereo(struct hdac_device *codec, hda_nid_t nid, @@ -192,14 +201,15 @@ snd_hdac_regmap_get_amp_stereo(struct hdac_device *codec, hda_nid_t nid, * snd_hdac_regmap_update_amp_stereo - update the stereo AMP value * @codec: HD-audio codec * @nid: NID to read the AMP value - * @direction: #HDA_INPUT or #HDA_OUTPUT + * @dir: #HDA_INPUT or #HDA_OUTPUT * @idx: the index value (only for input direction) * @mask: bit mask to set * @val: the bits value to set * * Update the stereo AMP value with a bit mask. * The lower byte is left, the upper byte is right. - * Returns 0 if the value is unchanged, 1 if changed, or a negative error. + * + * Returns: 0 if the value is unchanged, 1 if changed, or a negative error. */ static inline int snd_hdac_regmap_update_amp_stereo(struct hdac_device *codec, hda_nid_t nid, diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h index f11bfc6b9f42..aa994d6e6d35 100644 --- a/include/sound/hdaudio.h +++ b/include/sound/hdaudio.h @@ -11,6 +11,7 @@ #include <linux/io.h> #include <linux/io-64-nonatomic-lo-hi.h> #include <linux/iopoll.h> +#include <linux/device-id/hda.h> #include <linux/pci.h> #include <linux/pm_runtime.h> #include <linux/timecounter.h> diff --git a/include/sound/pcm.h b/include/sound/pcm.h index 76fc33dce537..02d8689354c4 100644 --- a/include/sound/pcm.h +++ b/include/sound/pcm.h @@ -145,61 +145,60 @@ struct snd_pcm_ops { #define SNDRV_PCM_RATE_8000_768000 (SNDRV_PCM_RATE_8000_384000|\ SNDRV_PCM_RATE_705600|\ SNDRV_PCM_RATE_768000) -#define _SNDRV_PCM_FMTBIT(fmt) (1ULL << (__force int)SNDRV_PCM_FORMAT_##fmt) -#define SNDRV_PCM_FMTBIT_S8 _SNDRV_PCM_FMTBIT(S8) -#define SNDRV_PCM_FMTBIT_U8 _SNDRV_PCM_FMTBIT(U8) -#define SNDRV_PCM_FMTBIT_S16_LE _SNDRV_PCM_FMTBIT(S16_LE) -#define SNDRV_PCM_FMTBIT_S16_BE _SNDRV_PCM_FMTBIT(S16_BE) -#define SNDRV_PCM_FMTBIT_U16_LE _SNDRV_PCM_FMTBIT(U16_LE) -#define SNDRV_PCM_FMTBIT_U16_BE _SNDRV_PCM_FMTBIT(U16_BE) -#define SNDRV_PCM_FMTBIT_S24_LE _SNDRV_PCM_FMTBIT(S24_LE) -#define SNDRV_PCM_FMTBIT_S24_BE _SNDRV_PCM_FMTBIT(S24_BE) -#define SNDRV_PCM_FMTBIT_U24_LE _SNDRV_PCM_FMTBIT(U24_LE) -#define SNDRV_PCM_FMTBIT_U24_BE _SNDRV_PCM_FMTBIT(U24_BE) +#define SNDRV_PCM_FMTBIT_S8 (1ULL << SNDRV_PCM_FORMAT_S8) +#define SNDRV_PCM_FMTBIT_U8 (1ULL << SNDRV_PCM_FORMAT_U8) +#define SNDRV_PCM_FMTBIT_S16_LE (1ULL << SNDRV_PCM_FORMAT_S16_LE) +#define SNDRV_PCM_FMTBIT_S16_BE (1ULL << SNDRV_PCM_FORMAT_S16_BE) +#define SNDRV_PCM_FMTBIT_U16_LE (1ULL << SNDRV_PCM_FORMAT_U16_LE) +#define SNDRV_PCM_FMTBIT_U16_BE (1ULL << SNDRV_PCM_FORMAT_U16_BE) +#define SNDRV_PCM_FMTBIT_S24_LE (1ULL << SNDRV_PCM_FORMAT_S24_LE) +#define SNDRV_PCM_FMTBIT_S24_BE (1ULL << SNDRV_PCM_FORMAT_S24_BE) +#define SNDRV_PCM_FMTBIT_U24_LE (1ULL << SNDRV_PCM_FORMAT_U24_LE) +#define SNDRV_PCM_FMTBIT_U24_BE (1ULL << SNDRV_PCM_FORMAT_U24_BE) // For S32/U32 formats, 'msbits' hardware parameter is often used to deliver information about the // available bit count in most significant bit. It's for the case of so-called 'left-justified' or // `right-padding` sample which has less width than 32 bit. -#define SNDRV_PCM_FMTBIT_S32_LE _SNDRV_PCM_FMTBIT(S32_LE) -#define SNDRV_PCM_FMTBIT_S32_BE _SNDRV_PCM_FMTBIT(S32_BE) -#define SNDRV_PCM_FMTBIT_U32_LE _SNDRV_PCM_FMTBIT(U32_LE) -#define SNDRV_PCM_FMTBIT_U32_BE _SNDRV_PCM_FMTBIT(U32_BE) -#define SNDRV_PCM_FMTBIT_FLOAT_LE _SNDRV_PCM_FMTBIT(FLOAT_LE) -#define SNDRV_PCM_FMTBIT_FLOAT_BE _SNDRV_PCM_FMTBIT(FLOAT_BE) -#define SNDRV_PCM_FMTBIT_FLOAT64_LE _SNDRV_PCM_FMTBIT(FLOAT64_LE) -#define SNDRV_PCM_FMTBIT_FLOAT64_BE _SNDRV_PCM_FMTBIT(FLOAT64_BE) -#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE _SNDRV_PCM_FMTBIT(IEC958_SUBFRAME_LE) -#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE _SNDRV_PCM_FMTBIT(IEC958_SUBFRAME_BE) -#define SNDRV_PCM_FMTBIT_MU_LAW _SNDRV_PCM_FMTBIT(MU_LAW) -#define SNDRV_PCM_FMTBIT_A_LAW _SNDRV_PCM_FMTBIT(A_LAW) -#define SNDRV_PCM_FMTBIT_IMA_ADPCM _SNDRV_PCM_FMTBIT(IMA_ADPCM) -#define SNDRV_PCM_FMTBIT_MPEG _SNDRV_PCM_FMTBIT(MPEG) -#define SNDRV_PCM_FMTBIT_GSM _SNDRV_PCM_FMTBIT(GSM) -#define SNDRV_PCM_FMTBIT_S20_LE _SNDRV_PCM_FMTBIT(S20_LE) -#define SNDRV_PCM_FMTBIT_U20_LE _SNDRV_PCM_FMTBIT(U20_LE) -#define SNDRV_PCM_FMTBIT_S20_BE _SNDRV_PCM_FMTBIT(S20_BE) -#define SNDRV_PCM_FMTBIT_U20_BE _SNDRV_PCM_FMTBIT(U20_BE) -#define SNDRV_PCM_FMTBIT_SPECIAL _SNDRV_PCM_FMTBIT(SPECIAL) -#define SNDRV_PCM_FMTBIT_S24_3LE _SNDRV_PCM_FMTBIT(S24_3LE) -#define SNDRV_PCM_FMTBIT_U24_3LE _SNDRV_PCM_FMTBIT(U24_3LE) -#define SNDRV_PCM_FMTBIT_S24_3BE _SNDRV_PCM_FMTBIT(S24_3BE) -#define SNDRV_PCM_FMTBIT_U24_3BE _SNDRV_PCM_FMTBIT(U24_3BE) -#define SNDRV_PCM_FMTBIT_S20_3LE _SNDRV_PCM_FMTBIT(S20_3LE) -#define SNDRV_PCM_FMTBIT_U20_3LE _SNDRV_PCM_FMTBIT(U20_3LE) -#define SNDRV_PCM_FMTBIT_S20_3BE _SNDRV_PCM_FMTBIT(S20_3BE) -#define SNDRV_PCM_FMTBIT_U20_3BE _SNDRV_PCM_FMTBIT(U20_3BE) -#define SNDRV_PCM_FMTBIT_S18_3LE _SNDRV_PCM_FMTBIT(S18_3LE) -#define SNDRV_PCM_FMTBIT_U18_3LE _SNDRV_PCM_FMTBIT(U18_3LE) -#define SNDRV_PCM_FMTBIT_S18_3BE _SNDRV_PCM_FMTBIT(S18_3BE) -#define SNDRV_PCM_FMTBIT_U18_3BE _SNDRV_PCM_FMTBIT(U18_3BE) -#define SNDRV_PCM_FMTBIT_G723_24 _SNDRV_PCM_FMTBIT(G723_24) -#define SNDRV_PCM_FMTBIT_G723_24_1B _SNDRV_PCM_FMTBIT(G723_24_1B) -#define SNDRV_PCM_FMTBIT_G723_40 _SNDRV_PCM_FMTBIT(G723_40) -#define SNDRV_PCM_FMTBIT_G723_40_1B _SNDRV_PCM_FMTBIT(G723_40_1B) -#define SNDRV_PCM_FMTBIT_DSD_U8 _SNDRV_PCM_FMTBIT(DSD_U8) -#define SNDRV_PCM_FMTBIT_DSD_U16_LE _SNDRV_PCM_FMTBIT(DSD_U16_LE) -#define SNDRV_PCM_FMTBIT_DSD_U32_LE _SNDRV_PCM_FMTBIT(DSD_U32_LE) -#define SNDRV_PCM_FMTBIT_DSD_U16_BE _SNDRV_PCM_FMTBIT(DSD_U16_BE) -#define SNDRV_PCM_FMTBIT_DSD_U32_BE _SNDRV_PCM_FMTBIT(DSD_U32_BE) +#define SNDRV_PCM_FMTBIT_S32_LE (1ULL << SNDRV_PCM_FORMAT_S32_LE) +#define SNDRV_PCM_FMTBIT_S32_BE (1ULL << SNDRV_PCM_FORMAT_S32_BE) +#define SNDRV_PCM_FMTBIT_U32_LE (1ULL << SNDRV_PCM_FORMAT_U32_LE) +#define SNDRV_PCM_FMTBIT_U32_BE (1ULL << SNDRV_PCM_FORMAT_U32_BE) +#define SNDRV_PCM_FMTBIT_FLOAT_LE (1ULL << SNDRV_PCM_FORMAT_FLOAT_LE) +#define SNDRV_PCM_FMTBIT_FLOAT_BE (1ULL << SNDRV_PCM_FORMAT_FLOAT_BE) +#define SNDRV_PCM_FMTBIT_FLOAT64_LE (1ULL << SNDRV_PCM_FORMAT_FLOAT64_LE) +#define SNDRV_PCM_FMTBIT_FLOAT64_BE (1ULL << SNDRV_PCM_FORMAT_FLOAT64_BE) +#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE (1ULL << SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE) +#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE (1ULL << SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE) +#define SNDRV_PCM_FMTBIT_MU_LAW (1ULL << SNDRV_PCM_FORMAT_MU_LAW) +#define SNDRV_PCM_FMTBIT_A_LAW (1ULL << SNDRV_PCM_FORMAT_A_LAW) +#define SNDRV_PCM_FMTBIT_IMA_ADPCM (1ULL << SNDRV_PCM_FORMAT_IMA_ADPCM) +#define SNDRV_PCM_FMTBIT_MPEG (1ULL << SNDRV_PCM_FORMAT_MPEG) +#define SNDRV_PCM_FMTBIT_GSM (1ULL << SNDRV_PCM_FORMAT_GSM) +#define SNDRV_PCM_FMTBIT_S20_LE (1ULL << SNDRV_PCM_FORMAT_S20_LE) +#define SNDRV_PCM_FMTBIT_U20_LE (1ULL << SNDRV_PCM_FORMAT_U20_LE) +#define SNDRV_PCM_FMTBIT_S20_BE (1ULL << SNDRV_PCM_FORMAT_S20_BE) +#define SNDRV_PCM_FMTBIT_U20_BE (1ULL << SNDRV_PCM_FORMAT_U20_BE) +#define SNDRV_PCM_FMTBIT_SPECIAL (1ULL << SNDRV_PCM_FORMAT_SPECIAL) +#define SNDRV_PCM_FMTBIT_S24_3LE (1ULL << SNDRV_PCM_FORMAT_S24_3LE) +#define SNDRV_PCM_FMTBIT_U24_3LE (1ULL << SNDRV_PCM_FORMAT_U24_3LE) +#define SNDRV_PCM_FMTBIT_S24_3BE (1ULL << SNDRV_PCM_FORMAT_S24_3BE) +#define SNDRV_PCM_FMTBIT_U24_3BE (1ULL << SNDRV_PCM_FORMAT_U24_3BE) +#define SNDRV_PCM_FMTBIT_S20_3LE (1ULL << SNDRV_PCM_FORMAT_S20_3LE) +#define SNDRV_PCM_FMTBIT_U20_3LE (1ULL << SNDRV_PCM_FORMAT_U20_3LE) +#define SNDRV_PCM_FMTBIT_S20_3BE (1ULL << SNDRV_PCM_FORMAT_S20_3BE) +#define SNDRV_PCM_FMTBIT_U20_3BE (1ULL << SNDRV_PCM_FORMAT_U20_3BE) +#define SNDRV_PCM_FMTBIT_S18_3LE (1ULL << SNDRV_PCM_FORMAT_S18_3LE) +#define SNDRV_PCM_FMTBIT_U18_3LE (1ULL << SNDRV_PCM_FORMAT_U18_3LE) +#define SNDRV_PCM_FMTBIT_S18_3BE (1ULL << SNDRV_PCM_FORMAT_S18_3BE) +#define SNDRV_PCM_FMTBIT_U18_3BE (1ULL << SNDRV_PCM_FORMAT_U18_3BE) +#define SNDRV_PCM_FMTBIT_G723_24 (1ULL << SNDRV_PCM_FORMAT_G723_24) +#define SNDRV_PCM_FMTBIT_G723_24_1B (1ULL << SNDRV_PCM_FORMAT_G723_24_1B) +#define SNDRV_PCM_FMTBIT_G723_40 (1ULL << SNDRV_PCM_FORMAT_G723_40) +#define SNDRV_PCM_FMTBIT_G723_40_1B (1ULL << SNDRV_PCM_FORMAT_G723_40_1B) +#define SNDRV_PCM_FMTBIT_DSD_U8 (1ULL << SNDRV_PCM_FORMAT_DSD_U8) +#define SNDRV_PCM_FMTBIT_DSD_U16_LE (1ULL << SNDRV_PCM_FORMAT_DSD_U16_LE) +#define SNDRV_PCM_FMTBIT_DSD_U32_LE (1ULL << SNDRV_PCM_FORMAT_DSD_U32_LE) +#define SNDRV_PCM_FMTBIT_DSD_U16_BE (1ULL << SNDRV_PCM_FORMAT_DSD_U16_BE) +#define SNDRV_PCM_FMTBIT_DSD_U32_BE (1ULL << SNDRV_PCM_FORMAT_DSD_U32_BE) #ifdef SNDRV_LITTLE_ENDIAN #define SNDRV_PCM_FMTBIT_S16 SNDRV_PCM_FMTBIT_S16_LE @@ -228,11 +227,10 @@ struct snd_pcm_ops { #define SNDRV_PCM_FMTBIT_U20 SNDRV_PCM_FMTBIT_U20_BE #endif -#define _SNDRV_PCM_SUBFMTBIT(fmt) BIT((__force int)SNDRV_PCM_SUBFORMAT_##fmt) -#define SNDRV_PCM_SUBFMTBIT_STD _SNDRV_PCM_SUBFMTBIT(STD) -#define SNDRV_PCM_SUBFMTBIT_MSBITS_MAX _SNDRV_PCM_SUBFMTBIT(MSBITS_MAX) -#define SNDRV_PCM_SUBFMTBIT_MSBITS_20 _SNDRV_PCM_SUBFMTBIT(MSBITS_20) -#define SNDRV_PCM_SUBFMTBIT_MSBITS_24 _SNDRV_PCM_SUBFMTBIT(MSBITS_24) +#define SNDRV_PCM_SUBFMTBIT_STD (1U << SNDRV_PCM_SUBFORMAT_STD) +#define SNDRV_PCM_SUBFMTBIT_MSBITS_MAX (1U << SNDRV_PCM_SUBFORMAT_MSBITS_MAX) +#define SNDRV_PCM_SUBFMTBIT_MSBITS_20 (1U << SNDRV_PCM_SUBFORMAT_MSBITS_20) +#define SNDRV_PCM_SUBFMTBIT_MSBITS_24 (1U << SNDRV_PCM_SUBFORMAT_MSBITS_24) struct snd_pcm_file { struct snd_pcm_substream *substream; @@ -1515,7 +1513,7 @@ int snd_pcm_add_chmap_ctls(struct snd_pcm *pcm, int stream, */ static inline u64 pcm_format_to_bits(snd_pcm_format_t pcm_format) { - return 1ULL << (__force int) pcm_format; + return 1ULL << pcm_format; } /** @@ -1523,9 +1521,7 @@ static inline u64 pcm_format_to_bits(snd_pcm_format_t pcm_format) * @f: the iterator variable in snd_pcm_format_t type */ #define pcm_for_each_format(f) \ - for ((f) = SNDRV_PCM_FORMAT_FIRST; \ - (__force int)(f) <= (__force int)SNDRV_PCM_FORMAT_LAST; \ - (f) = (__force snd_pcm_format_t)((__force int)(f) + 1)) + for ((f) = SNDRV_PCM_FORMAT_FIRST; (f) <= SNDRV_PCM_FORMAT_LAST; (f)++) /* printk helpers */ #define pcm_err(pcm, fmt, args...) \ diff --git a/include/sound/pcm_params.h b/include/sound/pcm_params.h index fbf35df6e5cf..bc43955fcb76 100644 --- a/include/sound/pcm_params.h +++ b/include/sound/pcm_params.h @@ -71,7 +71,7 @@ static inline void snd_mask_set(struct snd_mask *mask, unsigned int val) static inline void snd_mask_set_format(struct snd_mask *mask, snd_pcm_format_t format) { - snd_mask_set(mask, (__force unsigned int)format); + snd_mask_set(mask, format); } static inline void snd_mask_reset(struct snd_mask *mask, unsigned int val) @@ -132,7 +132,7 @@ static inline int snd_mask_test(const struct snd_mask *mask, unsigned int val) static inline int snd_mask_test_format(const struct snd_mask *mask, snd_pcm_format_t format) { - return snd_mask_test(mask, (__force unsigned int)format); + return snd_mask_test(mask, format); } static inline int snd_mask_single(const struct snd_mask *mask) @@ -302,8 +302,7 @@ static inline int snd_interval_eq(const struct snd_interval *i1, const struct sn */ static inline snd_pcm_access_t params_access(const struct snd_pcm_hw_params *p) { - return (__force snd_pcm_access_t)snd_mask_min(hw_param_mask_c(p, - SNDRV_PCM_HW_PARAM_ACCESS)); + return snd_mask_min(hw_param_mask_c(p, SNDRV_PCM_HW_PARAM_ACCESS)); } /** @@ -312,8 +311,7 @@ static inline snd_pcm_access_t params_access(const struct snd_pcm_hw_params *p) */ static inline snd_pcm_format_t params_format(const struct snd_pcm_hw_params *p) { - return (__force snd_pcm_format_t)snd_mask_min(hw_param_mask_c(p, - SNDRV_PCM_HW_PARAM_FORMAT)); + return snd_mask_min(hw_param_mask_c(p, SNDRV_PCM_HW_PARAM_FORMAT)); } /** @@ -323,8 +321,7 @@ static inline snd_pcm_format_t params_format(const struct snd_pcm_hw_params *p) static inline snd_pcm_subformat_t params_subformat(const struct snd_pcm_hw_params *p) { - return (__force snd_pcm_subformat_t)snd_mask_min(hw_param_mask_c(p, - SNDRV_PCM_HW_PARAM_SUBFORMAT)); + return snd_mask_min(hw_param_mask_c(p, SNDRV_PCM_HW_PARAM_SUBFORMAT)); } /** diff --git a/include/sound/pxa2xx-lib.h b/include/sound/pxa2xx-lib.h index 0a6f8dabf8c4..2d86f62f9408 100644 --- a/include/sound/pxa2xx-lib.h +++ b/include/sound/pxa2xx-lib.h @@ -2,55 +2,7 @@ #ifndef PXA2XX_LIB_H #define PXA2XX_LIB_H -#include <uapi/sound/asound.h> -#include <linux/platform_device.h> - -/* PCM */ -struct snd_pcm_substream; -struct snd_pcm_hw_params; -struct snd_soc_pcm_runtime; -struct snd_pcm; -struct snd_soc_component; - -extern int pxa2xx_pcm_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params); -extern int pxa2xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd); -extern snd_pcm_uframes_t pxa2xx_pcm_pointer(struct snd_pcm_substream *substream); -extern int pxa2xx_pcm_prepare(struct snd_pcm_substream *substream); -extern int pxa2xx_pcm_open(struct snd_pcm_substream *substream); -extern int pxa2xx_pcm_close(struct snd_pcm_substream *substream); -extern int pxa2xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm); -extern int pxa2xx_soc_pcm_new(struct snd_soc_component *component, - struct snd_soc_pcm_runtime *rtd); -extern int pxa2xx_soc_pcm_open(struct snd_soc_component *component, - struct snd_pcm_substream *substream); -extern int pxa2xx_soc_pcm_close(struct snd_soc_component *component, - struct snd_pcm_substream *substream); -extern int pxa2xx_soc_pcm_hw_params(struct snd_soc_component *component, - struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params); -extern int pxa2xx_soc_pcm_prepare(struct snd_soc_component *component, - struct snd_pcm_substream *substream); -extern int pxa2xx_soc_pcm_trigger(struct snd_soc_component *component, - struct snd_pcm_substream *substream, int cmd); -extern snd_pcm_uframes_t -pxa2xx_soc_pcm_pointer(struct snd_soc_component *component, - struct snd_pcm_substream *substream); - -/* AC97 */ - -extern int pxa2xx_ac97_read(int slot, unsigned short reg); -extern int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val); - -extern bool pxa2xx_ac97_try_warm_reset(void); -extern bool pxa2xx_ac97_try_cold_reset(void); -extern void pxa2xx_ac97_finish_reset(void); - -extern int pxa2xx_ac97_hw_suspend(void); -extern int pxa2xx_ac97_hw_resume(void); - -extern int pxa2xx_ac97_hw_probe(struct platform_device *dev); -extern void pxa2xx_ac97_hw_remove(struct platform_device *dev); +#include <linux/types.h> /* modem registers, used by touchscreen driver */ u32 pxa2xx_ac97_read_modr(void); diff --git a/include/sound/rawmidi.h b/include/sound/rawmidi.h index 6916f7133597..4154035af414 100644 --- a/include/sound/rawmidi.h +++ b/include/sound/rawmidi.h @@ -176,9 +176,11 @@ int snd_rawmidi_proceed(struct snd_rawmidi_substream *substream); /* main midi functions */ int snd_rawmidi_info_select(struct snd_card *card, struct snd_rawmidi_info *info); -int snd_rawmidi_kernel_open(struct snd_rawmidi *rmidi, int subdevice, - int mode, struct snd_rawmidi_file *rfile); -int snd_rawmidi_kernel_release(struct snd_rawmidi_file *rfile); +int snd_rawmidi_kernel_open_nested(struct snd_rawmidi *rmidi, int subdevice, + int mode, struct snd_rawmidi_file *rfile, + int depth); +int snd_rawmidi_kernel_release_nested(struct snd_rawmidi_file *rfile, + int depth); int snd_rawmidi_output_params(struct snd_rawmidi_substream *substream, struct snd_rawmidi_params *params); int snd_rawmidi_input_params(struct snd_rawmidi_substream *substream, @@ -191,6 +193,20 @@ long snd_rawmidi_kernel_read(struct snd_rawmidi_substream *substream, long snd_rawmidi_kernel_write(struct snd_rawmidi_substream *substream, const unsigned char *buf, long count); +/* non-nested version */ +static inline int snd_rawmidi_kernel_open(struct snd_rawmidi *rmidi, + int subdevice, + int mode, + struct snd_rawmidi_file *rfile) +{ + return snd_rawmidi_kernel_open_nested(rmidi, subdevice, mode, rfile, 0); +} + +static inline int snd_rawmidi_kernel_release(struct snd_rawmidi_file *rfile) +{ + return snd_rawmidi_kernel_release_nested(rfile, 0); +} + /* set up the tied devices */ static inline void snd_rawmidi_tie_devices(struct snd_rawmidi *r1, struct snd_rawmidi *r2) diff --git a/include/sound/sdca.h b/include/sound/sdca.h index 67ff3c88705d..2bdf4e333e04 100644 --- a/include/sound/sdca.h +++ b/include/sound/sdca.h @@ -26,6 +26,8 @@ struct sdca_dev; * @name: Human-readable string. * @type: Function topology type. * @adr: ACPI address (used for SDCA register access). + * @duplicate: Internal flag to indicate if other functions of the same type + * exist. */ struct sdca_function_desc { struct fwnode_handle *node; @@ -33,6 +35,8 @@ struct sdca_function_desc { const char *name; u32 type; u8 adr; + + bool duplicate; }; /** diff --git a/include/sound/sdca_asoc.h b/include/sound/sdca_asoc.h index 46a61a52decc..599a72f33515 100644 --- a/include/sound/sdca_asoc.h +++ b/include/sound/sdca_asoc.h @@ -13,6 +13,7 @@ struct device; struct regmap; struct sdca_function_data; +struct sdca_pde_delay; struct snd_ctl_elem_value; struct snd_kcontrol; struct snd_kcontrol_new; @@ -24,6 +25,8 @@ struct snd_soc_dai_driver; struct snd_soc_dai_ops; struct snd_soc_dapm_route; struct snd_soc_dapm_widget; +struct snd_soc_pcm_stream; +struct sdca_entity; /* convenient macro to handle the mono volume in 7.8 fixed format representation */ #define SDCA_SINGLE_Q78_TLV(xname, xreg, xmin, xmax, xstep, tlv_array) \ @@ -81,6 +84,11 @@ int sdca_asoc_populate_component(struct device *dev, struct snd_soc_dai_driver **dai_drv, int *num_dai_drv, const struct snd_soc_dai_ops *ops); +int sdca_asoc_populate_rate_format(struct device *dev, + struct sdca_function_data *function, + struct sdca_entity *entity, + struct snd_soc_pcm_stream *stream); + int sdca_asoc_set_constraints(struct device *dev, struct regmap *regmap, struct sdca_function_data *function, struct snd_pcm_substream *substream, @@ -99,4 +107,9 @@ int sdca_asoc_q78_put_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); int sdca_asoc_q78_get_volsw(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); +int sdca_asoc_pde_poll_actual_ps(struct regmap *regmap, + int function_id, int entity_id, + int from_ps, int to_ps, + const struct sdca_pde_delay *pde_delays, + int num_delays); #endif // __SDCA_ASOC_H__ diff --git a/include/sound/sdca_fdl.h b/include/sound/sdca_fdl.h index fbaf4b384c8a..bc3600cdd2ec 100644 --- a/include/sound/sdca_fdl.h +++ b/include/sound/sdca_fdl.h @@ -67,6 +67,8 @@ struct fdl_state { #if IS_ENABLED(CONFIG_SND_SOC_SDCA_FDL) int sdca_fdl_alloc_state(struct sdca_interrupt *interrupt); +void sdca_fdl_free_state(struct sdca_interrupt *interrupt); + int sdca_fdl_process(struct sdca_interrupt *interrupt); int sdca_fdl_sync(struct device *dev, struct sdca_function_data *function, struct sdca_interrupt_info *info); @@ -81,6 +83,10 @@ static inline int sdca_fdl_alloc_state(struct sdca_interrupt *interrupt) return 0; } +static inline void sdca_fdl_free_state(struct sdca_interrupt *interrupt) +{ +} + static inline int sdca_fdl_process(struct sdca_interrupt *interrupt) { return 0; diff --git a/include/sound/sdca_function.h b/include/sound/sdca_function.h index 0e871c786513..e580201d69d5 100644 --- a/include/sound/sdca_function.h +++ b/include/sound/sdca_function.h @@ -298,7 +298,7 @@ enum sdca_xu_controls { }; /** - * enum sdca_set_index_range - Column definitions UMP SetIndex + * enum sdca_fdl_set_index_range - Column definitions UMP SetIndex */ enum sdca_fdl_set_index_range { SDCA_FDL_SET_INDEX_SET_NUMBER = 0, @@ -803,6 +803,8 @@ struct sdca_control_range { * @mode: Access mode of the Control. * @layers: Bitmask of access layers of the Control. * @deferrable: Indicates if the access to the Control can be deferred. + * @is_volatile: Indicates the Control registers are forced to be treated + * as volatile. * @has_default: Indicates the Control has a default value to be written. * @has_reset: Indicates the Control has a defined reset value. * @has_fixed: Indicates the Control only supports a single value. @@ -1116,7 +1118,6 @@ struct sdca_entity_ge { /** * struct sdca_entity_hide - information specific to HIDE Entities - * @hid: HID device structure * @num_hidtx_ids: number of HIDTx Report ID * @num_hidrx_ids: number of HIDRx Report ID * @hidtx_ids: HIDTx Report ID @@ -1127,11 +1128,8 @@ struct sdca_entity_ge { * within this Device * @max_delay: the maximum time in microseconds allowed for the Device * to change the ownership from Device to Host - * @hid_report_desc: HID Report Descriptor for the HIDE Entity - * @hid_desc: HID descriptor for the HIDE Entity */ struct sdca_entity_hide { - struct hid_device *hid; unsigned int *hidtx_ids; unsigned int *hidrx_ids; int num_hidtx_ids; @@ -1139,12 +1137,10 @@ struct sdca_entity_hide { unsigned int af_number_list[SDCA_MAX_FUNCTION_COUNT]; unsigned int hide_reside_function_num; unsigned int max_delay; - unsigned char *hid_report_desc; - struct hid_descriptor hid_desc; }; /** - * enum sdca_xu_reset_machanism - SDCA FDL Resets + * enum sdca_xu_reset_mechanism - SDCA FDL Resets */ enum sdca_xu_reset_mechanism { SDCA_XU_RESET_FUNCTION = 0x0, @@ -1402,6 +1398,16 @@ struct sdca_fdl_data { }; /** + * struct sdca_function_hid - information about a function's HID descriptors + * @report_desc: HID Report Descriptor for the HID Function + * @desc: HID descriptor for the HID Function + */ +struct sdca_function_hid { + unsigned char *report_desc; + struct hid_descriptor desc; +}; + +/** * struct sdca_function_data - top-level information for one SDCA function * @desc: Pointer to short descriptor from initial parsing. * @init_table: Pointer to a table of initialization writes. @@ -1415,6 +1421,7 @@ struct sdca_fdl_data { * @reset_max_delay: Maximum Function reset delay in microseconds, before an * error should be reported. * @fdl_data: FDL data for this Function, if available. + * @hid: HID data for this Function, if available. */ struct sdca_function_data { struct sdca_function_desc *desc; @@ -1430,6 +1437,10 @@ struct sdca_function_data { unsigned int reset_max_delay; struct sdca_fdl_data fdl_data; + + union { + struct sdca_function_hid hid; + }; }; static inline u32 sdca_range(struct sdca_control_range *range, @@ -1451,9 +1462,7 @@ static inline u32 sdca_range_search(struct sdca_control_range *range, return 0; } -int sdca_parse_function(struct device *dev, struct sdw_slave *sdw, - struct sdca_function_desc *desc, - struct sdca_function_data *function); +int sdca_parse_function(struct device *dev, struct sdca_function_data *function); const char *sdca_find_terminal_name(enum sdca_terminal_type type); @@ -1470,5 +1479,7 @@ struct sdca_control_range *sdca_selector_find_range(struct device *dev, struct sdca_cluster *sdca_id_find_cluster(struct device *dev, struct sdca_function_data *function, const int id); +struct sdca_entity *sdca_find_entity_by_label(struct sdca_function_data *function, + const char *entity_label); #endif diff --git a/include/sound/sdca_hid.h b/include/sound/sdca_hid.h index 18bebbe428c9..848081df3e4e 100644 --- a/include/sound/sdca_hid.h +++ b/include/sound/sdca_hid.h @@ -16,18 +16,21 @@ struct sdca_interrupt; #if IS_ENABLED(CONFIG_SND_SOC_SDCA_HID) -int sdca_add_hid_device(struct device *dev, struct sdw_slave *sdw, - struct sdca_entity *entity); +int sdca_add_hid_device(struct sdca_interrupt *interrupt); +void sdca_destroy_hid_device(struct sdca_interrupt *interrupt); int sdca_hid_process_report(struct sdca_interrupt *interrupt); #else -static inline int sdca_add_hid_device(struct device *dev, struct sdw_slave *sdw, - struct sdca_entity *entity) +static inline int sdca_add_hid_device(struct sdca_interrupt *interrupt) { return 0; } +static inline void sdca_destroy_hid_device(struct sdca_interrupt *interrupt) +{ +} + static inline int sdca_hid_process_report(struct sdca_interrupt *interrupt) { return 0; diff --git a/include/sound/sdca_interrupts.h b/include/sound/sdca_interrupts.h index a515cc3df097..3b30146e21db 100644 --- a/include/sound/sdca_interrupts.h +++ b/include/sound/sdca_interrupts.h @@ -30,9 +30,12 @@ struct sdca_function_data; * @function: Pointer to the Function that the interrupt is associated with. * @entity: Pointer to the Entity that the interrupt is associated with. * @control: Pointer to the Control that the interrupt is associated with. + * @handler: Handler function to be called for the IRQ. * @priv: Pointer to private data for use by the handler. + * @free_priv: Pointer to a function that can be used to free the priv data. * @irq: IRQ number allocated to this interrupt, also used internally to track * the IRQ being assigned. + * @early_request: Flag to indicate this IRQ was requested at bus probe time. */ struct sdca_interrupt { const char *name; @@ -44,10 +47,13 @@ struct sdca_interrupt { struct sdca_function_data *function; struct sdca_entity *entity; struct sdca_control *control; + irq_handler_t handler; void *priv; + void (*free_priv)(struct sdca_interrupt *interrupt); int irq; + bool early_request; }; /** @@ -86,8 +92,12 @@ int sdca_irq_populate(struct sdca_function_data *function, void sdca_irq_cleanup(struct device *dev, struct sdca_function_data *function, struct sdca_interrupt_info *info); -struct sdca_interrupt_info *sdca_irq_allocate(struct device *dev, - struct regmap *regmap, int irq); +void sdca_irq_cleanup_late(struct device *dev, + struct sdca_function_data *function, + struct sdca_interrupt_info *info); + +struct sdca_interrupt_info *devm_sdca_irq_allocate(struct device *dev, + struct regmap *regmap, int irq); void sdca_irq_enable_early(struct sdca_function_data *function, struct sdca_interrupt_info *info); diff --git a/include/sound/sdca_jack.h b/include/sound/sdca_jack.h index 3ec22046d3eb..871ba2d8146a 100644 --- a/include/sound/sdca_jack.h +++ b/include/sound/sdca_jack.h @@ -18,13 +18,19 @@ struct snd_soc_jack; * struct jack_state - Jack state structure to keep data between interrupts * @kctl: Pointer to the ALSA control attached to this jack * @jack: Pointer to the ASoC jack struct for this jack + * @mask: Possible reported jack status bits for this jack */ struct jack_state { struct snd_kcontrol *kctl; struct snd_soc_jack *jack; + + unsigned int mask; }; int sdca_jack_alloc_state(struct sdca_interrupt *interrupt); +int sdca_jack_init_state(struct sdca_interrupt *interrupt); +void sdca_jack_free_state(struct sdca_interrupt *interrupt); + int sdca_jack_process(struct sdca_interrupt *interrupt); int sdca_jack_set_jack(struct sdca_interrupt_info *info, struct snd_soc_jack *jack); int sdca_jack_report(struct sdca_interrupt *interrupt); diff --git a/include/sound/seq_device.h b/include/sound/seq_device.h index a72380c202e9..3137d4c5f5a8 100644 --- a/include/sound/seq_device.h +++ b/include/sound/seq_device.h @@ -22,6 +22,7 @@ struct snd_seq_device { void *private_data; /* private data for the caller */ void (*private_free)(struct snd_seq_device *device); struct device dev; + unsigned char args[]; /* driver-specific argument */ }; #define to_seq_dev(_dev) \ @@ -64,7 +65,7 @@ void snd_seq_device_load_drivers(void); int snd_seq_device_new(struct snd_card *card, int device, const char *id, int argsize, struct snd_seq_device **result); -#define SNDRV_SEQ_DEVICE_ARGPTR(dev) (void *)((char *)(dev) + sizeof(struct snd_seq_device)) +#define SNDRV_SEQ_DEVICE_ARGPTR(dev) ((void *)(dev)->args) int __must_check __snd_seq_driver_register(struct snd_seq_driver *drv, struct module *mod); diff --git a/include/sound/seq_midi_emul.h b/include/sound/seq_midi_emul.h index 88799d1e1f53..afc765437870 100644 --- a/include/sound/seq_midi_emul.h +++ b/include/sound/seq_midi_emul.h @@ -55,14 +55,14 @@ struct snd_midi_channel_set { int client; /* Client for this port */ int port; /* The port number */ - int max_channels; /* Size of the channels array */ - struct snd_midi_channel *channels; - unsigned char midi_mode; /* MIDI operating mode */ unsigned char gs_master_volume; /* SYSEX master volume: 0-127 */ unsigned char gs_chorus_mode; unsigned char gs_reverb_mode; + int max_channels; /* Size of the channels array */ + struct snd_midi_channel channels[] __counted_by(max_channels); + }; struct snd_midi_op { diff --git a/include/sound/seq_virmidi.h b/include/sound/seq_virmidi.h index 56a3f38df8c3..359cb363369d 100644 --- a/include/sound/seq_virmidi.h +++ b/include/sound/seq_virmidi.h @@ -46,7 +46,6 @@ struct snd_virmidi_dev { int client; /* created/attached client */ int port; /* created/attached port */ unsigned int flags; /* SNDRV_VIRMIDI_* */ - rwlock_t filelist_lock; struct rw_semaphore filelist_sem; struct list_head filelist; }; diff --git a/include/sound/simple_card_utils.h b/include/sound/simple_card_utils.h index 915e6ae5f68d..bd8c3a033577 100644 --- a/include/sound/simple_card_utils.h +++ b/include/sound/simple_card_utils.h @@ -181,7 +181,7 @@ void simple_util_canonicalize_platform(struct snd_soc_dai_link_component *platfo void simple_util_canonicalize_cpu(struct snd_soc_dai_link_component *cpus, int is_single_links); -void simple_util_clean_reference(struct snd_soc_card *card); +void simple_util_clean_reference(struct simple_util_priv *priv); void simple_util_parse_convert(struct device_node *np, char *prefix, struct simple_util_data *data); @@ -189,18 +189,37 @@ bool simple_util_is_convert_required(const struct simple_util_data *data); int simple_util_get_sample_fmt(struct simple_util_data *data); -int simple_util_parse_routing(struct snd_soc_card *card, - char *prefix); -int simple_util_parse_widgets(struct snd_soc_card *card, - char *prefix); -int simple_util_parse_pin_switches(struct snd_soc_card *card, - char *prefix); +int simple_util_parse_property(struct simple_util_priv *priv, + int (*func)(struct snd_soc_card *card, const char *propname), + char *prefix, char *property); +static inline int simple_util_parse_routing(struct simple_util_priv *priv, char *prefix) +{ + return simple_util_parse_property(priv, snd_soc_of_parse_audio_routing, + prefix, "routing"); +} + +static inline int simple_util_parse_widgets(struct simple_util_priv *priv, char *prefix) +{ + return simple_util_parse_property(priv, snd_soc_of_parse_audio_simple_widgets, + prefix, "widgets"); +} + +static inline int simple_util_parse_pin_switches(struct simple_util_priv *priv, char *prefix) +{ + return simple_util_parse_property(priv, snd_soc_of_parse_pin_switches, + prefix, "pin-switches"); +} + +static inline int simple_util_parse_aux_devs(struct simple_util_priv *priv, char *prefix) +{ + return simple_util_parse_property(priv, snd_soc_of_parse_aux_devs, + prefix, "aux-devs"); +} int simple_util_init_jack(struct snd_soc_card *card, struct simple_util_jack *sjack, int is_hp, char *prefix, char *pin); -int simple_util_init_aux_jacks(struct simple_util_priv *priv, - char *prefix); +int simple_util_init_aux_jacks(struct snd_soc_card *card, char *prefix); int simple_util_init_priv(struct simple_util_priv *priv, struct link_info *li); void simple_util_remove(struct platform_device *pdev); diff --git a/include/sound/snd_wavefront.h b/include/sound/snd_wavefront.h index 30f508a56766..ac749bb2b836 100644 --- a/include/sound/snd_wavefront.h +++ b/include/sound/snd_wavefront.h @@ -12,6 +12,7 @@ struct _snd_wavefront_midi; struct _snd_wavefront_card; struct _snd_wavefront; +struct snd_wss; typedef struct _snd_wavefront_midi snd_wavefront_midi_t; typedef struct _snd_wavefront_card snd_wavefront_card_t; @@ -46,6 +47,8 @@ extern void snd_wavefront_midi_enable_virtual (snd_wavefront_card_t *); extern void snd_wavefront_midi_disable_virtual (snd_wavefront_card_t *); extern void snd_wavefront_midi_interrupt (snd_wavefront_card_t *); extern int snd_wavefront_midi_start (snd_wavefront_card_t *); +void snd_wavefront_midi_suspend(snd_wavefront_card_t *card); +void snd_wavefront_midi_resume(snd_wavefront_card_t *card); struct _snd_wavefront { unsigned long irq; /* "you were one, one of the few ..." */ @@ -93,6 +96,7 @@ struct _snd_wavefront { int samples_used; /* how many */ char interrupts_are_midi; /* h/w MPU interrupts enabled ? */ char rom_samples_rdonly; /* can we write on ROM samples */ + char midi_in_to_synth; /* route external MIDI to synth */ spinlock_t irq_lock; wait_queue_head_t interrupt_sleeper; snd_wavefront_midi_t midi; /* ICS2115 MIDI interface */ @@ -101,6 +105,7 @@ struct _snd_wavefront { struct _snd_wavefront_card { snd_wavefront_t wavefront; + struct snd_wss *chip; #ifdef CONFIG_PNP struct pnp_dev *wss; struct pnp_dev *ctrl; @@ -110,8 +115,10 @@ struct _snd_wavefront_card { }; extern void snd_wavefront_internal_interrupt (snd_wavefront_card_t *card); +void snd_wavefront_cache_firmware(snd_wavefront_t *dev); extern int snd_wavefront_start (snd_wavefront_t *dev); extern int snd_wavefront_detect (snd_wavefront_card_t *card); +int snd_wavefront_resume_synth(snd_wavefront_card_t *card); extern int snd_wavefront_cmd (snd_wavefront_t *, int, unsigned char *, unsigned char *); diff --git a/include/sound/soc-acpi.h b/include/sound/soc-acpi.h index 0519afd7217f..2ee303b791dc 100644 --- a/include/sound/soc-acpi.h +++ b/include/sound/soc-acpi.h @@ -57,7 +57,7 @@ static inline struct snd_soc_acpi_mach *snd_soc_acpi_codec_list(void *arg) #endif /** - * snd_soc_acpi_mach_params: interface for machine driver configuration + * struct snd_soc_acpi_mach_params - interface for machine driver configuration * * @acpi_ipc_irq_index: used for BYT-CR detection * @platform: string used for HDAudio codec support @@ -93,7 +93,7 @@ struct snd_soc_acpi_mach_params { }; /** - * snd_soc_acpi_endpoint - endpoint descriptor + * struct snd_soc_acpi_endpoint - endpoint descriptor * @num: endpoint number (mandatory, unique per device) * @aggregated: 0 (independent) or 1 (logically grouped) * @group_position: zero-based order (only when @aggregated is 1) @@ -107,7 +107,7 @@ struct snd_soc_acpi_endpoint { }; /** - * snd_soc_acpi_adr_device - descriptor for _ADR-enumerated device + * struct snd_soc_acpi_adr_device - descriptor for _ADR-enumerated device * @adr: 64 bit ACPI _ADR value * @num_endpoints: number of endpoints for this device * @endpoints: array of endpoints @@ -121,7 +121,7 @@ struct snd_soc_acpi_adr_device { }; /** - * snd_soc_acpi_link_adr - ACPI-based list of _ADR enumerated devices + * struct snd_soc_acpi_link_adr - ACPI-based list of _ADR enumerated devices * @mask: one bit set indicates the link this list applies to * @num_adr: ARRAY_SIZE of devices * @adr_d: array of devices @@ -167,8 +167,8 @@ struct snd_soc_acpi_link_adr { #define SND_SOC_ACPI_TPLG_INTEL_CODEC_NAME BIT(4) /** - * snd_soc_acpi_mach: ACPI-based machine descriptor. Most of the fields are - * related to the hardware, except for the firmware and topology file names. + * struct snd_soc_acpi_mach - ACPI-based machine descriptor. Most of the fields + * are related to the hardware, except for the firmware and topology file names. * A platform supported by legacy and Sound Open Firmware (SOF) would expose * all firmware/topology related fields. * @@ -192,6 +192,7 @@ struct snd_soc_acpi_link_adr { * the initial selection in the snd_soc_acpi_mach table. * @pdata: intended for platform data or machine specific-ops. This structure * is not constant since this field may be updated at run-time + * @mach_params: machine driver configuration * @sof_tplg_filename: Sound Open Firmware topology file name, if enabled * @tplg_quirk_mask: quirks to select different topology files dynamically * @get_function_tplg_files: This is an optional callback, if specified then instead of @@ -199,11 +200,11 @@ struct snd_soc_acpi_link_adr { * files to be loaded. * Return value: The number of the files or negative ERRNO. 0 means that the single topology * file should be used, no function topology split can be used on the machine. - * @card: the pointer of the card - * @mach: the pointer of the machine driver - * @prefix: the prefix of the topology file name. Typically, it is the path. - * @tplg_files: the pointer of the array of the topology file names. - * @best_effort: ignore non supported links and try to build the card in best effort + * card: the pointer of the card + * mach: the pointer of the machine driver + * prefix: the prefix of the topology file name. Typically, it is the path. + * tplg_files: the pointer of the array of the topology file names. + * best_effort: ignore non supported links and try to build the card in best effort * with supported links */ /* Descriptor for SST ASoC machine driver */ diff --git a/include/sound/soc-card.h b/include/sound/soc-card.h index ecc02e955279..1f1e7d45f553 100644 --- a/include/sound/soc-card.h +++ b/include/sound/soc-card.h @@ -47,6 +47,8 @@ int snd_soc_card_late_probe(struct snd_soc_card *card); void snd_soc_card_fixup_controls(struct snd_soc_card *card); int snd_soc_card_remove(struct snd_soc_card *card); +void snd_soc_card_set_topology_name(struct snd_soc_card *card, const char *preifx); + int snd_soc_card_set_bias_level(struct snd_soc_card *card, struct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level); diff --git a/include/sound/soc-component.h b/include/sound/soc-component.h index 7e158d27ae8d..c49b59630101 100644 --- a/include/sound/soc-component.h +++ b/include/sound/soc-component.h @@ -10,6 +10,8 @@ #include <sound/soc.h> +struct device_link; + /* * Component probe and remove ordering levels for components with runtime * dependencies. @@ -76,6 +78,7 @@ struct snd_soc_component_driver { unsigned int num_dapm_routes; int (*probe)(struct snd_soc_component *component); + int (*fixup_controls)(struct snd_soc_component *component); void (*remove)(struct snd_soc_component *component); int (*suspend)(struct snd_soc_component *component); int (*resume)(struct snd_soc_component *component); @@ -199,9 +202,7 @@ struct snd_soc_component_driver { bool use_dai_pcm_id; /* use DAI link PCM ID as PCM device number */ int be_pcm_base; /* base device ID for all BE PCMs */ -#ifdef CONFIG_DEBUG_FS const char *debugfs_prefix; -#endif }; struct snd_soc_component { @@ -218,6 +219,8 @@ struct snd_soc_component { struct list_head card_aux_list; /* for auxiliary bound components */ struct list_head card_list; + struct device_link *card_device_link; + const struct snd_soc_component_driver *driver; struct list_head dai_list; @@ -250,7 +253,9 @@ struct snd_soc_component { void *mark_pm; struct dentry *debugfs_root; - const char *debugfs_prefix; + + /* Component private data */ + void *priv; }; #define for_each_component_dais(component, dai)\ @@ -281,6 +286,14 @@ static inline int snd_soc_component_cache_sync( return regcache_sync(component->regmap); } +struct snd_soc_component *snd_soc_component_alloc(struct device *dev); + +void snd_soc_component_set_name(struct snd_soc_component *component, const char *name); +const char *snd_soc_component_name(struct snd_soc_component *component); + +void snd_soc_component_set_priv(struct snd_soc_component *component, void *priv); +void *snd_soc_component_to_priv(struct snd_soc_component *component); + void snd_soc_component_set_aux(struct snd_soc_component *component, struct snd_soc_aux_dev *aux); int snd_soc_component_init(struct snd_soc_component *component); @@ -379,6 +392,7 @@ void snd_soc_component_suspend(struct snd_soc_component *component); void snd_soc_component_resume(struct snd_soc_component *component); int snd_soc_component_is_suspended(struct snd_soc_component *component); int snd_soc_component_probe(struct snd_soc_component *component); +int snd_soc_component_fixup_controls(struct snd_soc_component *component); void snd_soc_component_remove(struct snd_soc_component *component); int snd_soc_component_of_xlate_dai_id(struct snd_soc_component *component, struct device_node *ep); diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h index 6a42812bba8c..ba3ae56c6b06 100644 --- a/include/sound/soc-dai.h +++ b/include/sound/soc-dai.h @@ -17,6 +17,7 @@ struct snd_pcm_substream; struct snd_soc_dapm_widget; struct snd_compr_stream; +struct clk; /* * DAI hardware audio formats. @@ -80,10 +81,10 @@ struct snd_compr_stream; /* * define GATED -> CONT. GATED will be selected if both are selected. * see - * snd_soc_runtime_get_dai_fmt() + * soc_dai_convert_possiblefmt_to_daifmt() */ #define SND_SOC_POSSIBLE_DAIFMT_CLOCK_SHIFT 16 -#define SND_SOC_POSSIBLE_DAIFMT_CLOCK_MASK (0xFFFF << SND_SOC_POSSIBLE_DAIFMT_CLOCK_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_CLOCK_MASK (0xFFFFULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_SHIFT) #define SND_SOC_POSSIBLE_DAIFMT_GATED (0x1ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_SHIFT) #define SND_SOC_POSSIBLE_DAIFMT_CONT (0x2ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_SHIFT) @@ -139,14 +140,6 @@ struct snd_compr_stream; #define SND_SOC_DAIFMT_BP_FC SND_SOC_DAIFMT_CBP_CFC #define SND_SOC_DAIFMT_BC_FC SND_SOC_DAIFMT_CBC_CFC -/* Describes the possible PCM format */ -#define SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_SHIFT 48 -#define SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_MASK (0xFFFFULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_SHIFT) -#define SND_SOC_POSSIBLE_DAIFMT_CBP_CFP (0x1ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_SHIFT) -#define SND_SOC_POSSIBLE_DAIFMT_CBC_CFP (0x2ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_SHIFT) -#define SND_SOC_POSSIBLE_DAIFMT_CBP_CFC (0x4ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_SHIFT) -#define SND_SOC_POSSIBLE_DAIFMT_CBC_CFC (0x8ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_SHIFT) - #define SND_SOC_DAIFMT_FORMAT_MASK 0x000f #define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0 #define SND_SOC_DAIFMT_INV_MASK 0x0f00 @@ -188,9 +181,10 @@ int snd_soc_dai_set_pll(struct snd_soc_dai *dai, int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio); +void snd_soc_dai_set_bclk_clk(struct snd_soc_dai *dai, struct clk *bclk); + /* Digital Audio interface formatting */ -int snd_soc_dai_get_fmt_max_priority(const struct snd_soc_pcm_runtime *rtd); -u64 snd_soc_dai_get_fmt(const struct snd_soc_dai *dai, int priority); +unsigned int snd_soc_dai_auto_select_format(const struct snd_soc_pcm_runtime *rtd); int snd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt); int snd_soc_dai_set_tdm_slot(struct snd_soc_dai *dai, @@ -473,6 +467,10 @@ struct snd_soc_dai { unsigned int symmetric_channels; unsigned int symmetric_sample_bits; + /* shared BCLK clock for cross-DAI rate constraints */ + struct clk *bclk; + unsigned int bclk_ratio; /* BCLK = rate * bclk_ratio (0 = use channels * sample_bits) */ + /* parent platform/codec */ struct snd_soc_component *component; diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h index 4f8fb7622a13..33c4a3e9c1d4 100644 --- a/include/sound/soc-dapm.h +++ b/include/sound/soc-dapm.h @@ -636,6 +636,7 @@ int snd_soc_dapm_new_dai_widgets(struct snd_soc_dapm_context *dapm, struct snd_s void snd_soc_dapm_free_widget(struct snd_soc_dapm_widget *w); int snd_soc_dapm_link_dai_widgets(struct snd_soc_card *card); void snd_soc_dapm_connect_dai_link_widgets(struct snd_soc_card *card); +int snd_soc_dapm_ignore_suspend_widgets(struct snd_soc_card *card); int snd_soc_dapm_update_dai(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai); @@ -673,6 +674,7 @@ int snd_soc_dapm_mux_update_power(struct snd_soc_dapm_context *dapm, /* dapm sys fs - used by the core */ extern struct attribute *snd_soc_dapm_dev_attrs[]; void snd_soc_dapm_debugfs_init(struct snd_soc_dapm_context *dapm, struct dentry *parent); +void snd_soc_dapm_debugfs_pop_time(struct dentry *parent); /* dapm audio pin control and status */ int snd_soc_dapm_enable_pin(struct snd_soc_dapm_context *dapm, const char *pin); @@ -685,6 +687,7 @@ int snd_soc_dapm_sync_unlocked(struct snd_soc_dapm_context *dapm); int snd_soc_dapm_force_enable_pin(struct snd_soc_dapm_context *dapm, const char *pin); int snd_soc_dapm_force_enable_pin_unlocked(struct snd_soc_dapm_context *dapm, const char *pin); int snd_soc_dapm_ignore_suspend(struct snd_soc_dapm_context *dapm, const char *pin); +bool snd_soc_dapm_pin_has_prefix(struct snd_soc_card *card, const char *pin); void snd_soc_dapm_mark_endpoints_dirty(struct snd_soc_card *card); /* dapm path query */ diff --git a/include/sound/soc.h b/include/sound/soc.h index 5e3eb617d832..5afc34b147b5 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -431,7 +431,7 @@ struct snd_soc_jack_pin; int snd_soc_register_card(struct snd_soc_card *card); void snd_soc_unregister_card(struct snd_soc_card *card); int devm_snd_soc_register_card(struct device *dev, struct snd_soc_card *card); -int devm_snd_soc_register_deferrable_card(struct device *dev, struct snd_soc_card *card); +#define devm_snd_soc_register_deferrable_card(d, c) devm_snd_soc_register_card(d, c) #ifdef CONFIG_PM_SLEEP int snd_soc_suspend(struct device *dev); int snd_soc_resume(struct device *dev); @@ -447,15 +447,16 @@ static inline int snd_soc_resume(struct device *dev) } #endif int snd_soc_poweroff(struct device *dev); -int snd_soc_component_initialize(struct snd_soc_component *component, - const struct snd_soc_component_driver *driver, - struct device *dev); -int snd_soc_add_component(struct snd_soc_component *component, - struct snd_soc_dai_driver *dai_drv, - int num_dai); -int snd_soc_register_component(struct device *dev, +int snd_soc_register_component_c(struct snd_soc_component *component, const struct snd_soc_component_driver *component_driver, struct snd_soc_dai_driver *dai_drv, int num_dai); +int snd_soc_register_component_d(struct device *dev, + const struct snd_soc_component_driver *component_driver, + struct snd_soc_dai_driver *dai_drv, int num_dai); +#define snd_soc_register_component(x, ...) _Generic((x), \ +struct device * : snd_soc_register_component_d, \ +struct snd_soc_component * : snd_soc_register_component_c)(x, __VA_ARGS__) + int devm_snd_soc_register_component(struct device *dev, const struct snd_soc_component_driver *component_driver, struct snd_soc_dai_driver *dai_drv, int num_dai); @@ -698,7 +699,8 @@ struct snd_soc_dai_link_component { struct snd_soc_dai_link_ch_map { unsigned int cpu; unsigned int codec; - unsigned int ch_mask; + unsigned int cpu_ch_mask; + unsigned int codec_ch_mask; }; struct snd_soc_dai_link { @@ -976,9 +978,6 @@ struct snd_soc_card { const char *long_name; const char *driver_name; const char *components; -#ifdef CONFIG_DMI - char dmi_longname[80]; -#endif /* CONFIG_DMI */ #ifdef CONFIG_PCI /* @@ -990,7 +989,7 @@ struct snd_soc_card { bool pci_subsystem_set; #endif /* CONFIG_PCI */ - char topology_shortname[32]; + char *topology_shortname; struct device *dev; struct snd_card *snd_card; @@ -1057,10 +1056,14 @@ struct snd_soc_card { int num_dapm_widgets; const struct snd_soc_dapm_route *dapm_routes; int num_dapm_routes; + const char **ignore_suspend_widgets; + int num_ignore_suspend_widgets; const struct snd_soc_dapm_widget *of_dapm_widgets; int num_of_dapm_widgets; const struct snd_soc_dapm_route *of_dapm_routes; int num_of_dapm_routes; + const char **of_ignore_suspend_widgets; + int num_of_ignore_suspend_widgets; /* lists of probed devices belonging to this card */ struct list_head component_dev_list; @@ -1081,11 +1084,8 @@ struct snd_soc_card { #ifdef CONFIG_PM_SLEEP struct work_struct deferred_resume_work; #endif - u32 pop_time; - /* bit field */ unsigned int instantiated:1; - unsigned int topology_shortname_created:1; unsigned int fully_routed:1; unsigned int probed:1; unsigned int component_chaining:1; @@ -1339,6 +1339,7 @@ void snd_soc_of_parse_node_prefix(struct device_node *np, int snd_soc_of_parse_audio_routing(struct snd_soc_card *card, const char *propname); int snd_soc_of_parse_aux_devs(struct snd_soc_card *card, const char *propname); +int snd_soc_of_parse_ignore_suspend_widgets(struct snd_soc_card *card, const char *propname); unsigned int snd_soc_daifmt_clock_provider_flipped(unsigned int dai_fmt); unsigned int snd_soc_daifmt_clock_provider_from_bitmap(unsigned int bit_frame); diff --git a/include/sound/soc_sdw_utils.h b/include/sound/soc_sdw_utils.h index 489083183673..9fbb69b9052d 100644 --- a/include/sound/soc_sdw_utils.h +++ b/include/sound/soc_sdw_utils.h @@ -44,6 +44,18 @@ struct asoc_sdw_codec_info; +struct asoc_sdw_mc_private { + struct snd_soc_card card; + struct snd_soc_jack sdw_headset; + struct device *headset_codec_dev; /* only one headset per card */ + struct device *amp_dev1, *amp_dev2; + bool append_dai_type; + bool ignore_internal_dmic; + void *private; + unsigned long mc_quirk; + int codec_info_list_count; +}; + struct asoc_sdw_dai_info { const bool direction[2]; /* playback & capture support */ const char *codec_name; @@ -88,25 +100,13 @@ struct asoc_sdw_codec_info { int (*codec_card_late_probe)(struct snd_soc_card *card); - int (*count_sidecar)(struct snd_soc_card *card, + int (*count_sidecar)(struct asoc_sdw_mc_private *ctx, int *num_dais, int *num_devs); int (*add_sidecar)(struct snd_soc_card *card, struct snd_soc_dai_link **dai_links, struct snd_soc_codec_conf **codec_conf); }; -struct asoc_sdw_mc_private { - struct snd_soc_card card; - struct snd_soc_jack sdw_headset; - struct device *headset_codec_dev; /* only one headset per card */ - struct device *amp_dev1, *amp_dev2; - bool append_dai_type; - bool ignore_internal_dmic; - void *private; - unsigned long mc_quirk; - int codec_info_list_count; -}; - struct asoc_sdw_endpoint { struct list_head list; @@ -182,7 +182,8 @@ struct asoc_sdw_dailink *asoc_sdw_find_dailink(struct asoc_sdw_dailink *dailinks const struct snd_soc_acpi_endpoint *new); int asoc_sdw_get_dai_type(u32 type); -int asoc_sdw_parse_sdw_endpoints(struct snd_soc_card *card, +int asoc_sdw_parse_sdw_endpoints(struct device *dev, + struct asoc_sdw_mc_private *ctx, struct snd_soc_aux_dev *soc_aux, struct asoc_sdw_dailink *soc_dais, struct asoc_sdw_endpoint *soc_ends, @@ -223,8 +224,19 @@ int asoc_sdw_cs42l43_spk_init(struct snd_soc_card *card, struct asoc_sdw_codec_info *info, bool playback); +/* es9356 codec support */ +int asoc_sdw_es9356_init(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_links, + struct asoc_sdw_codec_info *info, + bool playback); +int asoc_sdw_es9356_amp_init(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_links, + struct asoc_sdw_codec_info *info, + bool playback); +int asoc_sdw_es9356_exit(struct snd_soc_card *card, struct snd_soc_dai_link *dai_link); + /* CS AMP support */ -int asoc_sdw_bridge_cs35l56_count_sidecar(struct snd_soc_card *card, +int asoc_sdw_bridge_cs35l56_count_sidecar(struct asoc_sdw_mc_private *ctx, int *num_dais, int *num_devs); int asoc_sdw_bridge_cs35l56_add_sidecar(struct snd_soc_card *card, struct snd_soc_dai_link **dai_links, @@ -238,8 +250,6 @@ int asoc_sdw_cs_amp_init(struct snd_soc_card *card, struct snd_soc_dai_link *dai_links, struct asoc_sdw_codec_info *info, bool playback); -int asoc_sdw_cs_spk_feedback_rtd_init(struct snd_soc_pcm_runtime *rtd, - struct snd_soc_dai *dai); int asoc_sdw_cs35l56_volume_limit(struct snd_soc_card *card, const char *name_prefix); /* MAXIM codec support */ @@ -272,7 +282,14 @@ int asoc_sdw_ti_amp_init(struct snd_soc_card *card, struct asoc_sdw_codec_info *info, bool playback); int asoc_sdw_ti_spk_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_ti_tac5xx2_spk_rtd_init(struct snd_soc_pcm_runtime *rtd, + struct snd_soc_dai *dai); int asoc_sdw_ti_amp_initial_settings(struct snd_soc_card *card, const char *name_prefix); +int asoc_sdw_ti_dmic_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_ti_sdca_jack_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_es9356_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_es9356_spk_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); +int asoc_sdw_es9356_dmic_rtd_init(struct snd_soc_pcm_runtime *rtd, struct snd_soc_dai *dai); #endif diff --git a/include/sound/sof/dai-amd.h b/include/sound/sof/dai-amd.h index 59cd014392c1..e2107da6558f 100644 --- a/include/sound/sof/dai-amd.h +++ b/include/sound/sof/dai-amd.h @@ -18,6 +18,7 @@ struct sof_ipc_dai_acp_params { uint32_t fsync_rate; /* FSYNC frequency in Hz */ uint32_t tdm_slots; uint32_t tdm_mode; + uint32_t format; } __packed; /* ACPDMIC Configuration Request - SOF_IPC_DAI_AMD_CONFIG */ diff --git a/include/sound/sof/dai.h b/include/sound/sof/dai.h index 36809f712723..e3fe492e78f5 100644 --- a/include/sound/sof/dai.h +++ b/include/sound/sof/dai.h @@ -90,6 +90,8 @@ enum sof_ipc_dai_type { SOF_DAI_AMD_HS_VIRTUAL, /**< AMD ACP HS VIRTUAL */ SOF_DAI_IMX_MICFIL, /** < i.MX MICFIL PDM */ SOF_DAI_AMD_SDW, /**< AMD ACP SDW */ + SOF_DAI_INTEL_UAOL, /**< Intel UAOL */ + SOF_DAI_AMD_I2S, /**< AMD ACP I2S */ }; /* general purpose DAI configuration */ @@ -121,6 +123,7 @@ struct sof_ipc_dai_config { struct sof_ipc_dai_mtk_afe_params afe; struct sof_ipc_dai_micfil_params micfil; struct sof_ipc_dai_acp_sdw_params acp_sdw; + struct sof_ipc_dai_acp_params acp_i2s; }; } __packed; diff --git a/include/sound/sof/header.h b/include/sound/sof/header.h index 4e406dc22f31..6c2c3a5fc90d 100644 --- a/include/sound/sof/header.h +++ b/include/sound/sof/header.h @@ -179,7 +179,7 @@ struct sof_ipc_compound_hdr { uint32_t count; /**< count of 0 means end of compound sequence */ } __packed; -/** +/* * OOPS header architecture specific data. */ struct sof_ipc_dsp_oops_arch_hdr { @@ -187,7 +187,7 @@ struct sof_ipc_dsp_oops_arch_hdr { uint32_t totalsize; /* Total size of oops message */ } __packed; -/** +/* * OOPS header platform specific data. */ struct sof_ipc_dsp_oops_plat_hdr { diff --git a/include/sound/sof/ipc4/header.h b/include/sound/sof/ipc4/header.h index 4554e5e8cab5..cea3d9453b84 100644 --- a/include/sound/sof/ipc4/header.h +++ b/include/sound/sof/ipc4/header.h @@ -187,6 +187,10 @@ enum sof_ipc4_pipeline_state { #define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_MASK GENMASK(23, 20) #define SOF_IPC4_GLB_PIPE_EXT_CORE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT) +#define SOF_IPC4_GLB_PIPE_PAYLOAD_SHIFT 29 +#define SOF_IPC4_GLB_PIPE_PAYLOAD_MASK BIT(29) +#define SOF_IPC4_GLB_PIPE_PAYLOAD(x) ((x) << SOF_IPC4_GLB_PIPE_PAYLOAD_SHIFT) + /* pipeline set state ipc msg */ #define SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT 16 #define SOF_IPC4_GLB_PIPE_STATE_ID_MASK GENMASK(23, 16) @@ -536,12 +540,63 @@ enum sof_ipc4_notification_type { SOF_IPC4_NOTIFY_TYPE_LAST, }; +enum sof_ipc4_resource_type { + SOF_IPC4_MODULE_INSTANCE, + SOF_IPC4_PIPELINE, + SOF_IPC4_GATEWAY, + SOF_IPC4_EDF_TASK, + SOF_IPC4_INVALID_RESOURCE_TYPE, +}; + +enum sof_ipc4_event_type { + /* Underrun detected by the Mixer */ + SOF_IPC4_MIXER_UNDERRUN_DETECTED = 1, + /* Error caught during data processing */ + SOF_IPC4_PROCESS_DATA_ERROR = 3, + /* Underrun detected by gateway. */ + SOF_IPC4_GATEWAY_UNDERRUN_DETECTED = 6, + /* Overrun detected by gateway */ + SOF_IPC4_GATEWAY_OVERRUN_DETECTED, +}; + +/** + * struct sof_ipc4_process_data_error_event_data - process data error event payload + * @error_code: Error code returned by data processing function + */ +struct sof_ipc4_process_data_error_event_data { + uint32_t error_code; +}; + +/** + * struct sof_ipc4_mixer_underrun_event_data - mixer underrun event payload + * @eos_flag: Indicates EndOfStream + * @data_mixed: Data processed by module (in bytes) + * @expected_data_mixed: Expected data to be processed (in bytes) + */ +struct sof_ipc4_mixer_underrun_event_data { + uint32_t eos_flag; + uint32_t data_mixed; + uint32_t expected_data_mixed; +}; + +/** + * union sof_ipc4_resource_event_data - resource event specific payload + * @dws: Raw event data payload as six dwords + * @process_data_error: SOF_IPC4_PROCESS_DATA_ERROR payload + * @mixer_underrun: SOF_IPC4_MIXER_UNDERRUN_DETECTED payload + */ +union sof_ipc4_resource_event_data { + uint32_t dws[6]; + struct sof_ipc4_process_data_error_event_data process_data_error; + struct sof_ipc4_mixer_underrun_event_data mixer_underrun; +}; + struct sof_ipc4_notify_resource_data { uint32_t resource_type; uint32_t resource_id; uint32_t event_type; uint32_t reserved; - uint32_t data[6]; + union sof_ipc4_resource_event_data data; } __packed __aligned(4); #define SOF_IPC4_DEBUG_DESCRIPTOR_SIZE 12 /* 3 x u32 */ @@ -654,11 +709,81 @@ enum sof_ipc4_mod_init_ext_obj_id { SOF_IPC4_MOD_INIT_DATA_ID_MAX = SOF_IPC4_MOD_INIT_DATA_ID_DP_DATA, }; -/* DP module memory configuration data object for ext_init object array */ +/* DP module memory configuration data object for object array */ struct sof_ipc4_mod_init_ext_dp_memory_data { + u32 domain_id; /* userspace domain ID */ + u32 stack_bytes; /* required stack size in bytes */ + u32 heap_bytes; /* required heap size in bytes */ +} __packed __aligned(4); + +/* + * This set of macros are very similar to the set above, but these are + * for building payload to SOF_IPC4_GLB_CREATE_PIPELINE message. + * + * Macros for creating struct sof_ipc4_glb_pipe_payload payload with + * its associated data. struct sof_ipc4_glb_pipe_payload should be the + * first piece of payload following SOF_IPC4_GLB_CREATE_PIPELINE msg, + * and its existence is indicated with SOF_IPC4_GLB_PIPE_PAYLOAD bit. + * + * The macros below apply to sof_ipc4_glb_pipe_payload.word0 + */ +#define SOF_IPC4_GLB_PIPE_PAYLOAD_WORDS_SHIFT 0 +#define SOF_IPC4_GLB_PIPE_PAYLOAD_WORDS_MASK GENMASK(23, 0) +#define SOF_IPC4_GLB_PIPE_PAYLOAD_WORDS(x) ((x) << SOF_IPC4_GLB_PIPE_PAYLOAD_WORDS_SHIFT) + +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY_SHIFT 24 +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY_MASK BIT(24) +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY_SHIFT) + +struct sof_ipc4_glb_pipe_payload { + u32 word0; + u32 rsvd1; + u32 rsvd2; +} __packed __aligned(4); + +/* + * SOF_IPC4_GLB_CREATE_PIPELINE payload may be followed by arbitrary + * number of object array objects. SOF_IPC4_GLB_PIPE_EXT_OBJ_ARRAY-bit + * indicates that an array object follows struct + * sof_ipc4_glb_pipe_payload. + * + * The object header's SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST-bit in struct + * sof_ipc4_glb_pipe_ext_object indicates if the array is continued + * with another object. The header has also fields to identify the + * object, SOF_IPC4_GLB_PIPE_EXT_OBJ_ID, and to indicate the object's + * size in 32-bit words, SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS, not + * including the header itself. + * + * The macros below apply to sof_ipc4_glb_pipe_ext_object.header + */ +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST_SHIFT 0 +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST_MASK BIT(0) +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_OBJ_LAST_SHIFT) + +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ID_SHIFT 1 +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ID_MASK GENMASK(15, 1) +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_ID(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_OBJ_ID_SHIFT) + +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS_SHIFT 16 +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS_MASK GENMASK(31, 16) +#define SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_OBJ_WORDS_SHIFT) + +struct sof_ipc4_glb_pipe_ext_object { + u32 header; + u32 data[]; +} __packed __aligned(4); + +enum sof_ipc4_glb_pipe_ext_obj_id { + SOF_IPC4_GLB_PIPE_DATA_ID_INVALID = 0, + SOF_IPC4_GLB_PIPE_DATA_ID_MEM_DATA, + SOF_IPC4_GLB_PIPE_DATA_ID_MAX = SOF_IPC4_GLB_PIPE_DATA_ID_MEM_DATA, +}; + +/* Pipeline memory configuration data object for ext_init object array */ +struct sof_ipc4_glb_pipe_ext_obj_memory_data { u32 domain_id; /* userspace domain ID */ - u32 stack_bytes; /* stack size in bytes, 0 means default size */ - u32 heap_bytes; /* stack size in bytes, 0 means default size */ + u32 stack_bytes; /* stack size in bytes */ + u32 heap_bytes; /* heap size in bytes */ } __packed __aligned(4); /** @}*/ diff --git a/include/sound/tas2781-dsp.h b/include/sound/tas2781-dsp.h index dd6ee45ad096..e845687decf9 100644 --- a/include/sound/tas2781-dsp.h +++ b/include/sound/tas2781-dsp.h @@ -202,6 +202,11 @@ struct tasdevice_rca { struct tasdevice_config_info **cfg_info; int profile_cfg_id; /* + * Used among SmartAMP for PDM microphone recording or IV data + * capture. + */ + int capture_profile_id; + /* * Since version 0x105, the keyword 'init' was introduced into the * profile, which is used for chip initialization, particularly to * store common settings for other non-initialization profiles. @@ -222,7 +227,7 @@ void tasdevice_calbin_remove(void *context); int tasdevice_select_tuningprm_cfg(void *context, int prm, int cfg_no, int rca_conf_no); int tasdevice_prmg_load(void *context, int prm_no); -void tasdevice_tuning_switch(void *context, int state); +void tasdevice_tuning_switch(void *context, int state, bool is_cap); int tas2781_load_calibration(void *context, char *file_name, unsigned short i); diff --git a/include/sound/tas2781.h b/include/sound/tas2781.h index 95296bb4a33a..b763da613769 100644 --- a/include/sound/tas2781.h +++ b/include/sound/tas2781.h @@ -59,9 +59,9 @@ #define TASDEVICE_CHECKSUM_REG TASDEVICE_REG(0x0, 0x0, 0x7e) /* XM_340 */ -#define TASDEVICE_XM_A1_REG TASDEVICE_REG(0x64, 0x63, 0x3c) +#define TASDEVICE_XM_A1_REG TASDEVICE_REG(0x64, 0x02, 0x4c) /* XM_341 */ -#define TASDEVICE_XM_A2_REG TASDEVICE_REG(0x64, 0x63, 0x38) +#define TASDEVICE_XM_A2_REG TASDEVICE_REG(0x64, 0x02, 0x64) /* Volume control */ #define TAS2563_DVC_LVL TASDEVICE_REG(0x00, 0x02, 0x0c) @@ -120,6 +120,7 @@ enum audio_device { TAS2568, TAS2570, TAS2572, + TAS2573, TAS2574, TAS2781, TAS5802, diff --git a/include/sound/timer.h b/include/sound/timer.h index 83bafe70cf33..e549eab7145b 100644 --- a/include/sound/timer.h +++ b/include/sound/timer.h @@ -75,6 +75,7 @@ struct snd_timer { struct list_head ack_list_head; struct list_head sack_list_head; /* slow ack list head */ struct work_struct task_work; + struct kref kref; int max_instances; /* upper limit of timer instances */ int num_instances; /* current number of timer instances */ }; @@ -131,4 +132,9 @@ int snd_timer_pause(struct snd_timer_instance *timeri); void snd_timer_interrupt(struct snd_timer *timer, unsigned long ticks_left); +struct snd_timer *snd_timeri_timer_get(struct snd_timer_instance *timeri); +void snd_timeri_timer_put(struct snd_timer *timer); + +DEFINE_FREE(snd_timeri_timer, struct snd_timer *, if (_T) snd_timeri_timer_put(_T)) + #endif /* __SOUND_TIMER_H */ diff --git a/include/sound/tlv320aic32x4.h b/include/sound/tlv320aic32x4.h deleted file mode 100644 index b779d671a995..000000000000 --- a/include/sound/tlv320aic32x4.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * tlv320aic32x4.h -- TLV320AIC32X4 Soc Audio driver platform data - * - * Copyright 2011 Vista Silicon S.L. - * - * Author: Javier Martin <javier.martin@vista-silicon.com> - */ - -#ifndef _AIC32X4_PDATA_H -#define _AIC32X4_PDATA_H - -#define AIC32X4_PWR_MICBIAS_2075_LDOIN 0x00000001 -#define AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE 0x00000002 -#define AIC32X4_PWR_AIC32X4_LDO_ENABLE 0x00000004 -#define AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36 0x00000008 -#define AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED 0x00000010 - -#define AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K 0x00000001 -#define AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K 0x00000002 - -/* GPIO API */ -#define AIC32X4_MFPX_DEFAULT_VALUE 0xff - -#define AIC32X4_MFP1_DIN_DISABLED 0 -#define AIC32X4_MFP1_DIN_ENABLED 0x2 -#define AIC32X4_MFP1_GPIO_IN 0x4 - -#define AIC32X4_MFP2_GPIO_OUT_LOW 0x0 -#define AIC32X4_MFP2_GPIO_OUT_HIGH 0x1 - -#define AIC32X4_MFP_GPIO_ENABLED 0x4 - -#define AIC32X4_MFP5_GPIO_DISABLED 0x0 -#define AIC32X4_MFP5_GPIO_INPUT 0x8 -#define AIC32X4_MFP5_GPIO_OUTPUT 0xc -#define AIC32X4_MFP5_GPIO_OUT_LOW 0x0 -#define AIC32X4_MFP5_GPIO_OUT_HIGH 0x1 - -struct aic32x4_setup_data { - unsigned int gpio_func[5]; -}; -#endif diff --git a/include/sound/wm8904.h b/include/sound/wm8904.h index 8b2c16b524f7..151a05b13dfc 100644 --- a/include/sound/wm8904.h +++ b/include/sound/wm8904.h @@ -116,7 +116,7 @@ #define WM8904_DRC_REGS 4 #define WM8904_EQ_REGS 24 -/** +/* * DRC configurations are specified with a label and a set of register * values to write (the enable bits will be ignored). At runtime an * enumerated control will be presented for each DRC block allowing @@ -131,7 +131,7 @@ struct wm8904_drc_cfg { u16 regs[WM8904_DRC_REGS]; }; -/** +/* * ReTune Mobile configurations are specified with a label, sample * rate and set of values to write (the enable bits will be ignored). * |