ALL_CRTCS, &adp_plane_funcs,

plane_formats, ARRAY_SIZE(plane_formats),

NULL, DRM_PLANE_TYPE_PRIMARY, "plane");

drm_err(drm, "failed to allocate plane");

}

drm_plane_helper_add(plane, &adp_plane_helper_funcs);

{

const struct aca_bank_ops *bank_ops = handle->bank_ops;

if (!aca_bank_hwip_is_matched(bank, handle->hwip))

return false;

(ACA_REG__STATUS__POISON((bank)->regs[ACA_REG_IDX_STATUS]) || \

ACA_REG__STATUS__DEFERRED((bank)->regs[ACA_REG_IDX_STATUS]))

enum aca_reg_idx {

ACA_REG_IDX_CTL = 0,

ACA_REG_IDX_STATUS = 1,

return true;

}

static bool amdgpu_get_bios_dgpu(struct amdgpu_device *adev)

{

if (amdgpu_atrm_get_bios(adev)) {

goto success;

}

}

if (amdgpu_read_bios_from_rom(adev)) {

}

static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj,

loff_t ppos, size_t count)

{

struct device *dev = kobj_to_dev(kobj);

return bytes_read;

}

int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev)

{

};

static const struct pci_device_id pciidlist[] = {

{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},

{0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},

{0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},

{0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},

{0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},

{0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},

/* Kaveri */

{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},

{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},

{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},

{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},

{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},

/* topaz */

{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},

{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},

return -ENOTSUPP;

}

#ifdef CONFIG_DRM_AMDGPU_SI

dev_info(&pdev->dev,

"SI support provided by radeon.\n");

dev_info(&pdev->dev,

);

return -ENODEV;

}

#endif

#ifdef CONFIG_DRM_AMDGPU_CIK

dev_info(&pdev->dev,

"CIK support provided by radeon.\n");

dev_info(&pdev->dev,

);

return -ENODEV;

}

#endif

adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);

if (IS_ERR(adev))

} while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);

seq != ring->fence_drv.sync_seq)

amdgpu_fence_schedule_fallback(ring);

amdgpu_irq_put(adev, ring->fence_drv.irq_src,

ring->fence_drv.irq_type);

}

}

return;

amdgpu_mes_remove_hw_queue(adev, ring->hw_queue_id);

amdgpu_ring_fini(ring);

kfree(ring);

}

}

static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,

char *buffer, loff_t pos, size_t count)

{

struct device *dev = kobj_to_dev(kobj);

}

static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,

loff_t pos, size_t count)

{

struct device *dev = kobj_to_dev(kobj);

* Writing to this file will stage an IFWI for update. Reading from this file

* will trigger the update process.

*/

.attr = {.name = "psp_vbflash", .mode = 0660},

.size = 0,

};

/**

}

static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);

&psp_vbflash_bin_attr,

NULL

};

const struct attribute_group amdgpu_flash_attr_group = {

.attrs = flash_attrs,

.is_bin_visible = amdgpu_bin_flash_attr_is_visible,

.is_visible = amdgpu_flash_attr_is_visible,

};

"jpeg",

"ih",

"mpio",

};

const char *ras_mca_block_string[] = {

*/

static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,

char *buf, loff_t ppos, size_t count)

{

struct amdgpu_ras *con =

/* debugfs end */

/* ras fs */

static DEVICE_ATTR(features, S_IRUGO,

amdgpu_ras_sysfs_features_read, NULL);

static DEVICE_ATTR(version, 0444,

&con->event_state_attr.attr,

NULL

};

NULL,

NULL,

};

if (amdgpu_bad_page_threshold != 0) {

/* add bad_page_features entry */

con->badpages_attr = bin_attr_gpu_vram_bad_pages;

bin_attrs[0] = &con->badpages_attr;

}

r = sysfs_create_group(&adev->dev->kobj, &group);

AMDGPU_RAS_BLOCK__JPEG,

AMDGPU_RAS_BLOCK__IH,

AMDGPU_RAS_BLOCK__MPIO,

AMDGPU_RAS_BLOCK__LAST,

AMDGPU_RAS_BLOCK__ANY = -1

return TA_RAS_BLOCK__VCN;

case AMDGPU_RAS_BLOCK__JPEG:

return TA_RAS_BLOCK__JPEG;

default:

WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);

return TA_RAS_BLOCK__UMC;

size_t size, loff_t *pos)

{

struct amdgpu_ring *ring = file_inode(f)->i_private;

}

static const struct file_operations amdgpu_debugfs_mqd_fops = {

}

}

mux->s_resubmit = false;

}

break;

case ACA_SMU_TYPE_CE:

count = ext_error_code == 6 ? count : 0ULL;

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, count);

break;

default:

break;

case AMDGPU_DPX_PARTITION_MODE:

num_xcp = 2;

break;

case AMDGPU_TPX_PARTITION_MODE:

num_xcp = 3;

static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)

{

int r, i;

for (i = 0; i < adev->gfx.num_gfx_rings; i++) {

if (r)

return r;

}

static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)

{

return 0;

}

static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)

{

gfx_v10_0_cp_compute_enable(adev, true);

for (i = 0; i < adev->gfx.num_compute_rings; i++) {

if (r)

}

}

static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)

if (r)

return r;

if (r) {

return r;

}

return r;

}

if (r) {

return r;

}

adev->gfx.me.num_me = 1;

adev->gfx.me.num_pipe_per_me = 1;

adev->gfx.me.num_queue_per_pipe = 1;

adev->gfx.mec.num_pipe_per_mec = 4;

adev->gfx.mec.num_queue_per_pipe = 4;

break;

static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)

{

int r, i;

for (i = 0; i < adev->gfx.num_gfx_rings; i++) {

if (r)

return r;

}

static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev)

{

return 0;

}

static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev)

{

if (!amdgpu_async_gfx_ring)

gfx_v11_0_cp_compute_enable(adev, true);

for (i = 0; i < adev->gfx.num_compute_rings; i++) {

if (r)

}

}

static int gfx_v11_0_cp_resume(struct amdgpu_device *adev)

if (r)

return r;

if (r) {

return r;

}

return r;

}

if (r) {

return r;

}

r = amdgpu_mes_map_legacy_queue(adev, ring);

adev->gfx.me.num_me = 1;

adev->gfx.me.num_pipe_per_me = 1;

adev->gfx.me.num_queue_per_pipe = 1;

adev->gfx.mec.num_pipe_per_mec = 2;

adev->gfx.mec.num_queue_per_pipe = 4;

break;

static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)

{

for (i = 0; i < adev->gfx.num_gfx_rings; i++) {

if (r)

}

r = amdgpu_gfx_enable_kgq(adev, 0);

if (r)

}

static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,

static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev)

{

return 0;

}

static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev)

{

if (!amdgpu_async_gfx_ring)

gfx_v12_0_cp_compute_enable(adev, true);

for (i = 0; i < adev->gfx.num_compute_rings; i++) {

if (r)

}

}

static int gfx_v12_0_cp_resume(struct amdgpu_device *adev)

return r;

}

if (r) {

return r;

}

return r;

}

if (r) {

return r;

}

r = amdgpu_mes_map_legacy_queue(adev, ring);

static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)

{

return 0;

}

static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)

{

gfx_v8_0_cp_compute_enable(adev, true);

for (i = 0; i < adev->gfx.num_compute_rings; i++) {

if (r)

}

gfx_v8_0_set_mec_doorbell_range(adev);

}

static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)

adev->gfx.mec_fw_write_wait = false;

if ((amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 1)) &&

((adev->gfx.mec_fw_version < 0x000001a5) ||

(adev->gfx.mec_feature_version < 46) ||

(adev->gfx.pfp_fw_version < 0x000000b7) ||

static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)

{

return 0;

}

static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)

{

gfx_v9_0_cp_compute_enable(adev, true);

for (i = 0; i < adev->gfx.num_compute_rings; i++) {

if (r)

}

}

static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)

return r;

}

if (r) {

return r;

}

spin_lock_irqsave(&kiq->ring_lock, flags);

switch (type) {

case ACA_SMU_TYPE_UE:

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1ULL);

break;

case ACA_SMU_TYPE_CE:

ACA_REG__MISC0__ERRCNT(misc0));

break;

default:

static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id)

{

return 0;

}

static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id)

{

gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id);

for (i = 0; i < adev->gfx.num_compute_rings; i++) {

if (r)

}

}

static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id)

return r;

}

if (r) {

return r;

}

spin_lock_irqsave(&kiq->ring_lock, flags);

1ULL);

break;

case ACA_SMU_TYPE_CE:

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

ACA_REG__MISC0__ERRCNT(misc0));

break;

1ULL);

break;

case ACA_SMU_TYPE_CE:

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

ACA_REG__MISC0__ERRCNT(misc0));

break;

#include "amdgpu_ucode.h"

#include "amdgpu_trace.h"

#include "amdgpu_reset.h"

#include "sdma/sdma_4_4_2_offset.h"

#include "sdma/sdma_4_4_2_sh_mask.h"

seq, 0xffffffff, 4);

}

*

*/

static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,

{

}

static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,

3 + /* hdp invalidate */

6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */

/* sdma_v4_4_2_ring_emit_vm_flush */

10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */

.emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */

.emit_ib = sdma_v4_4_2_ring_emit_ib,

3 + /* hdp invalidate */

6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */

/* sdma_v4_4_2_ring_emit_vm_flush */

10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */

.emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */

.emit_ib = sdma_v4_4_2_ring_emit_ib,

1ULL);

break;

case ACA_SMU_TYPE_CE:

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

ACA_REG__MISC0__ERRCNT(misc0));

break;

TA_RAS_BLOCK__MCA,

TA_RAS_BLOCK__VCN,

TA_RAS_BLOCK__JPEG,

TA_NUM_BLOCK_MAX

};

return (amdgpu_ras_is_poison_mode_supported(adev) &&

(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&

}

bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status)

1ULL);

break;

case ACA_SMU_TYPE_CE:

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

ACA_REG__MISC0__ERRCNT(misc0));

break;

#define HEADER_BARRIER 5

#define SDMA_OP_AQL_COPY 0

#define SDMA_OP_AQL_BARRIER_OR 0

/*define for op field*/

#define SDMA_PKT_HEADER_op_offset 0

#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0

#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift)

#endif /* __SDMA_PKT_OPEN_H_ */

int offdelay;

if (acrtc_state) {

offdelay = DIV64_U64_ROUND_UP((u64)20 *

timing->v_total *

timing->h_total,

config.offdelay_ms = offdelay ?: 30;

} else {

config.disable_immediate = true;

}

* incorrect/corrupted and we should correct our SRM by getting it from PSP

*/

static ssize_t srm_data_write(struct file *filp, struct kobject *kobj,

loff_t pos, size_t count)

{

struct hdcp_workqueue *work;

}

static ssize_t srm_data_read(struct file *filp, struct kobject *kobj,

loff_t pos, size_t count)

{

struct hdcp_workqueue *work;

static const struct bin_attribute data_attr = {

.attr = {.name = "hdcp_srm", .mode = 0664},

.size = PSP_HDCP_SRM_FIRST_GEN_MAX_SIZE, /* Limit SRM size */

};

struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev,

p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz;

p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz;

p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz;

p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz;

/* Dependent states. */

p->out_states->state_array[i].dram_speed_mts = p->in_states->state_array[i].dram_speed_mts;

p->out_states->state_array[i].fabricclk_mhz = p->in_states->state_array[i].fabricclk_mhz;

p->out_states->state_array[i].socclk_mhz = p->in_states->state_array[i].socclk_mhz;

dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);

phyd32clk = get_phyd32clk_src(link);

} else {

if (dccg->funcs->enable_symclk_se)

dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) {

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

dccg->funcs->set_dpstreamclk(dccg, DPREFCLK, tg->inst, dp_hpo_inst);

} else {

dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

link_enc->transmitter - TRANSMITTER_UNIPHY_A);

#define MAX_CLKS 4

#define NUM_VCN 4

#define NUM_JPEG_ENG 32

#define MAX_XCC 8

#define NUM_XCP 8

struct seq_file;

uint64_t gfx_below_host_limit_acc[MAX_XCC];

};

struct amd_pm_funcs {

/* export for dpm on ci and si */

int (*pre_set_power_state)(void *handle);

uint32_t pcie_lc_perf_other_end_recovery;

};

/*

* gpu_metrics_v2_0 is not recommended as it's not naturally aligned.

* Use gpu_metrics_v2_1 or later instead.

if (hwmgr->thermal_controller.fanInfo.bNoFan ||

(hwmgr->thermal_controller.fanInfo.

ucTachometerPulsesPerRevolution == 0) ||

(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||

(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))

if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))

smu7_fan_ctrl_stop_smc_fan_control(hwmgr);

int result = 0;

if (hwmgr->thermal_controller.fanInfo.bNoFan ||

(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||

(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))

if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))

result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);

uint32_t tach_period, crystal_clock_freq;

int result = 0;

return -EINVAL;

if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {

VOLTAGE_GUARDBAND_COUNT

} GFX_GUARDBAND_e;

// Unified metrics table for smu_v13_0_6

typedef struct __attribute__((packed, aligned(4))) {

uint32_t PCIeOtherEndRecoveryAcc; // The Pcie counter itself is accumulated

//Total App Clock Counter

} MetricsTableV0_t;

// Metrics table for smu_v13_0_6 APUS

uint32_t crystal_clock_freq = 2500;

uint32_t tach_period;

tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);

WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT,

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),

uint32_t tach_period;

int ret;

return -EINVAL;

ret = smu_v13_0_auto_fan_control(smu, 0);

SMU_CAP(OTHER_END_METRICS),

SMU_CAP(SET_UCLK_MAX),

SMU_CAP(PCIE_METRICS),

SMU_CAP(MCA_DEBUG_MODE),

SMU_CAP(PER_INST_METRICS),

SMU_CAP(CTF_LIMIT),

if (fw_ver >= 0x05550E00)

smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));

if (fw_ver >= 0x05550B00)

smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));

if (fw_ver >= 0x5551200)

SMU_CAP(RMA_MSG),

SMU_CAP(ACA_SYND),

SMU_CAP(OTHER_END_METRICS),

SMU_CAP(PER_INST_METRICS) };

uint32_t fw_ver = smu->smc_fw_version;

smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));

smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));

if (fw_ver >= 0x04556A00)

smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));

} else {

smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));

if (fw_ver < 0x00555600)

smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));

}

if (((pgm == 7) && (fw_ver >= 0x7550700)) ||

((pgm == 0) && (fw_ver >= 0x00557900)) ||

gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] =

SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusyAcc,

version)[inst]);

idx++;

}

}

#define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8

#define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9

#define PP_OD_FEATURE_FAN_MINIMUM_PWM 10

static struct cmn2asic_msg_mapping smu_v14_0_2_message_map[SMU_MSG_MAX_COUNT] = {

MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),

od_min_setting = overdrive_lowerlimits->FanMinimumPwm;

od_max_setting = overdrive_upperlimits->FanMinimumPwm;

break;

default:

od_min_setting = od_max_setting = INT_MAX;

break;

min_value, max_value);

break;

case SMU_OD_RANGE:

if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&

!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&

OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |

OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |

OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |

}

static int smu_v14_0_2_get_overdrive_table(struct smu_context *smu,

user_od_table_bak.OverDriveTable.FanTargetTemperature;

user_od_table->OverDriveTable.FanMinimumPwm =

user_od_table_bak.OverDriveTable.FanMinimumPwm;

}

smu_v14_0_2_set_supported_od_feature_mask(smu);

od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;

od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);

break;

case PP_OD_EDIT_ACOUSTIC_LIMIT:

od_table->OverDriveTable.AcousticLimitRpmThreshold =

boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;

od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);

break;

case PP_OD_RESTORE_DEFAULT_TABLE:

if (size == 1) {

ret = smu_v14_0_2_od_restore_table_single(smu, input[0]);

case METRICS_VERSION(1, 7):

structure_size = sizeof(struct gpu_metrics_v1_7);

break;

case METRICS_VERSION(2, 0):

structure_size = sizeof(struct gpu_metrics_v2_0);

break;

Support for i.MX8MP DPI-to-LVDS on-SoC encoder.

config DRM_I2C_NXP_TDA998X

config DRM_ITE_IT6263

tristate "ITE IT6263 LVDS/HDMI bridge"

if (priv->hdmi->irq)

free_irq(priv->hdmi->irq, priv);

cancel_work_sync(&priv->detect_work);

i2c_unregister_device(priv->cec);

goto err_unmap;

}

zdd = page->zone_device_data;

if (i > 0) {

err = -EOPNOTSUPP;

goto err_unmap;

}

dpagemap = zdd->devmem_allocation->dpagemap;

if (drm_WARN_ON(gpusvm->drm, !dpagemap)) {

/*

stream.workspace = NULL;

}

static int drm_panic_get_qr_code_url(u8 **qr_image)

{

struct kmsg_dump_iter iter;

//! * <https://github.com/erwanvivien/fast_qr>

//! * <https://github.com/bjguillot/qr>

#[derive(Debug, Clone, Copy, PartialEq, Eq, Ord, PartialOrd)]

struct Version(usize);

/// * `tmp` must be valid for reading and writing for `tmp_size` bytes.

///

/// They must remain valid for the duration of the function call.

pub unsafe extern "C" fn drm_panic_qr_generate(

url: *const kernel::ffi::c_char,

data: *mut u8,

/// * If `url_len` > 0, remove the 2 segments header/length and also count the

/// conversion to numeric segments.

/// * If `url_len` = 0, only removes 3 bytes for 1 binary segment.

#[expect(clippy::manual_range_contains)]

if version < 1 || version > 40 {

return 0;

}

static ssize_t edid_show(struct file *filp, struct kobject *kobj,

size_t count)

{

struct device *connector_dev = kobj_to_dev(kobj);

NULL

};

.attr.name = "edid",

.attr.mode = 0444,

.size = 0,

};

&edid_attr,

NULL

};

static const struct attribute_group connector_dev_group = {

.attrs = connector_dev_attrs,

};

static const struct attribute_group *connector_dev_groups[] = {

drm_core_check_feature(dev, DRIVER_MODESET));

drm_vblank_destroy_worker(vblank);

}

/**

{

struct vidi_context *ctx = dev_get_drvdata(dev);

}

static const struct component_ops vidi_component_ops = {

usb_sg_wait(&ctx.sgr);

ret = -ETIMEDOUT;

else if (ctx.sgr.status < 0)

ret = ctx.sgr.status;

#ifndef __INTEL_FBDEV_H__

#define __INTEL_FBDEV_H__

struct drm_fb_helper;

struct drm_fb_helper_surface_size;

struct drm_i915_private;

static int

dsc_prefill_latency(const struct intel_crtc_state *crtc_state)

{

const struct intel_crtc_scaler_state *scaler_state =

&crtc_state->scaler_state;

int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,

crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;

u32 dsc_prefill_latency = 0;

return dsc_prefill_latency;

dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);

ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI));

ENGINE_TRACE(engine, "semaphore yield: %08x\n",

engine->execlists.yield);

tasklet = true;

}

static void execlists_shutdown(struct intel_engine_cs *engine)

{

/* Synchronise with residual timers and any softirq they raise */

tasklet_kill(&engine->sched_engine->tasklet);

}

static void rps_stop_timer(struct intel_rps *rps)

{

rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp);

cancel_work_sync(&rps->work);

}

struct i915_request *rq;

unsigned long flags;

spin_lock_irqsave(&engine->sched_engine->lock, flags);

container_of(engine, typeof(*mock), base);

struct i915_request *request, *rn;

spin_lock_irq(&mock->hw_lock);

list_for_each_entry_safe(request, rn, &mock->hw_queue, mock.link)

ENGINE_TRACE(engine, "forcing tasklet for rewind\n");

while (i915_request_is_active(rq[A2])) { /* semaphore yield! */

/* Wait for the timeslice to kick in */

tasklet_hi_schedule(&engine->sched_engine->tasklet);

intel_engine_flush_submission(engine);

}

/* force preempt reset [failure] */

while (!engine->execlists.pending[0])

intel_engine_flush_submission(engine);

intel_engine_flush_submission(engine);

cancel_reset_timeout(engine);

out_rq:

i915_request_add(rq); /* GEM_BUG_ON(rq->reserved_space > ring->space)? */

destroy_timer_on_stack(&st.timer);

out_unpin:

intel_context_unpin(ce);

}

static ssize_t error_state_read(struct file *filp, struct kobject *kobj,

loff_t off, size_t count)

{

}

static ssize_t error_state_write(struct file *file, struct kobject *kobj,

loff_t off, size_t count)

{

struct device *kdev = kobj_to_dev(kobj);

.attr.name = "error",

.attr.mode = S_IRUSR | S_IWUSR,

.size = 0,

};

void i915_gpu_error_sysfs_setup(struct drm_i915_private *i915)

{

return 0;

}

#endif

#endif /* __I915_IOSF_MBI_H__ */

static ssize_t

i915_l3_read(struct file *filp, struct kobject *kobj,

loff_t offset, size_t count)

{

struct device *kdev = kobj_to_dev(kobj);

static ssize_t

i915_l3_write(struct file *filp, struct kobject *kobj,

loff_t offset, size_t count)

{

struct device *kdev = kobj_to_dev(kobj);

static const struct bin_attribute dpf_attrs = {

.attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},

.size = GEN7_L3LOG_SIZE,

.mmap = NULL,

.private = (void *)0

};

static const struct bin_attribute dpf_attrs_1 = {

.attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},

.size = GEN7_L3LOG_SIZE,

.mmap = NULL,

.private = (void *)1

};

if (!timer_active(t))

return;

WRITE_ONCE(t->expires, 0);

}

unsigned long flags;

if (!timeout) {

wakeref_auto_timeout(&wf->timer);

return;

}

void timed_fence_fini(struct timed_fence *tf)

{

i915_sw_fence_commit(&tf->fence);

destroy_timer_on_stack(&tf->timer);

}

static ssize_t lima_error_state_read(struct file *filp, struct kobject *kobj,

loff_t off, size_t count)

{

struct device *dev = kobj_to_dev(kobj);

}

static ssize_t lima_error_state_write(struct file *file, struct kobject *kobj,

loff_t off, size_t count)

{

struct device *dev = kobj_to_dev(kobj);

.attr.name = "error",

.attr.mode = 0600,

.size = 0,

};

static int lima_pdev_probe(struct platform_device *pdev)

pm_runtime_put(&pdev->dev);

pm_runtime_disable(&pdev->dev);

if (mtk_dp->data->bridge_type != DRM_MODE_CONNECTOR_eDP)

platform_device_unregister(mtk_dp->phy_dev);

if (mtk_dp->audio_pdev)

platform_device_unregister(mtk_dp->audio_pdev);

gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ));

/* Turn off the hangcheck timer to keep it from bothering us */

kthread_queue_work(gpu->worker, &gpu->recover_work);

}

return;

/* Delete the preemption watchdog timer */

/*

* The hardware should be setting CP_CONTEXT_SWITCH_CNTL to zero before

gmu->hung = true;

/* Turn off the hangcheck timer while we are resetting */

/* Queue the GPU handler because we need to treat this as a recovery */

kthread_queue_work(gpu->worker, &gpu->recover_work);

gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));

/* Turn off the hangcheck timer to keep it from bothering us */

kthread_queue_work(gpu->worker, &gpu->recover_work);

}

*/

if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |

A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {

kthread_queue_work(gpu->worker, &gpu->recover_work);

}

return;

/* Delete the preemption watchdog timer */

/*

* The hardware should be setting the stop bit of CP_CONTEXT_SWITCH_CNTL

if (do_devcoredump) {

/* Turn off the hangcheck timer to keep it from bothering us */

gpu->fault_info.ttbr0 = info->ttbr0;

gpu->fault_info.iova = iova;

/* after phys waits for frame-done, should be no more frames pending */

if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {

DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);

}

dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);

if (!dpu_enc->frame_busy_mask[0]) {

atomic_set(&dpu_enc->frame_done_timeout_ms, 0);

dpu_encoder_resource_control(drm_enc,

DPU_ENC_RC_EVENT_FRAME_DONE);

static struct nouveau_dmem_chunk *nouveau_page_to_chunk(struct page *page)

{

}

static struct nouveau_drm *page_to_drm(struct page *page)

notifier_seq = mmu_interval_read_begin(&notifier->notifier);

mmap_read_lock(mm);

mmap_read_unlock(mm);

ret = -EINVAL;

goto out;

}

#ifdef DSI_CATCH_MISSING_TE

if (irqstatus & DSI_IRQ_TE_TRIGGER)

#endif

/* make a copy and unlock, so that isrs can unregister

struct vc4_dev *vc4 = to_vc4_dev(dev);

int i;

cancel_work_sync(&vc4->bo_cache.time_work);

vc4_bo_cache_purge(dev);

{

struct vgem_fence *fence = container_of(base, typeof(*fence), base);

dma_fence_free(&fence->base);

}

return -EINVAL;

}

/**

config DRM_XE_DISPLAY

bool "Enable display support"

depends on DRM_XE && DRM_XE=m && HAS_IOPORT

select I2C

select I2C_ALGOBIT

default y

#define RING_EXECLIST_STATUS_LO(base) XE_REG((base) + 0x234)

#define RING_EXECLIST_STATUS_HI(base) XE_REG((base) + 0x234 + 4)

#define RING_CONTEXT_CONTROL(base) XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)

#define CTX_CTRL_PXP_ENABLE REG_BIT(10)

#define CTX_CTRL_OAC_CONTEXT_ENABLE REG_BIT(8)

#include "xe_pxp.h"

#include "xe_query.h"

#include "xe_shrinker.h"

#include "xe_sriov.h"

#include "xe_tile.h"

#include "xe_ttm_stolen_mgr.h"

sriov_update_device_info(xe);

err = xe_pcode_probe_early(xe);

err = wait_for_lmem_ready(xe);

if (err)

goto exit_free;

}

exit_free:

mutex_destroy(&gt->eu_stall->stream_lock);

kfree(gt->eu_stall);

void xe_execlist_port_destroy(struct xe_execlist_port *port)

{

/* Prevent an interrupt while we're destroying */

spin_lock_irq(&gt_to_xe(port->hwe->gt)->irq.lock);

#include "xe_macros.h"

#include "xe_mmio.h"

{

u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK,

rpm_config_reg);

switch (crystal_clock) {

case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:

case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:

case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:

case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:

default:

}

}

{

/*

* CTC_MODE[0] = 1 is definitely not supported for Xe2 and later

* platforms. In theory it could be a valid setting for pre-Xe2

*/

if (xe_mmio_read32(&gt->mmio, CTC_MODE) & CTC_SOURCE_DIVIDE_LOGIC)

xe_gt_warn(gt, "CTC_MODE[0] is set; this is unexpected and undocumented\n");

/*

* Now figure out how the command stream's timestamp

enum xe_gt_type type;

/** @info.reference_clock: clock frequency */

u32 reference_clock;

/**

* @info.engine_mask: mask of engines present on GT. Some of

* them may be reserved in runtime and not available for user.

#include <linux/nospec.h>

#include <drm/drm_managed.h>

#include <uapi/drm/xe_drm.h>

#include "regs/xe_engine_regs.h"

#include "regs/xe_gt_regs.h"

#include "xe_gsc.h"

#include "xe_gt.h"

#include "xe_gt_ccs_mode.h"

#include "xe_gt_printk.h"

#include "xe_gt_mcr.h"

#include "xe_gt_topology.h"

xe_reg_whitelist_process_engine(hwe);

}

static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe,

enum xe_hw_engine_id id)

{

if (xe->info.has_usm && hwe->class == XE_ENGINE_CLASS_COPY)

gt->usm.reserved_bcs_instance = hwe->instance;

return devm_add_action_or_reset(xe->drm.dev, hw_engine_fini, hwe);

err_hwsp:

return err;

err = xe_device_probe_early(xe);

if (err) {

return 0;

return err;

if (ret)

return ret;

ret = xe_heci_gsc_init(xe);

return ret;

xe_vsec_init(xe);

dev_err(dev, "In Survivability Mode\n");

return 0;

return xe->survivability.mode;

}

*

*

*/

{

struct xe_survivability *survivability = &xe->survivability;

struct xe_mmio *mmio = xe_root_tile_mmio(xe);

*

* Initialize survivability information and enable survivability mode

*

*/

int xe_survivability_mode_enable(struct xe_device *xe)

{

struct xe_survivability_info *info;

struct pci_dev *pdev = to_pci_dev(xe->drm.dev);

survivability->size = MAX_SCRATCH_MMIO;

info = devm_kcalloc(xe->drm.dev, survivability->size, sizeof(*info),

int xe_survivability_mode_enable(struct xe_device *xe);

bool xe_survivability_mode_is_enabled(struct xe_device *xe);

#endif /* _XE_SURVIVABILITY_MODE_H_ */

static struct xe_vram_region *page_to_vr(struct page *page)

{

}

static struct xe_tile *vr_to_tile(struct xe_vram_region *vr)

FUNC(xe_rtp_match_first_render_or_compute)),

XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))

},

};

static const struct xe_rtp_entry_sr lrc_was[] = {

GRAPHICS_VERSION_RANGE(1270, 1274)

1508761755 GRAPHICS_VERSION(1255)

GRAPHICS_VERSION(1260), GRAPHICS_STEP(A0, B0)

// SPDX-License-Identifier: GPL-2.0

use crate::gpu::Gpu;

type IdInfo = ();

const ID_TABLE: pci::IdTable<Self::IdInfo> = &PCI_TABLE;

dev_dbg!(pdev.as_ref(), "Probe Nova Core GPU driver.\n");

pdev.enable_device_mem()?;

impl Boot0 {

#[inline]

pub(crate) fn read(bar: &Bar0) -> Self {

}

#[inline]