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path: root/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
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Diffstat (limited to 'drivers/gpu/drm/xe/display/xe_dsb_buffer.c')
-rw-r--r--drivers/gpu/drm/xe/display/xe_dsb_buffer.c96
1 files changed, 58 insertions, 38 deletions
diff --git a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
index f95375451e2f..a7158c73a14c 100644
--- a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
+++ b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
@@ -3,80 +3,100 @@
* Copyright 2023, Intel Corporation.
*/
-#include "i915_vma.h"
-#include "intel_display_types.h"
-#include "intel_dsb_buffer.h"
+#include <drm/intel/display_parent_interface.h>
+
#include "xe_bo.h"
#include "xe_device.h"
#include "xe_device_types.h"
+#include "xe_dsb_buffer.h"
+
+struct intel_dsb_buffer {
+ u32 *cmd_buf;
+ struct xe_bo *bo;
+ size_t buf_size;
+};
-u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
+static u32 xe_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
{
- return xe_bo_ggtt_addr(dsb_buf->vma->bo);
+ return xe_bo_ggtt_addr(dsb_buf->bo);
}
-void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
+static void xe_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
{
- struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
-
- iosys_map_wr(&dsb_buf->vma->bo->vmap, idx * 4, u32, val);
- xe_device_l2_flush(xe);
+ iosys_map_wr(&dsb_buf->bo->vmap, idx * 4, u32, val);
}
-u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
+static u32 xe_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
{
- return iosys_map_rd(&dsb_buf->vma->bo->vmap, idx * 4, u32);
+ return iosys_map_rd(&dsb_buf->bo->vmap, idx * 4, u32);
}
-void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
+static void xe_dsb_buffer_fill(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
{
- struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
-
WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
- iosys_map_memset(&dsb_buf->vma->bo->vmap, idx * 4, val, size);
- xe_device_l2_flush(xe);
+ iosys_map_memset(&dsb_buf->bo->vmap, idx * 4, val, size);
}
-bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)
+static struct intel_dsb_buffer *xe_dsb_buffer_create(struct drm_device *drm, size_t size)
{
- struct xe_device *xe = to_xe_device(crtc->base.dev);
+ struct xe_device *xe = to_xe_device(drm);
+ struct intel_dsb_buffer *dsb_buf;
struct xe_bo *obj;
- struct i915_vma *vma;
+ int ret;
- vma = kzalloc(sizeof(*vma), GFP_KERNEL);
- if (!vma)
- return false;
+ dsb_buf = kzalloc_obj(*dsb_buf);
+ if (!dsb_buf)
+ return ERR_PTR(-ENOMEM);
/* Set scanout flag for WC mapping */
- obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe),
- NULL, PAGE_ALIGN(size),
- ttm_bo_type_kernel,
- XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) |
- XE_BO_FLAG_SCANOUT | XE_BO_FLAG_GGTT);
+ obj = xe_bo_create_pin_map_novm(xe, xe_device_get_root_tile(xe),
+ PAGE_ALIGN(size),
+ ttm_bo_type_kernel,
+ XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) |
+ XE_BO_FLAG_FORCE_WC |
+ XE_BO_FLAG_GGTT,
+ false);
if (IS_ERR(obj)) {
- kfree(vma);
- return false;
+ ret = PTR_ERR(obj);
+ goto err_pin_map;
}
- vma->bo = obj;
- dsb_buf->vma = vma;
+ dsb_buf->bo = obj;
dsb_buf->buf_size = size;
- return true;
+ return dsb_buf;
+
+err_pin_map:
+ kfree(dsb_buf);
+
+ return ERR_PTR(ret);
}
-void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
+static void xe_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
{
- xe_bo_unpin_map_no_vm(dsb_buf->vma->bo);
- kfree(dsb_buf->vma);
+ xe_bo_unpin_map_no_vm(dsb_buf->bo);
+ kfree(dsb_buf);
}
-void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
+static void xe_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
{
+ struct xe_device *xe = dsb_buf->bo->tile->xe;
+
/*
* The memory barrier here is to ensure coherency of DSB vs MMIO,
* both for weak ordering archs and discrete cards.
*/
- xe_device_wmb(dsb_buf->vma->bo->tile->xe);
+ xe_device_wmb(xe);
+ xe_device_l2_flush(xe);
}
+
+const struct intel_display_dsb_interface xe_display_dsb_interface = {
+ .ggtt_offset = xe_dsb_buffer_ggtt_offset,
+ .write = xe_dsb_buffer_write,
+ .read = xe_dsb_buffer_read,
+ .fill = xe_dsb_buffer_fill,
+ .create = xe_dsb_buffer_create,
+ .cleanup = xe_dsb_buffer_cleanup,
+ .flush_map = xe_dsb_buffer_flush_map,
+};