diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dpp')
4 files changed, 81 insertions, 80 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h index f09cba8e29cc..85f359b5da67 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h @@ -26,7 +26,6 @@ #define __DCN20_DPP_H__ #include "dcn10/dcn10_dpp.h" -#include "spl/dc_spl_types.h" #define TO_DCN20_DPP(dpp)\ container_of(dpp, struct dcn20_dpp, base) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c index 40acebd13e46..abf439e743f2 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c @@ -425,11 +425,6 @@ bool dpp3_get_optimal_number_of_taps( int min_taps_y, min_taps_c; enum lb_memory_config lb_config; - if (scl_data->viewport.width > scl_data->h_active && - dpp->ctx->dc->debug.max_downscale_src_width != 0 && - scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) - return false; - /* * Set default taps if none are provided * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling @@ -467,6 +462,12 @@ bool dpp3_get_optimal_number_of_taps( else scl_data->taps.h_taps_c = in_taps->h_taps_c; + // Avoid null data in the scl data with this early return, proceed non-adaptive calcualtion first + if (scl_data->viewport.width > scl_data->h_active && + dpp->ctx->dc->debug.max_downscale_src_width != 0 && + scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) + return false; + /*Ensure we can support the requested number of vtaps*/ min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert); min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c); diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h index 992df172378c..f33dddbfcc31 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.h @@ -27,7 +27,6 @@ #include "dcn20/dcn20_dpp.h" #include "dcn30/dcn30_dpp.h" -#include "spl/dc_spl_types.h" bool dpp32_construct(struct dcn3_dpp *dpp3, struct dc_context *ctx, diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h index 4bc85aaf17da..ecaa976e1f52 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h @@ -567,80 +567,82 @@ type ISHARP_NLDELTA_SCLIP_PIVOT_N; \ type ISHARP_NLDELTA_SCLIP_SLOPE_N +#define DPP_REG_VARIABLE_LIST_DCN401 \ + DPP_DCN3_REG_VARIABLE_LIST_COMMON; \ + uint32_t CURSOR0_FP_SCALE_BIAS_G_Y; \ + uint32_t CURSOR0_FP_SCALE_BIAS_RB_CRCB; \ + uint32_t CUR0_MATRIX_MODE; \ + uint32_t CUR0_MATRIX_C11_C12_A; \ + uint32_t CUR0_MATRIX_C13_C14_A; \ + uint32_t CUR0_MATRIX_C21_C22_A; \ + uint32_t CUR0_MATRIX_C23_C24_A; \ + uint32_t CUR0_MATRIX_C31_C32_A; \ + uint32_t CUR0_MATRIX_C33_C34_A; \ + uint32_t CUR0_MATRIX_C11_C12_B; \ + uint32_t CUR0_MATRIX_C13_C14_B; \ + uint32_t CUR0_MATRIX_C21_C22_B; \ + uint32_t CUR0_MATRIX_C23_C24_B; \ + uint32_t CUR0_MATRIX_C31_C32_B; \ + uint32_t CUR0_MATRIX_C33_C34_B; \ + uint32_t DSCL_SC_MODE; \ + uint32_t DSCL_EASF_H_MODE; \ + uint32_t DSCL_EASF_H_BF_CNTL; \ + uint32_t DSCL_EASF_H_RINGEST_EVENTAP_REDUCE; \ + uint32_t DSCL_EASF_H_RINGEST_EVENTAP_GAIN; \ + uint32_t DSCL_EASF_H_BF_FINAL_MAX_MIN; \ + uint32_t DSCL_EASF_H_BF1_PWL_SEG0; \ + uint32_t DSCL_EASF_H_BF1_PWL_SEG1; \ + uint32_t DSCL_EASF_H_BF1_PWL_SEG2; \ + uint32_t DSCL_EASF_H_BF1_PWL_SEG3; \ + uint32_t DSCL_EASF_H_BF1_PWL_SEG4; \ + uint32_t DSCL_EASF_H_BF1_PWL_SEG5; \ + uint32_t DSCL_EASF_H_BF1_PWL_SEG6; \ + uint32_t DSCL_EASF_H_BF1_PWL_SEG7; \ + uint32_t DSCL_EASF_H_BF3_PWL_SEG0; \ + uint32_t DSCL_EASF_H_BF3_PWL_SEG1; \ + uint32_t DSCL_EASF_H_BF3_PWL_SEG2; \ + uint32_t DSCL_EASF_H_BF3_PWL_SEG3; \ + uint32_t DSCL_EASF_H_BF3_PWL_SEG4; \ + uint32_t DSCL_EASF_H_BF3_PWL_SEG5; \ + uint32_t DSCL_EASF_V_MODE; \ + uint32_t DSCL_EASF_V_BF_CNTL; \ + uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL1; \ + uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL2; \ + uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL3; \ + uint32_t DSCL_EASF_V_RINGEST_EVENTAP_REDUCE; \ + uint32_t DSCL_EASF_V_RINGEST_EVENTAP_GAIN; \ + uint32_t DSCL_EASF_V_BF_FINAL_MAX_MIN; \ + uint32_t DSCL_EASF_V_BF1_PWL_SEG0; \ + uint32_t DSCL_EASF_V_BF1_PWL_SEG1; \ + uint32_t DSCL_EASF_V_BF1_PWL_SEG2; \ + uint32_t DSCL_EASF_V_BF1_PWL_SEG3; \ + uint32_t DSCL_EASF_V_BF1_PWL_SEG4; \ + uint32_t DSCL_EASF_V_BF1_PWL_SEG5; \ + uint32_t DSCL_EASF_V_BF1_PWL_SEG6; \ + uint32_t DSCL_EASF_V_BF1_PWL_SEG7; \ + uint32_t DSCL_EASF_V_BF3_PWL_SEG0; \ + uint32_t DSCL_EASF_V_BF3_PWL_SEG1; \ + uint32_t DSCL_EASF_V_BF3_PWL_SEG2; \ + uint32_t DSCL_EASF_V_BF3_PWL_SEG3; \ + uint32_t DSCL_EASF_V_BF3_PWL_SEG4; \ + uint32_t DSCL_EASF_V_BF3_PWL_SEG5; \ + uint32_t DSCL_SC_MATRIX_C0C1; \ + uint32_t DSCL_SC_MATRIX_C2C3; \ + uint32_t ISHARP_MODE; \ + uint32_t ISHARP_NOISEDET_THRESHOLD; \ + uint32_t ISHARP_NOISE_GAIN_PWL; \ + uint32_t ISHARP_LBA_PWL_SEG0; \ + uint32_t ISHARP_LBA_PWL_SEG1; \ + uint32_t ISHARP_LBA_PWL_SEG2; \ + uint32_t ISHARP_LBA_PWL_SEG3; \ + uint32_t ISHARP_LBA_PWL_SEG4; \ + uint32_t ISHARP_LBA_PWL_SEG5; \ + uint32_t ISHARP_DELTA_CTRL; \ + uint32_t ISHARP_DELTA_DATA; \ + uint32_t ISHARP_DELTA_INDEX; \ + uint32_t ISHARP_NLDELTA_SOFT_CLIP struct dcn401_dpp_registers { - DPP_DCN3_REG_VARIABLE_LIST_COMMON; - uint32_t CURSOR0_FP_SCALE_BIAS_G_Y; - uint32_t CURSOR0_FP_SCALE_BIAS_RB_CRCB; - uint32_t CUR0_MATRIX_MODE; - uint32_t CUR0_MATRIX_C11_C12_A; - uint32_t CUR0_MATRIX_C13_C14_A; - uint32_t CUR0_MATRIX_C21_C22_A; - uint32_t CUR0_MATRIX_C23_C24_A; - uint32_t CUR0_MATRIX_C31_C32_A; - uint32_t CUR0_MATRIX_C33_C34_A; - uint32_t CUR0_MATRIX_C11_C12_B; - uint32_t CUR0_MATRIX_C13_C14_B; - uint32_t CUR0_MATRIX_C21_C22_B; - uint32_t CUR0_MATRIX_C23_C24_B; - uint32_t CUR0_MATRIX_C31_C32_B; - uint32_t CUR0_MATRIX_C33_C34_B; - uint32_t DSCL_SC_MODE; - uint32_t DSCL_EASF_H_MODE; - uint32_t DSCL_EASF_H_BF_CNTL; - uint32_t DSCL_EASF_H_RINGEST_EVENTAP_REDUCE; - uint32_t DSCL_EASF_H_RINGEST_EVENTAP_GAIN; - uint32_t DSCL_EASF_H_BF_FINAL_MAX_MIN; - uint32_t DSCL_EASF_H_BF1_PWL_SEG0; - uint32_t DSCL_EASF_H_BF1_PWL_SEG1; - uint32_t DSCL_EASF_H_BF1_PWL_SEG2; - uint32_t DSCL_EASF_H_BF1_PWL_SEG3; - uint32_t DSCL_EASF_H_BF1_PWL_SEG4; - uint32_t DSCL_EASF_H_BF1_PWL_SEG5; - uint32_t DSCL_EASF_H_BF1_PWL_SEG6; - uint32_t DSCL_EASF_H_BF1_PWL_SEG7; - uint32_t DSCL_EASF_H_BF3_PWL_SEG0; - uint32_t DSCL_EASF_H_BF3_PWL_SEG1; - uint32_t DSCL_EASF_H_BF3_PWL_SEG2; - uint32_t DSCL_EASF_H_BF3_PWL_SEG3; - uint32_t DSCL_EASF_H_BF3_PWL_SEG4; - uint32_t DSCL_EASF_H_BF3_PWL_SEG5; - uint32_t DSCL_EASF_V_MODE; - uint32_t DSCL_EASF_V_BF_CNTL; - uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL1; - uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL2; - uint32_t DSCL_EASF_V_RINGEST_3TAP_CNTL3; - uint32_t DSCL_EASF_V_RINGEST_EVENTAP_REDUCE; - uint32_t DSCL_EASF_V_RINGEST_EVENTAP_GAIN; - uint32_t DSCL_EASF_V_BF_FINAL_MAX_MIN; - uint32_t DSCL_EASF_V_BF1_PWL_SEG0; - uint32_t DSCL_EASF_V_BF1_PWL_SEG1; - uint32_t DSCL_EASF_V_BF1_PWL_SEG2; - uint32_t DSCL_EASF_V_BF1_PWL_SEG3; - uint32_t DSCL_EASF_V_BF1_PWL_SEG4; - uint32_t DSCL_EASF_V_BF1_PWL_SEG5; - uint32_t DSCL_EASF_V_BF1_PWL_SEG6; - uint32_t DSCL_EASF_V_BF1_PWL_SEG7; - uint32_t DSCL_EASF_V_BF3_PWL_SEG0; - uint32_t DSCL_EASF_V_BF3_PWL_SEG1; - uint32_t DSCL_EASF_V_BF3_PWL_SEG2; - uint32_t DSCL_EASF_V_BF3_PWL_SEG3; - uint32_t DSCL_EASF_V_BF3_PWL_SEG4; - uint32_t DSCL_EASF_V_BF3_PWL_SEG5; - uint32_t DSCL_SC_MATRIX_C0C1; - uint32_t DSCL_SC_MATRIX_C2C3; - uint32_t ISHARP_MODE; - uint32_t ISHARP_NOISEDET_THRESHOLD; - uint32_t ISHARP_NOISE_GAIN_PWL; - uint32_t ISHARP_LBA_PWL_SEG0; - uint32_t ISHARP_LBA_PWL_SEG1; - uint32_t ISHARP_LBA_PWL_SEG2; - uint32_t ISHARP_LBA_PWL_SEG3; - uint32_t ISHARP_LBA_PWL_SEG4; - uint32_t ISHARP_LBA_PWL_SEG5; - uint32_t ISHARP_DELTA_CTRL; - uint32_t ISHARP_DELTA_DATA; - uint32_t ISHARP_DELTA_INDEX; - uint32_t ISHARP_NLDELTA_SOFT_CLIP; + DPP_REG_VARIABLE_LIST_DCN401; }; struct dcn401_dpp_shift { |