diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 242 |
1 files changed, 131 insertions, 111 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 2df2444ee892..1aae49f4df49 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -41,6 +41,7 @@ #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 #define AMDGPU_MES_MSCRATCH_SIZE 0x40000 +#define AMDGPU_MES_INVALID_DB_OFFSET 0xffffffff enum amdgpu_mes_priority_level { AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, @@ -56,20 +57,26 @@ enum amdgpu_mes_priority_level { struct amdgpu_mes_funcs; -enum admgpu_mes_pipe { - AMDGPU_MES_SCHED_PIPE = 0, - AMDGPU_MES_KIQ_PIPE, +enum amdgpu_mes_pipe { + AMDGPU_MES_PIPE_0 = 0, + AMDGPU_MES_PIPE_1, AMDGPU_MAX_MES_PIPES = 2, }; +#define AMDGPU_MES_SCHED_PIPE AMDGPU_MES_PIPE_0 +#define AMDGPU_MES_KIQ_PIPE AMDGPU_MES_PIPE_1 + +#define AMDGPU_MAX_MES_INST_PIPES \ + (AMDGPU_MAX_MES_PIPES * AMDGPU_MAX_GC_INSTANCES) + +#define MES_PIPE_INST(xcc_id, pipe_id) \ + (xcc_id * AMDGPU_MAX_MES_PIPES + pipe_id) + struct amdgpu_mes { struct amdgpu_device *adev; struct mutex mutex_hidden; - struct idr pasid_idr; - struct idr gang_id_idr; - struct idr queue_id_idr; struct ida doorbell_ida; spinlock_t queue_id_lock; @@ -85,48 +92,51 @@ struct amdgpu_mes { uint64_t default_process_quantum; uint64_t default_gang_quantum; - struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES]; - spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES]; + struct amdgpu_ring ring[AMDGPU_MAX_MES_INST_PIPES]; + spinlock_t ring_lock[AMDGPU_MAX_MES_INST_PIPES]; const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; /* mes ucode */ - struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; - uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; - uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; + struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; + uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; /* mes ucode data */ - struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; - uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; - uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; + struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; + uint32_t *data_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; /* eop gpu obj */ - struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; - uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; + struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t eop_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; - void *mqd_backup[AMDGPU_MAX_MES_PIPES]; - struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; + void *mqd_backup[AMDGPU_MAX_MES_INST_PIPES]; + struct amdgpu_irq_src irq[AMDGPU_MAX_MES_INST_PIPES]; uint32_t vmid_mask_gfxhub; uint32_t vmid_mask_mmhub; - uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; + uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; - uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES]; - uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES]; - uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES]; - uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES]; - uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES]; - uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES]; + + uint32_t sch_ctx_offs[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_INST_PIPES]; + uint32_t query_status_fence_offs[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_INST_PIPES]; uint32_t saved_flags; /* initialize kiq pipe */ - int (*kiq_hw_init)(struct amdgpu_device *adev); - int (*kiq_hw_fini)(struct amdgpu_device *adev); + int (*kiq_hw_init)(struct amdgpu_device *adev, + uint32_t xcc_id); + int (*kiq_hw_fini)(struct amdgpu_device *adev, + uint32_t xcc_id); /* MES doorbells */ uint32_t db_start_dw_offset; @@ -143,23 +153,34 @@ struct amdgpu_mes { const struct amdgpu_mes_funcs *funcs; /* mes resource_1 bo*/ - struct amdgpu_bo *resource_1; - uint64_t resource_1_gpu_addr; - void *resource_1_addr; - + struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES]; + uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES]; + void *resource_1_addr[AMDGPU_MAX_MES_PIPES]; + + int hung_queue_db_array_size; + int hung_queue_hqd_info_offset; + struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; + void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_INST_PIPES]; + + /* cooperative dispatch */ + bool enable_coop_mode; + int master_xcc_ids[AMDGPU_MAX_MES_INST_PIPES]; + struct amdgpu_bo *shared_cmd_buf_obj[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; }; -struct amdgpu_mes_process { - int pasid; - struct amdgpu_vm *vm; - uint64_t pd_gpu_addr; - struct amdgpu_bo *proc_ctx_bo; - uint64_t proc_ctx_gpu_addr; - void *proc_ctx_cpu_ptr; - uint64_t process_quantum; - struct list_head gang_list; - uint32_t doorbell_index; - struct mutex doorbell_lock; +struct amdgpu_mes_hung_queue_hqd_info { + union { + struct { + u32 queue_type: 3; // queue type + u32 pipe_index: 4; // pipe index + u32 queue_index: 8; // queue index + u32 reserved: 17; + }; + + u32 bit0_31; + }; }; struct amdgpu_mes_gang { @@ -215,6 +236,7 @@ struct amdgpu_mes_gang_properties { }; struct mes_add_queue_input { + uint32_t xcc_id; uint32_t process_id; uint64_t page_table_base_addr; uint64_t process_va_start; @@ -241,26 +263,19 @@ struct mes_add_queue_input { uint32_t is_aql_queue; uint32_t queue_size; uint32_t exclusively_scheduled; + uint32_t sh_mem_config_data; + uint32_t vm_cntx_cntl; }; struct mes_remove_queue_input { + uint32_t xcc_id; uint32_t doorbell_offset; uint64_t gang_context_addr; -}; - -struct mes_reset_queue_input { - uint32_t doorbell_offset; - uint64_t gang_context_addr; - bool use_mmio; - uint32_t queue_type; - uint32_t me_id; - uint32_t pipe_id; - uint32_t queue_id; - uint32_t xcc_id; - uint32_t vmid; + bool remove_queue_after_reset; }; struct mes_map_legacy_queue_input { + uint32_t xcc_id; uint32_t queue_type; uint32_t doorbell_offset; uint32_t pipe_id; @@ -270,6 +285,7 @@ struct mes_map_legacy_queue_input { }; struct mes_unmap_legacy_queue_input { + uint32_t xcc_id; enum amdgpu_unmap_queues_action action; uint32_t queue_type; uint32_t doorbell_offset; @@ -280,18 +296,24 @@ struct mes_unmap_legacy_queue_input { }; struct mes_suspend_gang_input { + uint32_t xcc_id; bool suspend_all_gangs; + bool suspend_all_sdma_gangs; uint64_t gang_context_addr; uint64_t suspend_fence_addr; uint32_t suspend_fence_value; + uint32_t doorbell_offset; }; struct mes_resume_gang_input { + uint32_t xcc_id; bool resume_all_gangs; uint64_t gang_context_addr; + uint32_t doorbell_offset; }; -struct mes_reset_legacy_queue_input { +struct mes_reset_queue_input { + uint32_t xcc_id; uint32_t queue_type; uint32_t doorbell_offset; bool use_mmio; @@ -301,6 +323,21 @@ struct mes_reset_legacy_queue_input { uint64_t mqd_addr; uint64_t wptr_addr; uint32_t vmid; + bool legacy_gfx; + bool is_kq; +}; + +struct mes_detect_and_reset_queue_input { + u32 queue_type; + bool detect_only; + u32 xcc_id; +}; + +struct mes_inv_tlbs_pasid_input { + uint32_t xcc_id; + uint16_t pasid; + uint8_t hub_id; + uint8_t flush_type; }; enum mes_misc_opcode { @@ -313,7 +350,8 @@ enum mes_misc_opcode { }; struct mes_misc_op_input { - enum mes_misc_opcode op; + uint32_t xcc_id; + enum mes_misc_opcode op; union { struct { @@ -388,90 +426,71 @@ struct amdgpu_mes_funcs { int (*misc_op)(struct amdgpu_mes *mes, struct mes_misc_op_input *input); - int (*reset_legacy_queue)(struct amdgpu_mes *mes, - struct mes_reset_legacy_queue_input *input); - int (*reset_hw_queue)(struct amdgpu_mes *mes, struct mes_reset_queue_input *input); -}; -#define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) -#define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) + int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes, + struct mes_detect_and_reset_queue_input *input); -int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs); + + int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes, + struct mes_inv_tlbs_pasid_input *input); +}; + +#define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ + (adev)->mes.kiq_hw_init((adev), (xcc_id)) +#define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ + (adev)->mes.kiq_hw_fini((adev), (xcc_id)) int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); +void amdgpu_mes_validate_fw_version(struct amdgpu_device *adev); int amdgpu_mes_init(struct amdgpu_device *adev); void amdgpu_mes_fini(struct amdgpu_device *adev); -int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid, - struct amdgpu_vm *vm); -void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid); - -int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid, - struct amdgpu_mes_gang_properties *gprops, - int *gang_id); -int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id); - -int amdgpu_mes_suspend(struct amdgpu_device *adev); -int amdgpu_mes_resume(struct amdgpu_device *adev); - -int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, - struct amdgpu_mes_queue_properties *qprops, - int *queue_id); -int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id); -int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id); -int amdgpu_mes_reset_hw_queue_mmio(struct amdgpu_device *adev, int queue_type, - int me_id, int pipe_id, int queue_id, int vmid); +int amdgpu_mes_suspend(struct amdgpu_device *adev, u32 xcc_id); +int amdgpu_mes_resume(struct amdgpu_device *adev, u32 xcc_id); int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, - struct amdgpu_ring *ring); + struct amdgpu_ring *ring, uint32_t xcc_id); int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring, enum amdgpu_unmap_queues_action action, - u64 gpu_addr, u64 seq); + u64 gpu_addr, u64 seq, uint32_t xcc_id); int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid, - bool use_mmio); - -uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); + bool use_mmio, + uint32_t xcc_id); + +int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev); +int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, + int queue_type, + bool detect_only, + unsigned int *hung_db_num, + u32 *hung_db_array, + uint32_t xcc_id); + +uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t xcc_id); int amdgpu_mes_wreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t val); -int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, - uint32_t val, uint32_t mask); + uint32_t reg, uint32_t val, uint32_t xcc_id); int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, uint32_t reg0, uint32_t reg1, - uint32_t ref, uint32_t mask); + uint32_t ref, uint32_t mask, uint32_t xcc_id); +int amdgpu_mes_hdp_flush(struct amdgpu_device *adev); int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, uint64_t process_context_addr, uint32_t spi_gdbg_per_vmid_cntl, const uint32_t *tcp_watch_cntl, uint32_t flags, - bool trap_en); + bool trap_en, + uint32_t xcc_id); int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, - uint64_t process_context_addr); -int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id, - int queue_type, int idx, - struct amdgpu_mes_ctx_data *ctx_data, - struct amdgpu_ring **out); -void amdgpu_mes_remove_ring(struct amdgpu_device *adev, - struct amdgpu_ring *ring); + uint64_t process_context_addr, uint32_t xcc_id); uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, enum amdgpu_mes_priority_level prio); -int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, - struct amdgpu_mes_ctx_data *ctx_data); -void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data); -int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev, - struct amdgpu_vm *vm, - struct amdgpu_mes_ctx_data *ctx_data); -int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev, - struct amdgpu_mes_ctx_data *ctx_data); - -int amdgpu_mes_self_test(struct amdgpu_device *adev); - int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); /* @@ -533,7 +552,8 @@ static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) } bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); +bool amdgpu_mes_queue_reset_by_mes_supported(struct amdgpu_device *adev); -int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev, uint32_t node_id, bool enable); +int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev); #endif /* __AMDGPU_MES_H__ */ |