1 files changed, 362 insertions, 242 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index f873dd3cae16..6860a3a4d466 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -120,9 +120,9 @@ static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev,
 		(u32)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
 		ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
 		/* Firmware request VRAM reservation for SR-IOV */
-		adev->mman.fw_vram_usage_start_offset = (start_addr &
-			(~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
-		adev->mman.fw_vram_usage_size = fw_size << 10;
+		amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_VRAM_USAGE,
+				  (start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10,
+				  fw_size << 10, true);
 		/* Use the default scratch size */
 		*usage_bytes = 0;
 	} else {
@@ -152,18 +152,18 @@ static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev,
 	    ((fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
 		ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
 		/* Firmware request VRAM reservation for SR-IOV */
-		adev->mman.fw_vram_usage_start_offset = (fw_start_addr &
-			(~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
-		adev->mman.fw_vram_usage_size = fw_size << 10;
+		amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_FW_VRAM_USAGE,
+				  (fw_start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10,
+				  fw_size << 10, true);
 	}
 
 	if (amdgpu_sriov_vf(adev) &&
 	    ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
 		ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
 		/* driver request VRAM reservation for SR-IOV */
-		adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
-			(~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
-		adev->mman.drv_vram_usage_size = drv_size << 10;
+		amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_DRV_VRAM_USAGE,
+				  (drv_start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10,
+				  drv_size << 10, true);
 	}
 
 	*usage_bytes = 0;
@@ -181,19 +181,22 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
 	u8 frev, crev;
 	int usage_bytes = 0;
 
-	if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) {
-		if (frev == 2 && crev == 1) {
-			fw_usage_v2_1 =
-				(struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
-			amdgpu_atomfirmware_allocate_fb_v2_1(adev,
-					fw_usage_v2_1,
-					&usage_bytes);
-		} else if (frev >= 2 && crev >= 2) {
-			fw_usage_v2_2 =
-				(struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset);
-			amdgpu_atomfirmware_allocate_fb_v2_2(adev,
-					fw_usage_v2_2,
-					&usage_bytes);
+	/* Skip atomfirmware allocation for SRIOV VFs when dynamic crit regn is enabled */
+	if (!(amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled)) {
+		if (amdgpu_atom_parse_data_header(ctx, index, NULL, &frev, &crev, &data_offset)) {
+			if (frev == 2 && crev == 1) {
+				fw_usage_v2_1 =
+					(struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
+				amdgpu_atomfirmware_allocate_fb_v2_1(adev,
+						fw_usage_v2_1,
+						&usage_bytes);
+			} else if (frev >= 2 && crev >= 2) {
+				fw_usage_v2_2 =
+					(struct vram_usagebyfirmware_v2_2 *)(ctx->bios + data_offset);
+				amdgpu_atomfirmware_allocate_fb_v2_2(adev,
+						fw_usage_v2_2,
+						&usage_bytes);
+			}
 		}
 	}
 
@@ -281,6 +284,9 @@ static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
 		case ATOM_DGPU_VRAM_TYPE_GDDR6:
 			vram_type = AMDGPU_VRAM_TYPE_GDDR6;
 			break;
+		case ATOM_DGPU_VRAM_TYPE_HBM3E:
+			vram_type = AMDGPU_VRAM_TYPE_HBM3E;
+			break;
 		default:
 			vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 			break;
@@ -290,249 +296,357 @@ static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev,
 	return vram_type;
 }
 
-int
-amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+static int amdgpu_atomfirmware_get_uma_carveout_info_v2_3(struct amdgpu_device *adev,
+							  union igp_info *igp_info,
+							  struct amdgpu_uma_carveout_info *uma_info)
+{
+	struct uma_carveout_option *opts;
+	uint8_t nr_uma_options;
+	int i;
+
+	nr_uma_options = igp_info->v23.UMACarveoutIndexMax;
+
+	if (!nr_uma_options)
+		return -ENODEV;
+
+	if (nr_uma_options > MAX_UMA_OPTION_ENTRIES) {
+		drm_dbg(adev_to_drm(adev),
+			"Number of UMA options exceeds max table size. Options will not be parsed");
+		return -EINVAL;
+	}
+
+	uma_info->num_entries = nr_uma_options;
+	uma_info->uma_option_index = igp_info->v23.UMACarveoutIndex;
+
+	opts = igp_info->v23.UMASizeControlOption;
+
+	for (i = 0; i < nr_uma_options; i++) {
+		if (!opts[i].memoryCarvedGb)
+			uma_info->entries[i].memory_carved_mb = 512;
+		else
+			uma_info->entries[i].memory_carved_mb = (uint32_t)opts[i].memoryCarvedGb << 10;
+
+		uma_info->entries[i].flags = opts[i].uma_carveout_option_flags.all8;
+		strscpy(uma_info->entries[i].name, opts[i].optionName, MAX_UMA_OPTION_NAME);
+	}
+
+	return 0;
+}
+
+int amdgpu_atomfirmware_get_uma_carveout_info(struct amdgpu_device *adev,
+					      struct amdgpu_uma_carveout_info *uma_info)
+{
+	struct amdgpu_mode_info *mode_info = &adev->mode_info;
+	union igp_info *igp_info;
+	u16 data_offset, size;
+	u8 frev, crev;
+	int index;
+
+	if (!(adev->flags & AMD_IS_APU))
+		return -ENODEV;
+
+	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+					    integratedsysteminfo);
+
+	if (!amdgpu_atom_parse_data_header(mode_info->atom_context,
+					  index, &size,
+					  &frev, &crev, &data_offset)) {
+		return -EINVAL;
+	}
+
+	igp_info = (union igp_info *)
+			(mode_info->atom_context->bios + data_offset);
+
+	switch (frev) {
+	case 2:
+		switch (crev) {
+		case 3:
+			return amdgpu_atomfirmware_get_uma_carveout_info_v2_3(adev, igp_info, uma_info);
+		break;
+		default:
+			break;
+		}
+		break;
+	default:
+		break;
+	}
+	return -ENODEV;
+}
+
+int amdgpu_atomfirmware_get_integrated_system_info(struct amdgpu_device *adev,
 				  int *vram_width, int *vram_type,
 				  int *vram_vendor)
 {
 	struct amdgpu_mode_info *mode_info = &adev->mode_info;
-	int index, i = 0;
+	int index;
 	u16 data_offset, size;
 	union igp_info *igp_info;
-	union vram_info *vram_info;
-	union umc_info *umc_info;
-	union vram_module *vram_module;
 	u8 frev, crev;
 	u8 mem_type;
-	u8 mem_vendor;
 	u32 mem_channel_number;
 	u32 mem_channel_width;
-	u32 module_id;
 
-	if (adev->flags & AMD_IS_APU)
-		index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 						    integratedsysteminfo);
-	else {
-		switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
-		case IP_VERSION(12, 0, 0):
-		case IP_VERSION(12, 0, 1):
-			index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info);
+	if (amdgpu_atom_parse_data_header(mode_info->atom_context,
+					  index, &size,
+					  &frev, &crev, &data_offset)) {
+		igp_info = (union igp_info *)
+			(mode_info->atom_context->bios + data_offset);
+		switch (frev) {
+		case 1:
+			switch (crev) {
+			case 11:
+			case 12:
+				mem_channel_number = igp_info->v11.umachannelnumber;
+				if (!mem_channel_number)
+					mem_channel_number = 1;
+				mem_type = igp_info->v11.memorytype;
+				if (mem_type == LpDdr5MemType)
+					mem_channel_width = 32;
+				else
+					mem_channel_width = 64;
+				if (vram_width)
+					*vram_width = mem_channel_number * mem_channel_width;
+				if (vram_type)
+					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+				break;
+			default:
+				return -EINVAL;
+			}
+			break;
+		case 2:
+			switch (crev) {
+			case 1:
+			case 2:
+				mem_channel_number = igp_info->v21.umachannelnumber;
+				if (!mem_channel_number)
+					mem_channel_number = 1;
+				mem_type = igp_info->v21.memorytype;
+				if (mem_type == LpDdr5MemType)
+					mem_channel_width = 32;
+				else
+					mem_channel_width = 64;
+				if (vram_width)
+					*vram_width = mem_channel_number * mem_channel_width;
+				if (vram_type)
+					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+				break;
+			case 3:
+				mem_channel_number = igp_info->v23.umachannelnumber;
+				if (!mem_channel_number)
+					mem_channel_number = 1;
+				mem_type = igp_info->v23.memorytype;
+				if (mem_type == LpDdr5MemType)
+					mem_channel_width = 32;
+				else
+					mem_channel_width = 64;
+				if (vram_width)
+					*vram_width = mem_channel_number * mem_channel_width;
+				if (vram_type)
+					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+				break;
+			default:
+				return -EINVAL;
+			}
 			break;
 		default:
-			index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_info);
+			return -EINVAL;
 		}
+	} else {
+		return -EINVAL;
 	}
+	return 0;
+}
+
+int amdgpu_atomfirmware_get_umc_info(struct amdgpu_device *adev,
+				  int *vram_width, int *vram_type,
+				  int *vram_vendor)
+{
+	struct amdgpu_mode_info *mode_info = &adev->mode_info;
+	int index;
+	u16 data_offset, size;
+	union umc_info *umc_info;
+	u8 frev, crev;
+	u8 mem_type;
+	u8 mem_vendor;
+	u32 mem_channel_number;
+	u32 mem_channel_width;
+
+	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info);
+
 	if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 					  index, &size,
 					  &frev, &crev, &data_offset)) {
-		if (adev->flags & AMD_IS_APU) {
-			igp_info = (union igp_info *)
-				(mode_info->atom_context->bios + data_offset);
-			switch (frev) {
-			case 1:
-				switch (crev) {
-				case 11:
-				case 12:
-					mem_channel_number = igp_info->v11.umachannelnumber;
-					if (!mem_channel_number)
-						mem_channel_number = 1;
-					mem_type = igp_info->v11.memorytype;
-					if (mem_type == LpDdr5MemType)
-						mem_channel_width = 32;
-					else
-						mem_channel_width = 64;
-					if (vram_width)
-						*vram_width = mem_channel_number * mem_channel_width;
-					if (vram_type)
-						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
-					break;
-				default:
-					return -EINVAL;
-				}
-				break;
-			case 2:
-				switch (crev) {
-				case 1:
-				case 2:
-					mem_channel_number = igp_info->v21.umachannelnumber;
-					if (!mem_channel_number)
-						mem_channel_number = 1;
-					mem_type = igp_info->v21.memorytype;
-					if (mem_type == LpDdr5MemType)
-						mem_channel_width = 32;
-					else
-						mem_channel_width = 64;
-					if (vram_width)
-						*vram_width = mem_channel_number * mem_channel_width;
-					if (vram_type)
-						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
-					break;
-				case 3:
-					mem_channel_number = igp_info->v23.umachannelnumber;
-					if (!mem_channel_number)
-						mem_channel_number = 1;
-					mem_type = igp_info->v23.memorytype;
-					if (mem_type == LpDdr5MemType)
-						mem_channel_width = 32;
-					else
-						mem_channel_width = 64;
-					if (vram_width)
-						*vram_width = mem_channel_number * mem_channel_width;
-					if (vram_type)
-						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
-					break;
-				default:
-					return -EINVAL;
-				}
+		umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);
+
+		if (frev == 4) {
+			switch (crev) {
+			case 0:
+				mem_channel_number = le32_to_cpu(umc_info->v40.channel_num);
+				mem_type = le32_to_cpu(umc_info->v40.vram_type);
+				mem_channel_width = le32_to_cpu(umc_info->v40.channel_width);
+				mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF;
+				if (vram_vendor)
+					*vram_vendor = mem_vendor;
+				if (vram_type)
+					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+				if (vram_width)
+					*vram_width = mem_channel_number * (1 << mem_channel_width);
 				break;
 			default:
 				return -EINVAL;
 			}
 		} else {
-			switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
-			case IP_VERSION(12, 0, 0):
-			case IP_VERSION(12, 0, 1):
-				umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);
-
-				if (frev == 4) {
-					switch (crev) {
-					case 0:
-						mem_channel_number = le32_to_cpu(umc_info->v40.channel_num);
-						mem_type = le32_to_cpu(umc_info->v40.vram_type);
-						mem_channel_width = le32_to_cpu(umc_info->v40.channel_width);
-						mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF;
-						if (vram_vendor)
-							*vram_vendor = mem_vendor;
-						if (vram_type)
-							*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
-						if (vram_width)
-							*vram_width = mem_channel_number * (1 << mem_channel_width);
-						break;
-					default:
-						return -EINVAL;
-					}
-				} else
-					return -EINVAL;
+			return -EINVAL;
+		}
+	} else {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
+				  int *vram_width, int *vram_type,
+				  int *vram_vendor)
+{
+	struct amdgpu_mode_info *mode_info = &adev->mode_info;
+	int index, i = 0;
+	u16 data_offset, size;
+	union vram_info *vram_info;
+	union vram_module *vram_module;
+	u8 frev, crev;
+	u8 mem_type;
+	u8 mem_vendor;
+	u32 mem_channel_number;
+	u32 mem_channel_width;
+	u32 module_id;
+
+	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_info);
+
+	if (amdgpu_atom_parse_data_header(mode_info->atom_context,
+					  index, &size,
+					  &frev, &crev, &data_offset)) {
+		vram_info = (union vram_info *)
+			(mode_info->atom_context->bios + data_offset);
+
+		module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
+		if (frev == 3) {
+			switch (crev) {
+			/* v30 */
+			case 0:
+				vram_module = (union vram_module *)vram_info->v30.vram_module;
+				mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF;
+				if (vram_vendor)
+					*vram_vendor = mem_vendor;
+				mem_type = vram_info->v30.memory_type;
+				if (vram_type)
+					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+				mem_channel_number = vram_info->v30.channel_num;
+				mem_channel_width = vram_info->v30.channel_width;
+				if (vram_width)
+					*vram_width = mem_channel_number * 16;
 				break;
 			default:
-				vram_info = (union vram_info *)
-					(mode_info->atom_context->bios + data_offset);
-
-				module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16;
-				if (frev == 3) {
-					switch (crev) {
-					/* v30 */
-					case 0:
-						vram_module = (union vram_module *)vram_info->v30.vram_module;
-						mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF;
-						if (vram_vendor)
-							*vram_vendor = mem_vendor;
-						mem_type = vram_info->v30.memory_type;
-						if (vram_type)
-							*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
-						mem_channel_number = vram_info->v30.channel_num;
-						mem_channel_width = vram_info->v30.channel_width;
-						if (vram_width)
-							*vram_width = mem_channel_number * 16;
-						break;
-					default:
-						return -EINVAL;
-					}
-				} else if (frev == 2) {
-					switch (crev) {
-					/* v23 */
-					case 3:
-						if (module_id > vram_info->v23.vram_module_num)
-							module_id = 0;
-						vram_module = (union vram_module *)vram_info->v23.vram_module;
-						while (i < module_id) {
-							vram_module = (union vram_module *)
-								((u8 *)vram_module + vram_module->v9.vram_module_size);
-							i++;
-						}
-						mem_type = vram_module->v9.memory_type;
-						if (vram_type)
-							*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
-						mem_channel_number = vram_module->v9.channel_num;
-						mem_channel_width = vram_module->v9.channel_width;
-						if (vram_width)
-							*vram_width = mem_channel_number * (1 << mem_channel_width);
-						mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
-						if (vram_vendor)
-							*vram_vendor = mem_vendor;
-						break;
-					/* v24 */
-					case 4:
-						if (module_id > vram_info->v24.vram_module_num)
-							module_id = 0;
-						vram_module = (union vram_module *)vram_info->v24.vram_module;
-						while (i < module_id) {
-							vram_module = (union vram_module *)
-								((u8 *)vram_module + vram_module->v10.vram_module_size);
-							i++;
-						}
-						mem_type = vram_module->v10.memory_type;
-						if (vram_type)
-							*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
-						mem_channel_number = vram_module->v10.channel_num;
-						mem_channel_width = vram_module->v10.channel_width;
-						if (vram_width)
-							*vram_width = mem_channel_number * (1 << mem_channel_width);
-						mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
-						if (vram_vendor)
-							*vram_vendor = mem_vendor;
-						break;
-					/* v25 */
-					case 5:
-						if (module_id > vram_info->v25.vram_module_num)
-							module_id = 0;
-						vram_module = (union vram_module *)vram_info->v25.vram_module;
-						while (i < module_id) {
-							vram_module = (union vram_module *)
-								((u8 *)vram_module + vram_module->v11.vram_module_size);
-							i++;
-						}
-						mem_type = vram_module->v11.memory_type;
-						if (vram_type)
-							*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
-						mem_channel_number = vram_module->v11.channel_num;
-						mem_channel_width = vram_module->v11.channel_width;
-						if (vram_width)
-							*vram_width = mem_channel_number * (1 << mem_channel_width);
-						mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
-						if (vram_vendor)
-							*vram_vendor = mem_vendor;
-						break;
-					/* v26 */
-					case 6:
-						if (module_id > vram_info->v26.vram_module_num)
-							module_id = 0;
-						vram_module = (union vram_module *)vram_info->v26.vram_module;
-						while (i < module_id) {
-							vram_module = (union vram_module *)
-								((u8 *)vram_module + vram_module->v9.vram_module_size);
-							i++;
-						}
-						mem_type = vram_module->v9.memory_type;
-						if (vram_type)
-							*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
-						mem_channel_number = vram_module->v9.channel_num;
-						mem_channel_width = vram_module->v9.channel_width;
-						if (vram_width)
-							*vram_width = mem_channel_number * (1 << mem_channel_width);
-						mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
-						if (vram_vendor)
-							*vram_vendor = mem_vendor;
-						break;
-					default:
-						return -EINVAL;
-					}
-				} else {
-					/* invalid frev */
-					return -EINVAL;
+				return -EINVAL;
+			}
+		} else if (frev == 2) {
+			switch (crev) {
+			/* v23 */
+			case 3:
+				if (module_id > vram_info->v23.vram_module_num)
+					module_id = 0;
+				vram_module = (union vram_module *)vram_info->v23.vram_module;
+				while (i < module_id) {
+					vram_module = (union vram_module *)
+						((u8 *)vram_module + vram_module->v9.vram_module_size);
+					i++;
+				}
+				mem_type = vram_module->v9.memory_type;
+				if (vram_type)
+					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+				mem_channel_number = vram_module->v9.channel_num;
+				mem_channel_width = vram_module->v9.channel_width;
+				if (vram_width)
+					*vram_width = mem_channel_number * (1 << mem_channel_width);
+				mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
+				if (vram_vendor)
+					*vram_vendor = mem_vendor;
+				break;
+			/* v24 */
+			case 4:
+				if (module_id > vram_info->v24.vram_module_num)
+					module_id = 0;
+				vram_module = (union vram_module *)vram_info->v24.vram_module;
+				while (i < module_id) {
+					vram_module = (union vram_module *)
+						((u8 *)vram_module + vram_module->v10.vram_module_size);
+					i++;
 				}
+				mem_type = vram_module->v10.memory_type;
+				if (vram_type)
+					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+				mem_channel_number = vram_module->v10.channel_num;
+				mem_channel_width = vram_module->v10.channel_width;
+				if (vram_width)
+					*vram_width = mem_channel_number * (1 << mem_channel_width);
+				mem_vendor = (vram_module->v10.vender_rev_id) & 0xF;
+				if (vram_vendor)
+					*vram_vendor = mem_vendor;
+				break;
+			/* v25 */
+			case 5:
+				if (module_id > vram_info->v25.vram_module_num)
+					module_id = 0;
+				vram_module = (union vram_module *)vram_info->v25.vram_module;
+				while (i < module_id) {
+					vram_module = (union vram_module *)
+						((u8 *)vram_module + vram_module->v11.vram_module_size);
+					i++;
+				}
+				mem_type = vram_module->v11.memory_type;
+				if (vram_type)
+					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+				mem_channel_number = vram_module->v11.channel_num;
+				mem_channel_width = vram_module->v11.channel_width;
+				if (vram_width)
+					*vram_width = mem_channel_number * (1 << mem_channel_width);
+				mem_vendor = (vram_module->v11.vender_rev_id) & 0xF;
+				if (vram_vendor)
+					*vram_vendor = mem_vendor;
+				break;
+			/* v26 */
+			case 6:
+				if (module_id > vram_info->v26.vram_module_num)
+					module_id = 0;
+				vram_module = (union vram_module *)vram_info->v26.vram_module;
+				while (i < module_id) {
+					vram_module = (union vram_module *)
+						((u8 *)vram_module + vram_module->v9.vram_module_size);
+					i++;
+				}
+				mem_type = vram_module->v9.memory_type;
+				if (vram_type)
+					*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
+				mem_channel_number = vram_module->v9.channel_num;
+				mem_channel_width = vram_module->v9.channel_width;
+				if (vram_width)
+					*vram_width = mem_channel_number * (1 << mem_channel_width);
+				mem_vendor = (vram_module->v9.vender_rev_id) & 0xF;
+				if (vram_vendor)
+					*vram_vendor = mem_vendor;
+				break;
+			default:
+				return -EINVAL;
 			}
+		} else {
+			/* invalid frev */
+			return -EINVAL;
 		}
+
+	} else {
+		return -EINVAL;
 	}
 
 	return 0;
@@ -549,9 +663,10 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 	u16 data_offset, size;
 	union umc_info *umc_info;
 	u8 frev, crev;
-	bool ecc_default_enabled = false;
+	bool mem_ecc_enabled = false;
 	u8 umc_config;
 	u32 umc_config1;
+	adev->ras_default_ecc_enabled = false;
 
 	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 			umc_info);
@@ -563,20 +678,22 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 			switch (crev) {
 			case 1:
 				umc_config = le32_to_cpu(umc_info->v31.umc_config);
-				ecc_default_enabled =
+				mem_ecc_enabled =
 					(umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 				break;
 			case 2:
 				umc_config = le32_to_cpu(umc_info->v32.umc_config);
-				ecc_default_enabled =
+				mem_ecc_enabled =
 					(umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 				break;
 			case 3:
 				umc_config = le32_to_cpu(umc_info->v33.umc_config);
 				umc_config1 = le32_to_cpu(umc_info->v33.umc_config1);
-				ecc_default_enabled =
+				mem_ecc_enabled =
 					((umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ||
 					 (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE)) ? true : false;
+				adev->ras_default_ecc_enabled =
+					(umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 				break;
 			default:
 				/* unsupported crev */
@@ -585,9 +702,12 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 		} else if (frev == 4) {
 			switch (crev) {
 			case 0:
+				umc_config = le32_to_cpu(umc_info->v40.umc_config);
 				umc_config1 = le32_to_cpu(umc_info->v40.umc_config1);
-				ecc_default_enabled =
+				mem_ecc_enabled =
 					(umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;
+				adev->ras_default_ecc_enabled =
+					(umc_config & UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 				break;
 			default:
 				/* unsupported crev */
@@ -599,7 +719,7 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 		}
 	}
 
-	return ecc_default_enabled;
+	return mem_ecc_enabled;
 }
 
 /*