diff options
Diffstat (limited to 'drivers/accel/ivpu')
21 files changed, 567 insertions, 877 deletions
diff --git a/drivers/accel/ivpu/ivpu_drv.c b/drivers/accel/ivpu/ivpu_drv.c index 8c1c87e69f91..247ed6b2ff62 100644 --- a/drivers/accel/ivpu/ivpu_drv.c +++ b/drivers/accel/ivpu/ivpu_drv.c @@ -67,6 +67,48 @@ bool ivpu_force_snoop; module_param_named(force_snoop, ivpu_force_snoop, bool, 0444); MODULE_PARM_DESC(force_snoop, "Force snooping for NPU host memory access"); +static struct pci_device_id ivpu_pci_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_MTL) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_ARL) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_LNL) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PTL) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_WCL) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_NVL) }, + {} +}; +MODULE_DEVICE_TABLE(pci, ivpu_pci_ids); + +static int ivpu_ip_gen_init(struct ivpu_device *vdev) +{ + vdev->platform = IVPU_PLATFORM_INVALID; + + switch (ivpu_device_id(vdev)) { + case PCI_DEVICE_ID_MTL: + case PCI_DEVICE_ID_ARL: + vdev->hw_ip_gen = IVPU_HW_IP_37XX; + vdev->btrs_gen = IVPU_HW_BTRS_MTL; + break; + case PCI_DEVICE_ID_LNL: + vdev->hw_ip_gen = IVPU_HW_IP_40XX; + vdev->btrs_gen = IVPU_HW_BTRS_LNL; + break; + case PCI_DEVICE_ID_PTL: + case PCI_DEVICE_ID_WCL: + vdev->hw_ip_gen = IVPU_HW_IP_50XX; + vdev->btrs_gen = IVPU_HW_BTRS_LNL; + break; + case PCI_DEVICE_ID_NVL: + vdev->hw_ip_gen = IVPU_HW_IP_60XX; + vdev->btrs_gen = IVPU_HW_BTRS_LNL; + break; + default: + ivpu_err(vdev, "Unknown PCI device [%04x:%04x]\n", ivpu_vendor_id(vdev), + ivpu_device_id(vdev)); + return -EINVAL; + } + return 0; +} + static struct ivpu_user_limits *ivpu_user_limits_alloc(struct ivpu_device *vdev, uid_t uid) { struct ivpu_user_limits *limits; @@ -205,6 +247,7 @@ bool ivpu_is_capable(struct ivpu_device *vdev, u32 capability) case DRM_IVPU_CAP_BO_CREATE_FROM_USERPTR: return true; case DRM_IVPU_CAP_MANAGE_CMDQ: + case DRM_IVPU_CAP_CMDQ_SET_PRIORITY: return vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW; default: return false; @@ -247,10 +290,7 @@ static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_f break; case DRM_IVPU_PARAM_FW_API_VERSION: if (args->index < VPU_FW_API_VER_NUM) { - struct vpu_firmware_header *fw_hdr; - - fw_hdr = (struct vpu_firmware_header *)vdev->fw->file->data; - args->value = fw_hdr->api_version[args->index]; + args->value = vdev->fw->api_version[args->index]; } else { ret = -EINVAL; } @@ -273,6 +313,9 @@ static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_f case DRM_IVPU_PARAM_PREEMPT_BUFFER_SIZE: args->value = ivpu_fw_preempt_buf_size(vdev); break; + case DRM_IVPU_PARAM_CMDQ_PRIORITY: + ret = ivpu_cmdq_get_priority(file_priv, args->index, &args->value); + break; default: ret = -EINVAL; break; @@ -284,14 +327,23 @@ static int ivpu_get_param_ioctl(struct drm_device *dev, void *data, struct drm_f static int ivpu_set_param_ioctl(struct drm_device *dev, void *data, struct drm_file *file) { + struct ivpu_file_priv *file_priv = file->driver_priv; struct drm_ivpu_param *args = data; int ret = 0; + int idx; + + if (!drm_dev_enter(dev, &idx)) + return -ENODEV; switch (args->param) { + case DRM_IVPU_PARAM_CMDQ_PRIORITY: + ret = ivpu_cmdq_set_priority(file_priv, args->index, args->value); + break; default: ret = -EINVAL; } + drm_dev_exit(idx); return ret; } @@ -468,6 +520,14 @@ int ivpu_boot(struct ivpu_device *vdev) ivpu_fw_boot_params_setup(vdev, ivpu_bo_vaddr(vdev->fw->mem_bp)); vdev->fw->last_boot_mode = vdev->fw->next_boot_mode; + if (!ivpu_fw_is_warm_boot(vdev)) { + ret = ivpu_fw_load(vdev); + if (ret) { + ivpu_err(vdev, "Failed to load the firmware: %d\n", ret); + return ret; + } + } + ret = ivpu_hw_boot_fw(vdev); if (ret) { ivpu_err(vdev, "Failed to start the firmware: %d\n", ret); @@ -484,6 +544,9 @@ int ivpu_boot(struct ivpu_device *vdev) ivpu_hw_irq_enable(vdev); ivpu_ipc_enable(vdev); + if (ivpu_test_mode & IVPU_TEST_MODE_FW_TEST) + return 0; + if (!ivpu_fw_is_warm_boot(vdev)) { ret = ivpu_pm_dct_init(vdev); if (ret) @@ -637,6 +700,7 @@ static int ivpu_pci_init(struct ivpu_device *vdev) struct pci_dev *pdev = to_pci_dev(vdev->drm.dev); struct resource *bar0 = &pdev->resource[0]; struct resource *bar4 = &pdev->resource[4]; + int dma_bits; int ret; ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0); @@ -653,7 +717,12 @@ static int ivpu_pci_init(struct ivpu_device *vdev) return PTR_ERR(vdev->regb); } - ret = dma_set_mask_and_coherent(vdev->drm.dev, DMA_BIT_MASK(vdev->hw->dma_bits)); + if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_40XX) + dma_bits = 42; + else + dma_bits = 38; + + ret = dma_set_mask_and_coherent(vdev->drm.dev, DMA_BIT_MASK(dma_bits)); if (ret) { ivpu_err(vdev, "Failed to set DMA mask: %d\n", ret); return ret; @@ -701,12 +770,10 @@ static int ivpu_dev_init(struct ivpu_device *vdev) if (!vdev->pm) return -ENOMEM; - if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_40XX) - vdev->hw->dma_bits = 48; - else - vdev->hw->dma_bits = 38; + ret = ivpu_ip_gen_init(vdev); + if (ret) + return ret; - vdev->platform = IVPU_PLATFORM_INVALID; vdev->context_xa_limit.min = IVPU_USER_CONTEXT_MIN_SSID; vdev->context_xa_limit.max = IVPU_USER_CONTEXT_MAX_SSID; atomic64_set(&vdev->unique_id_counter, 0); @@ -839,17 +906,6 @@ static void ivpu_dev_fini(struct ivpu_device *vdev) xa_destroy(&vdev->context_xa); } -static struct pci_device_id ivpu_pci_ids[] = { - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_MTL) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_ARL) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_LNL) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_PTL_P) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_WCL) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_NVL) }, - {} -}; -MODULE_DEVICE_TABLE(pci, ivpu_pci_ids); - static int ivpu_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct ivpu_device *vdev; diff --git a/drivers/accel/ivpu/ivpu_drv.h b/drivers/accel/ivpu/ivpu_drv.h index 6f4012926478..a713f3645bfd 100644 --- a/drivers/accel/ivpu/ivpu_drv.h +++ b/drivers/accel/ivpu/ivpu_drv.h @@ -27,21 +27,13 @@ #define PCI_DEVICE_ID_MTL 0x7d1d #define PCI_DEVICE_ID_ARL 0xad1d #define PCI_DEVICE_ID_LNL 0x643e -#define PCI_DEVICE_ID_PTL_P 0xb03e +#define PCI_DEVICE_ID_PTL 0xb03e #define PCI_DEVICE_ID_WCL 0xfd3e #define PCI_DEVICE_ID_NVL 0xd71d -#define IVPU_HW_IP_37XX 37 -#define IVPU_HW_IP_40XX 40 -#define IVPU_HW_IP_50XX 50 -#define IVPU_HW_IP_60XX 60 - #define IVPU_HW_IP_REV_LNL_B0 4 #define IVPU_HW_IP_REV_NVL_A0 0 -#define IVPU_HW_BTRS_MTL 1 -#define IVPU_HW_BTRS_LNL 2 - #define IVPU_GLOBAL_CONTEXT_MMU_SSID 0 /* SSID 1 is used by the VPU to represent reserved context */ #define IVPU_RESERVED_CONTEXT_MMU_SSID 1 @@ -91,7 +83,7 @@ drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) #define ivpu_warn_ratelimited(vdev, fmt, ...) \ - drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) + drm_warn_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__) #define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__) @@ -107,10 +99,21 @@ ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \ } while (0) +enum vpu_hw_ip { + IVPU_HW_IP_37XX = 37, + IVPU_HW_IP_40XX = 40, + IVPU_HW_IP_50XX = 50, + IVPU_HW_IP_60XX = 60, +}; + +enum vpu_hw_btrs { + IVPU_HW_BTRS_MTL = 1, + IVPU_HW_BTRS_LNL = 2, +}; + struct ivpu_wa_table { bool punit_disabled; bool clear_runtime_mem; - bool interrupt_clear_with_0; bool disable_clock_relinquish; bool wp0_during_power_up; bool disable_d0i2; @@ -136,6 +139,8 @@ struct ivpu_device { struct drm_device drm; void __iomem *regb; void __iomem *regv; + enum vpu_hw_ip hw_ip_gen; + enum vpu_hw_btrs btrs_gen; u32 platform; u32 irq; @@ -186,6 +191,9 @@ struct ivpu_device { int autosuspend; int d0i3_entry_msg; int state_dump_msg; + int mmu_reg; + int mmu_queue; + int pwr_island_status; } timeout; }; @@ -222,6 +230,7 @@ extern bool ivpu_force_snoop; #define IVPU_TEST_MODE_FW_TEST BIT(0) #define IVPU_TEST_MODE_NULL_HW BIT(1) #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2) +#define IVPU_TEST_MODE_FREQ_CHANGE_ENABLE BIT(3) #define IVPU_TEST_MODE_MIP_DISABLE BIT(6) #define IVPU_TEST_MODE_DISABLE_TIMEOUTS BIT(8) #define IVPU_TEST_MODE_TURBO_ENABLE BIT(9) @@ -244,47 +253,24 @@ static inline u8 ivpu_revision(struct ivpu_device *vdev) return to_pci_dev(vdev->drm.dev)->revision; } +static inline u16 ivpu_vendor_id(struct ivpu_device *vdev) +{ + return to_pci_dev(vdev->drm.dev)->vendor; +} + static inline u16 ivpu_device_id(struct ivpu_device *vdev) { return to_pci_dev(vdev->drm.dev)->device; } -static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev) +static inline enum vpu_hw_ip ivpu_hw_ip_gen(struct ivpu_device *vdev) { - switch (ivpu_device_id(vdev)) { - case PCI_DEVICE_ID_MTL: - case PCI_DEVICE_ID_ARL: - return IVPU_HW_IP_37XX; - case PCI_DEVICE_ID_LNL: - return IVPU_HW_IP_40XX; - case PCI_DEVICE_ID_PTL_P: - case PCI_DEVICE_ID_WCL: - return IVPU_HW_IP_50XX; - case PCI_DEVICE_ID_NVL: - return IVPU_HW_IP_60XX; - default: - dump_stack(); - ivpu_err(vdev, "Unknown NPU IP generation\n"); - return 0; - } + return vdev->hw_ip_gen; } -static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev) +static inline enum vpu_hw_btrs ivpu_hw_btrs_gen(struct ivpu_device *vdev) { - switch (ivpu_device_id(vdev)) { - case PCI_DEVICE_ID_MTL: - case PCI_DEVICE_ID_ARL: - return IVPU_HW_BTRS_MTL; - case PCI_DEVICE_ID_LNL: - case PCI_DEVICE_ID_PTL_P: - case PCI_DEVICE_ID_WCL: - case PCI_DEVICE_ID_NVL: - return IVPU_HW_BTRS_LNL; - default: - dump_stack(); - ivpu_err(vdev, "Unknown buttress generation\n"); - return 0; - } + return vdev->btrs_gen; } static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev) diff --git a/drivers/accel/ivpu/ivpu_fw.c b/drivers/accel/ivpu/ivpu_fw.c index b78b7c35cd9b..96f5be23a867 100644 --- a/drivers/accel/ivpu/ivpu_fw.c +++ b/drivers/accel/ivpu/ivpu_fw.c @@ -28,15 +28,15 @@ #define ADDR_TO_L2_CACHE_CFG(addr) ((addr) >> 31) /* Check if FW API is compatible with the driver */ -#define IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, name, min_major) \ - ivpu_fw_check_api(vdev, fw_hdr, #name, \ +#define IVPU_FW_CHECK_API_COMPAT(vdev, name, min_major) \ + ivpu_fw_check_api(vdev, #name, \ VPU_##name##_API_VER_INDEX, \ VPU_##name##_API_VER_MAJOR, \ VPU_##name##_API_VER_MINOR, min_major) /* Check if API version is lower that the given version */ -#define IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, name, major, minor) \ - ivpu_fw_check_api_ver_lt(vdev, fw_hdr, #name, VPU_##name##_API_VER_INDEX, major, minor) +#define IVPU_FW_CHECK_API_VER_LT(vdev, name, major, minor) \ + ivpu_fw_check_api_ver_lt(vdev, #name, VPU_##name##_API_VER_INDEX, major, minor) #define IVPU_FOCUS_PRESENT_TIMER_MS 1000 @@ -93,12 +93,11 @@ static int ivpu_fw_request(struct ivpu_device *vdev) } static int -ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, - const char *str, int index, u16 expected_major, u16 expected_minor, - u16 min_major) +ivpu_fw_check_api(struct ivpu_device *vdev, const char *str, int index, u16 expected_major, + u16 expected_minor, u16 min_major) { - u16 major = (u16)(fw_hdr->api_version[index] >> 16); - u16 minor = (u16)(fw_hdr->api_version[index]); + u16 major = (u16)(vdev->fw->api_version[index] >> 16); + u16 minor = (u16)(vdev->fw->api_version[index]); if (major < min_major) { ivpu_err(vdev, "Incompatible FW %s API version: %d.%d, required %d.0 or later\n", @@ -116,11 +115,10 @@ ivpu_fw_check_api(struct ivpu_device *vdev, const struct vpu_firmware_header *fw } static bool -ivpu_fw_check_api_ver_lt(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr, - const char *str, int index, u16 major, u16 minor) +ivpu_fw_check_api_ver_lt(struct ivpu_device *vdev, const char *str, int index, u16 major, u16 minor) { - u16 fw_major = (u16)(fw_hdr->api_version[index] >> 16); - u16 fw_minor = (u16)(fw_hdr->api_version[index]); + u16 fw_major = (u16)(vdev->fw->api_version[index] >> 16); + u16 fw_minor = (u16)(vdev->fw->api_version[index]); if (fw_major < major || (fw_major == major && fw_minor < minor)) return true; @@ -142,7 +140,7 @@ bool ivpu_is_within_range(u64 addr, size_t size, struct ivpu_addr_range *range) } static u32 -ivpu_fw_sched_mode_select(struct ivpu_device *vdev, const struct vpu_firmware_header *fw_hdr) +ivpu_fw_sched_mode_select(struct ivpu_device *vdev) { if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_60XX && ivpu_sched_mode == VPU_SCHEDULING_MODE_OS) { @@ -153,7 +151,7 @@ ivpu_fw_sched_mode_select(struct ivpu_device *vdev, const struct vpu_firmware_he if (ivpu_sched_mode != IVPU_SCHED_MODE_AUTO) return ivpu_sched_mode; - if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, JSM, 3, 24)) + if (IVPU_FW_CHECK_API_VER_LT(vdev, JSM, 3, 24)) return VPU_SCHEDULING_MODE_OS; return VPU_SCHEDULING_MODE_HW; @@ -302,9 +300,11 @@ static int ivpu_fw_parse(struct ivpu_device *vdev) ivpu_info(vdev, "Firmware: %s, version: %s\n", fw->name, fw->version); - if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, BOOT, 3)) + memcpy(fw->api_version, fw_hdr->api_version, sizeof(fw->api_version)); + + if (IVPU_FW_CHECK_API_COMPAT(vdev, BOOT, 3)) return -EINVAL; - if (IVPU_FW_CHECK_API_COMPAT(vdev, fw_hdr, JSM, 3)) + if (IVPU_FW_CHECK_API_COMPAT(vdev, JSM, 3)) return -EINVAL; fw->boot_params_addr = boot_params_addr; @@ -324,7 +324,7 @@ static int ivpu_fw_parse(struct ivpu_device *vdev) fw->dvfs_mode = 0; - fw->sched_mode = ivpu_fw_sched_mode_select(vdev, fw_hdr); + fw->sched_mode = ivpu_fw_sched_mode_select(vdev); ivpu_info(vdev, "Scheduler mode: %s\n", fw->sched_mode ? "HW" : "OS"); ivpu_preemption_config_parse(vdev, fw_hdr); @@ -364,6 +364,25 @@ static void ivpu_fw_release(struct ivpu_device *vdev) } +static void ivpu_fw_mem_fini(struct ivpu_device *vdev) +{ + struct ivpu_fw_info *fw = vdev->fw; + + ivpu_bo_free(fw->mem_shave_nn); + ivpu_bo_free(fw->mem_log_verb); + ivpu_bo_free(fw->mem_log_crit); + ivpu_bo_free(fw->mem); + ivpu_bo_free(fw->mem_fw_ver); + ivpu_bo_free(fw->mem_bp); + + fw->mem_shave_nn = NULL; + fw->mem_log_verb = NULL; + fw->mem_log_crit = NULL; + fw->mem = NULL; + fw->mem_fw_ver = NULL; + fw->mem_bp = NULL; +} + static int ivpu_fw_mem_init(struct ivpu_device *vdev) { struct ivpu_fw_info *fw = vdev->fw; @@ -382,7 +401,7 @@ static int ivpu_fw_mem_init(struct ivpu_device *vdev) if (!fw->mem_fw_ver) { ivpu_err(vdev, "Failed to create firmware version memory buffer\n"); ret = -ENOMEM; - goto err_free_bp; + goto err_free; } fw->mem = ivpu_bo_create_runtime(vdev, fw->runtime_addr, fw->runtime_size, @@ -390,14 +409,14 @@ static int ivpu_fw_mem_init(struct ivpu_device *vdev) if (!fw->mem) { ivpu_err(vdev, "Failed to create firmware runtime memory buffer\n"); ret = -ENOMEM; - goto err_free_fw_ver; + goto err_free; } ret = ivpu_mmu_context_set_pages_ro(vdev, &vdev->gctx, fw->read_only_addr, fw->read_only_size); if (ret) { ivpu_err(vdev, "Failed to set firmware image read-only\n"); - goto err_free_fw_mem; + goto err_free; } fw->mem_log_crit = ivpu_bo_create_global(vdev, IVPU_FW_CRITICAL_BUFFER_SIZE, @@ -405,7 +424,7 @@ static int ivpu_fw_mem_init(struct ivpu_device *vdev) if (!fw->mem_log_crit) { ivpu_err(vdev, "Failed to create critical log buffer\n"); ret = -ENOMEM; - goto err_free_fw_mem; + goto err_free; } if (ivpu_fw_log_level <= IVPU_FW_LOG_INFO) @@ -418,7 +437,7 @@ static int ivpu_fw_mem_init(struct ivpu_device *vdev) if (!fw->mem_log_verb) { ivpu_err(vdev, "Failed to create verbose log buffer\n"); ret = -ENOMEM; - goto err_free_log_crit; + goto err_free; } if (fw->shave_nn_size) { @@ -427,47 +446,17 @@ static int ivpu_fw_mem_init(struct ivpu_device *vdev) if (!fw->mem_shave_nn) { ivpu_err(vdev, "Failed to create shavenn buffer\n"); ret = -ENOMEM; - goto err_free_log_verb; + goto err_free; } } return 0; -err_free_log_verb: - ivpu_bo_free(fw->mem_log_verb); -err_free_log_crit: - ivpu_bo_free(fw->mem_log_crit); -err_free_fw_mem: - ivpu_bo_free(fw->mem); -err_free_fw_ver: - ivpu_bo_free(fw->mem_fw_ver); -err_free_bp: - ivpu_bo_free(fw->mem_bp); +err_free: + ivpu_fw_mem_fini(vdev); return ret; } -static void ivpu_fw_mem_fini(struct ivpu_device *vdev) -{ - struct ivpu_fw_info *fw = vdev->fw; - - if (fw->mem_shave_nn) { - ivpu_bo_free(fw->mem_shave_nn); - fw->mem_shave_nn = NULL; - } - - ivpu_bo_free(fw->mem_log_verb); - ivpu_bo_free(fw->mem_log_crit); - ivpu_bo_free(fw->mem); - ivpu_bo_free(fw->mem_fw_ver); - ivpu_bo_free(fw->mem_bp); - - fw->mem_log_verb = NULL; - fw->mem_log_crit = NULL; - fw->mem = NULL; - fw->mem_fw_ver = NULL; - fw->mem_bp = NULL; -} - int ivpu_fw_init(struct ivpu_device *vdev) { int ret; @@ -484,8 +473,6 @@ int ivpu_fw_init(struct ivpu_device *vdev) if (ret) goto err_fw_release; - ivpu_fw_load(vdev); - return 0; err_fw_release: @@ -499,7 +486,7 @@ void ivpu_fw_fini(struct ivpu_device *vdev) ivpu_fw_release(vdev); } -void ivpu_fw_load(struct ivpu_device *vdev) +int ivpu_fw_load(struct ivpu_device *vdev) { struct ivpu_fw_info *fw = vdev->fw; u64 image_end_offset = fw->image_load_offset + fw->image_size; @@ -516,6 +503,7 @@ void ivpu_fw_load(struct ivpu_device *vdev) } wmb(); /* Flush WC buffers after writing fw->mem */ + return 0; } static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) diff --git a/drivers/accel/ivpu/ivpu_fw.h b/drivers/accel/ivpu/ivpu_fw.h index d3c410912c9c..45a705431f22 100644 --- a/drivers/accel/ivpu/ivpu_fw.h +++ b/drivers/accel/ivpu/ivpu_fw.h @@ -20,6 +20,7 @@ struct ivpu_fw_info { const struct firmware *file; const char *name; char version[FW_VERSION_STR_SIZE]; + u32 api_version[VPU_FW_API_VER_NUM]; struct ivpu_bo *mem_bp; struct ivpu_bo *mem_fw_ver; struct ivpu_bo *mem; @@ -54,7 +55,7 @@ struct ivpu_fw_info { bool ivpu_is_within_range(u64 addr, size_t size, struct ivpu_addr_range *range); int ivpu_fw_init(struct ivpu_device *vdev); void ivpu_fw_fini(struct ivpu_device *vdev); -void ivpu_fw_load(struct ivpu_device *vdev); +int ivpu_fw_load(struct ivpu_device *vdev); void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params); static inline bool ivpu_fw_is_warm_boot(struct ivpu_device *vdev) diff --git a/drivers/accel/ivpu/ivpu_gem.c b/drivers/accel/ivpu/ivpu_gem.c index 4f2005a8d496..c521a53f89bb 100644 --- a/drivers/accel/ivpu/ivpu_gem.c +++ b/drivers/accel/ivpu/ivpu_gem.c @@ -12,7 +12,7 @@ #include <drm/drm_cache.h> #include <drm/drm_debugfs.h> #include <drm/drm_file.h> -#include <drm/drm_utils.h> +#include <drm/drm_timeout.h> #include "ivpu_drv.h" #include "ivpu_fw.h" @@ -471,6 +471,9 @@ struct ivpu_bo *ivpu_bo_create_global(struct ivpu_device *vdev, u64 size, u32 fl void ivpu_bo_free(struct ivpu_bo *bo) { + if (!bo) + return; + struct iosys_map map = IOSYS_MAP_INIT_VADDR(bo->base.vaddr); if (bo->flags & DRM_IVPU_BO_MAPPABLE) { diff --git a/drivers/accel/ivpu/ivpu_hw.c b/drivers/accel/ivpu/ivpu_hw.c index 647dc045c231..86679d64fc14 100644 --- a/drivers/accel/ivpu/ivpu_hw.c +++ b/drivers/accel/ivpu/ivpu_hw.c @@ -67,9 +67,6 @@ static void wa_init(struct ivpu_device *vdev) vdev->wa.punit_disabled = false; vdev->wa.clear_runtime_mem = false; - if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) - vdev->wa.interrupt_clear_with_0 = ivpu_hw_btrs_irqs_clear_with_0_mtl(vdev); - if ((ivpu_device_id(vdev) == PCI_DEVICE_ID_LNL && ivpu_revision(vdev) < IVPU_HW_IP_REV_LNL_B0) || (ivpu_device_id(vdev) == PCI_DEVICE_ID_NVL && @@ -90,7 +87,6 @@ static void wa_init(struct ivpu_device *vdev) IVPU_PRINT_WA(punit_disabled); IVPU_PRINT_WA(clear_runtime_mem); - IVPU_PRINT_WA(interrupt_clear_with_0); IVPU_PRINT_WA(disable_clock_relinquish); IVPU_PRINT_WA(wp0_during_power_up); IVPU_PRINT_WA(disable_d0i2); @@ -98,14 +94,22 @@ static void wa_init(struct ivpu_device *vdev) static void timeouts_init(struct ivpu_device *vdev) { - if (ivpu_test_mode & IVPU_TEST_MODE_DISABLE_TIMEOUTS) { + if (ivpu_test_mode & (IVPU_TEST_MODE_DISABLE_TIMEOUTS | IVPU_TEST_MODE_FW_TEST)) { + /* in milliseconds, negative value disables the timeout */ vdev->timeout.boot = -1; vdev->timeout.jsm = -1; vdev->timeout.tdr = -1; vdev->timeout.inference = -1; vdev->timeout.autosuspend = -1; vdev->timeout.d0i3_entry_msg = -1; + /* fixed delay, not a timeout - has to remain finite */ + vdev->timeout.state_dump_msg = 100; + /* in microseconds, zero disables the timeout */ + vdev->timeout.mmu_reg = 0; + vdev->timeout.mmu_queue = 0; + vdev->timeout.pwr_island_status = 0; } else if (ivpu_is_fpga(vdev)) { + /* in milliseconds */ vdev->timeout.boot = 50; vdev->timeout.jsm = 15000; vdev->timeout.tdr = 30000; @@ -113,7 +117,12 @@ static void timeouts_init(struct ivpu_device *vdev) vdev->timeout.autosuspend = -1; vdev->timeout.d0i3_entry_msg = 500; vdev->timeout.state_dump_msg = 10000; + /* in microseconds */ + vdev->timeout.mmu_reg = 100 * USEC_PER_MSEC; + vdev->timeout.mmu_queue = 1000 * USEC_PER_MSEC; + vdev->timeout.pwr_island_status = 5 * USEC_PER_MSEC; } else if (ivpu_is_simics(vdev)) { + /* in milliseconds */ vdev->timeout.boot = 50; vdev->timeout.jsm = 500; vdev->timeout.tdr = 10000; @@ -121,7 +130,12 @@ static void timeouts_init(struct ivpu_device *vdev) vdev->timeout.autosuspend = 100; vdev->timeout.d0i3_entry_msg = 100; vdev->timeout.state_dump_msg = 10; + /* in microseconds */ + vdev->timeout.mmu_reg = 10 * USEC_PER_MSEC; + vdev->timeout.mmu_queue = 100 * USEC_PER_MSEC; + vdev->timeout.pwr_island_status = 5 * USEC_PER_MSEC; } else { + /* in milliseconds */ vdev->timeout.boot = 1000; vdev->timeout.jsm = 500; vdev->timeout.tdr = 2000; @@ -132,6 +146,10 @@ static void timeouts_init(struct ivpu_device *vdev) vdev->timeout.autosuspend = 100; vdev->timeout.d0i3_entry_msg = 5; vdev->timeout.state_dump_msg = 100; + /* in microseconds */ + vdev->timeout.mmu_reg = 10 * USEC_PER_MSEC; + vdev->timeout.mmu_queue = 100 * USEC_PER_MSEC; + vdev->timeout.pwr_island_status = 5 * USEC_PER_MSEC; } } @@ -356,11 +374,6 @@ void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable) void ivpu_irq_handlers_init(struct ivpu_device *vdev) { - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_37xx; - else - vdev->hw->irq.ip_irq_handler = ivpu_hw_ip_irq_handler_40xx; - if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) vdev->hw->irq.btrs_irq_handler = ivpu_hw_btrs_irq_handler_mtl; else diff --git a/drivers/accel/ivpu/ivpu_hw.h b/drivers/accel/ivpu/ivpu_hw.h index 487a918e2fa9..8c1b61df6cd4 100644 --- a/drivers/accel/ivpu/ivpu_hw.h +++ b/drivers/accel/ivpu/ivpu_hw.h @@ -18,7 +18,6 @@ struct ivpu_addr_range { struct ivpu_hw_info { struct { bool (*btrs_irq_handler)(struct ivpu_device *vdev, int irq); - bool (*ip_irq_handler)(struct ivpu_device *vdev, int irq); } irq; struct { struct ivpu_addr_range runtime; @@ -49,9 +48,9 @@ struct ivpu_hw_info { u32 tile_fuse; u32 sku; u16 config; - int dma_bits; ktime_t d0i3_entry_host_ts; u64 d0i3_entry_vpu_ts; + u32 btrs_irq_mask; atomic_t firewall_irq_counter; }; @@ -74,11 +73,6 @@ static inline u32 ivpu_hw_btrs_irq_handler(struct ivpu_device *vdev, int irq) return vdev->hw->irq.btrs_irq_handler(vdev, irq); } -static inline u32 ivpu_hw_ip_irq_handler(struct ivpu_device *vdev, int irq) -{ - return vdev->hw->irq.ip_irq_handler(vdev, irq); -} - static inline u64 ivpu_hw_range_size(const struct ivpu_addr_range *range) { return range->end - range->start; diff --git a/drivers/accel/ivpu/ivpu_hw_40xx_reg.h b/drivers/accel/ivpu/ivpu_hw_40xx_reg.h deleted file mode 100644 index fc0ee8d637f9..000000000000 --- a/drivers/accel/ivpu/ivpu_hw_40xx_reg.h +++ /dev/null @@ -1,195 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2020-2023 Intel Corporation - */ - -#ifndef __IVPU_HW_40XX_REG_H__ -#define __IVPU_HW_40XX_REG_H__ - -#include <linux/bits.h> - -#define VPU_40XX_HOST_SS_CPR_CLK_EN 0x00000080u -#define VPU_40XX_HOST_SS_CPR_CLK_EN_TOP_NOC_MASK BIT_MASK(1) -#define VPU_40XX_HOST_SS_CPR_CLK_EN_DSS_MAS_MASK BIT_MASK(10) -#define VPU_40XX_HOST_SS_CPR_CLK_EN_CSS_MAS_MASK BIT_MASK(11) - -#define VPU_40XX_HOST_SS_CPR_CLK_SET 0x00000084u -#define VPU_40XX_HOST_SS_CPR_CLK_SET_TOP_NOC_MASK BIT_MASK(1) -#define VPU_40XX_HOST_SS_CPR_CLK_SET_DSS_MAS_MASK BIT_MASK(10) -#define VPU_40XX_HOST_SS_CPR_CLK_SET_MSS_MAS_MASK BIT_MASK(11) - -#define VPU_40XX_HOST_SS_CPR_RST_EN 0x00000090u -#define VPU_40XX_HOST_SS_CPR_RST_EN_TOP_NOC_MASK BIT_MASK(1) -#define VPU_40XX_HOST_SS_CPR_RST_EN_DSS_MAS_MASK BIT_MASK(10) -#define VPU_40XX_HOST_SS_CPR_RST_EN_CSS_MAS_MASK BIT_MASK(11) - -#define VPU_40XX_HOST_SS_CPR_RST_SET 0x00000094u -#define VPU_40XX_HOST_SS_CPR_RST_SET_TOP_NOC_MASK BIT_MASK(1) -#define VPU_40XX_HOST_SS_CPR_RST_SET_DSS_MAS_MASK BIT_MASK(10) -#define VPU_40XX_HOST_SS_CPR_RST_SET_MSS_MAS_MASK BIT_MASK(11) - -#define VPU_40XX_HOST_SS_CPR_RST_CLR 0x00000098u -#define VPU_40XX_HOST_SS_CPR_RST_CLR_TOP_NOC_MASK BIT_MASK(1) -#define VPU_40XX_HOST_SS_CPR_RST_CLR_DSS_MAS_MASK BIT_MASK(10) -#define VPU_40XX_HOST_SS_CPR_RST_CLR_MSS_MAS_MASK BIT_MASK(11) - -#define VPU_40XX_HOST_SS_HW_VERSION 0x00000108u -#define VPU_40XX_HOST_SS_HW_VERSION_SOC_REVISION_MASK GENMASK(7, 0) -#define VPU_40XX_HOST_SS_HW_VERSION_SOC_NUMBER_MASK GENMASK(15, 8) -#define VPU_40XX_HOST_SS_HW_VERSION_VPU_GENERATION_MASK GENMASK(23, 16) - -#define VPU_40XX_HOST_SS_SW_VERSION 0x0000010cu - -#define VPU_40XX_HOST_SS_GEN_CTRL 0x00000118u -#define VPU_40XX_HOST_SS_GEN_CTRL_PS_MASK GENMASK(31, 29) - -#define VPU_40XX_HOST_SS_NOC_QREQN 0x00000154u -#define VPU_40XX_HOST_SS_NOC_QREQN_TOP_SOCMMIO_MASK BIT_MASK(0) - -#define VPU_40XX_HOST_SS_NOC_QACCEPTN 0x00000158u -#define VPU_40XX_HOST_SS_NOC_QACCEPTN_TOP_SOCMMIO_MASK BIT_MASK(0) - -#define VPU_40XX_HOST_SS_NOC_QDENY 0x0000015cu -#define VPU_40XX_HOST_SS_NOC_QDENY_TOP_SOCMMIO_MASK BIT_MASK(0) - -#define VPU_40XX_TOP_NOC_QREQN 0x00000160u -#define VPU_40XX_TOP_NOC_QREQN_CPU_CTRL_MASK BIT_MASK(0) -#define VPU_40XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK BIT_MASK(2) - -#define VPU_40XX_TOP_NOC_QACCEPTN 0x00000164u -#define VPU_40XX_TOP_NOC_QACCEPTN_CPU_CTRL_MASK BIT_MASK(0) -#define VPU_40XX_TOP_NOC_QACCEPTN_HOSTIF_L2CACHE_MASK BIT_MASK(2) - -#define VPU_40XX_TOP_NOC_QDENY 0x00000168u -#define VPU_40XX_TOP_NOC_QDENY_CPU_CTRL_MASK BIT_MASK(0) -#define VPU_40XX_TOP_NOC_QDENY_HOSTIF_L2CACHE_MASK BIT_MASK(2) - -#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN 0x00000170u -#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_ROM_CMX_MASK BIT_MASK(0) -#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_DBG_MASK BIT_MASK(1) -#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_CTRL_MASK BIT_MASK(2) -#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_DEC400_MASK BIT_MASK(3) -#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_NCE_MASK BIT_MASK(4) -#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_MASK BIT_MASK(5) -#define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_CMX_MASK BIT_MASK(6) - -#define VPU_40XX_HOST_SS_ICB_STATUS_0 0x00010210u -#define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_0_INT_MASK BIT_MASK(0) -#define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_1_INT_MASK BIT_MASK(1) -#define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_2_INT_MASK BIT_MASK(2) -#define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_3_INT_MASK BIT_MASK(3) -#define VPU_40XX_HOST_SS_ICB_STATUS_0_HOST_IPC_FIFO_INT_MASK BIT_MASK(4) -#define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_0_INT_MASK BIT_MASK(5) -#define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_1_INT_MASK BIT_MASK(6) -#define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_2_INT_MASK BIT_MASK(7) -#define VPU_40XX_HOST_SS_ICB_STATUS_0_NOC_FIREWALL_INT_MASK BIT_MASK(8) -#define VPU_40XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_0_INT_MASK BIT_MASK(30) -#define VPU_40XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_1_INT_MASK BIT_MASK(31) - -#define VPU_40XX_HOST_SS_ICB_STATUS_1 0x00010214u -#define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_2_INT_MASK BIT_MASK(0) -#define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_3_INT_MASK BIT_MASK(1) -#define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_4_INT_MASK BIT_MASK(2) - -#define VPU_40XX_HOST_SS_ICB_CLEAR_0 0x00010220u -#define VPU_40XX_HOST_SS_ICB_CLEAR_1 0x00010224u -#define VPU_40XX_HOST_SS_ICB_ENABLE_0 0x00010240u -#define VPU_40XX_HOST_SS_ICB_ENABLE_1 0x00010244u - -#define VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM 0x000200f4u - -#define VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT 0x000200fcu -#define VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT_FILL_LEVEL_MASK GENMASK(23, 16) - -#define VPU_40XX_HOST_SS_AON_PWR_ISO_EN0 0x00030020u -#define VPU_40XX_HOST_SS_AON_PWR_ISO_EN0_CSS_CPU_MASK BIT_MASK(3) - -#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0 0x00030024u -#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0_CSS_CPU_MASK BIT_MASK(3) - -#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0 0x00030028u -#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0_CSS_CPU_MASK BIT_MASK(3) - -#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0 0x0003002cu -#define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0_CSS_CPU_MASK BIT_MASK(3) - -#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY 0x00030068u -#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST_DLY_MASK GENMASK(7, 0) -#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST1_DLY_MASK GENMASK(15, 8) -#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST2_DLY_MASK GENMASK(23, 16) - -#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY 0x0003006cu -#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK GENMASK(7, 0) - -#define VPU_40XX_HOST_SS_AON_IDLE_GEN 0x00030200u -#define VPU_40XX_HOST_SS_AON_IDLE_GEN_EN_MASK BIT_MASK(0) -#define VPU_40XX_HOST_SS_AON_IDLE_GEN_HW_PG_EN_MASK BIT_MASK(1) - -#define VPU_40XX_HOST_SS_AON_DPU_ACTIVE 0x00030204u -#define VPU_40XX_HOST_SS_AON_DPU_ACTIVE_DPU_ACTIVE_MASK BIT_MASK(0) - -#define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE 0x00030210u -#define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE_REQ_OVERRIDE_MASK BIT_MASK(0) - -#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO 0x00040040u -#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_DONE_MASK BIT_MASK(0) -#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IOSF_RS_ID_MASK GENMASK(2, 1) -#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK GENMASK(31, 3) - -#define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR 0x00082020u -#define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_FINAL_PLL_FREQ_MASK GENMASK(15, 0) -#define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_CONFIG_ID_MASK GENMASK(31, 16) - -#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES 0x00360000u -#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_CACHE_OVERRIDE_EN_MASK BIT_MASK(0) -#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AWCACHE_OVERRIDE_MASK BIT_MASK(1) -#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_ARCACHE_OVERRIDE_MASK BIT_MASK(2) -#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_SNOOP_OVERRIDE_EN_MASK BIT_MASK(3) -#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AW_SNOOP_OVERRIDE_MASK BIT_MASK(4) -#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AR_SNOOP_OVERRIDE_MASK BIT_MASK(5) -#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AW_CONTEXT_FLAG_MASK GENMASK(10, 6) -#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AR_CONTEXT_FLAG_MASK GENMASK(15, 11) - -#define VPU_40XX_HOST_IF_TBU_MMUSSIDV 0x00360004u -#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU0_AWMMUSSIDV_MASK BIT_MASK(0) -#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU0_ARMMUSSIDV_MASK BIT_MASK(1) -#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU1_AWMMUSSIDV_MASK BIT_MASK(2) -#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU1_ARMMUSSIDV_MASK BIT_MASK(3) -#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU2_AWMMUSSIDV_MASK BIT_MASK(4) -#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU2_ARMMUSSIDV_MASK BIT_MASK(5) -#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU3_AWMMUSSIDV_MASK BIT_MASK(6) -#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU3_ARMMUSSIDV_MASK BIT_MASK(7) -#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU4_AWMMUSSIDV_MASK BIT_MASK(8) -#define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU4_ARMMUSSIDV_MASK BIT_MASK(9) - -#define VPU_40XX_CPU_SS_DSU_LEON_RT_BASE 0x04000000u -#define VPU_40XX_CPU_SS_DSU_LEON_RT_DSU_CTRL 0x04000000u -#define VPU_40XX_CPU_SS_DSU_LEON_RT_PC_REG 0x04400010u -#define VPU_40XX_CPU_SS_DSU_LEON_RT_NPC_REG 0x04400014u -#define VPU_40XX_CPU_SS_DSU_LEON_RT_DSU_TRAP_REG 0x04400020u - -#define VPU_40XX_CPU_SS_TIM_WATCHDOG 0x0102009cu -#define VPU_40XX_CPU_SS_TIM_WDOG_EN 0x010200a4u -#define VPU_40XX_CPU_SS_TIM_SAFE 0x010200a8u - -#define VPU_40XX_CPU_SS_TIM_GEN_CONFIG 0x01021008u -#define VPU_40XX_CPU_SS_TIM_GEN_CONFIG_WDOG_TO_INT_CLR_MASK BIT_MASK(9) - -#define VPU_40XX_CPU_SS_CPR_NOC_QREQN 0x01010030u -#define VPU_40XX_CPU_SS_CPR_NOC_QREQN_TOP_MMIO_MASK BIT_MASK(0) - -#define VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN 0x01010034u -#define VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN_TOP_MMIO_MASK BIT_MASK(0) - -#define VPU_40XX_CPU_SS_CPR_NOC_QDENY 0x01010038u -#define VPU_40XX_CPU_SS_CPR_NOC_QDENY_TOP_MMIO_MASK BIT_MASK(0) - -#define VPU_40XX_CPU_SS_TIM_IPC_FIFO 0x010200f0u -#define VPU_40XX_CPU_SS_TIM_PERF_EXT_FREE_CNT 0x01029008u - -#define VPU_40XX_CPU_SS_DOORBELL_0 0x01300000u -#define VPU_40XX_CPU_SS_DOORBELL_0_SET_MASK BIT_MASK(0) - -#define VPU_40XX_CPU_SS_DOORBELL_1 0x01301000u - -#endif /* __IVPU_HW_40XX_REG_H__ */ diff --git a/drivers/accel/ivpu/ivpu_hw_btrs.c b/drivers/accel/ivpu/ivpu_hw_btrs.c index a17c829adb89..840983a618ca 100644 --- a/drivers/accel/ivpu/ivpu_hw_btrs.c +++ b/drivers/accel/ivpu/ivpu_hw_btrs.c @@ -8,8 +8,7 @@ #include "ivpu_drv.h" #include "ivpu_hw.h" #include "ivpu_hw_btrs.h" -#include "ivpu_hw_btrs_lnl_reg.h" -#include "ivpu_hw_btrs_mtl_reg.h" +#include "ivpu_hw_btrs_reg.h" #include "ivpu_hw_reg_io.h" #include "ivpu_jsm_msg.h" #include "ivpu_pm.h" @@ -24,9 +23,6 @@ (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR)) | \ (REG_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, SURV_ERR))) -#define BTRS_MTL_ALL_IRQ_MASK (BTRS_MTL_IRQ_MASK | (REG_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, \ - FREQ_CHANGE))) - #define BTRS_IRQ_DISABLE_MASK ((u32)-1) #define BTRS_LNL_ALL_IRQ_MASK ((u32)-1) @@ -49,9 +45,6 @@ #define BTRS_MTL_TILE_FUSE_ENABLE_BOTH 0x0 #define BTRS_MTL_TILE_SKU_BOTH 0x3630 -#define BTRS_LNL_TILE_MAX_NUM 6 -#define BTRS_LNL_TILE_MAX_MASK 0x3f - #define WEIGHTS_DEFAULT 0xf711f711u #define WEIGHTS_ATS_DEFAULT 0x0000f711u @@ -59,18 +52,6 @@ #define DCT_ENABLE 0x1 #define DCT_DISABLE 0x0 -int ivpu_hw_btrs_irqs_clear_with_0_mtl(struct ivpu_device *vdev) -{ - REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, BTRS_MTL_ALL_IRQ_MASK); - if (REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) == BTRS_MTL_ALL_IRQ_MASK) { - /* Writing 1s does not clear the interrupt status register */ - REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, 0x0); - return true; - } - - return false; -} - static void freq_ratios_init_mtl(struct ivpu_device *vdev) { struct ivpu_hw_info *hw = vdev->hw; @@ -115,13 +96,9 @@ void ivpu_hw_btrs_freq_ratios_init(struct ivpu_device *vdev) static bool tile_disable_check(u32 config) { - /* Allowed values: 0 or one bit from range 0-5 (6 tiles) */ if (config == 0) return true; - if (config > BIT(BTRS_LNL_TILE_MAX_NUM - 1)) - return false; - if ((config & (config - 1)) == 0) return true; @@ -156,6 +133,11 @@ static int info_init_mtl(struct ivpu_device *vdev) hw->tile_fuse = BTRS_MTL_TILE_FUSE_ENABLE_BOTH; hw->sku = BTRS_MTL_TILE_SKU_BOTH; hw->config = WP_CONFIG(MTL_CONFIG_2_TILE, MTL_PLL_RATIO_4_3); + hw->btrs_irq_mask = BTRS_MTL_IRQ_MASK; + + if (ivpu_test_mode & IVPU_TEST_MODE_FREQ_CHANGE_ENABLE) + hw->btrs_irq_mask = REG_SET_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, FREQ_CHANGE, + hw->btrs_irq_mask); return 0; } @@ -172,6 +154,11 @@ static int info_init_lnl(struct ivpu_device *vdev) hw->tile_fuse = tile_fuse_config; hw->pll.profiling_freq = PLL_PROFILING_FREQ_DEFAULT; + hw->btrs_irq_mask = BTRS_LNL_IRQ_MASK; + + if (ivpu_test_mode & IVPU_TEST_MODE_FREQ_CHANGE_ENABLE) + hw->btrs_irq_mask = REG_SET_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, FREQ_CHANGE, + hw->btrs_irq_mask); return 0; } @@ -698,7 +685,7 @@ int ivpu_hw_btrs_cfg_freq_init(struct ivpu_device *vdev) /* Handler for IRQs from Buttress core (irqB) */ bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq) { - u32 status = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & BTRS_MTL_IRQ_MASK; + u32 status = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & vdev->hw->btrs_irq_mask; bool schedule_recovery = false; if (!status) @@ -729,14 +716,7 @@ bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq) } /* This must be done after interrupts are cleared at the source. */ - if (IVPU_WA(interrupt_clear_with_0)) - /* - * Writing 1 triggers an interrupt, so we can't perform read update write. - * Clear local interrupt status by writing 0 to all bits. - */ - REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, 0x0); - else - REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, status); + REGB_WR32(VPU_HW_BTRS_MTL_INTERRUPT_STAT, status); if (schedule_recovery) ivpu_pm_trigger_recovery(vdev, "Buttress IRQ"); @@ -747,7 +727,7 @@ bool ivpu_hw_btrs_irq_handler_mtl(struct ivpu_device *vdev, int irq) /* Handler for IRQs from Buttress core (irqB) */ bool ivpu_hw_btrs_irq_handler_lnl(struct ivpu_device *vdev, int irq) { - u32 status = REGB_RD32(VPU_HW_BTRS_LNL_INTERRUPT_STAT) & BTRS_LNL_IRQ_MASK; + u32 status = REGB_RD32(VPU_HW_BTRS_LNL_INTERRUPT_STAT) & vdev->hw->btrs_irq_mask; bool schedule_recovery = false; if (!status) @@ -889,10 +869,10 @@ void ivpu_hw_btrs_global_int_enable(struct ivpu_device *vdev) void ivpu_hw_btrs_irq_enable(struct ivpu_device *vdev) { if (ivpu_hw_btrs_gen(vdev) == IVPU_HW_BTRS_MTL) { - REGB_WR32(VPU_HW_BTRS_MTL_LOCAL_INT_MASK, (u32)(~BTRS_MTL_IRQ_MASK)); + REGB_WR32(VPU_HW_BTRS_MTL_LOCAL_INT_MASK, (u32)(~vdev->hw->btrs_irq_mask)); REGB_WR32(VPU_HW_BTRS_MTL_GLOBAL_INT_MASK, 0x0); } else { - REGB_WR32(VPU_HW_BTRS_LNL_LOCAL_INT_MASK, (u32)(~BTRS_LNL_IRQ_MASK)); + REGB_WR32(VPU_HW_BTRS_LNL_LOCAL_INT_MASK, (u32)(~vdev->hw->btrs_irq_mask)); REGB_WR32(VPU_HW_BTRS_LNL_GLOBAL_INT_MASK, 0x0); } } @@ -910,7 +890,7 @@ void ivpu_hw_btrs_irq_disable(struct ivpu_device *vdev) static void diagnose_failure_mtl(struct ivpu_device *vdev) { - u32 reg = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & BTRS_MTL_IRQ_MASK; + u32 reg = REGB_RD32(VPU_HW_BTRS_MTL_INTERRUPT_STAT) & vdev->hw->btrs_irq_mask; if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, reg)) ivpu_err(vdev, "ATS_ERR irq 0x%016llx", REGB_RD64(VPU_HW_BTRS_MTL_ATS_ERR_LOG_0)); @@ -927,7 +907,7 @@ static void diagnose_failure_mtl(struct ivpu_device *vdev) static void diagnose_failure_lnl(struct ivpu_device *vdev) { - u32 reg = REGB_RD32(VPU_HW_BTRS_LNL_INTERRUPT_STAT) & BTRS_LNL_IRQ_MASK; + u32 reg = REGB_RD32(VPU_HW_BTRS_LNL_INTERRUPT_STAT) & vdev->hw->btrs_irq_mask; if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, ATS_ERR, reg)) { ivpu_err(vdev, "ATS_ERR_LOG1 0x%08x ATS_ERR_LOG2 0x%08x\n", diff --git a/drivers/accel/ivpu/ivpu_hw_btrs.h b/drivers/accel/ivpu/ivpu_hw_btrs.h index d6343d734570..30c89ab8e4bd 100644 --- a/drivers/accel/ivpu/ivpu_hw_btrs.h +++ b/drivers/accel/ivpu/ivpu_hw_btrs.h @@ -7,8 +7,6 @@ #define __IVPU_HW_BTRS_H__ #include "ivpu_drv.h" -#include "ivpu_hw_37xx_reg.h" -#include "ivpu_hw_40xx_reg.h" #include "ivpu_hw_reg_io.h" #define PLL_PROFILING_FREQ_DEFAULT 38400000 @@ -19,7 +17,6 @@ int ivpu_hw_btrs_info_init(struct ivpu_device *vdev); void ivpu_hw_btrs_freq_ratios_init(struct ivpu_device *vdev); -int ivpu_hw_btrs_irqs_clear_with_0_mtl(struct ivpu_device *vdev); int ivpu_hw_btrs_wp_drive(struct ivpu_device *vdev, bool enable); int ivpu_hw_btrs_wait_for_clock_res_own_ack(struct ivpu_device *vdev); int ivpu_hw_btrs_d0i3_enable(struct ivpu_device *vdev); diff --git a/drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h b/drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h deleted file mode 100644 index e93d539e066f..000000000000 --- a/drivers/accel/ivpu/ivpu_hw_btrs_mtl_reg.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2020-2023 Intel Corporation - */ - -#ifndef __IVPU_HW_BTRS_MTL_REG_H__ -#define __IVPU_HW_BTRS_MTL_REG_H__ - -#include <linux/bits.h> - -#define VPU_HW_BTRS_MTL_INTERRUPT_TYPE 0x00000000u - -#define VPU_HW_BTRS_MTL_INTERRUPT_STAT 0x00000004u -#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0) -#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1) -#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_UFI_ERR_MASK BIT_MASK(2) - -#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0 0x00000008u -#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0) -#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16) - -#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1 0x0000000cu -#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0) -#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16) - -#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2 0x00000010u -#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0) - -#define VPU_HW_BTRS_MTL_WP_REQ_CMD 0x00000014u -#define VPU_HW_BTRS_MTL_WP_REQ_CMD_SEND_MASK BIT_MASK(0) - -#define VPU_HW_BTRS_MTL_WP_DOWNLOAD 0x00000018u -#define VPU_HW_BTRS_MTL_WP_DOWNLOAD_TARGET_RATIO_MASK GENMASK(15, 0) - -#define VPU_HW_BTRS_MTL_CURRENT_PLL 0x0000001cu -#define VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK GENMASK(15, 0) - -#define VPU_HW_BTRS_MTL_PLL_ENABLE 0x00000020u - -#define VPU_HW_BTRS_MTL_FMIN_FUSE 0x00000024u -#define VPU_HW_BTRS_MTL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0) -#define VPU_HW_BTRS_MTL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8) - -#define VPU_HW_BTRS_MTL_FMAX_FUSE 0x00000028u -#define VPU_HW_BTRS_MTL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0) - -#define VPU_HW_BTRS_MTL_TILE_FUSE 0x0000002cu -#define VPU_HW_BTRS_MTL_TILE_FUSE_VALID_MASK BIT_MASK(0) -#define VPU_HW_BTRS_MTL_TILE_FUSE_SKU_MASK GENMASK(3, 2) - -#define VPU_HW_BTRS_MTL_LOCAL_INT_MASK 0x00000030u -#define VPU_HW_BTRS_MTL_GLOBAL_INT_MASK 0x00000034u - -#define VPU_HW_BTRS_MTL_PLL_STATUS 0x00000040u -#define VPU_HW_BTRS_MTL_PLL_STATUS_LOCK_MASK BIT_MASK(1) - -#define VPU_HW_BTRS_MTL_VPU_STATUS 0x00000044u -#define VPU_HW_BTRS_MTL_VPU_STATUS_READY_MASK BIT_MASK(0) -#define VPU_HW_BTRS_MTL_VPU_STATUS_IDLE_MASK BIT_MASK(1) - -#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL 0x00000060u -#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0) -#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_I3_MASK BIT_MASK(2) - -#define VPU_HW_BTRS_MTL_VPU_IP_RESET 0x00000050u -#define VPU_HW_BTRS_MTL_VPU_IP_RESET_TRIGGER_MASK BIT_MASK(0) - -#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET 0x00000080u -#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE 0x00000084u -#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE 0x00000088u - -#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_0 0x000000a0u -#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_1 0x000000a4u -#define VPU_HW_BTRS_MTL_ATS_ERR_CLEAR 0x000000a8u - -#define VPU_HW_BTRS_MTL_UFI_ERR_LOG 0x000000b0u -#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_CQ_ID_MASK GENMASK(11, 0) -#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_AXI_ID_MASK GENMASK(19, 12) -#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_OPCODE_MASK GENMASK(24, 20) - -#define VPU_HW_BTRS_MTL_UFI_ERR_CLEAR 0x000000b4u - -#endif /* __IVPU_HW_BTRS_MTL_REG_H__ */ diff --git a/drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h b/drivers/accel/ivpu/ivpu_hw_btrs_reg.h index a81a9ba540fa..b9628bd9cb56 100644 --- a/drivers/accel/ivpu/ivpu_hw_btrs_lnl_reg.h +++ b/drivers/accel/ivpu/ivpu_hw_btrs_reg.h @@ -1,13 +1,85 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (C) 2020-2024 Intel Corporation + * Copyright (C) 2020-2026 Intel Corporation */ -#ifndef __IVPU_HW_BTRS_LNL_REG_H__ -#define __IVPU_HW_BTRS_LNL_REG_H__ +#ifndef __IVPU_HW_BTRS_REG_H__ +#define __IVPU_HW_BTRS_REG_H__ #include <linux/bits.h> +#define VPU_HW_BTRS_MTL_INTERRUPT_TYPE 0x00000000u + +#define VPU_HW_BTRS_MTL_INTERRUPT_STAT 0x00000004u +#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0) +#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1) +#define VPU_HW_BTRS_MTL_INTERRUPT_STAT_UFI_ERR_MASK BIT_MASK(2) + +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0 0x00000008u +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0) +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16) + +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1 0x0000000cu +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0) +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16) + +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2 0x00000010u +#define VPU_HW_BTRS_MTL_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0) + +#define VPU_HW_BTRS_MTL_WP_REQ_CMD 0x00000014u +#define VPU_HW_BTRS_MTL_WP_REQ_CMD_SEND_MASK BIT_MASK(0) + +#define VPU_HW_BTRS_MTL_WP_DOWNLOAD 0x00000018u +#define VPU_HW_BTRS_MTL_WP_DOWNLOAD_TARGET_RATIO_MASK GENMASK(15, 0) + +#define VPU_HW_BTRS_MTL_CURRENT_PLL 0x0000001cu +#define VPU_HW_BTRS_MTL_CURRENT_PLL_RATIO_MASK GENMASK(15, 0) + +#define VPU_HW_BTRS_MTL_PLL_ENABLE 0x00000020u + +#define VPU_HW_BTRS_MTL_FMIN_FUSE 0x00000024u +#define VPU_HW_BTRS_MTL_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0) +#define VPU_HW_BTRS_MTL_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8) + +#define VPU_HW_BTRS_MTL_FMAX_FUSE 0x00000028u +#define VPU_HW_BTRS_MTL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0) + +#define VPU_HW_BTRS_MTL_TILE_FUSE 0x0000002cu +#define VPU_HW_BTRS_MTL_TILE_FUSE_VALID_MASK BIT_MASK(0) +#define VPU_HW_BTRS_MTL_TILE_FUSE_SKU_MASK GENMASK(3, 2) + +#define VPU_HW_BTRS_MTL_LOCAL_INT_MASK 0x00000030u +#define VPU_HW_BTRS_MTL_GLOBAL_INT_MASK 0x00000034u + +#define VPU_HW_BTRS_MTL_PLL_STATUS 0x00000040u +#define VPU_HW_BTRS_MTL_PLL_STATUS_LOCK_MASK BIT_MASK(1) + +#define VPU_HW_BTRS_MTL_VPU_STATUS 0x00000044u +#define VPU_HW_BTRS_MTL_VPU_STATUS_READY_MASK BIT_MASK(0) +#define VPU_HW_BTRS_MTL_VPU_STATUS_IDLE_MASK BIT_MASK(1) + +#define VPU_HW_BTRS_MTL_VPU_IP_RESET 0x00000050u +#define VPU_HW_BTRS_MTL_VPU_IP_RESET_TRIGGER_MASK BIT_MASK(0) + +#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL 0x00000060u +#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0) +#define VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL_I3_MASK BIT_MASK(2) + +#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_OFFSET 0x00000080u +#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_SIZE 0x00000084u +#define VPU_HW_BTRS_MTL_VPU_TELEMETRY_ENABLE 0x00000088u + +#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_0 0x000000a0u +#define VPU_HW_BTRS_MTL_ATS_ERR_LOG_1 0x000000a4u +#define VPU_HW_BTRS_MTL_ATS_ERR_CLEAR 0x000000a8u + +#define VPU_HW_BTRS_MTL_UFI_ERR_LOG 0x000000b0u +#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_CQ_ID_MASK GENMASK(11, 0) +#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_AXI_ID_MASK GENMASK(19, 12) +#define VPU_HW_BTRS_MTL_UFI_ERR_LOG_OPCODE_MASK GENMASK(24, 20) + +#define VPU_HW_BTRS_MTL_UFI_ERR_CLEAR 0x000000b4u + #define VPU_HW_BTRS_LNL_INTERRUPT_STAT 0x00000000u #define VPU_HW_BTRS_LNL_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0) #define VPU_HW_BTRS_LNL_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1) @@ -79,12 +151,12 @@ #define VPU_HW_BTRS_LNL_TILE_FUSE 0x00000150u #define VPU_HW_BTRS_LNL_TILE_FUSE_VALID_MASK BIT_MASK(0) -#define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK GENMASK(6, 1) +#define VPU_HW_BTRS_LNL_TILE_FUSE_CONFIG_MASK GENMASK(7, 1) #define VPU_HW_BTRS_LNL_VPU_STATUS 0x00000154u #define VPU_HW_BTRS_LNL_VPU_STATUS_READY_MASK BIT_MASK(0) #define VPU_HW_BTRS_LNL_VPU_STATUS_IDLE_MASK BIT_MASK(1) -#define VPU_HW_BTRS_LNL_VPU_STATUS_DUP_IDLE_MASK BIT_MASK(2) +#define VPU_HW_BTRS_LNL_VPU_STATUS_DPU_IDLE_MASK BIT_MASK(2) #define VPU_HW_BTRS_LNL_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK BIT_MASK(6) #define VPU_HW_BTRS_LNL_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK BIT_MASK(7) #define VPU_HW_BTRS_LNL_VPU_STATUS_PERF_CLK_MASK BIT_MASK(11) @@ -109,4 +181,4 @@ #define VPU_HW_BTRS_LNL_FMAX_FUSE 0x00000178u #define VPU_HW_BTRS_LNL_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0) -#endif /* __IVPU_HW_BTRS_LNL_REG_H__ */ +#endif /* __IVPU_HW_BTRS_REG_H__ */ diff --git a/drivers/accel/ivpu/ivpu_hw_ip.c b/drivers/accel/ivpu/ivpu_hw_ip.c index 81f0b1f8f5a6..47f4f9e17d8a 100644 --- a/drivers/accel/ivpu/ivpu_hw_ip.c +++ b/drivers/accel/ivpu/ivpu_hw_ip.c @@ -7,62 +7,37 @@ #include "ivpu_fw.h" #include "ivpu_gem.h" #include "ivpu_hw.h" -#include "ivpu_hw_37xx_reg.h" -#include "ivpu_hw_40xx_reg.h" #include "ivpu_hw_btrs.h" #include "ivpu_hw_ip.h" +#include "ivpu_hw_ip_reg.h" #include "ivpu_hw_reg_io.h" #include "ivpu_mmu.h" #include "ivpu_pm.h" -#define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC) - #define TIM_SAFE_ENABLE 0xf1d0dead #define TIM_WATCHDOG_RESET_VALUE 0xffffffff -#define ICB_0_IRQ_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \ - (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \ - (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \ - (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \ - (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \ - (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \ - (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT))) - -#define ICB_1_IRQ_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \ - (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \ - (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT))) - -#define ICB_0_1_IRQ_MASK_37XX ((((u64)ICB_1_IRQ_MASK_37XX) << 32) | ICB_0_IRQ_MASK_37XX) - -#define ICB_0_IRQ_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \ - (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \ - (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \ - (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \ - (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \ - (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \ - (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT))) - -#define ICB_1_IRQ_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \ - (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \ - (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT))) - -#define ICB_0_1_IRQ_MASK_40XX ((((u64)ICB_1_IRQ_MASK_40XX) << 32) | ICB_0_IRQ_MASK_40XX) - -#define ITF_FIREWALL_VIOLATION_MASK_37XX ((REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \ - (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \ - (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \ - (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \ - (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \ - (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \ - (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX))) - -#define ITF_FIREWALL_VIOLATION_MASK_40XX ((REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \ - (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \ - (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \ - (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \ - (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \ - (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \ - (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX))) +#define ICB_0_IRQ_MASK ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \ + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \ + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \ + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \ + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \ + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \ + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT))) + +#define ICB_1_IRQ_MASK ((REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \ + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \ + (REG_FLD(VPU_37XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT))) + +#define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK) + +#define ITF_FIREWALL_VIOLATION_MASK ((REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \ + (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \ + (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \ + (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \ + (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \ + (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \ + (REG_FLD(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX))) static int wait_for_ip_bar(struct ivpu_device *vdev) { @@ -80,7 +55,7 @@ static void host_ss_rst_clr(struct ivpu_device *vdev) REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val); } -static int host_ss_noc_qreqn_check_37xx(struct ivpu_device *vdev, u32 exp_val) +static int host_ss_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val) { u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); @@ -90,25 +65,7 @@ static int host_ss_noc_qreqn_check_37xx(struct ivpu_device *vdev, u32 exp_val) return 0; } -static int host_ss_noc_qreqn_check_40xx(struct ivpu_device *vdev, u32 exp_val) -{ - u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); - - if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, exp_val, val)) - return -EIO; - - return 0; -} - -static int host_ss_noc_qreqn_check(struct ivpu_device *vdev, u32 exp_val) -{ - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - return host_ss_noc_qreqn_check_37xx(vdev, exp_val); - else - return host_ss_noc_qreqn_check_40xx(vdev, exp_val); -} - -static int host_ss_noc_qacceptn_check_37xx(struct ivpu_device *vdev, u32 exp_val) +static int host_ss_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) { u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN); @@ -118,25 +75,7 @@ static int host_ss_noc_qacceptn_check_37xx(struct ivpu_device *vdev, u32 exp_val return 0; } -static int host_ss_noc_qacceptn_check_40xx(struct ivpu_device *vdev, u32 exp_val) -{ - u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN); - - if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QACCEPTN, TOP_SOCMMIO, exp_val, val)) - return -EIO; - - return 0; -} - -static int host_ss_noc_qacceptn_check(struct ivpu_device *vdev, u32 exp_val) -{ - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - return host_ss_noc_qacceptn_check_37xx(vdev, exp_val); - else - return host_ss_noc_qacceptn_check_40xx(vdev, exp_val); -} - -static int host_ss_noc_qdeny_check_37xx(struct ivpu_device *vdev, u32 exp_val) +static int host_ss_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) { u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY); @@ -146,24 +85,6 @@ static int host_ss_noc_qdeny_check_37xx(struct ivpu_device *vdev, u32 exp_val) return 0; } -static int host_ss_noc_qdeny_check_40xx(struct ivpu_device *vdev, u32 exp_val) -{ - u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY); - - if (!REG_TEST_FLD_NUM(VPU_40XX_HOST_SS_NOC_QDENY, TOP_SOCMMIO, exp_val, val)) - return -EIO; - - return 0; -} - -static int host_ss_noc_qdeny_check(struct ivpu_device *vdev, u32 exp_val) -{ - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - return host_ss_noc_qdeny_check_37xx(vdev, exp_val); - else - return host_ss_noc_qdeny_check_40xx(vdev, exp_val); -} - static int top_noc_qrenqn_check_37xx(struct ivpu_device *vdev, u32 exp_val) { u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); @@ -177,9 +98,9 @@ static int top_noc_qrenqn_check_37xx(struct ivpu_device *vdev, u32 exp_val) static int top_noc_qrenqn_check_40xx(struct ivpu_device *vdev, u32 exp_val) { - u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); + u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); - if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || + if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val)) return -EIO; @@ -226,7 +147,7 @@ int ivpu_hw_ip_host_ss_configure(struct ivpu_device *vdev) return ret; } -static void idle_gen_drive_37xx(struct ivpu_device *vdev, bool enable) +static void idle_gen_drive(struct ivpu_device *vdev, bool enable) { u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN); @@ -238,75 +159,59 @@ static void idle_gen_drive_37xx(struct ivpu_device *vdev, bool enable) REGV_WR32(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, val); } -static void idle_gen_drive_40xx(struct ivpu_device *vdev, bool enable) -{ - u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN); - - if (enable) - val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); - else - val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); - - REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val); -} - void ivpu_hw_ip_idle_gen_enable(struct ivpu_device *vdev) { - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - idle_gen_drive_37xx(vdev, true); - else - idle_gen_drive_40xx(vdev, true); + idle_gen_drive(vdev, true); } void ivpu_hw_ip_idle_gen_disable(struct ivpu_device *vdev) { - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - idle_gen_drive_37xx(vdev, false); - else - idle_gen_drive_40xx(vdev, false); + idle_gen_drive(vdev, false); } static void -pwr_island_delay_set_50xx(struct ivpu_device *vdev, u32 post, u32 post1, u32 post2, u32 status) +pwr_island_delay_write(struct ivpu_device *vdev, u32 post, u32 post1, u32 post2, u32 status) { u32 val; - val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY); - val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST_DLY, post, val); + val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST_DLY, post, 0); val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST1_DLY, post1, val); val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, POST2_DLY, post2, val); REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY, val); - val = REGV_RD32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY); - val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, STATUS_DLY, status, val); + val = REG_SET_FLD_NUM(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, STATUS_DLY, status, 0); REGV_WR32(VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY, val); } -static void pwr_island_trickle_drive_37xx(struct ivpu_device *vdev, bool enable) +static void pwr_island_delay_set_50xx(struct ivpu_device *vdev) { - u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); - - if (enable) - val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); + if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_HIGH) + pwr_island_delay_write(vdev, 18, 0, 0, 46); else - val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); + pwr_island_delay_write(vdev, 0, 0, 0, 3); +} - REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); +static void pwr_island_delay_set_60xx(struct ivpu_device *vdev) +{ + if (vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_HIGH) + pwr_island_delay_write(vdev, 198, 0, 198, 0); + else + pwr_island_delay_write(vdev, 17, 0, 17, 0); } -static void pwr_island_trickle_drive_40xx(struct ivpu_device *vdev, bool enable) +static void pwr_island_trickle_drive(struct ivpu_device *vdev, bool enable) { - u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); + u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); if (enable) - val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val); + val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); else - val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, CSS_CPU, val); + val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); - REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); + REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); } -static void pwr_island_drive_37xx(struct ivpu_device *vdev, bool enable) +static void pwr_island_drive(struct ivpu_device *vdev, bool enable) { u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0); @@ -318,29 +223,11 @@ static void pwr_island_drive_37xx(struct ivpu_device *vdev, bool enable) REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val); } -static void pwr_island_drive_40xx(struct ivpu_device *vdev, bool enable) -{ - u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0); - - if (enable) - val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); - else - val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val); - - REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val); -} - static void pwr_island_enable(struct ivpu_device *vdev) { - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { - pwr_island_trickle_drive_37xx(vdev, true); - ndelay(500); - pwr_island_drive_37xx(vdev, true); - } else { - pwr_island_trickle_drive_40xx(vdev, true); - ndelay(500); - pwr_island_drive_40xx(vdev, true); - } + pwr_island_trickle_drive(vdev, true); + ndelay(500); + pwr_island_drive(vdev, true); } static int wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val) @@ -348,15 +235,11 @@ static int wait_for_pwr_island_status(struct ivpu_device *vdev, u32 exp_val) if (IVPU_WA(punit_disabled)) return 0; - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - return REGV_POLL_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0, MSS_CPU, exp_val, - PWR_ISLAND_STATUS_TIMEOUT_US); - else - return REGV_POLL_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0, CSS_CPU, exp_val, - PWR_ISLAND_STATUS_TIMEOUT_US); + return REGV_POLL_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0, MSS_CPU, exp_val, + vdev->timeout.pwr_island_status); } -static void pwr_island_isolation_drive_37xx(struct ivpu_device *vdev, bool enable) +static void pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable) { u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0); @@ -368,26 +251,6 @@ static void pwr_island_isolation_drive_37xx(struct ivpu_device *vdev, bool enabl REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val); } -static void pwr_island_isolation_drive_40xx(struct ivpu_device *vdev, bool enable) -{ - u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0); - - if (enable) - val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val); - else - val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val); - - REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val); -} - -static void pwr_island_isolation_drive(struct ivpu_device *vdev, bool enable) -{ - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - pwr_island_isolation_drive_37xx(vdev, enable); - else - pwr_island_isolation_drive_40xx(vdev, enable); -} - static void pwr_island_isolation_disable(struct ivpu_device *vdev) { pwr_island_isolation_drive(vdev, false); @@ -487,7 +350,7 @@ static void host_ss_rst_enable(struct ivpu_device *vdev) host_ss_rst_drive(vdev, true); } -static void host_ss_noc_qreqn_top_socmmio_drive_37xx(struct ivpu_device *vdev, bool enable) +static void host_ss_noc_qreqn_top_socmmio_drive(struct ivpu_device *vdev, bool enable) { u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); @@ -498,25 +361,6 @@ static void host_ss_noc_qreqn_top_socmmio_drive_37xx(struct ivpu_device *vdev, b REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val); } -static void host_ss_noc_qreqn_top_socmmio_drive_40xx(struct ivpu_device *vdev, bool enable) -{ - u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); - - if (enable) - val = REG_SET_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); - else - val = REG_CLR_FLD(VPU_40XX_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); - REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val); -} - -static void host_ss_noc_qreqn_top_socmmio_drive(struct ivpu_device *vdev, bool enable) -{ - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - host_ss_noc_qreqn_top_socmmio_drive_37xx(vdev, enable); - else - host_ss_noc_qreqn_top_socmmio_drive_40xx(vdev, enable); -} - static int host_ss_axi_drive(struct ivpu_device *vdev, bool enable) { int ret; @@ -538,17 +382,17 @@ static int host_ss_axi_drive(struct ivpu_device *vdev, bool enable) static void top_noc_qreqn_drive_40xx(struct ivpu_device *vdev, bool enable) { - u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); + u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); if (enable) { - val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); + val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val); val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); } else { - val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); + val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val); val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); } - REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val); + REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val); } static void top_noc_qreqn_drive_37xx(struct ivpu_device *vdev, bool enable) @@ -592,9 +436,9 @@ static int top_noc_qacceptn_check_37xx(struct ivpu_device *vdev, u32 exp_val) static int top_noc_qacceptn_check_40xx(struct ivpu_device *vdev, u32 exp_val) { - u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN); + u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN); - if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || + if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, HOSTIF_L2CACHE, exp_val, val)) return -EIO; @@ -622,9 +466,9 @@ static int top_noc_qdeny_check_37xx(struct ivpu_device *vdev, u32 exp_val) static int top_noc_qdeny_check_40xx(struct ivpu_device *vdev, u32 exp_val) { - u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY); + u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY); - if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || + if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, HOSTIF_L2CACHE, exp_val, val)) return -EIO; @@ -677,35 +521,19 @@ static void dpu_active_drive_37xx(struct ivpu_device *vdev, bool enable) static void pwr_island_delay_set(struct ivpu_device *vdev) { - bool high = vdev->hw->pll.profiling_freq == PLL_PROFILING_FREQ_HIGH; - u32 post, post1, post2, status; + switch (ivpu_hw_ip_gen(vdev)) { + case IVPU_HW_IP_37XX: + case IVPU_HW_IP_40XX: + return; - if (ivpu_hw_ip_gen(vdev) < IVPU_HW_IP_50XX) + case IVPU_HW_IP_50XX: + pwr_island_delay_set_50xx(vdev); return; - switch (ivpu_device_id(vdev)) { - case PCI_DEVICE_ID_WCL: - case PCI_DEVICE_ID_PTL_P: - post = high ? 18 : 0; - post1 = 0; - post2 = 0; - status = high ? 46 : 3; - break; - - case PCI_DEVICE_ID_NVL: - post = high ? 198 : 17; - post1 = 0; - post2 = high ? 198 : 17; - status = 0; - break; - - default: - dump_stack(); - ivpu_err(vdev, "Unknown device ID\n"); + case IVPU_HW_IP_60XX: + pwr_island_delay_set_60xx(vdev); return; } - - pwr_island_delay_set_50xx(vdev, post, post1, post2, status); } int ivpu_hw_ip_pwr_domain_enable(struct ivpu_device *vdev) @@ -762,7 +590,7 @@ static void ivpu_hw_ip_snoop_disable_37xx(struct ivpu_device *vdev) static void ivpu_hw_ip_snoop_disable_40xx(struct ivpu_device *vdev) { - u32 val = REGV_RD32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES); + u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES); val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, SNOOP_OVERRIDE_EN, val); val = REG_SET_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AW_SNOOP_OVERRIDE, val); @@ -772,7 +600,7 @@ static void ivpu_hw_ip_snoop_disable_40xx(struct ivpu_device *vdev) else val = REG_CLR_FLD(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, AR_SNOOP_OVERRIDE, val); - REGV_WR32(VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES, val); + REGV_WR32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES, val); } void ivpu_hw_ip_snoop_disable(struct ivpu_device *vdev) @@ -797,24 +625,29 @@ static void ivpu_hw_ip_tbu_mmu_enable_37xx(struct ivpu_device *vdev) static void ivpu_hw_ip_tbu_mmu_enable_40xx(struct ivpu_device *vdev) { - u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV); + u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV); - val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); - val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); - val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val); - val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val); - val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); - val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); + val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); + val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); + val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val); + val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val); + val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); + val = REG_SET_FLD(VPU_37XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); - REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val); + REGV_WR32(VPU_37XX_HOST_IF_TBU_MMUSSIDV, val); } void ivpu_hw_ip_tbu_mmu_enable(struct ivpu_device *vdev) { - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) + switch (ivpu_hw_ip_gen(vdev)) { + case IVPU_HW_IP_37XX: return ivpu_hw_ip_tbu_mmu_enable_37xx(vdev); - else + + case IVPU_HW_IP_40XX: + case IVPU_HW_IP_50XX: + case IVPU_HW_IP_60XX: return ivpu_hw_ip_tbu_mmu_enable_40xx(vdev); + } } static inline u64 get_entry_point_addr(struct ivpu_device *vdev) @@ -938,29 +771,22 @@ static int soc_cpu_boot_60xx(struct ivpu_device *vdev) int ivpu_hw_ip_soc_cpu_boot(struct ivpu_device *vdev) { - int ret; + ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", + ivpu_fw_is_warm_boot(vdev) ? "warm boot" : "cold boot"); switch (ivpu_hw_ip_gen(vdev)) { case IVPU_HW_IP_37XX: - ret = soc_cpu_boot_37xx(vdev); - break; + return soc_cpu_boot_37xx(vdev); case IVPU_HW_IP_40XX: case IVPU_HW_IP_50XX: - ret = soc_cpu_boot_40xx(vdev); - break; + return soc_cpu_boot_40xx(vdev); - default: - ret = soc_cpu_boot_60xx(vdev); + case IVPU_HW_IP_60XX: + return soc_cpu_boot_60xx(vdev); } - if (ret) - return ret; - - ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", - ivpu_fw_is_warm_boot(vdev) ? "warm boot" : "cold boot"); - - return 0; + return -EINVAL; } static void wdt_disable_37xx(struct ivpu_device *vdev) @@ -1004,55 +830,30 @@ void ivpu_hw_ip_wdt_disable(struct ivpu_device *vdev) return wdt_disable_40xx(vdev); } -static u32 ipc_rx_count_get_37xx(struct ivpu_device *vdev) +u32 ivpu_hw_ip_ipc_rx_count_get(struct ivpu_device *vdev) { u32 count = readl(vdev->regv + VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT); return REG_GET_FLD(VPU_37XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count); } -static u32 ipc_rx_count_get_40xx(struct ivpu_device *vdev) -{ - u32 count = readl(vdev->regv + VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT); - - return REG_GET_FLD(VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT, FILL_LEVEL, count); -} - -u32 ivpu_hw_ip_ipc_rx_count_get(struct ivpu_device *vdev) -{ - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - return ipc_rx_count_get_37xx(vdev); - else - return ipc_rx_count_get_40xx(vdev); -} - void ivpu_hw_ip_irq_enable(struct ivpu_device *vdev) { - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { - REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK_37XX); - REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK_37XX); - } else { - REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK_40XX); - REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK_40XX); - } + REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK); + REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK); } void ivpu_hw_ip_irq_disable(struct ivpu_device *vdev) { - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) { - REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, 0x0ull); - REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0); - } else { - REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, 0x0ull); - REGV_WR32(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, 0x0ul); - } + REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, 0x0ull); + REGV_WR32(VPU_37XX_HOST_SS_FW_SOC_IRQ_EN, 0x0); } -static void diagnose_failure_37xx(struct ivpu_device *vdev) +void ivpu_hw_ip_diagnose_failure(struct ivpu_device *vdev) { - u32 reg = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_37XX; + u32 reg = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK; - if (ipc_rx_count_get_37xx(vdev)) + if (ivpu_hw_ip_ipc_rx_count_get(vdev)) ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ"); if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, reg)) @@ -1065,37 +866,9 @@ static void diagnose_failure_37xx(struct ivpu_device *vdev) ivpu_err(vdev, "NOC Firewall irq detected\n"); } -static void diagnose_failure_40xx(struct ivpu_device *vdev) -{ - u32 reg = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_40XX; - - if (ipc_rx_count_get_40xx(vdev)) - ivpu_err(vdev, "IPC FIFO queue not empty, missed IPC IRQ"); - - if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, reg)) - ivpu_err(vdev, "WDT MSS timeout detected\n"); - - if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, reg)) - ivpu_err(vdev, "WDT NCE timeout detected\n"); - - if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, reg)) - ivpu_err(vdev, "NOC Firewall irq detected\n"); -} - -void ivpu_hw_ip_diagnose_failure(struct ivpu_device *vdev) -{ - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - diagnose_failure_37xx(vdev); - else - diagnose_failure_40xx(vdev); -} - void ivpu_hw_ip_irq_clear(struct ivpu_device *vdev) { - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - REGV_WR64(VPU_37XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK_37XX); - else - REGV_WR64(VPU_40XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK_40XX); + REGV_WR64(VPU_37XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK); } static void irq_wdt_nce_handler(struct ivpu_device *vdev) @@ -1118,9 +891,9 @@ static void irq_noc_firewall_handler(struct ivpu_device *vdev) } /* Handler for IRQs from NPU core */ -bool ivpu_hw_ip_irq_handler_37xx(struct ivpu_device *vdev, int irq) +bool ivpu_hw_ip_irq_handler(struct ivpu_device *vdev, int irq) { - u32 status = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_37XX; + u32 status = REGV_RD32(VPU_37XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK; if (!status) return false; @@ -1151,40 +924,6 @@ bool ivpu_hw_ip_irq_handler_37xx(struct ivpu_device *vdev, int irq) return true; } -/* Handler for IRQs from NPU core */ -bool ivpu_hw_ip_irq_handler_40xx(struct ivpu_device *vdev, int irq) -{ - u32 status = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK_40XX; - - if (!status) - return false; - - REGV_WR32(VPU_40XX_HOST_SS_ICB_CLEAR_0, status); - - if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status)) - ivpu_mmu_irq_evtq_handler(vdev); - - if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status)) - ivpu_ipc_irq_handler(vdev); - - if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status)) - ivpu_dbg(vdev, IRQ, "MMU sync complete\n"); - - if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status)) - ivpu_mmu_irq_gerr_handler(vdev); - - if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT, status)) - irq_wdt_mss_handler(vdev); - - if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT, status)) - irq_wdt_nce_handler(vdev); - - if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status)) - irq_noc_firewall_handler(vdev); - - return true; -} - static void db_set_37xx(struct ivpu_device *vdev, u32 db_id) { u32 reg_stride = VPU_37XX_CPU_SS_DOORBELL_1 - VPU_37XX_CPU_SS_DOORBELL_0; @@ -1211,10 +950,7 @@ void ivpu_hw_ip_db_set(struct ivpu_device *vdev, u32 db_id) u32 ivpu_hw_ip_ipc_rx_addr_get(struct ivpu_device *vdev) { - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - return REGV_RD32(VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM); - else - return REGV_RD32(VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM); + return REGV_RD32(VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM); } void ivpu_hw_ip_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr) diff --git a/drivers/accel/ivpu/ivpu_hw_ip.h b/drivers/accel/ivpu/ivpu_hw_ip.h index dbbcdd10a5f8..59ef904c08da 100644 --- a/drivers/accel/ivpu/ivpu_hw_ip.h +++ b/drivers/accel/ivpu/ivpu_hw_ip.h @@ -22,8 +22,7 @@ void ivpu_hw_ip_wdt_disable(struct ivpu_device *vdev); void ivpu_hw_ip_diagnose_failure(struct ivpu_device *vdev); u32 ivpu_hw_ip_ipc_rx_count_get(struct ivpu_device *vdev); void ivpu_hw_ip_irq_clear(struct ivpu_device *vdev); -bool ivpu_hw_ip_irq_handler_37xx(struct ivpu_device *vdev, int irq); -bool ivpu_hw_ip_irq_handler_40xx(struct ivpu_device *vdev, int irq); +bool ivpu_hw_ip_irq_handler(struct ivpu_device *vdev, int irq); void ivpu_hw_ip_db_set(struct ivpu_device *vdev, u32 db_id); u32 ivpu_hw_ip_ipc_rx_addr_get(struct ivpu_device *vdev); void ivpu_hw_ip_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr); diff --git a/drivers/accel/ivpu/ivpu_hw_37xx_reg.h b/drivers/accel/ivpu/ivpu_hw_ip_reg.h index cf5e2f01049c..126df1012f23 100644 --- a/drivers/accel/ivpu/ivpu_hw_37xx_reg.h +++ b/drivers/accel/ivpu/ivpu_hw_ip_reg.h @@ -1,18 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (C) 2020-2023 Intel Corporation + * Copyright (C) 2020-2026 Intel Corporation */ -#ifndef __IVPU_HW_37XX_REG_H__ -#define __IVPU_HW_37XX_REG_H__ +#ifndef __IVPU_HW_IP_REG_H__ +#define __IVPU_HW_IP_REG_H__ #include <linux/bits.h> +#define VPU_40XX_HOST_SS_CPR_CLK_EN 0x00000080u +#define VPU_40XX_HOST_SS_CPR_CLK_EN_TOP_NOC_MASK BIT_MASK(1) +#define VPU_40XX_HOST_SS_CPR_CLK_EN_DSS_MAS_MASK BIT_MASK(10) +#define VPU_40XX_HOST_SS_CPR_CLK_EN_CSS_MAS_MASK BIT_MASK(11) + #define VPU_37XX_HOST_SS_CPR_CLK_SET 0x00000084u #define VPU_37XX_HOST_SS_CPR_CLK_SET_TOP_NOC_MASK BIT_MASK(1) #define VPU_37XX_HOST_SS_CPR_CLK_SET_DSS_MAS_MASK BIT_MASK(10) #define VPU_37XX_HOST_SS_CPR_CLK_SET_MSS_MAS_MASK BIT_MASK(11) +#define VPU_40XX_HOST_SS_CPR_RST_EN 0x00000090u +#define VPU_40XX_HOST_SS_CPR_RST_EN_TOP_NOC_MASK BIT_MASK(1) +#define VPU_40XX_HOST_SS_CPR_RST_EN_DSS_MAS_MASK BIT_MASK(10) +#define VPU_40XX_HOST_SS_CPR_RST_EN_CSS_MAS_MASK BIT_MASK(11) + #define VPU_37XX_HOST_SS_CPR_RST_SET 0x00000094u #define VPU_37XX_HOST_SS_CPR_RST_SET_TOP_NOC_MASK BIT_MASK(1) #define VPU_37XX_HOST_SS_CPR_RST_SET_DSS_MAS_MASK BIT_MASK(10) @@ -29,6 +39,8 @@ #define VPU_37XX_HOST_SS_HW_VERSION_SOC_NUMBER_MASK GENMASK(15, 8) #define VPU_37XX_HOST_SS_HW_VERSION_VPU_GENERATION_MASK GENMASK(23, 16) +#define VPU_40XX_HOST_SS_SW_VERSION 0x0000010cu + #define VPU_37XX_HOST_SS_GEN_CTRL 0x00000118u #define VPU_37XX_HOST_SS_GEN_CTRL_PS_MASK GENMASK(31, 29) @@ -44,14 +56,17 @@ #define VPU_37XX_TOP_NOC_QREQN 0x00000160u #define VPU_37XX_TOP_NOC_QREQN_CPU_CTRL_MASK BIT_MASK(0) #define VPU_37XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK BIT_MASK(1) +#define VPU_40XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK BIT_MASK(2) #define VPU_37XX_TOP_NOC_QACCEPTN 0x00000164u #define VPU_37XX_TOP_NOC_QACCEPTN_CPU_CTRL_MASK BIT_MASK(0) #define VPU_37XX_TOP_NOC_QACCEPTN_HOSTIF_L2CACHE_MASK BIT_MASK(1) +#define VPU_40XX_TOP_NOC_QACCEPTN_HOSTIF_L2CACHE_MASK BIT_MASK(2) #define VPU_37XX_TOP_NOC_QDENY 0x00000168u #define VPU_37XX_TOP_NOC_QDENY_CPU_CTRL_MASK BIT_MASK(0) #define VPU_37XX_TOP_NOC_QDENY_HOSTIF_L2CACHE_MASK BIT_MASK(1) +#define VPU_40XX_TOP_NOC_QDENY_HOSTIF_L2CACHE_MASK BIT_MASK(2) #define VPU_37XX_HOST_SS_FW_SOC_IRQ_EN 0x00000170u #define VPU_37XX_HOST_SS_FW_SOC_IRQ_EN_CSS_ROM_CMX_MASK BIT_MASK(0) @@ -83,6 +98,7 @@ #define VPU_37XX_HOST_SS_ICB_CLEAR_0 0x00010220u #define VPU_37XX_HOST_SS_ICB_CLEAR_1 0x00010224u #define VPU_37XX_HOST_SS_ICB_ENABLE_0 0x00010240u +#define VPU_40XX_HOST_SS_ICB_ENABLE_1 0x00010244u #define VPU_37XX_HOST_SS_TIM_IPC_FIFO_ATM 0x000200f4u @@ -104,12 +120,29 @@ #define VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0 0x0003002cu #define VPU_37XX_HOST_SS_AON_PWR_ISLAND_STATUS0_MSS_CPU_MASK BIT_MASK(3) +#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY 0x00030068u +#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST_DLY_MASK GENMASK(7, 0) +#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST1_DLY_MASK GENMASK(15, 8) +#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_EN_POST_DLY_POST2_DLY_MASK GENMASK(23, 16) + +#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY 0x0003006cu +#define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK GENMASK(7, 0) + #define VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN 0x00030200u #define VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN_EN_MASK BIT_MASK(0) +#define VPU_40XX_HOST_SS_AON_VPU_IDLE_GEN_HW_PG_EN_MASK BIT_MASK(1) #define VPU_37XX_HOST_SS_AON_DPU_ACTIVE 0x00030204u #define VPU_37XX_HOST_SS_AON_DPU_ACTIVE_DPU_ACTIVE_MASK BIT_MASK(0) +#define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE 0x00030210u +#define VPU_50XX_HOST_SS_AON_FABRIC_REQ_OVERRIDE_REQ_OVERRIDE_MASK BIT_MASK(0) + +#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO 0x00040040u +#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_DONE_MASK BIT_MASK(0) +#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IOSF_RS_ID_MASK GENMASK(2, 1) +#define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK GENMASK(31, 3) + #define VPU_37XX_HOST_SS_LOADING_ADDRESS_LO 0x00041040u #define VPU_37XX_HOST_SS_LOADING_ADDRESS_LO_DONE_MASK BIT_MASK(0) #define VPU_37XX_HOST_SS_LOADING_ADDRESS_LO_IOSF_RS_ID_MASK GENMASK(2, 1) @@ -126,6 +159,9 @@ #define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_NOSNOOP_OVERRIDE_EN_MASK BIT_MASK(3) #define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_AW_NOSNOOP_OVERRIDE_MASK BIT_MASK(4) #define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_AR_NOSNOOP_OVERRIDE_MASK BIT_MASK(5) +#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_SNOOP_OVERRIDE_EN_MASK BIT_MASK(3) +#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AW_SNOOP_OVERRIDE_MASK BIT_MASK(4) +#define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AR_SNOOP_OVERRIDE_MASK BIT_MASK(5) #define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AW_CONTEXT_FLAG_MASK GENMASK(10, 6) #define VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AR_CONTEXT_FLAG_MASK GENMASK(15, 11) @@ -141,6 +177,17 @@ #define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU4_AWMMUSSIDV_MASK BIT_MASK(8) #define VPU_37XX_HOST_IF_TBU_MMUSSIDV_TBU4_ARMMUSSIDV_MASK BIT_MASK(9) +#define VPU_40XX_CPU_SS_CPR_NOC_QREQN 0x01010030u +#define VPU_40XX_CPU_SS_CPR_NOC_QREQN_TOP_MMIO_MASK BIT_MASK(0) + +#define VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN 0x01010034u +#define VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN_TOP_MMIO_MASK BIT_MASK(0) + +#define VPU_40XX_CPU_SS_CPR_NOC_QDENY 0x01010038u +#define VPU_40XX_CPU_SS_CPR_NOC_QDENY_TOP_MMIO_MASK BIT_MASK(0) + +#define VPU_40XX_CPU_SS_TIM_PERF_EXT_FREE_CNT 0x01029008u + #define VPU_37XX_CPU_SS_DSU_LEON_RT_BASE 0x04000000u #define VPU_37XX_CPU_SS_DSU_LEON_RT_DSU_CTRL 0x04000000u #define VPU_37XX_CPU_SS_DSU_LEON_RT_PC_REG 0x04400010u @@ -161,18 +208,32 @@ #define VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC_IRQI_RSTVEC_MASK GENMASK(31, 4) #define VPU_37XX_CPU_SS_TIM_WATCHDOG 0x0602009cu +#define VPU_40XX_CPU_SS_TIM_WATCHDOG 0x0102009cu + #define VPU_37XX_CPU_SS_TIM_WDOG_EN 0x060200a4u +#define VPU_40XX_CPU_SS_TIM_WDOG_EN 0x010200a4u + #define VPU_37XX_CPU_SS_TIM_SAFE 0x060200a8u +#define VPU_40XX_CPU_SS_TIM_SAFE 0x010200a8u + #define VPU_37XX_CPU_SS_TIM_IPC_FIFO 0x060200f0u +#define VPU_40XX_CPU_SS_TIM_IPC_FIFO 0x010200f0u #define VPU_37XX_CPU_SS_TIM_GEN_CONFIG 0x06021008u #define VPU_37XX_CPU_SS_TIM_GEN_CONFIG_WDOG_TO_INT_CLR_MASK BIT_MASK(9) +#define VPU_40XX_CPU_SS_TIM_GEN_CONFIG 0x01021008u +#define VPU_40XX_CPU_SS_TIM_GEN_CONFIG_WDOG_TO_INT_CLR_MASK BIT_MASK(9) + #define VPU_37XX_CPU_SS_TIM_PERF_FREE_CNT 0x06029000u #define VPU_37XX_CPU_SS_DOORBELL_0 0x06300000u #define VPU_37XX_CPU_SS_DOORBELL_0_SET_MASK BIT_MASK(0) +#define VPU_40XX_CPU_SS_DOORBELL_0 0x01300000u +#define VPU_40XX_CPU_SS_DOORBELL_0_SET_MASK BIT_MASK(0) + #define VPU_37XX_CPU_SS_DOORBELL_1 0x06301000u +#define VPU_40XX_CPU_SS_DOORBELL_1 0x01301000u -#endif /* __IVPU_HW_37XX_REG_H__ */ +#endif /* __IVPU_HW_IP_REG_H__ */ diff --git a/drivers/accel/ivpu/ivpu_ipc.c b/drivers/accel/ivpu/ivpu_ipc.c index 8e960293b77a..79d34f9b1f07 100644 --- a/drivers/accel/ivpu/ivpu_ipc.c +++ b/drivers/accel/ivpu/ivpu_ipc.c @@ -509,7 +509,7 @@ int ivpu_ipc_init(struct ivpu_device *vdev) if (!ipc->mem_rx) { ivpu_err(vdev, "Failed to allocate mem_rx\n"); ret = -ENOMEM; - goto err_free_tx; + goto err_free_bo; } ipc->mm_tx = devm_gen_pool_create(vdev->drm.dev, __ffs(IVPU_IPC_ALIGNMENT), @@ -517,13 +517,13 @@ int ivpu_ipc_init(struct ivpu_device *vdev) if (IS_ERR(ipc->mm_tx)) { ret = PTR_ERR(ipc->mm_tx); ivpu_err(vdev, "Failed to create gen pool, %pe\n", ipc->mm_tx); - goto err_free_rx; + goto err_free_bo; } ret = gen_pool_add(ipc->mm_tx, ipc->mem_tx->vpu_addr, ivpu_bo_size(ipc->mem_tx), -1); if (ret) { ivpu_err(vdev, "gen_pool_add failed, ret %d\n", ret); - goto err_free_rx; + goto err_free_bo; } spin_lock_init(&ipc->cons_lock); @@ -532,14 +532,13 @@ int ivpu_ipc_init(struct ivpu_device *vdev) ret = drmm_mutex_init(&vdev->drm, &ipc->lock); if (ret) { ivpu_err(vdev, "Failed to initialize ipc->lock, ret %d\n", ret); - goto err_free_rx; + goto err_free_bo; } ivpu_ipc_reset(vdev); return 0; -err_free_rx: +err_free_bo: ivpu_bo_free(ipc->mem_rx); -err_free_tx: ivpu_bo_free(ipc->mem_tx); err_destroy_cache: kmem_cache_destroy(ipc->rx_msg_cache); diff --git a/drivers/accel/ivpu/ivpu_job.c b/drivers/accel/ivpu/ivpu_job.c index 4689b8ab519d..b9b6efea43e8 100644 --- a/drivers/accel/ivpu/ivpu_job.c +++ b/drivers/accel/ivpu/ivpu_job.c @@ -64,10 +64,8 @@ err_free_primary: static void ivpu_preemption_buffers_free(struct ivpu_device *vdev, struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq) { - if (cmdq->primary_preempt_buf) - ivpu_bo_free(cmdq->primary_preempt_buf); - if (cmdq->secondary_preempt_buf) - ivpu_bo_free(cmdq->secondary_preempt_buf); + ivpu_bo_free(cmdq->primary_preempt_buf); + ivpu_bo_free(cmdq->secondary_preempt_buf); } static int ivpu_preemption_job_init(struct ivpu_device *vdev, struct ivpu_file_priv *file_priv, @@ -323,6 +321,11 @@ static inline u8 ivpu_job_to_jsm_priority(u8 priority) return priority - 1; } +static inline u8 ivpu_jsm_to_job_priority(u8 priority) +{ + return priority + 1; +} + static void ivpu_cmdq_destroy(struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq) { lockdep_assert_held(&file_priv->lock); @@ -1126,6 +1129,86 @@ int ivpu_cmdq_destroy_ioctl(struct drm_device *dev, void *data, struct drm_file return ret; } +static int ivpu_cmdq_priority_args_check(struct ivpu_device *vdev, u32 cmdq_id, u64 priority) +{ + if (!ivpu_is_capable(vdev, DRM_IVPU_CAP_CMDQ_SET_PRIORITY)) { + ivpu_dbg(vdev, IOCTL, "Command queue priority not supported\n"); + return -ENODEV; + } + + if (cmdq_id < IVPU_CMDQ_MIN_ID || cmdq_id > IVPU_CMDQ_MAX_ID) { + ivpu_dbg(vdev, IOCTL, "Invalid command queue ID %u\n", cmdq_id); + return -EINVAL; + } + + if (priority > DRM_IVPU_JOB_PRIORITY_REALTIME) + return -EINVAL; + + return 0; +} + +int ivpu_cmdq_get_priority(struct ivpu_file_priv *file_priv, u32 cmdq_id, u64 *priority) +{ + struct ivpu_device *vdev = file_priv->vdev; + struct ivpu_cmdq *cmdq; + int ret; + + ret = ivpu_cmdq_priority_args_check(vdev, cmdq_id, DRM_IVPU_JOB_PRIORITY_NORMAL); + if (ret) + return ret; + + guard(mutex)(&file_priv->lock); + + cmdq = ivpu_cmdq_acquire(file_priv, cmdq_id); + if (!cmdq || cmdq->is_legacy) + return -EINVAL; + + *priority = ivpu_jsm_to_job_priority(cmdq->priority); + return 0; +} + +int ivpu_cmdq_set_priority(struct ivpu_file_priv *file_priv, u32 cmdq_id, u64 priority) +{ + struct ivpu_device *vdev = file_priv->vdev; + struct ivpu_cmdq *cmdq; + u8 jsm_priority; + int ret = 0; + + ret = ivpu_cmdq_priority_args_check(vdev, cmdq_id, priority); + if (ret) + return ret; + + ret = ivpu_rpm_get(vdev); + if (ret < 0) + return ret; + + mutex_lock(&file_priv->lock); + + cmdq = ivpu_cmdq_acquire(file_priv, cmdq_id); + if (!cmdq || cmdq->is_legacy) { + ret = -EINVAL; + goto out; + } + + jsm_priority = ivpu_job_to_jsm_priority(priority); + if (cmdq->priority == jsm_priority) + goto out; + + if (cmdq->db_id) { + ret = ivpu_jsm_hws_set_context_sched_properties(vdev, file_priv->ctx.id, cmdq_id, + jsm_priority); + if (ret) + goto out; + } + + cmdq->priority = jsm_priority; + +out: + mutex_unlock(&file_priv->lock); + ivpu_rpm_put(vdev); + return ret; +} + static void ivpu_job_done_callback(struct ivpu_device *vdev, struct ivpu_ipc_hdr *ipc_hdr, struct vpu_jsm_msg *jsm_msg) @@ -1215,9 +1298,12 @@ void ivpu_context_abort_work_fn(struct work_struct *work) unsigned long ctx_id; unsigned long id; - if (drm_WARN_ON(&vdev->drm, pm_runtime_get_if_active(vdev->drm.dev) <= 0)) + if (!down_read_trylock(&vdev->pm->reset_lock)) return; + if (drm_WARN_ON(&vdev->drm, pm_runtime_get_if_active(vdev->drm.dev) <= 0)) + goto unlock; + if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) if (reset_engine_and_mark_faulty_contexts(vdev)) goto runtime_put; @@ -1258,4 +1344,6 @@ void ivpu_context_abort_work_fn(struct work_struct *work) runtime_put: pm_runtime_put_autosuspend(vdev->drm.dev); +unlock: + up_read(&vdev->pm->reset_lock); } diff --git a/drivers/accel/ivpu/ivpu_job.h b/drivers/accel/ivpu/ivpu_job.h index d8dbce82447a..6e32fea1eb62 100644 --- a/drivers/accel/ivpu/ivpu_job.h +++ b/drivers/accel/ivpu/ivpu_job.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (C) 2020-2025 Intel Corporation + * Copyright (C) 2020-2026 Intel Corporation */ #ifndef __IVPU_JOB_H__ @@ -81,6 +81,9 @@ int ivpu_cmdq_create_ioctl(struct drm_device *dev, void *data, struct drm_file * int ivpu_cmdq_destroy_ioctl(struct drm_device *dev, void *data, struct drm_file *file); int ivpu_cmdq_submit_ioctl(struct drm_device *dev, void *data, struct drm_file *file); +int ivpu_cmdq_get_priority(struct ivpu_file_priv *file_priv, u32 cmdq_id, u64 *priority); +int ivpu_cmdq_set_priority(struct ivpu_file_priv *file_priv, u32 cmdq_id, u64 priority); + void ivpu_context_abort_locked(struct ivpu_file_priv *file_priv); void ivpu_cmdq_release_all_locked(struct ivpu_file_priv *file_priv); diff --git a/drivers/accel/ivpu/ivpu_mmu.c b/drivers/accel/ivpu/ivpu_mmu.c index b2025274f91d..c846499d96ce 100644 --- a/drivers/accel/ivpu/ivpu_mmu.c +++ b/drivers/accel/ivpu/ivpu_mmu.c @@ -220,9 +220,6 @@ #define IVPU_MMU_STE_1_S1DSS GENMASK_ULL(1, 0) #define IVPU_MMU_STE_1_S1DSS_TERMINATE 0x0 -#define IVPU_MMU_REG_TIMEOUT_US (10 * USEC_PER_MSEC) -#define IVPU_MMU_QUEUE_TIMEOUT_US (100 * USEC_PER_MSEC) - #define IVPU_MMU_GERROR_ERR_MASK ((REG_FLD(IVPU_MMU_REG_GERROR, CMDQ)) | \ (REG_FLD(IVPU_MMU_REG_GERROR, EVTQ_ABT)) | \ (REG_FLD(IVPU_MMU_REG_GERROR, PRIQ_ABT)) | \ @@ -438,14 +435,14 @@ static int ivpu_mmu_reg_write_cr0(struct ivpu_device *vdev, u32 val) { REGV_WR32(IVPU_MMU_REG_CR0, val); - return REGV_POLL_FLD(IVPU_MMU_REG_CR0ACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US); + return REGV_POLL_FLD(IVPU_MMU_REG_CR0ACK, VAL, val, vdev->timeout.mmu_reg); } static int ivpu_mmu_reg_write_irq_ctrl(struct ivpu_device *vdev, u32 val) { REGV_WR32(IVPU_MMU_REG_IRQ_CTRL, val); - return REGV_POLL_FLD(IVPU_MMU_REG_IRQ_CTRLACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US); + return REGV_POLL_FLD(IVPU_MMU_REG_IRQ_CTRLACK, VAL, val, vdev->timeout.mmu_reg); } static int ivpu_mmu_irqs_setup(struct ivpu_device *vdev) @@ -465,8 +462,7 @@ static int ivpu_mmu_cmdq_wait_for_cons(struct ivpu_device *vdev) struct ivpu_mmu_queue *cmdq = &vdev->mmu->cmdq; int ret; - ret = REGV_POLL_FLD(IVPU_MMU_REG_CMDQ_CONS, VAL, cmdq->prod, - IVPU_MMU_QUEUE_TIMEOUT_US); + ret = REGV_POLL_FLD(IVPU_MMU_REG_CMDQ_CONS, VAL, cmdq->prod, vdev->timeout.mmu_queue); if (ret) return ret; @@ -880,7 +876,7 @@ static int ivpu_mmu_evtq_set(struct ivpu_device *vdev, bool enable) val = REG_CLR_FLD(IVPU_MMU_REG_CR0, EVTQEN, val); REGV_WR32(IVPU_MMU_REG_CR0, val); - return REGV_POLL_FLD(IVPU_MMU_REG_CR0ACK, VAL, val, IVPU_MMU_REG_TIMEOUT_US); + return REGV_POLL_FLD(IVPU_MMU_REG_CR0ACK, VAL, val, vdev->timeout.mmu_reg); } static int ivpu_mmu_evtq_enable(struct ivpu_device *vdev) diff --git a/drivers/accel/ivpu/ivpu_ms.c b/drivers/accel/ivpu/ivpu_ms.c index cd176e77b9a0..489ab51d3341 100644 --- a/drivers/accel/ivpu/ivpu_ms.c +++ b/drivers/accel/ivpu/ivpu_ms.c @@ -69,7 +69,7 @@ int ivpu_ms_start_ioctl(struct drm_device *dev, void *data, struct drm_file *fil ret = ivpu_jsm_metric_streamer_info(vdev, ms->mask, 0, 0, &sample_size, NULL); if (ret) - goto err_free_ms; + goto err_free; buf_size = PAGE_ALIGN((u64)args->read_period_samples * sample_size * MS_READ_PERIOD_MULTIPLIER * MS_NUM_BUFFERS); @@ -77,14 +77,14 @@ int ivpu_ms_start_ioctl(struct drm_device *dev, void *data, struct drm_file *fil ivpu_dbg(vdev, IOCTL, "Requested MS buffer size %llu exceeds range size %llu\n", buf_size, ivpu_hw_range_size(&vdev->hw->ranges.global)); ret = -EINVAL; - goto err_free_ms; + goto err_free; } ms->bo = ivpu_bo_create_global(vdev, buf_size, DRM_IVPU_BO_CACHED | DRM_IVPU_BO_MAPPABLE); if (!ms->bo) { ivpu_dbg(vdev, IOCTL, "Failed to allocate MS buffer (size %llu)\n", buf_size); ret = -ENOMEM; - goto err_free_ms; + goto err_free; } ms->buff_size = ivpu_bo_size(ms->bo) / MS_NUM_BUFFERS; @@ -96,16 +96,15 @@ int ivpu_ms_start_ioctl(struct drm_device *dev, void *data, struct drm_file *fil ret = ivpu_jsm_metric_streamer_start(vdev, ms->mask, args->sampling_period_ns, ms->active_buff_vpu_addr, ms->buff_size); if (ret) - goto err_free_bo; + goto err_free; args->sample_size = sample_size; args->max_data_size = ivpu_bo_size(ms->bo); list_add_tail(&ms->ms_instance_node, &file_priv->ms_instance_list); goto unlock; -err_free_bo: +err_free: ivpu_bo_free(ms->bo); -err_free_ms: kfree(ms); unlock: mutex_unlock(&file_priv->ms_lock); @@ -322,10 +321,8 @@ void ivpu_ms_cleanup(struct ivpu_file_priv *file_priv) mutex_lock(&file_priv->ms_lock); - if (file_priv->ms_info_bo) { - ivpu_bo_free(file_priv->ms_info_bo); - file_priv->ms_info_bo = NULL; - } + ivpu_bo_free(file_priv->ms_info_bo); + file_priv->ms_info_bo = NULL; list_for_each_entry_safe(ms, tmp, &file_priv->ms_instance_list, ms_instance_node) free_instance(file_priv, ms); diff --git a/drivers/accel/ivpu/ivpu_pm.c b/drivers/accel/ivpu/ivpu_pm.c index de0becbfdffb..aa813262253e 100644 --- a/drivers/accel/ivpu/ivpu_pm.c +++ b/drivers/accel/ivpu/ivpu_pm.c @@ -46,7 +46,6 @@ static void ivpu_pm_prepare_cold_boot(struct ivpu_device *vdev) ivpu_cmdq_reset_all_contexts(vdev); ivpu_ipc_reset(vdev); ivpu_fw_log_reset(vdev); - ivpu_fw_load(vdev); fw->last_heartbeat = 0; ivpu_dbg(vdev, FW_BOOT, "Cold boot entry point 0x%llx", vdev->fw->cold_boot_entry_point); |