Architectures that select this option can run floating-point code in

the kernel, as described in Documentation/core-api/floating-point.rst.

source "kernel/gcov/Kconfig"

source "scripts/gcc-plugins/Kconfig"

if (tty->count == 1) {

port->tty = NULL;

}

spin_unlock_irqrestore(&port->lock, flags);

static int __init

srmcons_init(void)

{

timer_setup(&srmcons_singleton.timer, srmcons_receive_chars, 0);

}

device_initcall(srmcons_init);

/*

* The console driver

*/

}

#endif

static const pgprot_t protection_map[16] = {

[VM_NONE] = _PAGE_P(_PAGE_FOE | _PAGE_FOW |

_PAGE_FOR),

* Needed for primary domain lookup to succeed

* This is a primary irqchip, and can never have a parent

*/

#ifdef CONFIG_SMP

irq_create_mapping(root_domain, IPI_IRQ);

* Needed for primary domain lookup to succeed

* This is a primary irqchip, and can never have a parent

*/

return 0;

}

*/

max_zone_pfn[ZONE_HIGHMEM] = max_high_pfn;

arch_pfn_offset = min(min_low_pfn, min_high_pfn);

kmap_init();

#endif /* CONFIG_HIGHMEM */

free_area_init(max_zone_pfn);

}

{

#ifdef CONFIG_HIGHMEM

memblock_phys_free(high_mem_start, high_mem_sz);

#endif

BUILD_BUG_ON((PTRS_PER_PGD * sizeof(pgd_t)) > PAGE_SIZE);

BUILD_BUG_ON((PTRS_PER_PUD * sizeof(pud_t)) > PAGE_SIZE);

return (void __iomem *)(u32)paddr;

return ioremap_prot(paddr, size,

}

EXPORT_SYMBOL(ioremap);

* might need finer access control (R/W/X)

*/

void __iomem *ioremap_prot(phys_addr_t paddr, size_t size,

{

/* force uncached */

return generic_ioremap_prot(paddr, size, pgprot_noncached(prot));

}

select HAVE_KERNEL_XZ

select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M

select HAVE_KRETPROBES if HAVE_KPROBES

select HAVE_MOD_ARCH_SPECIFIC

select HAVE_NMI

select HAVE_OPTPROBES if !THUMB2_KERNEL

select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE

select HAVE_REGS_AND_STACK_ACCESS_API

select HAVE_RSEQ

select HAVE_STACKPROTECTOR

select HAVE_SYSCALL_TRACEPOINTS

select HAVE_UID16

KBUILD_CPPFLAGS +=$(cpp-y)

KBUILD_CFLAGS +=$(CFLAGS_ABI) $(CFLAGS_ISA) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm

KBUILD_AFLAGS +=$(CFLAGS_ABI) $(AFLAGS_ISA) -Wa,$(arch-y) $(tune-y) -include asm/unified.h -msoft-float

CHECKFLAGS += -D__arm__

CONFIG_CRYPTO_DEV_ATMEL_AES=y

CONFIG_CRYPTO_DEV_ATMEL_TDES=y

CONFIG_CRYPTO_DEV_ATMEL_SHA=y

CONFIG_FONTS=y

CONFIG_FONT_8x8=y

CONFIG_FONT_ACORN_8x8=y

CONFIG_NLS_DEFAULT="cp437"

CONFIG_NLS_CODEPAGE_437=y

CONFIG_NLS_ISO8859_1=y

CONFIG_FONTS=y

CONFIG_FONT_MINI_4x6=y

# CONFIG_DEBUG_BUGVERBOSE is not set

CONFIG_NLS_ISO8859_1=y

CONFIG_NLS_UTF8=m

# CONFIG_CRYPTO_HW is not set

CONFIG_DMA_CMA=y

CONFIG_DEBUG_FS=y

CONFIG_DEBUG_RT_MUTEXES=y

CONFIG_CRYPTO_LZO=y

# CONFIG_CRYPTO_ANSI_CPRNG is not set

CONFIG_CRYPTO_DEV_MARVELL_CESA=y

CONFIG_PRINTK_TIME=y

# CONFIG_DEBUG_BUGVERBOSE is not set

CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y

CONFIG_CRYPTO_CHACHA20_NEON=m

CONFIG_CRYPTO_DEV_EXYNOS_RNG=y

CONFIG_CRYPTO_DEV_S5P=y

CONFIG_DMA_CMA=y

CONFIG_CMA_SIZE_MBYTES=96

CONFIG_FONTS=y

CONFIG_CRYPTO_DEV_FSL_CAAM=y

CONFIG_CRYPTO_DEV_SAHARA=y

CONFIG_CRYPTO_DEV_MXS_DCP=y

CONFIG_CMA_SIZE_MBYTES=64

CONFIG_FONTS=y

CONFIG_FONT_8x8=y

# CONFIG_INOTIFY_USER is not set

CONFIG_JFFS2_FS=y

# CONFIG_NETWORK_FILESYSTEMS is not set

CONFIG_PRINTK_TIME=y

# CONFIG_ENABLE_MUST_CHECK is not set

# CONFIG_DEBUG_BUGVERBOSE is not set

CONFIG_NLS_UTF8=y

CONFIG_CRYPTO_ANSI_CPRNG=y

# CONFIG_CRYPTO_HW is not set

CONFIG_PRINTK_TIME=y

CONFIG_DYNAMIC_DEBUG=y

CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y

CONFIG_CRYPTO_AES_ARM_CE=m

CONFIG_CRYPTO_CHACHA20_NEON=m

# CONFIG_CRYPTO_HW is not set

CONFIG_DMA_CMA=y

CONFIG_CMA_SIZE_MBYTES=64

CONFIG_PRINTK_TIME=y

CONFIG_NFS_V3_ACL=y

CONFIG_NFS_V4=y

CONFIG_ROOT_NFS=y

CONFIG_PRINTK_TIME=y

CONFIG_DEBUG_KERNEL=y

CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y

CONFIG_VFAT_FS=y

CONFIG_CRAMFS=y

CONFIG_MINIX_FS=y

# CONFIG_FTRACE is not set

CONFIG_DEBUG_USER=y

CONFIG_CRYPTO_CBC=m

CONFIG_CRYPTO_PCBC=m

CONFIG_CRYPTO_DEV_MARVELL_CESA=y

CONFIG_DEBUG_KERNEL=y

CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y

CONFIG_MAGIC_SYSRQ=y

CONFIG_CRYPTO_CBC=m

CONFIG_CRYPTO_PCBC=m

CONFIG_CRYPTO_DEV_MARVELL_CESA=y

CONFIG_DEBUG_KERNEL=y

CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y

CONFIG_MAGIC_SYSRQ=y

CONFIG_NLS_ISO8859_1=y

CONFIG_NLS_ISO8859_15=y

CONFIG_CRYPTO_DEV_MXS_DCP=y

CONFIG_FONTS=y

CONFIG_PRINTK_TIME=y

CONFIG_DEBUG_KERNEL=y

CONFIG_CRYPTO_DEV_OMAP_SHAM=m

CONFIG_CRYPTO_DEV_OMAP_AES=m

CONFIG_CRYPTO_DEV_OMAP_DES=m

CONFIG_DMA_CMA=y

CONFIG_FONTS=y

CONFIG_FONT_8x8=y

CONFIG_CRYPTO_ECB=m

CONFIG_CRYPTO_PCBC=m

CONFIG_CRYPTO_DEV_MARVELL_CESA=y

# CONFIG_DEBUG_BUGVERBOSE is not set

CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y

CONFIG_MAGIC_SYSRQ=y

CONFIG_NFS_V3_ACL=y

CONFIG_NFS_V4=y

CONFIG_ROOT_NFS=y

CONFIG_PRINTK_TIME=y

CONFIG_DEBUG_KERNEL=y

CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y

CONFIG_NFS_V3_ACL=y

CONFIG_NFS_V4=y

CONFIG_ROOT_NFS=y

CONFIG_PRINTK_TIME=y

CONFIG_DEBUG_KERNEL=y

CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y

CONFIG_CRYPTO_SHA256_ARM=m

CONFIG_CRYPTO_SHA512_ARM=m

CONFIG_CRYPTO_AES_ARM=m

CONFIG_FONTS=y

CONFIG_FONT_8x8=y

CONFIG_FONT_8x16=y

CONFIG_NLS_ASCII=y

CONFIG_NLS_ISO8859_1=y

CONFIG_NLS_UTF8=y

CONFIG_DEBUG_KERNEL=y

CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y

CONFIG_MAGIC_SYSRQ=y

CONFIG_CRYPTO_DEV_ATMEL_AES=y

CONFIG_CRYPTO_DEV_ATMEL_TDES=y

CONFIG_CRYPTO_DEV_ATMEL_SHA=y

CONFIG_DMA_CMA=y

CONFIG_CMA_SIZE_MBYTES=32

CONFIG_CMA_ALIGNMENT=9

CONFIG_CRYPTO_MICHAEL_MIC=m

CONFIG_CRYPTO_SHA512=m

CONFIG_CRYPTO_WP512=m

CONFIG_FONTS=y

CONFIG_FONT_8x8=y

CONFIG_FONT_8x16=y

# CONFIG_DNOTIFY is not set

# CONFIG_INOTIFY_USER is not set

CONFIG_NLS=y

CONFIG_PRINTK_TIME=y

# CONFIG_DEBUG_BUGVERBOSE is not set

CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y

CONFIG_X509_CERTIFICATE_PARSER=y

CONFIG_PKCS7_MESSAGE_PARSER=y

CONFIG_SYSTEM_TRUSTED_KEYRING=y

CONFIG_PRINTK_TIME=y

CONFIG_DEBUG_KERNEL=y

CONFIG_MAGIC_SYSRQ=y

#define ZERO_PAGE(vaddr) (empty_zero_page)

#endif

#include <asm-generic/pgtable-nopud.h>

#include <asm/pgtable-nommu.h>

#else

#include <asm/page.h>

#include <asm/pgtable-hwdef.h>

#endif

#ifdef CONFIG_MMU

#define ARM_MMU_DISCARD(x)

#else

#define ARM_MMU_KEEP(x)

#define NOCROSSREFS

#endif

/* Set start/end symbol names to the LMA for the section */

#define ARM_LMA(sym, section) \

sym##_start = LOADADDR(section); \

__vectors_lma = .; \

OVERLAY 0xffff0000 : NOCROSSREFS AT(__vectors_lma) { \

.vectors { \

} \

.vectors.bhb.loop8 { \

} \

.vectors.bhb.bpiall { \

} \

} \

ARM_LMA(__vectors, .vectors); \

if (!ipi_desc[i])

continue;

for_each_online_cpu(cpu)

seq_printf(p, "%10u ", irq_desc_kstat_cpu(ipi_desc[i], cpu));

. = ALIGN(4);

__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {

__start___ex_table = .;

__stop___ex_table = .;

}

. = ALIGN(4);

__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {

__start___ex_table = .;

__stop___ex_table = .;

}

static void dc21285_enable_error(struct timer_list *timer)

{

if (timer == &serr_timer)

enable_irq(IRQ_PCI_SERR);

&pxa_irq_ops, NULL);

if (!pxa_irq_domain)

panic("Unable to add PXA IRQ domain\n");

for (n = 0; n < irq_nr; n += 32) {

void __iomem *base = irq_base(n >> 5);

if (sharpsl_pm.machinfo->exit)

sharpsl_pm.machinfo->exit();

}

static struct platform_driver sharpsl_pm_driver = {

*p++ = 0xe7fddef0;

}

{

#ifdef CONFIG_ARM_LPAE

swiotlb_init(max_pfn > arm_dma_pfn_limit, SWIOTLB_VERBOSE);

#endif

#ifdef CONFIG_SA1111

/* now that our DMA memory is actually so designated, we can free it */

#endif

/*

* Check boundaries twice: Some fundamental inconsistencies can

* be detected at build time already.

select ARCH_HAS_KEEPINITRD

select ARCH_HAS_MEMBARRIER_SYNC_CORE

select ARCH_HAS_MEM_ENCRYPT

select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS

select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE

select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT

select ARCH_HAS_PTE_DEVMAP

select ARCH_HAS_PTE_SPECIAL

select ARCH_HAS_HW_PTE_YOUNG

select GENERIC_IRQ_SHOW_LEVEL

select GENERIC_LIB_DEVMEM_IS_ALLOWED

select GENERIC_PCI_IOMAP

select GENERIC_SCHED_CLOCK

select GENERIC_SMP_IDLE_THREAD

select GENERIC_TIME_VSYSCALL

KBUILD_CFLAGS += $(call cc-disable-warning, psabi)

KBUILD_AFLAGS += $(compat_vdso)

KBUILD_RUSTFLAGS += --target=aarch64-unknown-none-softfloat

else

KBUILD_RUSTFLAGS += --target=aarch64-unknown-none -Ctarget-feature="-neon"

#define FUJITSU_CPU_PART_A64FX 0x001

#define HISI_CPU_PART_TSV110 0xD01

#define APPLE_CPU_PART_M1_ICESTORM 0x022

#define APPLE_CPU_PART_M1_FIRESTORM 0x023

#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)

#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)

#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)

#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)

#define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)

#define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n))

#define ESR_ELx_FSC_SECC (0x18)

#define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n))

/* Status codes for individual page table levels */

#define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + (n))

#define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0))

/* ISS field definitions for exceptions taken in to Hyp */

#define ESR_ELx_CV (UL(1) << 24)

#define ESR_ELx_COND_SHIFT (20)

#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)

(esr == ESR_ELx_FSC_ACCESS_L(0));

}

/* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */

static inline bool esr_iss_is_eretax(unsigned long esr)

{

#define _PAGE_IOREMAP PROT_DEVICE_nGnRE

#define ioremap_wc(addr, size) \

#define ioremap_np(addr, size) \

/*

* io{read,write}{16,32,64}be() macros

if (pfn_is_map_memory(__phys_to_pfn(addr)))

return (void __iomem *)__phys_to_virt(addr);

}

/*

static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)

{

}

static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)

* Was this synchronous external abort a RAS notification?

* Returns '0' for errors handled by some RAS subsystem, or -ENOENT.

*/

{

/* apei_claim_sea(NULL) expects to mask interrupts itself */

lockdep_assert_irqs_enabled();

#define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)

#define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))

#define pmd_pgprot pmd_pgprot

static inline pgprot_t pmd_pgprot(pmd_t pmd)

{

#include <linux/ptdump.h>

#include <linux/mm_types.h>

#include <linux/seq_file.h>

#else

static inline void note_page(struct ptdump_state *pt_st, unsigned long addr,

int level, u64 val) { }

#endif /* __ASM_PTDUMP_H */

#endif

#include <asm-generic/rqspinlock.h>

return true;

}

/*

* If mprotect/munmap/etc occurs during TLB batched flushing, we need to

* synchronise all the TLBI issued with a DSB to avoid the race mentioned in

return false;

}

unsigned long start, unsigned long end,

unsigned long stride, bool last_level,

int tlb_level)

pages = (end - start) >> PAGE_SHIFT;

if (__flush_tlb_range_limit_excess(start, end, pages, stride)) {

return;

}

dsb(ishst);

if (last_level)

__flush_tlb_range_op(vale1is, start, pages, stride, asid,

__flush_tlb_range_op(vae1is, start, pages, stride, asid,

tlb_level, true, lpa2_is_enabled());

}

static inline void __flush_tlb_range(struct vm_area_struct *vma,

unsigned long stride, bool last_level,

int tlb_level)

{

last_level, tlb_level);

dsb(ish);

}

dsb(ish);

isb();

}

#endif

#endif

int dstreg = ESR_ELx_MOPS_ISS_DESTREG(esr);

int srcreg = ESR_ELx_MOPS_ISS_SRCREG(esr);

int sizereg = ESR_ELx_MOPS_ISS_SIZEREG(esr);

dst = regs->regs[dstreg];

size = regs->regs[sizereg];

/*

}

} else {

/* CPY* instruction */

if (!(option_a ^ wrong_option)) {

/* Format is from Option B */

if (regs->pstate & PSR_N_BIT) {

prot = __acpi_get_writethrough_mem_attribute();

}

}

}

/*

return 1;

}

type = handler(addr, instr, regs);

if (type == TYPE_ERROR || type == TYPE_FAULT)

MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),

MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),

MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_GOLD),

{},

};

static const struct midr_range spectre_bhb_k11_list[] = {

mm->context.vdso = (void *)vdso_base;

ret = _install_special_mapping(mm, vdso_base, vdso_text_len,

VM_READ|VM_EXEC|gp_flags|

vdso_info[abi].cm);

if (IS_ERR(ret))

goto up_fail;

*/

ret = _install_special_mapping(mm, AARCH32_VECTORS_BASE, PAGE_SIZE,

VM_READ | VM_EXEC |

&aarch32_vdso_maps[AA32_MAP_VECTORS]);

return PTR_ERR_OR_ZERO(ret);

*/

ret = _install_special_mapping(mm, addr, PAGE_SIZE,

VM_READ | VM_EXEC | VM_MAYREAD |

&aarch32_vdso_maps[AA32_MAP_SIGPAGE]);

if (IS_ERR(ret))

goto out;

depends on KVM

depends on DEBUG_KERNEL

depends on DEBUG_FS

default n

help

Say Y here if you want to show the stage-2 kernel pagetables

#include <asm/kvm_hyp.h>

#include <asm/kvm_mmu.h>

static inline bool __translate_far_to_hpfar(u64 far, u64 *hpfar)

{

int ret;

return true;

}

{

/*

*

*/

hpfar = read_sysreg(hpfar_el2);

return true;

}

hyp_ffa_version = ffa_req_version;

}

res->a0 = FFA_RET_NOT_SUPPORTED;

res->a0 = hyp_ffa_version;

}

unlock:

if (!is_ffa_call(func_id))

return false;

ffa_to_smccc_error(&res, FFA_RET_INVALID_PARAMETERS);

goto out_handled;

}

return;

}

ret = host_stage2_idmap(addr);

BUG_ON(ret && ret != -EAGAIN);

}

gfn_t gfn;

int ret, idx;

esr = kvm_vcpu_get_esr(vcpu);

ipa = fault_ipa = kvm_vcpu_get_fault_ipa(vcpu);

is_iabt = kvm_vcpu_trap_is_iabt(vcpu);

if (esr_fsc_is_translation_fault(esr)) {

}

}

trace_kvm_guest_fault(*vcpu_pc(vcpu), kvm_vcpu_get_esr(vcpu),

kvm_vcpu_get_hfar(vcpu), fault_ipa);

context.o proc.o pageattr.o fixmap.o

obj-$(CONFIG_ARM64_CONTPTE) += contpte.o

obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o

obj-$(CONFIG_PTDUMP_DEBUGFS) += ptdump_debugfs.o

obj-$(CONFIG_TRANS_TABLE) += trans_pgd.o

obj-$(CONFIG_TRANS_TABLE) += trans_pgd-asm.o

* eliding the trailing DSB applies here.

*/

addr = ALIGN_DOWN(addr, CONT_PTE_SIZE);

PAGE_SIZE, true, 3);

}

{

unsigned long long low_size = 0;

unsigned long long crash_base, crash_size;

bool high = false;

int ret;

if (!IS_ENABLED(CONFIG_CRASH_RESERVE))

return;

&crash_size, &crash_base,

&low_size, &high);

if (ret)

return;

}

static phys_addr_t __init max_zone_phys(phys_addr_t zone_limit)

}

early_init_fdt_scan_reserved_mem();

}

void __init bootmem_init(void)

memblock_dump_all();

}

{

unsigned int flags = SWIOTLB_VERBOSE;

bool swiotlb = max_pfn > PFN_DOWN(arm64_dma_phys_limit);

swiotlb_init(swiotlb, flags);

swiotlb_update_mem_attributes();

/*

* Check boundaries twice: Some fundamental inconsistencies can be

* detected at build time already.

}

void __iomem *ioremap_prot(phys_addr_t phys_addr, size_t size,

{

unsigned long last_addr = phys_addr + size - 1;

/* Don't allow outside PHYS_MASK */

if (last_addr & ~PHYS_MASK)

__remove_pgd_mapping(swapper_pg_dir,

__phys_to_virt(start), size);

else {

max_low_pfn = max_pfn;

}

Field 4 P

Field 3:0 Align

EndSysreg

*/

#define ioremap_wc(addr, size) \

ioremap_prot((addr), (size), \

#include <asm-generic/io.h>

return ret;

}

extern void pagetable_init(void);

extern void mmu_init(unsigned long min_pfn, unsigned long max_pfn);

#include <asm/mmu_context.h>

#include <asm/pgalloc.h>

static void __init csky_memblock_init(void)

{

unsigned long lowmem_size = PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET);

max_low_pfn = min_low_pfn + sseg_size;

}

max_zone_pfn[ZONE_NORMAL] = max_low_pfn;

mmu_init(min_low_pfn, max_low_pfn);

__page_aligned_bss;

EXPORT_SYMBOL(empty_zero_page);

void free_initmem(void)

{

free_initmem_default(-1);

CONFIG_CRYPTO_MD5=y

# CONFIG_CRYPTO_ANSI_CPRNG is not set

# CONFIG_CRYPTO_HW is not set

CONFIG_FRAME_WARN=0

CONFIG_MAGIC_SYSRQ=y

CONFIG_DEBUG_FS=y

max_kernel_seg = pmdindex;

}

#endif

/* checkpatch says don't init this to 0. */

unsigned long long kmap_generation;

void sync_icache_dcache(pte_t pte)

{

unsigned long addr;

free_area_init(max_zone_pfn); /* sets up the zonelists and mem_map */

/*

*/

}

#ifndef DMA_RESERVE

select ARCH_HAS_SET_MEMORY

select ARCH_HAS_SET_DIRECT_MAP

select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST

select ARCH_HAS_VDSO_ARCH_DATA

select ARCH_INLINE_READ_LOCK if !PREEMPTION

select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION

select HAVE_STACKPROTECTOR

select HAVE_SYSCALL_TRACEPOINTS

select HAVE_TIF_NOHZ

select IRQ_FORCED_THREADING

select IRQ_LOONGARCH_CPU

select LOCK_MM_AND_FIND_VMA

config CMDLINE_EXTEND

bool "Use built-in to extend bootloader kernel arguments"

help

cases where the provided arguments are insufficient and

you don't want to or cannot modify them.

CONFIG_MEMCG=y

CONFIG_BLK_CGROUP=y

CONFIG_CFS_BANDWIDTH=y

CONFIG_CGROUP_PIDS=y

CONFIG_CGROUP_RDMA=y

CONFIG_CGROUP_FREEZER=y

CONFIG_CGROUP_HUGETLB=y

CONFIG_CPUSETS=y

CONFIG_ZPOOL=y

CONFIG_ZSWAP=y

CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y

# CONFIG_COMPAT_BRK is not set

CONFIG_MEMORY_HOTPLUG=y

# CONFIG_MHP_DEFAULT_ONLINE_TYPE_OFFLINE is not set

CONFIG_RTW88_8723DU=m

CONFIG_RTW88_8821CE=m

CONFIG_RTW88_8821CU=m

CONFIG_RTW89=m

CONFIG_RTW89_8851BE=m

CONFIG_RTW89_8852AE=m

CONFIG_VIDEO_BT848=m

CONFIG_DVB_BT8XX=m

CONFIG_DRM=y

CONFIG_DRM_RADEON=m

CONFIG_DRM_RADEON_USERPTR=y

CONFIG_DRM_AMDGPU=m

CONFIG_FB=y

CONFIG_FB_EFI=y

CONFIG_FB_RADEON=y

CONFIG_LCD_CLASS_DEVICE=y

CONFIG_LCD_PLATFORM=m

# CONFIG_VGA_CONSOLE is not set

CONFIG_TYPEC_UCSI=m

CONFIG_UCSI_ACPI=m

CONFIG_INFINIBAND=m

CONFIG_RTC_CLASS=y

CONFIG_RTC_DRV_EFI=y

CONFIG_RTC_DRV_LOONGSON=y

#define L1_CACHE_SHIFT CONFIG_L1_CACHE_SHIFT

#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)

#define __read_mostly __section(".data..read_mostly")

#endif /* _ASM_CACHE_H */

#ifdef CONFIG_ARCH_IOREMAP

static inline void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,

{

case _CACHE_CC:

return (void __iomem *)(unsigned long)(CACHE_BASE + offset);

case _CACHE_SUC:

}

#define ioremap(offset, size) \

#define iounmap(addr) ((void)(addr))

*/

#define ioremap_wc(offset, size) \

ioremap_prot((offset), (size), \

#define ioremap_cache(offset, size) \

#define mmiowb() wmb()

#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace

void arch_trigger_cpumask_backtrace(const struct cpumask *mask, int exclude_cpu);

#define NR_IRQS (64 + NR_VECTORS * (NR_CPUS + MAX_IO_PICS))

struct acpi_vector_group {

return pte;

}