diff options
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-j722s.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j722s.dtsi | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index 14c6c6a332ef..1b36dcf37925 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -56,6 +56,7 @@ d-cache-sets = <128>; next-level-cache = <&l2_0>; clocks = <&k3_clks 135 0>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -71,6 +72,7 @@ d-cache-sets = <128>; next-level-cache = <&l2_0>; clocks = <&k3_clks 136 0>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -86,6 +88,7 @@ d-cache-sets = <128>; next-level-cache = <&l2_0>; clocks = <&k3_clks 137 0>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -101,6 +104,7 @@ d-cache-sets = <128>; next-level-cache = <&l2_0>; clocks = <&k3_clks 138 0>; + #cooling-cells = <2>; }; }; @@ -156,9 +160,10 @@ <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */ <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */ <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */ - <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x0fe00000 0x00 0x0fe00000 0x00 0x000f0400>, /* Third peripheral window */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Fourth peripheral window */ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ - <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ + <0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */ <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ @@ -169,6 +174,7 @@ <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ |