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Diffstat (limited to 'arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi')
-rw-r--r--arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi541
1 files changed, 501 insertions, 40 deletions
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 51c6e19e40b8..02e62d954e94 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -37,6 +37,7 @@
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&L2>;
};
cpu1: cpu@1 {
@@ -44,6 +45,7 @@
reg = <0x100>;
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&L2>;
};
cpu2: cpu@2 {
@@ -51,6 +53,7 @@
reg = <0x200>;
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&L2>;
};
cpu3: cpu@3 {
@@ -58,6 +61,30 @@
reg = <0x300>;
device_type = "cpu";
enable-method = "psci";
+ next-level-cache = <&L2>;
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ next-level-cache = <&L3>;
+ cache-unified;
+ };
+
+ L3: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
+ };
+
+ };
+
+ firmware {
+ svc {
+ compatible = "intel,agilex5-svc";
+ method = "smc";
+ memory-region = <&service_reserved>;
+ iommus = <&smmu 10>;
};
};
@@ -75,8 +102,11 @@
#address-cells = <2>;
#size-cells = <2>;
interrupt-controller;
+ interrupt-parent = <&intc>;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
+ /* VGIC maintenance interrupt */
+ interrupts = <GIC_PPI 25 IRQ_TYPE_LEVEL_HIGH>;
its: msi-controller@1d040000 {
compatible = "arm,gic-v3-its";
@@ -122,10 +152,10 @@
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&intc>;
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
usbphy0: usbphy {
@@ -133,6 +163,12 @@
compatible = "usb-nop-xceiv";
};
+ pmu0: pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
soc: soc@0 {
compatible = "simple-bus";
ranges = <0 0 0 0xffffffff>;
@@ -203,7 +239,8 @@
};
i3c0: i3c@10da0000 {
- compatible = "snps,dw-i3c-master-1.00a";
+ compatible = "altr,agilex5-dw-i3c-master",
+ "snps,dw-i3c-master-1.00a";
reg = <0x10da0000 0x1000>;
#address-cells = <3>;
#size-cells = <0>;
@@ -213,7 +250,8 @@
};
i3c1: i3c@10da1000 {
- compatible = "snps,dw-i3c-master-1.00a";
+ compatible = "altr,agilex5-dw-i3c-master",
+ "snps,dw-i3c-master-1.00a";
reg = <0x10da1000 0x1000>;
#address-cells = <3>;
#size-cells = <0>;
@@ -222,9 +260,9 @@
status = "disabled";
};
- gpio0: gpio@ffc03200 {
+ gpio0: gpio@10c03200 {
compatible = "snps,dw-apb-gpio";
- reg = <0xffc03200 0x100>;
+ reg = <0x10c03200 0x100>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rst GPIO0_RESET>;
@@ -271,7 +309,10 @@
#size-cells = <0>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
+ clock-names = "nf_clk";
cdns,board-delay-ps = <4830>;
+ iommus = <&smmu 4>;
+ dma-coherent;
status = "disabled";
};
@@ -283,38 +324,50 @@
#size-cells = <1>;
};
- dmac0: dma-controller@10db0000 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x10db0000 0x500>;
- clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
- <&clkmgr AGILEX5_L4_MP_CLK>;
- clock-names = "core-clk", "cfgr-clk";
- interrupt-parent = <&intc>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- dma-channels = <4>;
- snps,dma-masters = <1>;
- snps,data-width = <2>;
- snps,block-size = <32767 32767 32767 32767>;
- snps,priority = <0 1 2 3>;
- snps,axi-max-burst-len = <8>;
- };
-
- dmac1: dma-controller@10dc0000 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x10dc0000 0x500>;
- clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
- <&clkmgr AGILEX5_L4_MP_CLK>;
- clock-names = "core-clk", "cfgr-clk";
- interrupt-parent = <&intc>;
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- dma-channels = <4>;
- snps,dma-masters = <1>;
- snps,data-width = <2>;
- snps,block-size = <32767 32767 32767 32767>;
- snps,priority = <0 1 2 3>;
- snps,axi-max-burst-len = <8>;
+ dma: dma-bus@10db0000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <2>;
+ ranges = <0x00 0x10db0000 0x00 0x20000>;
+ dma-ranges = <0x00 0x00 0x100 0x00>;
+
+ dmac0: dma-controller@0 {
+ compatible = "altr,agilex5-axi-dma",
+ "snps,axi-dma-1.01a";
+ reg = <0x0 0x0 0x500>;
+ clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
+ <&clkmgr AGILEX5_L4_MP_CLK>;
+ clock-names = "core-clk", "cfgr-clk";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,dma-masters = <1>;
+ snps,data-width = <2>;
+ snps,block-size = <32767 32767 32767 32767>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <8>;
+ iommus = <&smmu 8>;
+ };
+
+ dmac1: dma-controller@10000 {
+ compatible = "altr,agilex5-axi-dma",
+ "snps,axi-dma-1.01a";
+ reg = <0x10000 0x0 0x500>;
+ clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>,
+ <&clkmgr AGILEX5_L4_MP_CLK>;
+ clock-names = "core-clk", "cfgr-clk";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,dma-masters = <1>;
+ snps,data-width = <2>;
+ snps,block-size = <32767 32767 32767 32767>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <8>;
+ iommus = <&smmu 9>;
+ };
};
rst: rstmgr@10d11000 {
@@ -323,6 +376,18 @@
#reset-cells = <1>;
};
+ smmu: iommu@16000000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x16000000 0x30000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "gerror", "priq";
+ dma-coherent;
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
spi0: spi@10da4000 {
compatible = "snps,dw-apb-ssi";
reg = <0x10da4000 0x1000>;
@@ -423,6 +488,7 @@
phy-names = "usb2-phy";
resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
reset-names = "dwc2", "dwc2-ecc";
+ iommus = <&smmu 6>;
clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>;
clock-names = "otg";
status = "disabled";
@@ -486,5 +552,400 @@
clocks = <&qspi_clk>;
status = "disabled";
};
+
+ gmac0: ethernet@10810000 {
+ compatible = "altr,socfpga-stmmac-agilex5",
+ "snps,dwxgmac-2.10";
+ reg = <0x10810000 0x3500>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
+ reset-names = "stmmaceth", "ahb";
+ clocks = <&clkmgr AGILEX5_EMAC0_CLK>,
+ <&clkmgr AGILEX5_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
+ mac-address = [00 00 00 00 00 00];
+ tx-fifo-depth = <32768>;
+ rx-fifo-depth = <16384>;
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <64>;
+ snps,axi-config = <&stmmac_axi_emac0_setup>;
+ snps,mtl-rx-config = <&mtl_rx_emac0_setup>;
+ snps,mtl-tx-config = <&mtl_tx_emac0_setup>;
+ snps,pbl = <32>;
+ snps,tso;
+ altr,sysmgr-syscon = <&sysmgr 0x44 0>;
+ snps,clk-csr = <0>;
+ iommus = <&smmu 1>;
+ status = "disabled";
+
+ stmmac_axi_emac0_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <31>;
+ snps,rd_osr_lmt = <31>;
+ snps,blen = <0 0 0 32 16 8 4>;
+ };
+
+ mtl_rx_emac0_setup: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ };
+ queue2 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ };
+ queue3 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ };
+ queue4 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x4>;
+ };
+ queue5 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x5>;
+ };
+ queue6 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x6>;
+ };
+ queue7 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x7>;
+ };
+ };
+
+ mtl_tx_emac0_setup: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+ snps,tx-sched-wrr;
+ queue0 {
+ snps,weight = <0x09>;
+ snps,dcb-algorithm;
+ };
+ queue1 {
+ snps,weight = <0x0a>;
+ snps,dcb-algorithm;
+ };
+ queue2 {
+ snps,weight = <0x0b>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue3 {
+ snps,weight = <0x0c>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue4 {
+ snps,weight = <0x0d>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue5 {
+ snps,weight = <0x0e>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue6 {
+ snps,weight = <0x0f>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue7 {
+ snps,weight = <0x10>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
+ gmac1: ethernet@10820000 {
+ compatible = "altr,socfpga-stmmac-agilex5",
+ "snps,dwxgmac-2.10";
+ reg = <0x10820000 0x3500>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
+ reset-names = "stmmaceth", "ahb";
+ clocks = <&clkmgr AGILEX5_EMAC1_CLK>,
+ <&clkmgr AGILEX5_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
+ mac-address = [00 00 00 00 00 00];
+ tx-fifo-depth = <32768>;
+ rx-fifo-depth = <16384>;
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <64>;
+ snps,axi-config = <&stmmac_axi_emac1_setup>;
+ snps,mtl-rx-config = <&mtl_rx_emac1_setup>;
+ snps,mtl-tx-config = <&mtl_tx_emac1_setup>;
+ snps,pbl = <32>;
+ snps,tso;
+ altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+ snps,clk-csr = <0>;
+ iommus = <&smmu 2>;
+ status = "disabled";
+
+ stmmac_axi_emac1_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <31>;
+ snps,rd_osr_lmt = <31>;
+ snps,blen = <0 0 0 32 16 8 4>;
+ };
+
+ mtl_rx_emac1_setup: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ };
+ queue2 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ };
+ queue3 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ };
+ queue4 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x4>;
+ };
+ queue5 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x5>;
+ };
+ queue6 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x6>;
+ };
+ queue7 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x7>;
+ };
+ };
+
+ mtl_tx_emac1_setup: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+ snps,tx-sched-wrr;
+ queue0 {
+ snps,weight = <0x09>;
+ snps,dcb-algorithm;
+ };
+ queue1 {
+ snps,weight = <0x0a>;
+ snps,dcb-algorithm;
+ };
+ queue2 {
+ snps,weight = <0x0b>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue3 {
+ snps,weight = <0x0c>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue4 {
+ snps,weight = <0x0d>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue5 {
+ snps,weight = <0x0e>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue6 {
+ snps,weight = <0x0f>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue7 {
+ snps,weight = <0x10>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
+ gmac2: ethernet@10830000 {
+ compatible = "altr,socfpga-stmmac-agilex5",
+ "snps,dwxgmac-2.10";
+ reg = <0x10830000 0x3500>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
+ reset-names = "stmmaceth", "ahb";
+ clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
+ <&clkmgr AGILEX5_EMAC_PTP_CLK>;
+ clock-names = "stmmaceth", "ptp_ref";
+ mac-address = [00 00 00 00 00 00];
+ tx-fifo-depth = <32768>;
+ rx-fifo-depth = <16384>;
+ snps,multicast-filter-bins = <64>;
+ snps,perfect-filter-entries = <64>;
+ snps,axi-config = <&stmmac_axi_emac2_setup>;
+ snps,mtl-rx-config = <&mtl_rx_emac2_setup>;
+ snps,mtl-tx-config = <&mtl_tx_emac2_setup>;
+ snps,pbl = <32>;
+ snps,tso;
+ altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+ snps,clk-csr = <0>;
+ iommus = <&smmu 3>;
+ status = "disabled";
+
+ stmmac_axi_emac2_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <31>;
+ snps,rd_osr_lmt = <31>;
+ snps,blen = <0 0 0 32 16 8 4>;
+ };
+
+ mtl_rx_emac2_setup: rx-queues-config {
+ snps,rx-queues-to-use = <8>;
+ snps,rx-sched-sp;
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ };
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ };
+ queue2 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ };
+ queue3 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ };
+ queue4 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x4>;
+ };
+ queue5 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x5>;
+ };
+ queue6 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x6>;
+ };
+ queue7 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x7>;
+ };
+ };
+
+ mtl_tx_emac2_setup: tx-queues-config {
+ snps,tx-queues-to-use = <8>;
+ snps,tx-sched-wrr;
+ queue0 {
+ snps,weight = <0x09>;
+ snps,dcb-algorithm;
+ };
+ queue1 {
+ snps,weight = <0x0a>;
+ snps,dcb-algorithm;
+ };
+ queue2 {
+ snps,weight = <0x0b>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue3 {
+ snps,weight = <0x0c>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue4 {
+ snps,weight = <0x0d>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue5 {
+ snps,weight = <0x0e>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue6 {
+ snps,weight = <0x0f>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ queue7 {
+ snps,weight = <0x10>;
+ snps,coe-unsupported;
+ snps,dcb-algorithm;
+ };
+ };
+ };
+
+ pmu0_tcu: pmu@16002000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x16002000 0x1000>,
+ <0x16022000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmu0_tbu0: pmu@16042000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x16042000 0x1000>,
+ <0x16052000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmu0_tbu1: pmu@16062000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x16062000 0x1000>,
+ <0x16072000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmu0_tbu2: pmu@16082000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x16082000 0x1000>,
+ <0x16092000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmu0_tbu3: pmu@160a2000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x160a2000 0x1000>,
+ <0x160b2000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmu0_tbu4: pmu@160c2000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x160c2000 0x1000>,
+ <0x160d2000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmu0_tbu5: pmu@160e2000 {
+ compatible = "arm,smmu-v3-pmcg";
+ reg = <0x160e2000 0x1000>,
+ <0x160f2000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
+ };
};
};