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-rw-r--r--arch/arm64/boot/dts/arm/Makefile3
-rw-r--r--arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts15
-rw-r--r--arch/arm64/boot/dts/arm/corstone1000-a320.dtsi91
-rw-r--r--arch/arm64/boot/dts/arm/corstone1000-fvp.dts64
-rw-r--r--arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi44
-rw-r--r--arch/arm64/boot/dts/arm/corstone1000-mps3.dts13
-rw-r--r--arch/arm64/boot/dts/arm/corstone1000.dtsi13
-rw-r--r--arch/arm64/boot/dts/arm/foundation-v8.dtsi1
-rw-r--r--arch/arm64/boot/dts/arm/fvp-base-revc.dts101
-rw-r--r--arch/arm64/boot/dts/arm/juno-base.dtsi1
-rw-r--r--arch/arm64/boot/dts/arm/morello-fvp.dts77
-rw-r--r--arch/arm64/boot/dts/arm/morello-sdp.dts164
-rw-r--r--arch/arm64/boot/dts/arm/morello.dtsi323
-rw-r--r--arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts1
-rw-r--r--arch/arm64/boot/dts/arm/zena-css-fvp.dts63
-rw-r--r--arch/arm64/boot/dts/arm/zena-css.dtsi769
16 files changed, 1695 insertions, 48 deletions
diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index d908e96d7ddc..b35b03da2d84 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -7,3 +7,6 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-a320-fvp.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += zena-css-fvp.dtb
diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts
new file mode 100644
index 000000000000..0f72af78b5e1
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2026, Arm Limited. All rights reserved.
+ *
+ */
+
+/dts-v1/;
+
+#include "corstone1000-a320.dtsi"
+#include "corstone1000-fvp.dtsi"
+
+/ {
+ model = "ARM Corstone1000-A320 FVP (Fixed Virtual Platform)";
+ compatible = "arm,corstone1000-a320-fvp";
+};
diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi b/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi
new file mode 100644
index 000000000000..f0937914350c
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2026, Arm Limited. All rights reserved.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "corstone1000.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus: cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a320";
+ reg = <0 0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a320";
+ reg = <0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a320";
+ reg = <0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a320";
+ reg = <0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ sram: sram@2400000 {
+ compatible = "mmio-sram";
+ reg = <0x02400000 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ };
+
+ gic: interrupt-controller@1c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ reg = <0x1c000000 0x10000>,
+ <0x1c040000 0x80000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+
+ soc {
+ npu@1a050000 {
+ compatible = "arm,corstone1000-ethos-u85", "arm,ethos-u85";
+ reg = <0x1a050000 0x1400>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&refclk100mhz>, <&refclk100mhz>;
+ clock-names = "core", "apb";
+ sram = <&sram>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
index abd013562995..fac0999b1901 100644
--- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
+++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
@@ -8,44 +8,46 @@
/dts-v1/;
#include "corstone1000.dtsi"
+#include "corstone1000-fvp.dtsi"
/ {
model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
compatible = "arm,corstone1000-fvp";
- smsc: ethernet@4010000 {
- compatible = "smsc,lan91c111";
- reg = <0x40100000 0x10000>;
- phy-mode = "mii";
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <2>;
- };
+ cpus: cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
- vmmc_v3_3d: regulator-vmmc {
- compatible = "regulator-fixed";
- regulator-name = "vmmc_supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
+ cpu: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0 0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
- sdmmc0: mmc@40300000 {
- compatible = "arm,pl18x", "arm,primecell";
- reg = <0x40300000 0x1000>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- max-frequency = <12000000>;
- vmmc-supply = <&vmmc_v3_3d>;
- clocks = <&smbclk>, <&refclk100mhz>;
- clock-names = "smclk", "apb_pclk";
- };
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
- sdmmc1: mmc@50000000 {
- compatible = "arm,pl18x", "arm,primecell";
- reg = <0x50000000 0x10000>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- max-frequency = <12000000>;
- vmmc-supply = <&vmmc_v3_3d>;
- clocks = <&smbclk>, <&refclk100mhz>;
- clock-names = "smclk", "apb_pclk";
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi b/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi
new file mode 100644
index 000000000000..dc6d77446e8f
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited. All rights reserved.
+ *
+ */
+
+/ {
+ smsc: ethernet@4010000 {
+ compatible = "smsc,lan91c111";
+ reg = <0x40100000 0x10000>;
+ phy-mode = "mii";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <2>;
+ };
+
+ vmmc_v3_3d: regulator-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc_supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ sdmmc0: mmc@40300000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ reg = <0x40300000 0x1000>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <12000000>;
+ vmmc-supply = <&vmmc_v3_3d>;
+ clocks = <&smbclk>, <&refclk100mhz>;
+ clock-names = "smclk", "apb_pclk";
+ };
+
+ sdmmc1: mmc@50000000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ reg = <0x50000000 0x10000>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <12000000>;
+ vmmc-supply = <&vmmc_v3_3d>;
+ clocks = <&smbclk>, <&refclk100mhz>;
+ clock-names = "smclk", "apb_pclk";
+ };
+};
diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts
index 10d265be0c02..adcfaf7c55b8 100644
--- a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts
+++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts
@@ -13,6 +13,19 @@
model = "ARM Corstone1000 FPGA MPS3 board";
compatible = "arm,corstone1000-mps3";
+ cpus: cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0 0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ };
+
smsc: ethernet@4010000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x40100000 0x10000>;
diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
index bb9b96fb5314..4d57dc197918 100644
--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
@@ -21,18 +21,6 @@
stdout-path = "serial0:115200n8";
};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a35";
- reg = <0>;
- next-level-cache = <&L2_0>;
- };
- };
-
memory@88200000 {
device_type = "memory";
reg = <0x88200000 0x77e00000>;
@@ -108,7 +96,6 @@
reg = <0x1a220000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
- clock-frequency = <50000000>;
ranges;
frame@1a230000 {
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
index 083be35495b3..a4b2b78d4df3 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
@@ -77,7 +77,6 @@
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- clock-frequency = <100000000>;
};
pmu {
diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
index 9e10d7a6b5a2..68a69f17e93d 100644
--- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts
+++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts
@@ -44,6 +44,30 @@
#address-cells = <2>;
#size-cells = <0>;
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <40>;
+ exit-latency-us = <100>;
+ min-residency-us = <150>;
+ status = "disabled";
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <500>;
+ exit-latency-us = <1000>;
+ min-residency-us = <2500>;
+ status = "disabled";
+ };
+ };
+
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
@@ -56,6 +80,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C0_L2>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu1: cpu@100 {
device_type = "cpu";
@@ -69,6 +94,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C0_L2>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu2: cpu@200 {
device_type = "cpu";
@@ -82,6 +108,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C0_L2>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu3: cpu@300 {
device_type = "cpu";
@@ -95,6 +122,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C0_L2>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu4: cpu@10000 {
device_type = "cpu";
@@ -108,6 +136,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C1_L2>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu5: cpu@10100 {
device_type = "cpu";
@@ -121,6 +150,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C1_L2>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu6: cpu@10200 {
device_type = "cpu";
@@ -134,6 +164,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C1_L2>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu7: cpu@10300 {
device_type = "cpu";
@@ -147,6 +178,7 @@
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&C1_L2>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
C0_L2: l2-cache0 {
compatible = "cache";
@@ -169,7 +201,7 @@
memory@80000000 {
device_type = "memory";
- reg = <0x00000000 0x80000000 0 0x80000000>,
+ reg = <0x00000000 0x80000000 0 0x7c000000>,
<0x00000008 0x80000000 0 0x80000000>;
};
@@ -217,6 +249,19 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
+ timer@2a810000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x2a810000 0x0 0x10000>;
+ ranges = <0 0x0 0x2a820000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ frame@2a830000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x10000 0x10000>;
+ };
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -227,6 +272,60 @@
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
+ ete-0 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu0>;
+ status = "disabled";
+ };
+
+ ete-1 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu1>;
+ status = "disabled";
+ };
+
+ ete-2 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu2>;
+ status = "disabled";
+ };
+
+ ete-3 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu3>;
+ status = "disabled";
+ };
+
+ ete-4 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu4>;
+ status = "disabled";
+ };
+
+ ete-5 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu5>;
+ status = "disabled";
+ };
+
+ ete-6 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu6>;
+ status = "disabled";
+ };
+
+ ete-7 {
+ compatible = "arm,embedded-trace-extension";
+ cpu = <&cpu7>;
+ status = "disabled";
+ };
+
+ trbe {
+ compatible = "arm,trace-buffer-extension";
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_LOW>;
+ status = "disabled";
+ };
+
pci: pci@40000000 {
#address-cells = <0x3>;
#size-cells = <0x2>;
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 055764d0b9e5..9ccb80821bdb 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -10,7 +10,6 @@
memtimer: timer@2a810000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x2a810000 0x0 0x10000>;
- clock-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x2a820000 0x20000>;
diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/arm/morello-fvp.dts
new file mode 100644
index 000000000000..4a3f217555f7
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/morello-fvp.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ */
+
+/dts-v1/;
+#include "morello.dtsi"
+
+/ {
+ model = "Arm Morello Fixed Virtual Platform";
+ compatible = "arm,morello-fvp", "arm,morello";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ bp_refclock24mhz: clock-24000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "bp:clock24mhz";
+ };
+
+ block_0: virtio-block@1c170000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x1c170000 0x0 0x200>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ net_0: virtio-net@1c180000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x1c180000 0x0 0x200>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ rng_0: virtio-rng@1c190000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x1c190000 0x0 0x200>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ p9_0: virtio-p9@1c1a0000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x1c1a0000 0x0 0x200>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ kmi_0: kmi@1c150000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x0 0x1c150000 0x0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>;
+ clock-names = "KMIREFCLK", "apb_pclk";
+ };
+
+ kmi_1: kmi@1c160000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x0 0x1c160000 0x0 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>;
+ clock-names = "KMIREFCLK", "apb_pclk";
+ };
+
+ eth_0: ethernet@1d100000 {
+ compatible = "smsc,lan91c111";
+ reg = <0x0 0x1d100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/arm/morello-sdp.dts
new file mode 100644
index 000000000000..42c85f450fa9
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/morello-sdp.dts
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ */
+
+/dts-v1/;
+#include "morello.dtsi"
+
+/ {
+ model = "Arm Morello System Development Platform";
+ compatible = "arm,morello-sdp", "arm,morello";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dpu_aclk: clock-350000000 {
+ /* 77.1 MHz derived from 24 MHz reference clock */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <350000000>;
+ clock-output-names = "aclk";
+ };
+
+ dpu_pixel_clk: clock-148500000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ clock-output-names = "pxclk";
+ };
+
+ i2c0: i2c@1c0f0000 {
+ compatible = "cdns,i2c-r1p14";
+ reg = <0x0 0x1c0f0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&dpu_aclk>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clock-frequency = <100000>;
+
+ hdmi_tx: hdmi-transmitter@70 {
+ compatible = "nxp,tda998x";
+ reg = <0x70>;
+ video-ports = <0x234501>;
+ port {
+ tda998x_0_input: endpoint {
+ remote-endpoint = <&dp_pl0_out0>;
+ };
+ };
+ };
+ };
+
+ dp0: display@2cc00000 {
+ compatible = "arm,mali-d32", "arm,mali-d71";
+ reg = <0x0 0x2cc00000 0x0 0x20000>;
+ interrupts = <0 69 4>;
+ clocks = <&dpu_aclk>;
+ clock-names = "aclk";
+ iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>,
+ <&smmu_dp 8>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pl0: pipeline@0 {
+ reg = <0>;
+ clocks = <&dpu_pixel_clk>;
+ clock-names = "pxclk";
+ port {
+ dp_pl0_out0: endpoint {
+ remote-endpoint = <&tda998x_0_input>;
+ };
+ };
+ };
+ };
+
+ smmu_ccix: iommu@4f000000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0x4f000000 0x0 0x40000>;
+
+ interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ msi-parent = <&its1 0>;
+ #iommu-cells = <1>;
+ dma-coherent;
+ };
+
+ smmu_pcie: iommu@4f400000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0x4f400000 0x0 0x40000>;
+
+ interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+ msi-parent = <&its2 0>;
+ #iommu-cells = <1>;
+ dma-coherent;
+ };
+
+ pmu@50000000 {
+ compatible = "arm,cmn-600";
+ reg = <0x0 0x50000000 0x0 0x4000000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ arm,root-node = <0x804000>;
+ };
+
+ pcie_ctlr: pcie@28c0000000 {
+ device_type = "pci";
+ compatible = "pci-host-ecam-generic";
+ reg = <0x28 0xC0000000 0 0x10000000>;
+ ranges = <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>,
+ <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>,
+ <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>;
+ bus-range = <0 255>;
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ dma-coherent;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
+ msi-map = <0 &its_pcie 0 0x10000>;
+ iommu-map = <0 &smmu_pcie 0 0x10000>;
+ };
+
+ ccix_pcie_ctlr: pcie@4fc0000000 {
+ device_type = "pci";
+ compatible = "pci-host-ecam-generic";
+ reg = <0x4f 0xC0000000 0 0x10000000>;
+ ranges = <0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000>,
+ <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000>,
+ <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000>;
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ dma-coherent;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
+ msi-map = <0 &its_ccix 0 0x10000>;
+ iommu-map = <0 &smmu_ccix 0 0x10000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi
new file mode 100644
index 000000000000..5bc1c725dc86
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/morello.dtsi
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ soc_refclk50mhz: clock-50000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "apb_pclk";
+ };
+
+ soc_refclk85mhz: clock-85000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <85000000>;
+ clock-output-names = "iofpga:aclk";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,rainier";
+ reg = <0x0 0x0>;
+ device_type = "cpu";
+ enable-method = "psci";
+ /* 4 ways set associative */
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <512>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_0>;
+ clocks = <&scmi_dvfs 0>;
+
+ l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ /* 8 ways set associative */
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ cpu1: cpu@100 {
+ compatible = "arm,rainier";
+ reg = <0x0 0x100>;
+ device_type = "cpu";
+ enable-method = "psci";
+ /* 4 ways set associative */
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <512>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_1>;
+ clocks = <&scmi_dvfs 0>;
+
+ l2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ /* 8 ways set associative */
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ cpu2: cpu@10000 {
+ compatible = "arm,rainier";
+ reg = <0x0 0x10000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ /* 4 ways set associative */
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <512>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_2>;
+ clocks = <&scmi_dvfs 1>;
+
+ l2_2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ /* 8 ways set associative */
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ cpu3: cpu@10100 {
+ compatible = "arm,rainier";
+ reg = <0x0 0x10100>;
+ device_type = "cpu";
+ enable-method = "psci";
+ /* 4 ways set associative */
+ i-cache-size = <0x10000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <512>;
+ d-cache-size = <0x10000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_3>;
+ clocks = <&scmi_dvfs 1>;
+
+ l2_3: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ /* 8 ways set associative */
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-size = <0x100000>;
+ cache-unified;
+ };
+ };
+
+ firmware {
+ interrupt-parent = <&gic>;
+
+ scmi {
+ compatible = "arm,scmi";
+ mbox-names = "tx", "rx";
+ mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
+ shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_dvfs: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+ };
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ /* The first bank of memory, memory map is actually provided by UEFI. */
+ memory@80000000 {
+ device_type = "memory";
+ /* [0x80000000-0xffffffff] */
+ reg = <0x00000000 0x80000000 0x0 0x7f000000>;
+ };
+
+ memory@8080000000 {
+ device_type = "memory";
+ /* [0x8080000000-0x83f7ffffff] */
+ reg = <0x00000080 0x80000000 0x3 0x78000000>;
+ };
+
+ pmu {
+ compatible = "arm,rainier-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure-firmware@ff000000 {
+ reg = <0x0 0xff000000 0x0 0x01000000>;
+ no-map;
+ };
+ };
+
+ spe-pmu {
+ compatible = "arm,statistical-profiling-extension-v1";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ uart0: serial@2a400000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x2a400000 0x0 0x1000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_refclk50mhz>, <&soc_refclk50mhz>;
+ clock-names = "uartclk", "apb_pclk";
+
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@30000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x30000000 0x0 0x10000>, /* GICD */
+ <0x0 0x300c0000 0x0 0x80000>; /* GICR */
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ #interrupt-cells = <3>;
+ interrupt-controller;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ its1: msi-controller@30040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30040000 0x0 0x20000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+ };
+
+ its2: msi-controller@30060000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30060000 0x0 0x20000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+ };
+
+ its_ccix: msi-controller@30080000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x30080000 0x0 0x20000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+ };
+
+ its_pcie: msi-controller@300a0000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x300a0000 0x0 0x20000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ smmu_dp: iommu@2ce00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0x2ce00000 0x0 0x40000>;
+
+ interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "gerror", "cmdq-sync";
+ #iommu-cells = <1>;
+ };
+
+ mailbox: mhu@45000000 {
+ compatible = "arm,mhu-doorbell", "arm,primecell";
+ reg = <0x0 0x45000000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ clocks = <&soc_refclk50mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ sram: sram@6000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x06000000 0x0 0x8000>;
+ ranges = <0 0x0 0x06000000 0x8000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_scp_hpri0: scp-sram@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x80>;
+ };
+
+ cpu_scp_hpri1: scp-sram@80 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x80 0x80>;
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index 7f7226711d4b..a4a29193d4eb 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -116,7 +116,6 @@
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- clock-frequency = <100000000>;
};
pmu {
diff --git a/arch/arm64/boot/dts/arm/zena-css-fvp.dts b/arch/arm64/boot/dts/arm/zena-css-fvp.dts
new file mode 100644
index 000000000000..53c5412d92b2
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/zena-css-fvp.dts
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "zena-css.dtsi"
+
+/ {
+ model = "Zena CSS Fixed Virtual Platform";
+ compatible = "arm,zena-css-fvp", "arm,zena-css", "arm,vexpress";
+
+ chosen {
+ stdout-path = &soc_serial0;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+
+ /* ~2GB mapped at 2GB, another 2GB at 2TB */
+ reg = <0x00000000 0x80000000 0x00000000 0x7f000000>,
+ <0x00000200 0x00000000 0x00000000 0x80000000>;
+ };
+};
+
+&soc {
+ virtio@30020000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x30020000 0x0 0x10000>;
+ interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ virtio@30030000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x30030000 0x0 0x10000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ virtio@30040000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x30040000 0x0 0x10000>;
+ interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ virtio@30050000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x30050000 0x0 0x10000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ virtio@30060000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x30060000 0x0 0x10000>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ virtio@30080000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x30080000 0x0 0x10000>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/arm64/boot/dts/arm/zena-css.dtsi b/arch/arm64/boot/dts/arm/zena-css.dtsi
new file mode 100644
index 000000000000..0b41ee4bf4c6
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/zena-css.dtsi
@@ -0,0 +1,769 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (c) 2025, Arm Limited. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ soc_clk24mhz: clock-24000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "refclk24mhz";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ /*
+ * The latency and residency numbers below are for illustrative
+ * purposes only and may vary on actual silicon. These values are
+ * considered just to demonstrate that the cpuidle governor logic
+ * works.
+ */
+ idle-states {
+ entry-method = "psci";
+
+ cpu_sleep: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x10000>;
+ entry-latency-us = <800>;
+ exit-latency-us = <3200>;
+ local-timer-stop;
+ min-residency-us = <4200>;
+ };
+
+ cluster_sleep: cluster-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <1000>;
+ exit-latency-us = <3200>;
+ local-timer-stop;
+ min-residency-us = <4500>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 { cpu = <&cpu0>; };
+ core1 { cpu = <&cpu1>; };
+ core2 { cpu = <&cpu2>; };
+ core3 { cpu = <&cpu3>; };
+ };
+
+ cluster1 {
+ core0 { cpu = <&cpu4>; };
+ core1 { cpu = <&cpu5>; };
+ core2 { cpu = <&cpu6>; };
+ core3 { cpu = <&cpu7>; };
+ };
+
+ cluster2 {
+ core0 { cpu = <&cpu8>; };
+ core1 { cpu = <&cpu9>; };
+ core2 { cpu = <&cpu10>; };
+ core3 { cpu = <&cpu11>; };
+ };
+
+ cluster3 {
+ core0 { cpu = <&cpu12>; };
+ core1 { cpu = <&cpu13>; };
+ core2 { cpu = <&cpu14>; };
+ core3 { cpu = <&cpu15>; };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x0000>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl0_l2_0>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl0_l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl0_l3>;
+ };
+ };
+
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x0100>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl0_l2_1>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl0_l2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl0_l3>;
+ };
+ };
+
+ cpu2: cpu@200 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x0200>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl0_l2_2>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl0_l2_2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl0_l3>;
+ };
+ };
+
+ cpu3: cpu@300 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x0300>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl0_l2_3>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl0_l2_3: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl0_l3>;
+ };
+ };
+
+ cpu4: cpu@10000 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x10000>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl1_l2_0>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl1_l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl1_l3>;
+ };
+ };
+
+ cpu5: cpu@10100 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x10100>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl1_l2_1>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl1_l2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl1_l3>;
+ };
+ };
+
+ cpu6: cpu@10200 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x10200>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl1_l2_2>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl1_l2_2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl1_l3>;
+ };
+ };
+
+ cpu7: cpu@10300 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x10300>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl1_l2_3>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl1_l2_3: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl1_l3>;
+ };
+ };
+
+ cpu8: cpu@20000 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x20000>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl2_l2_0>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl2_l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl2_l3>;
+ };
+ };
+
+ cpu9: cpu@20100 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x20100>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl2_l2_1>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl2_l2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl2_l3>;
+ };
+ };
+
+ cpu10: cpu@20200 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x20200>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl2_l2_2>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl2_l2_2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl2_l3>;
+ };
+ };
+
+ cpu11: cpu@20300 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x20300>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl2_l2_3>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl2_l2_3: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl2_l3>;
+ };
+ };
+
+ cpu12: cpu@30000 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x30000>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl3_l2_0>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl3_l2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl3_l3>;
+ };
+ };
+
+ cpu13: cpu@30100 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x30100>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl3_l2_1>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl3_l2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl3_l3>;
+ };
+ };
+
+ cpu14: cpu@30200 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x30200>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl3_l2_2>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl3_l2_2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl3_l3>;
+ };
+ };
+
+ cpu15: cpu@30300 {
+ compatible = "arm,cortex-a720ae";
+ device_type = "cpu";
+ reg = <0x00 0x30300>;
+ enable-method = "psci";
+
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
+ next-level-cache = <&cl3_l2_3>;
+
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <0x10000>;
+
+ cl3_l2_3: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <0x400>; /* 8-way set */
+ cache-size = <0x80000>; /* 512KB */
+ cache-unified;
+ next-level-cache = <&cl3_l3>;
+ };
+ };
+
+ cl0_l3: l3-cache0 {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-line-size = <64>;
+ cache-sets = <0x1000>; /* 16-way set */
+ cache-size = <0x400000>; /* 4MB */
+ cache-unified;
+ };
+
+ cl1_l3: l3-cache1 {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-line-size = <64>;
+ cache-sets = <0x1000>; /* 16-way set */
+ cache-size = <0x400000>; /* 4MB */
+ cache-unified;
+ };
+
+ cl2_l3: l3-cache2 {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-line-size = <64>;
+ cache-sets = <0x1000>; /* 16-way set */
+ cache-size = <0x400000>; /* 4MB */
+ cache-unified;
+ };
+
+ cl3_l3: l3-cache3 {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-line-size = <64>;
+ cache-sets = <0x1000>; /* 16-way set */
+ cache-size = <0x400000>; /* 4MB */
+ cache-unified;
+ };
+ };
+
+ firmware {
+ scmi {
+ compatible = "arm,scmi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mbox-names = "tx", "tx_reply", "rx";
+ mboxes = <&mbox_db_tx 0 0 0>,
+ <&mbox_db_rx 0 0 0>,
+ <&mbox_db_rx 0 0 2>;
+ shmem = <&scmi_shmem_tx &scmi_shmem_rx>;
+
+ scmi_dvfs: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ dsu-pmu-0 {
+ compatible = "arm,dsu-pmu";
+ cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ dsu-pmu-1 {
+ compatible = "arm,dsu-pmu";
+ cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ dsu-pmu-2 {
+ compatible = "arm,dsu-pmu";
+ cpus = <&cpu8 &cpu9 &cpu10 &cpu11>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ dsu-pmu-3 {
+ compatible = "arm,dsu-pmu";
+ cpus = <&cpu12 &cpu13 &cpu14 &cpu15>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ sram: sram@104000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x00104000 0x0 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x00104000 0x00001000>;
+
+ scmi_shmem_tx: scpshmem-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x100>;
+ };
+
+ scmi_shmem_rx: scpshmem-sram-section@100 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x100 0x100>;
+ };
+ };
+
+ timer@1a810000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x1a810000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * Map child space [0x0..0x30000) to parent @ 0x1a810000
+ */
+ ranges = <0x0 0x0 0x1a810000 0x00030000>;
+
+ frame@20000 {
+ reg = <0x20000 0x10000>;
+ frame-number = <0>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gic: interrupt-controller@20800000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #redistributor-regions = <16>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ ranges;
+
+ /*
+ * With GIC-A720AE multiview enabled, GICR_TYPER.Last is
+ * always reported as 1 on redistributor views other than
+ * view 0. This breaks discovery of a single contiguous
+ * GICR frame region, so each core is described with its own
+ * redistributor region.
+ */
+ reg = <0x0 0x20800000 0x0 0x10000>, /* GICD */
+ <0x0 0x20880000 0x0 0x40000>, /* 16 * GICR */
+ <0x0 0x208c0000 0x0 0x40000>,
+ <0x0 0x20900000 0x0 0x40000>,
+ <0x0 0x20940000 0x0 0x40000>,
+ <0x0 0x20980000 0x0 0x40000>,
+ <0x0 0x209c0000 0x0 0x40000>,
+ <0x0 0x20a00000 0x0 0x40000>,
+ <0x0 0x20a40000 0x0 0x40000>,
+ <0x0 0x20a80000 0x0 0x40000>,
+ <0x0 0x20ac0000 0x0 0x40000>,
+ <0x0 0x20b00000 0x0 0x40000>,
+ <0x0 0x20b40000 0x0 0x40000>,
+ <0x0 0x20b80000 0x0 0x40000>,
+ <0x0 0x20bc0000 0x0 0x40000>,
+ <0x0 0x20c00000 0x0 0x40000>,
+ <0x0 0x20c40000 0x0 0x40000>;
+
+ its: msi-controller@20840000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x20840000 0x0 0x40000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ /*
+ * UART is fixed at 24MHz, both UARTCLK and PCLK.
+ */
+ soc_serial0: serial@1a400000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x1a400000 0x0 0x10000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clk24mhz>, <&soc_clk24mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ };
+
+ watchdog@1a420000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0x1a420000 0x0 0x10000>,
+ <0x0 0x1a430000 0x0 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ rtc@300d0000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x0 0x300d0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&soc_clk24mhz>;
+ clock-names = "apb_pclk";
+ };
+
+ mbox_db_tx: mailbox@40020000 {
+ compatible = "arm,mhuv3";
+ reg = <0x0 0x40020000 0x0 0x30000>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "combined";
+ clocks = <&soc_clk24mhz>;
+ #mbox-cells = <3>;
+ };
+
+ mbox_db_rx: mailbox@40060000 {
+ compatible = "arm,mhuv3";
+ reg = <0x0 0x40060000 0x0 0x30000>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "combined";
+ clocks = <&soc_clk24mhz>;
+ #mbox-cells = <3>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ };
+};