diff options
Diffstat (limited to 'arch/arm/boot/dts/rockchip')
31 files changed, 1499 insertions, 102 deletions
diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile index 716f5540e438..d0154fd7ff24 100644 --- a/arch/arm/boot/dts/rockchip/Makefile +++ b/arch/arm/boot/dts/rockchip/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rv1103b-omega4-evb.dtb \ rv1108-elgin-r1.dtb \ rv1108-evb.dtb \ rv1109-relfor-saib.dtb \ diff --git a/arch/arm/boot/dts/rockchip/rk3036-evb.dts b/arch/arm/boot/dts/rockchip/rk3036-evb.dts index becdc0b664bf..c8100dc4c7ce 100644 --- a/arch/arm/boot/dts/rockchip/rk3036-evb.dts +++ b/arch/arm/boot/dts/rockchip/rk3036-evb.dts @@ -16,8 +16,6 @@ &emac { phy = <&phy0>; - phy-reset-duration = <10>; /* millisecond */ - phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ pinctrl-names = "default"; pinctrl-0 = <&emac_xfer>, <&emac_mdio>; status = "okay"; @@ -28,6 +26,8 @@ phy0: ethernet-phy@0 { reg = <0>; + reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; }; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts index 4f928c7898e9..bc6e6468fcc4 100644 --- a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts @@ -8,6 +8,12 @@ model = "Rockchip RK3036 KylinBoard"; compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + chosen { stdout-path = "serial2:115200n8"; }; @@ -96,8 +102,6 @@ &emac { phy = <&phy0>; - phy-reset-duration = <10>; /* millisecond */ - phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */ pinctrl-names = "default"; pinctrl-0 = <&emac_xfer>, <&emac_mdio>; status = "okay"; @@ -108,6 +112,8 @@ phy0: ethernet-phy@0 { reg = <0>; + reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; }; }; }; @@ -382,6 +388,18 @@ status = "okay"; }; +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + status = "okay"; +}; + +&usb2phy_otg { + status = "okay"; +}; + &vop { status = "okay"; }; diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi index 63b9912be06a..78afae42f8b2 100644 --- a/arch/arm/boot/dts/rockchip/rk3036.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi @@ -23,9 +23,6 @@ i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -213,6 +210,8 @@ g-np-tx-fifo-size = <16>; g-rx-fifo-size = <275>; g-tx-fifo-size = <256 128 128 64 64 32>; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -224,6 +223,8 @@ clocks = <&cru HCLK_OTG1>; clock-names = "otg"; dr_mode = "host"; + phys = <&usb2phy_host>; + phy-names = "usb2-phy"; status = "disabled"; }; @@ -342,6 +343,37 @@ grf: syscon@20008000 { compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; reg = <0x20008000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + usb2phy: usb2phy@17c { + compatible = "rockchip,rk3036-usb2phy"; + reg = <0x017c 0x20>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy"; + assigned-clocks = <&cru SCLK_USB480M>; + assigned-clock-parents = <&usb2phy>; + #clock-cells = <0>; + status = "disabled"; + + usb2phy_host: host-port { + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2phy_otg: otg-port { + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; power: power-controller { compatible = "rockchip,rk3036-power-controller"; @@ -398,8 +430,9 @@ compatible = "rockchip,rk3036-inno-hdmi"; reg = <0x20034000 0x4000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_HDMI>; - clock-names = "pclk"; + clocks = <&cru PCLK_HDMI>, <&cru SCLK_LCDC>; + clock-names = "pclk", "ref"; + rockchip,grf = <&grf>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_ctl>; #sound-dai-cells = <0>; diff --git a/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts index c227691013ea..65f8bc804d21 100644 --- a/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-bqcurie2.dts @@ -80,26 +80,33 @@ clock-frequency = <400000>; tps: tps@2d { + compatible = "ti,tps65910"; reg = <0x2d>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio6>; interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + vcc5-supply = <&vcc_io>; vcc6-supply = <&vcc_io>; regulators { - vcc_rtc: regulator@0 { + vcc_rtc: vrtc { regulator-name = "vcc_rtc"; regulator-always-on; }; - vcc_io: regulator@1 { + vcc_io: vio { regulator-name = "vcc_io"; regulator-always-on; }; - vdd_arm: regulator@2 { + vdd_arm: vdd1 { regulator-name = "vdd_arm"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -107,7 +114,7 @@ regulator-always-on; }; - vcc_ddr: regulator@3 { + vcc_ddr: vdd2 { regulator-name = "vcc_ddr"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -115,42 +122,42 @@ regulator-always-on; }; - vcc18_cif: regulator@5 { + vcc18_cif: vdig1 { regulator-name = "vcc18_cif"; regulator-always-on; }; - vdd_11: regulator@6 { + vdd_11: vdig2 { regulator-name = "vdd_11"; regulator-always-on; }; - vcc_25: regulator@7 { + vcc_25: vpll { regulator-name = "vcc_25"; regulator-always-on; }; - vcc_18: regulator@8 { + vcc_18: vdac { regulator-name = "vcc_18"; regulator-always-on; }; - vcc25_hdmi: regulator@9 { + vcc25_hdmi: vaux1 { regulator-name = "vcc25_hdmi"; regulator-always-on; }; - vcca_33: regulator@10 { + vcca_33: vaux2 { regulator-name = "vcca_33"; regulator-always-on; }; - vcc_tp: regulator@11 { + vcc_tp: vaux33 { regulator-name = "vcc_tp"; regulator-always-on; }; - vcc28_cif: regulator@12 { + vcc28_cif: vmmc { regulator-name = "vcc28_cif"; regulator-always-on; }; @@ -158,9 +165,6 @@ }; }; -/* must be included after &tps gets defined */ -#include "../tps65910.dtsi" - &mmc0 { /* sdmmc */ status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts index ada7dbfc06a5..15dbe1677e30 100644 --- a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts @@ -19,6 +19,17 @@ reg = <0x60000000 0x40000000>; }; + hdmi_con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + vdd_log: regulator-vdd-log { compatible = "pwm-regulator"; pwms = <&pwm3 0 1000>; @@ -58,16 +69,45 @@ cpu-supply = <&vdd_arm>; }; +&gpu { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vop1 { + status = "disabled"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; tps: tps@2d { + compatible = "ti,tps65910"; reg = <0x2d>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio6>; interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + vcc1-supply = <&vsys>; vcc2-supply = <&vsys>; vcc3-supply = <&vsys>; @@ -78,17 +118,17 @@ vccio-supply = <&vsys>; regulators { - vcc_rtc: regulator@0 { + vcc_rtc: vrtc { regulator-name = "vcc_rtc"; regulator-always-on; }; - vcc_io: regulator@1 { + vcc_io: vio { regulator-name = "vcc_io"; regulator-always-on; }; - vdd_arm: regulator@2 { + vdd_arm: vdd1 { regulator-name = "vdd_arm"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -96,7 +136,7 @@ regulator-always-on; }; - vcc_ddr: regulator@3 { + vcc_ddr: vdd2 { regulator-name = "vcc_ddr"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -104,41 +144,41 @@ regulator-always-on; }; - vcc18_cif: regulator@5 { + vcc18_cif: vdig1 { regulator-name = "vcc18_cif"; regulator-always-on; }; - vdd_11: regulator@6 { + vdd_11: vdig2 { regulator-name = "vdd_11"; regulator-always-on; }; - vcc_25: regulator@7 { + vcc_25: vpll { regulator-name = "vcc_25"; regulator-always-on; }; - vcc_18: regulator@8 { + vcc_18: vdac { regulator-name = "vcc_18"; regulator-always-on; }; - vcc25_hdmi: regulator@9 { + vcc25_hdmi: vaux1 { regulator-name = "vcc25_hdmi"; regulator-always-on; }; - vcca_33: regulator@10 { + vcca_33: vaux2 { regulator-name = "vcca_33"; regulator-always-on; }; - vcc_rmii: regulator@11 { + vcc_rmii: vaux33 { regulator-name = "vcc_rmii"; }; - vcc28_cif: regulator@12 { + vcc28_cif: vmmc { regulator-name = "vcc28_cif"; regulator-always-on; }; @@ -146,9 +186,6 @@ }; }; -/* must be included after &tps gets defined */ -#include "../tps65910.dtsi" - &emac { phy = <&phy0>; phy-supply = <&vcc_rmii>; @@ -216,6 +253,10 @@ status = "okay"; }; +&vop0 { + status = "okay"; +}; + &wdt { status = "okay"; }; diff --git a/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts index b0b029f14643..07c03ed6fac6 100644 --- a/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-rayeager.dts @@ -198,9 +198,18 @@ status = "okay"; tps: tps@2d { + compatible = "ti,tps65910"; reg = <0x2d>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio6>; interrupts = <RK_PA4 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; pinctrl-0 = <&pmic_int>, <&pwr_hold>; @@ -214,19 +223,19 @@ vccio-supply = <&vsys>; regulators { - vcc_rtc: regulator@0 { + vcc_rtc: vrtc { regulator-name = "vcc_rtc"; regulator-always-on; }; - vcc_io: regulator@1 { + vcc_io: vio { regulator-name = "vcc_io"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; - vdd_arm: regulator@2 { + vdd_arm: vdd1 { regulator-name = "vdd_arm"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -234,7 +243,7 @@ regulator-boot-on; }; - vcc_ddr: regulator@3 { + vcc_ddr: vdd2 { regulator-name = "vcc_ddr"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; @@ -242,52 +251,52 @@ regulator-boot-on; }; - vcc18: regulator@5 { + vcc18: vdig1 { regulator-name = "vcc18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; - vdd_11: regulator@6 { + vdd_11: vdig2 { regulator-name = "vdd_11"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-always-on; }; - vcc_25: regulator@7 { + vcc_25: vpll { regulator-name = "vcc_25"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; }; - vccio_wl: regulator@8 { + vccio_wl: vdac { regulator-name = "vccio_wl"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - vcc25_hdmi: regulator@9 { + vcc25_hdmi: vaux1 { regulator-name = "vcc25_hdmi"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; }; - vcca_33: regulator@10 { + vcca_33: vaux2 { regulator-name = "vcca_33"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc_rmii: regulator@11 { + vcc_rmii: vaux33 { regulator-name = "vcc_rmii"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vcc28_cif: regulator@12 { + vcc28_cif: vmmc { regulator-name = "vcc28_cif"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -296,8 +305,6 @@ }; }; -#include "../tps65910.dtsi" - &i2c2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts index 21f824b09191..decbf2726ec4 100644 --- a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts +++ b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts @@ -272,7 +272,7 @@ phy-mode = "rmii"; phy-handle = <&phy0>; assigned-clocks = <&cru SCLK_MAC_SRC>; - assigned-clock-rates= <50000000>; + assigned-clock-rates = <50000000>; pinctrl-names = "default"; pinctrl-0 = <&rmii_pins>; status = "okay"; diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index d4572146d135..c49099954c28 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -48,7 +48,6 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu_opp_table>; @@ -87,31 +86,38 @@ opp-216000000 { opp-hz = /bits/ 64 <216000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-696000000 { opp-hz = /bits/ 64 <696000000>; opp-microvolt = <975000 975000 1325000>; + clock-latency-ns = <40000>; }; opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1075000 1075000 1325000>; opp-suspend; + clock-latency-ns = <40000>; }; opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1200000 1200000 1325000>; + clock-latency-ns = <40000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1325000 1325000 1325000>; + clock-latency-ns = <40000>; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts b/arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts index edc2b7f9112d..b56095fc2441 100644 --- a/arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts +++ b/arch/arm/boot/dts/rockchip/rk3188-bqedison2qc.dts @@ -262,7 +262,7 @@ interrupts = <RK_PB7 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&gsensor_int>; - rotation-matrix = "1", "0", "0", + mount-matrix = "1", "0", "0", "0", "-1", "0", "0", "0", "1"; vdd-supply = <&vcc_io>; diff --git a/arch/arm/boot/dts/rockchip/rk3188.dtsi b/arch/arm/boot/dts/rockchip/rk3188.dtsi index 44b54af0bbf9..850bd6e67895 100644 --- a/arch/arm/boot/dts/rockchip/rk3188.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3188.dtsi @@ -23,7 +23,6 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; operating-points-v2 = <&cpu0_opp_table>; resets = <&cru SRST_CORE0>; diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi index 96421355c274..cd11a018105b 100644 --- a/arch/arm/boot/dts/rockchip/rk322x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi @@ -36,7 +36,6 @@ resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; enable-method = "psci"; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts index a55270672732..8b491b002992 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload.dts @@ -197,11 +197,10 @@ }; &i2c0 { - hym8563: hym8563@51 { + hym8563: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; - clock-frequency = <32768>; clock-output-names = "xin32k"; interrupt-parent = <&gpio7>; interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts index dd42f8d31f70..a5f5c6d38f80 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts @@ -78,6 +78,21 @@ regulator-always-on; regulator-boot-on; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "HDMI"; + simple-audio-card,mclk-fs = <512>; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s>; + }; + }; }; &cpu0 { @@ -130,6 +145,8 @@ &hdmi { ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec_c0>; status = "okay"; }; @@ -283,6 +300,11 @@ status = "okay"; }; +&i2s { + #sound-dai-cells = <0>; + status = "okay"; +}; + &io_domains { status = "okay"; diff --git a/arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts index 10ce0554d4fc..46362e804daf 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-phycore-rdk.dts @@ -86,6 +86,10 @@ touchscreen@44 { compatible = "st,stmpe811"; reg = <0x44>; + interrupt-parent = <&gpio5>; + interrupts = <RK_PB4 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_irq_pin>; }; adc@64 { @@ -94,7 +98,7 @@ }; i2c_rtc: rtc@68 { - compatible = "rv4162"; + compatible = "microcrystal,rv4162"; reg = <0x68>; pinctrl-names = "default"; pinctrl-0 = <&i2c_rtc_int>; @@ -121,25 +125,25 @@ compatible = "nxp,pca9533"; reg = <0x62>; - led1 { + led-1 { label = "red:user1"; linux,default-trigger = "none"; type = <PCA9532_TYPE_LED>; }; - led2 { + led-2 { label = "green:user2"; linux,default-trigger = "none"; type = <PCA9532_TYPE_LED>; }; - led3 { + led-3 { label = "blue:user3"; linux,default-trigger = "none"; type = <PCA9532_TYPE_LED>; }; - led4 { + led-4 { label = "red:user4"; linux,default-trigger = "none"; type = <PCA9532_TYPE_LED>; @@ -199,7 +203,7 @@ touchscreen { ts_irq_pin: ts-irq-pin { - rockchip,pins = <5 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <5 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi index 12ab10c4adde..0816e388852f 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-phycore-som.dtsi @@ -100,7 +100,7 @@ tx_delay = <0x0>; rx_delay = <0x0>; - mdio0 { + mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts index ade9cc291813..d7790eebfdcd 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-brain.dts @@ -91,14 +91,12 @@ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-name = "vdd10_lcd"; - regulator-suspend-mem-disabled; }; vcc18_hdmi: SWITCH_REG2 { regulator-always-on; regulator-boot-on; regulator-name = "vcc18_hdmi"; - regulator-suspend-mem-disabled; }; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts index 6a0844e16279..3da105060302 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-fievel.dts @@ -98,9 +98,8 @@ snps,reset-gpio = <&gpio4 RK_PB0 0>; snps,reset-active-low; snps,reset-delays-us = <0 10000 30000>; - wakeup-source; - mdio0 { + mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; @@ -177,7 +176,7 @@ #address-cells = <1>; #size-cells = <0>; - btmrvl: btmrvl@2 { + btmrvl: bluetooth@2 { compatible = "marvell,sd8897-bt"; reg = <2>; interrupt-parent = <&gpio4>; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts index 0d4c50e05558..cba2898f8b7d 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dts @@ -48,7 +48,7 @@ #address-cells = <1>; #size-cells = <0>; - btmrvl: btmrvl@2 { + btmrvl: bluetooth@2 { compatible = "marvell,sd8897-bt"; reg = <2>; interrupt-parent = <&gpio4>; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts index 6894763979f0..0bf03b1ff2ab 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-jerry.dts @@ -488,7 +488,7 @@ interrupts = <RK_PA3 IRQ_TYPE_EDGE_FALLING>; reg = <0x2c>; hid-descr-addr = <0x0020>; - vcc-supply = <&vcc33_io>; + vdd-supply = <&vcc33_io>; wakeup-source; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts index d665c3e8862c..20fe84683928 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-mickey.dts @@ -246,7 +246,6 @@ regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-name = "vdd10_lcd"; - regulator-suspend-mem-disabled; }; vcc18_lcd: LDO_REG8 { @@ -255,7 +254,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-name = "vcc18_lcd"; - regulator-suspend-mem-disabled; }; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts index cc27d116d025..e241f93b2310 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-pinky.dts @@ -47,6 +47,7 @@ key-power { gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_POWER>; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi index 260d6c92cfd1..2d6cf08d00f9 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi @@ -388,7 +388,7 @@ rx-sample-delay-ns = <12>; - flash@0 { + spi_flash: flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi index 3f1d640afafa..4f2c048aee54 100644 --- a/arch/arm/boot/dts/rockchip/rk3288.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi @@ -34,10 +34,6 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio0; - mshc3 = &sdio1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -70,7 +66,6 @@ resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -81,7 +76,6 @@ resets = <&cru SRST_CORE1>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -92,7 +86,6 @@ resets = <&cru SRST_CORE2>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -103,7 +96,6 @@ resets = <&cru SRST_CORE3>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -116,6 +108,7 @@ opp-126000000 { opp-hz = /bits/ 64 <126000000>; opp-microvolt = <900000>; + clock-latency-ns = <40000>; }; opp-216000000 { opp-hz = /bits/ 64 <216000000>; @@ -558,7 +551,6 @@ pinctrl-1 = <&otp_out>; pinctrl-2 = <&otp_pin>; #thermal-sensor-cells = <1>; - rockchip,grf = <&grf>; rockchip,hw-tshut-temp = <95000>; status = "disabled"; }; @@ -748,9 +740,6 @@ #address-cells = <1>; #size-cells = <0>; - assigned-clocks = <&cru SCLK_EDP_24M>; - assigned-clock-parents = <&xin24m>; - /* * Note: Although SCLK_* are the working clocks * of device without including on the NOC, needed for @@ -1200,6 +1189,8 @@ compatible = "rockchip,rk3288-dp"; reg = <0x0 0xff970000 0x0 0x4000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru SCLK_EDP_24M>; + assigned-clock-parents = <&xin24m>; clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; clock-names = "dp", "pclk"; phys = <&edp_phy>; @@ -1296,6 +1287,21 @@ power-domains = <&power RK3288_PD_VIDEO>; }; + hevc: video-codec@ff9c0000 { + compatible = "rockchip,rk3288-vdec"; + reg = <0x0 0xff9c0000 0x0 0x440>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, + <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, + <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; + assigned-clock-rates = <400000000>, <100000000>, + <300000000>, <300000000>; + iommus = <&hevc_mmu>; + power-domains = <&power RK3288_PD_HEVC>; + }; + hevc_mmu: iommu@ff9c0440 { compatible = "rockchip,iommu"; reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; @@ -1303,7 +1309,7 @@ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3288_PD_HEVC>; }; gpu: gpu@ffa30000 { diff --git a/arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts b/arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts new file mode 100644 index 000000000000..c6472f933aa5 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2025 plan44.ch/luz + * Copyright (c) 2026 Onion Corporation + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include "rv1103b-omega4.dtsi" + +/ { + model = "Onion Omega4 Evaluation Board"; + compatible = "onion,omega4-evb", "onion,omega4", "rockchip,rv1103b"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_BLUE>; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "sys"; + pinctrl-names = "default"; + pinctrl-0 = <&led>; + }; + }; +}; + +&fspi0 { + status = "okay"; +}; + +&pinctrl { + leds { + led: led { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc0 { + status = "okay"; +}; + +&sdmmc1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1103b-omega4.dtsi b/arch/arm/boot/dts/rockchip/rv1103b-omega4.dtsi new file mode 100644 index 000000000000..6a8e8e0f80c5 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1103b-omega4.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2025 plan44.ch/luz + * Copyright (c) 2026 Onion Corporation + */ + +/dts-v1/; + +#include "rv1103b.dtsi" + +/ { + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + post-power-on-delay-ms = <300>; + reset-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_sd: vcc3v3-sd { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccio_sd: vccio-sd { + compatible = "regulator-gpio"; + gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_volt>; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <3300000 1 1800000 0>; + }; +}; + +&uart0 { + bootph-all; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; +}; + +&fspi0 { + spi_nand: flash@0 { + compatible = "spi-nand"; + reg = <0>; + bootph-pre-ram; + bootph-some-ram; + spi-max-frequency = <75000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x00000000 0x00040000>; + label = "env"; + }; + + partition@40000 { + reg = <0x00040000 0x00100000>; + label = "idblock"; + read-only; + }; + + partition@140000 { + reg = <0x00140000 0x00100000>; + label = "uboot"; + read-only; + }; + + partition@240000 { + reg = <0x00240000 0x00800000>; + label = "boot"; + }; + + partition@a40000 { + reg = <0x00a40000 0x0f5c0000>; + label = "ubi"; + }; + }; + }; +}; + +&sdmmc0 { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "disabled"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-sd; + no-mmc; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_cmd &sdmmc1_clk &sdmmc1_bus4>; + status = "disabled"; +}; + +&pinctrl { + sdio-pwrseq { + /omit-if-no-ref/ + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sdmmc_volt: sdmmc-volt { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + /omit-if-no-ref/ + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi new file mode 100644 index 000000000000..15516c384139 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1103b-pinctrl.dtsi @@ -0,0 +1,816 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/pinctrl/rockchip.h> +#include <arm64/rockchip/rockchip-pinconf.dtsi> + +&pinctrl { + cam-clk0 { + /omit-if-no-ref/ + cam_clk0: cam-clk0 { + rockchip,pins = + /* cam_clk0_out */ + <1 RK_PB5 1 &pcfg_pull_none>; + }; + }; + + cam-clk1 { + /omit-if-no-ref/ + cam_clk1: cam-clk1 { + rockchip,pins = + /* cam_clk1_out */ + <1 RK_PB6 1 &pcfg_pull_none>; + }; + }; + + cam-spi { + /omit-if-no-ref/ + cam_spi_bus4: cam-spi-bus4 { + rockchip,pins = + /* cam_spi_d0 */ + <0 RK_PB5 4 &pcfg_pull_up_drv_level_2>, + /* cam_spi_d1 */ + <0 RK_PB2 4 &pcfg_pull_up_drv_level_2>, + /* cam_spi_d2 */ + <0 RK_PB1 4 &pcfg_pull_up_drv_level_2>, + /* cam_spi_d3 */ + <0 RK_PB0 4 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + cam_spi_clk: cam-spi-clk { + rockchip,pins = + /* cam_spi_clk */ + <0 RK_PB4 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + cam_spi_cs0n: cam-spi-cs0n { + rockchip,pins = + /* cam_spi_cs0n */ + <0 RK_PB3 4 &pcfg_pull_none>; + }; + }; + + clk { + /omit-if-no-ref/ + clk_32k: clk-32k { + rockchip,pins = + /* clk_32k */ + <0 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + clk-24m { + /omit-if-no-ref/ + clk_24m_out: clk-24m-out { + rockchip,pins = + /* clk_24m_out */ + <0 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu: cpu { + rockchip,pins = + /* cpu_avs */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_bus4: emmc-bus4 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clk */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_bus4: fspi-bus4 { + rockchip,pins = + /* fspi_d0 */ + <1 RK_PA1 2 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PA2 2 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PA3 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PA0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_cs0: fspi-cs0 { + rockchip,pins = + /* fspi_cs0n */ + <1 RK_PA5 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + fspi_clk: fspi-clk { + rockchip,pins = + /* fspi_clk */ + <1 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m0_xfer: i2c0m0-xfer { + rockchip,pins = + /* i2c0_scl_m0 */ + <0 RK_PA5 3 &pcfg_pull_none_smt>, + /* i2c0_sda_m0 */ + <0 RK_PA6 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m1_xfer: i2c0m1-xfer { + rockchip,pins = + /* i2c0_scl_m1 */ + <1 RK_PB4 5 &pcfg_pull_none_smt>, + /* i2c0_sda_m1 */ + <1 RK_PB3 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m2_xfer: i2c0m2-xfer { + rockchip,pins = + /* i2c0_scl_m2 */ + <1 RK_PB5 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m2 */ + <1 RK_PB6 2 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <0 RK_PB0 1 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <0 RK_PB1 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <2 RK_PA4 4 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <2 RK_PA5 4 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PB2 1 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PB3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <2 RK_PA6 4 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <2 RK_PA7 4 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <0 RK_PB4 1 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <2 RK_PB3 4 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <2 RK_PB2 4 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_scl_m0 */ + <2 RK_PB0 4 &pcfg_pull_none_smt>, + /* i2c4_sda_m0 */ + <2 RK_PB1 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_scl_m1 */ + <1 RK_PB7 2 &pcfg_pull_none_smt>, + /* i2c4_sda_m1 */ + <1 RK_PC0 2 &pcfg_pull_none_smt>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0: jtagm0 { + rockchip,pins = + /* jtag_tck_m0 */ + <0 RK_PA5 5 &pcfg_pull_none>, + /* jtag_tms_m0 */ + <0 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1: jtagm1 { + rockchip,pins = + /* jtag_tck_m1 */ + <0 RK_PB4 3 &pcfg_pull_none>, + /* jtag_tms_m1 */ + <0 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm2: jtagm2 { + rockchip,pins = + /* jtag_tck_m2 */ + <1 RK_PB4 3 &pcfg_pull_none>, + /* jtag_tms_m2 */ + <1 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + psram-spi { + /omit-if-no-ref/ + psram_spi_bus4: psram-spi-bus4 { + rockchip,pins = + /* psram_spi_d0 */ + <0 RK_PA2 4 &pcfg_pull_none>, + /* psram_spi_d1 */ + <0 RK_PA1 4 &pcfg_pull_none>, + /* psram_spi_d2 */ + <0 RK_PA5 4 &pcfg_pull_none>, + /* psram_spi_d3 */ + <0 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + psram_spi_clk: psram-spi-clk { + rockchip,pins = + /* psram_spi_clk */ + <0 RK_PA0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + psram_spi_cs0n: psram-spi-cs0n { + rockchip,pins = + /* psram_spi_cs0n */ + <0 RK_PA4 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_ch0: pwm0m0-ch0 { + rockchip,pins = + /* pwm0m0_ch0 */ + <0 RK_PA1 1 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m0_ch1: pwm0m0-ch1 { + rockchip,pins = + /* pwm0m0_ch1 */ + <0 RK_PA5 2 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m0_ch2: pwm0m0-ch2 { + rockchip,pins = + /* pwm0m0_ch2 */ + <0 RK_PA6 2 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m0_ch3: pwm0m0-ch3 { + rockchip,pins = + /* pwm0m0_ch3 */ + <0 RK_PA2 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm0m1_ch0: pwm0m1-ch0 { + rockchip,pins = + /* pwm0m1_ch0 */ + <2 RK_PA0 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m1_ch1: pwm0m1-ch1 { + rockchip,pins = + /* pwm0m1_ch1 */ + <2 RK_PA1 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m1_ch2: pwm0m1-ch2 { + rockchip,pins = + /* pwm0m1_ch2 */ + <2 RK_PA2 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m1_ch3: pwm0m1-ch3 { + rockchip,pins = + /* pwm0m1_ch3 */ + <2 RK_PB0 3 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm0m2_ch1: pwm0m2-ch1 { + rockchip,pins = + /* pwm0m2_ch1 */ + <1 RK_PB7 1 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm0m2_ch2: pwm0m2-ch2 { + rockchip,pins = + /* pwm0m2_ch2 */ + <1 RK_PC0 1 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_ch0: pwm1m0-ch0 { + rockchip,pins = + /* pwm1m0_ch0 */ + <0 RK_PB0 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm1m0_ch1: pwm1m0-ch1 { + rockchip,pins = + /* pwm1m0_ch1 */ + <0 RK_PB1 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm1m0_ch2: pwm1m0-ch2 { + rockchip,pins = + /* pwm1m0_ch2 */ + <0 RK_PB2 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm1m0_ch3: pwm1m0-ch3 { + rockchip,pins = + /* pwm1m0_ch3 */ + <0 RK_PB3 3 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm1m1_ch0: pwm1m1-ch0 { + rockchip,pins = + /* pwm1m1_ch0 */ + <2 RK_PA3 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm1m1_ch1: pwm1m1-ch1 { + rockchip,pins = + /* pwm1m1_ch1 */ + <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm1m1_ch2: pwm1m1-ch2 { + rockchip,pins = + /* pwm1m1_ch2 */ + <2 RK_PA5 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm1m1_ch3: pwm1m1-ch3 { + rockchip,pins = + /* pwm1m1_ch3 */ + <2 RK_PB1 3 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_ch0: pwm2m0-ch0 { + rockchip,pins = + /* pwm2m0_ch0 */ + <1 RK_PB0 4 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm2m0_ch1: pwm2m0-ch1 { + rockchip,pins = + /* pwm2m0_ch1 */ + <1 RK_PA7 4 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm2m0_ch2: pwm2m0-ch2 { + rockchip,pins = + /* pwm2m0_ch2 */ + <1 RK_PB4 4 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm2m0_ch3: pwm2m0-ch3 { + rockchip,pins = + /* pwm2m0_ch3 */ + <1 RK_PB3 4 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm2m1_ch0: pwm2m1-ch0 { + rockchip,pins = + /* pwm2m1_ch0 */ + <2 RK_PA6 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm2m1_ch1: pwm2m1-ch1 { + rockchip,pins = + /* pwm2m1_ch1 */ + <2 RK_PA7 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm2m1_ch2: pwm2m1-ch2 { + rockchip,pins = + /* pwm2m1_ch2 */ + <2 RK_PB2 3 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + pwm2m1_ch3: pwm2m1-ch3 { + rockchip,pins = + /* pwm2m1_ch3 */ + <2 RK_PB3 3 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwr { + /omit-if-no-ref/ + pwr: pwr { + rockchip,pins = + /* pwr_ctrl0 */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* pwr_ctrl1 */ + <0 RK_PA4 1 &pcfg_pull_none>; + }; + }; + + rtc_32k { + /omit-if-no-ref/ + rtc_32k: rtc-32k { + rockchip,pins = + /* rtc_32k_out */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sai { + /omit-if-no-ref/ + sai: sai { + rockchip,pins = + /* sai_lrck */ + <2 RK_PB1 5 &pcfg_pull_none>, + /* sai_mclk */ + <2 RK_PB0 5 &pcfg_pull_none>, + /* sai_sclk */ + <2 RK_PA7 5 &pcfg_pull_none>, + /* sai_sdi */ + <2 RK_PA6 5 &pcfg_pull_none>, + /* sai_sdo */ + <2 RK_PB2 5 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + /* sdmmc0_det */ + <1 RK_PA6 1 &pcfg_pull_up>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_clk: spi0m0-clk { + rockchip,pins = + /* spi0_clk_m0 */ + <2 RK_PB0 2 &pcfg_pull_none>, + /* spi0_miso_m0 */ + <2 RK_PB3 2 &pcfg_pull_none>, + /* spi0_mosi_m0 */ + <2 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0n_m0 */ + <2 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1n_m0 */ + <2 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_clk: spi0m1-clk { + rockchip,pins = + /* spi0_clk_m1 */ + <2 RK_PA2 5 &pcfg_pull_none>, + /* spi0_miso_m1 */ + <2 RK_PA4 5 &pcfg_pull_none>, + /* spi0_mosi_m1 */ + <2 RK_PA1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0n_m1 */ + <2 RK_PA3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_cs1: spi0m1-cs1 { + rockchip,pins = + /* spi0_cs1n_m1 */ + <2 RK_PA0 5 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <0 RK_PA6 1 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <0 RK_PA5 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <0 RK_PB5 2 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <0 RK_PB4 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m2_xfer: uart0m2-xfer { + rockchip,pins = + /* uart0_rx_m2 */ + <1 RK_PB3 2 &pcfg_pull_up>, + /* uart0_tx_m2 */ + <1 RK_PB4 2 &pcfg_pull_up>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <0 RK_PB2 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <0 RK_PB3 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <0 RK_PB5 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <0 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <1 RK_PA7 2 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <1 RK_PB0 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m2_xfer: uart1m2-xfer { + rockchip,pins = + /* uart1_rx_m2 */ + <2 RK_PA7 1 &pcfg_pull_up>, + /* uart1_tx_m2 */ + <2 RK_PA6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m2_ctsn: uart1m2-ctsn { + rockchip,pins = + /* uart1m2_ctsn */ + <2 RK_PA5 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m2_rtsn: uart1m2-rtsn { + rockchip,pins = + /* uart1m2_rtsn */ + <2 RK_PA4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m3_xfer: uart1m3-xfer { + rockchip,pins = + /* uart1_rx_m3 */ + <2 RK_PA3 2 &pcfg_pull_up>, + /* uart1_tx_m3 */ + <2 RK_PA2 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m3_ctsn: uart1m3-ctsn { + rockchip,pins = + /* uart1m3_ctsn */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m3_rtsn: uart1m3-rtsn { + rockchip,pins = + /* uart1m3_rtsn */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <0 RK_PB1 2 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <0 RK_PB0 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m0_ctsn: uart2m0-ctsn { + rockchip,pins = + /* uart2m0_ctsn */ + <0 RK_PB3 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m0_rtsn: uart2m0-rtsn { + rockchip,pins = + /* uart2m0_rtsn */ + <0 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <2 RK_PB1 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <2 RK_PB0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_ctsn: uart2m1-ctsn { + rockchip,pins = + /* uart2m1_ctsn */ + <2 RK_PB3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m1_rtsn: uart2m1-rtsn { + rockchip,pins = + /* uart2m1_rtsn */ + <2 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m2_xfer: uart2m2-xfer { + rockchip,pins = + /* uart2_rx_m2 */ + <1 RK_PB6 3 &pcfg_pull_up>, + /* uart2_tx_m2 */ + <1 RK_PB5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m2_ctsn: uart2m2-ctsn { + rockchip,pins = + /* uart2m2_ctsn */ + <1 RK_PC0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m2_rtsn: uart2m2-rtsn { + rockchip,pins = + /* uart2m2_rtsn */ + <1 RK_PB7 3 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1103b.dtsi b/arch/arm/boot/dts/rockchip/rv1103b.dtsi new file mode 100644 index 000000000000..39f78e0733c9 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1103b.dtsi @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/clock/rockchip,rv1103b-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,boot-mode.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rv1103b"; + + interrupt-parent = <&gic>; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + reg = <0x0>; + clocks = <&cru ARMCLK>; + device_type = "cpu"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + clock-frequency = <24000000>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + xin24m: oscillator-24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1103b-pinctrl"; + rockchip,grf = <&ioc>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + gpio0: gpio@20520000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20520000 0x200>; + clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>; + gpio-controller; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio1: gpio@20d80000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20d80000 0x200>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio2: gpio@20840000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20840000 0x200>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cru: clock-controller@20000000 { + compatible = "rockchip,rv1103b-cru"; + reg = <0x20000000 0x81000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pmu_grf: syscon@20160000 { + compatible = "rockchip,rv1103b-pmu-grf", "syscon", "simple-mfd"; + reg = <0x20160000 0x1000>; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-normal = <BOOT_NORMAL>; + mode-recovery = <BOOT_RECOVERY>; + mode-bootloader = <BOOT_FASTBOOT>; + mode-loader = <BOOT_BL_DOWNLOAD>; + }; + }; + + ioc: syscon@20170000 { + compatible = "rockchip,rv1103b-ioc", "syscon"; + reg = <0x20170000 0x60000>; + }; + + gic: interrupt-controller@20411000 { + compatible = "arm,gic-400"; + reg = <0x20411000 0x1000>, + <0x20412000 0x2000>, + <0x20414000 0x2000>, + <0x20416000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + uart0: serial@20540000 { + compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart"; + reg = <0x20540000 0x100>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + sdmmc1: mmc@20650000 { + compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc"; + reg = <0x20650000 0x4000>; + clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; + status = "disabled"; + }; + + uart1: serial@20870000 { + compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart"; + reg = <0x20870000 0x100>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@20880000 { + compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart"; + reg = <0x20880000 0x100>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + sdmmc0: mmc@20d20000 { + compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc"; + reg = <0x20d20000 0x4000>; + clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_det &sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4>; + status = "disabled"; + }; + + emmc: mmc@20d30000 { + compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc"; + reg = <0x20d30000 0x4000>; + clocks = <&cru HCLK_EMMC>, <&cru CCLK_EMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>; + status = "disabled"; + }; + + fspi0: spi@20d40000 { + compatible = "rockchip,sfc"; + reg = <0x20d40000 0x4000>; + clocks = <&cru SCLK_SFC_2X>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&fspi_bus4 &fspi_cs0 &fspi_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + system_sram: sram@210f6000 { + compatible = "mmio-sram"; + reg = <0x210f6000 0x8000>; + ranges = <0 0x210f6000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +#include "rv1103b-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/rockchip/rv1108.dtsi b/arch/arm/boot/dts/rockchip/rv1108.dtsi index f3291f3bbc6f..42a4d72597a5 100644 --- a/arch/arm/boot/dts/rockchip/rv1108.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1108.dtsi @@ -32,7 +32,6 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <75>; diff --git a/arch/arm/boot/dts/rockchip/rv1109-relfor-saib.dts b/arch/arm/boot/dts/rockchip/rv1109-relfor-saib.dts index c13829d32c32..8a92700349b4 100644 --- a/arch/arm/boot/dts/rockchip/rv1109-relfor-saib.dts +++ b/arch/arm/boot/dts/rockchip/rv1109-relfor-saib.dts @@ -250,9 +250,9 @@ &i2s0 { /delete-property/ pinctrl-0; rockchip,trcm-sync-rx-only; - pinctrl-0 = <&i2s0m0_sclk_rx>, - <&i2s0m0_lrck_rx>, - <&i2s0m0_sdi0>; + pinctrl-0 = <&i2s0m0_sclk_rx>, + <&i2s0m0_lrck_rx>, + <&i2s0m0_sdi0>; pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dtsi b/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dtsi index 9a87dc0d5f66..1aedcd3a2167 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-sonoff-ihost.dtsi @@ -323,15 +323,15 @@ }; &pmu_io_domains { - pmuio0-supply = <&vcc1v8_pmu>; + pmuio0-supply = <&vcc3v3_sys>; pmuio1-supply = <&vcc3v3_sys>; vccio1-supply = <&vcc_1v8>; vccio2-supply = <&vccio_sd>; vccio3-supply = <&vcc3v3_sd>; - vccio4-supply = <&vcc_dovdd>; - vccio5-supply = <&vcc_1v8>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_dovdd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_1v8>; status = "okay"; }; @@ -342,16 +342,14 @@ &sdio { bus-width = <4>; - cap-sd-highspeed; cap-sdio-irq; keep-power-in-suspend; - max-frequency = <50000000>; + max-frequency = <25000000>; mmc-pwrseq = <&sdio_pwrseq>; non-removable; pinctrl-names = "default"; pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; rockchip,default-sample-phase = <90>; - sd-uhs-sdr50; vmmc-supply = <&vcc3v3_sd>; vqmmc-supply = <&vcc_1v8>; status = "okay"; |